Data signal generating unit and display device including the same

Abstract

A data signal generating part and a display device including the same are disclosed. The data signal generating part includes a gray scale data generating part, an input data comparing part outputting one of a first control signal and a second control signal according to a condition, a first output part receiving the one of the first control signal and the second control signal and a first data signal and outputting a first output data signal to a first data line, and a second output part receiving the one of the first control signal and the second control signal and a second data signal and outputting a second output data signal to a second data line.

Description

Technical Field

[0001] The present invention relates to a data signal generating unit and a display device including the same, and to a data signal generating unit for comparing grayscale data output and outputting a modified data signal to a pixel array based on the comparison result, and a display device including the same. Background Technology

[0002] The content described in this section is only to provide background information for this embodiment and does not constitute prior art.

[0003] In recent years, as the size of display devices (e.g., liquid crystal displays) has increased, the required resolution has also increased. With increased resolution, each color needs to represent more than 10 bits of grayscale. Therefore, the amount of driving current supplied to the display panel by the data driving unit (e.g., the source driver) needs to increase.

[0004] If the current consumption of the data drive increases, the heat generated by the buffer of the channel (e.g., data line) will increase, which may cause the buffer to fail.

[0005] Therefore, a technology is needed that can provide a large driving current while reducing heat generation in large-size display devices.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent document 0001: Korean Patent Publication No. 10-2014-0035197 (Publication date: March 21, 2014) Summary of the Invention

[0009] The purpose of this invention is to provide a data signal generator capable of reducing heat generation and a display device including the same.

[0010] The objectives of this invention are not limited to those described above. Other objectives and advantages of this invention not mentioned herein will be understood through the following description and will become clearer through embodiments of the invention. Furthermore, it will be apparent that the objectives and advantages of this invention can be achieved by the means and combinations thereof pointed out in the claims.

[0011] The data signal generation unit of this invention includes: a grayscale data generation unit that outputs a plurality of data signals including a first data signal and a second data signal; an input data comparison unit that outputs one of a first control signal and a second control signal based on the first data signal and the second data signal according to a condition; a first output unit that receives one of the first control signal and the second control signal and the first data signal, and outputs a first output data signal to a first data line; and a second output unit that receives one of the first control signal and the second control signal and the second data signal, and outputs a second output data signal to a second data line. The condition relates to a first previous data signal and a second previous data signal input from the grayscale data generation unit to the first data line and input to the second data line at a previous line time, and a change in the first data signal input from the grayscale data generation unit to the first data line and input to the second data line at a current line time. The first control signal causes the first output unit and the second output unit to perform a first operation, and the second control signal causes the first output unit and the second output unit to perform the first operation and the second operation.

[0012] Furthermore, the conditions include a first condition for outputting the first control signal and a second condition for outputting the second control signal. The first condition is as follows: the first previous data signal and the second previous data signal correspond to a first grayscale voltage, and the first data signal and the second data signal correspond to a second grayscale voltage, thereby changing from the first grayscale voltage of the previous line time to the second grayscale voltage of the current line time. The second condition is as follows: the first previous data signal and the second previous data signal correspond to the second grayscale voltage, and the first data signal and the second data signal correspond to the first grayscale voltage, thereby changing from the second grayscale voltage of the previous line time to the first grayscale voltage of the current line time.

[0013] Furthermore, the first output section and the second output section respectively include a first buffer and a second buffer, the first buffer and the second buffer each include at least one transistor, the condition includes a first condition and a second condition, based on the satisfaction of the first condition, a first sub-control signal for performing the first operation is output from the input data comparison section, the first operation causes all at least one transistor included in the first buffer and the second buffer to be turned on, and the first control signal includes the first sub-control signal.

[0014] Furthermore, based on the satisfaction of the second condition, the first operation and the second operation are performed, and a second sub-control signal for performing the second operation is output from the input data comparison unit. The second operation causes the first output data signal of the first data line, which is the output line of the first output unit, and the second output data signal of the second data line, which is the output line of the second output unit, to be output at the same voltage level. The second control signal includes the first sub-control signal and the second sub-control signal.

[0015] Furthermore, based on the satisfaction of the second condition, the first operation and the second operation are executed, and the second sub-control signal for executing the second operation is output from the input data comparison unit. The second operation causes the first data line of the first output unit to be connected to the second data line of the second output unit.

[0016] Furthermore, the first control signal includes a first sub-control signal for performing the first operation, the second control signal includes the first sub-control signal and a second sub-control signal for performing the second operation, and the first output unit includes: a first switch group controlled by the first sub-control signal; and a first buffer controlled by the output of the first switch group.

[0017] Furthermore, the second output section includes: a second switch group controlled by the first sub-control signal; and a second buffer controlled by the output of the second switch group.

[0018] Furthermore, it also includes a third switch group for connecting the first output line of the first buffer and the second output line of the second buffer, controlled by the second sub-control signal.

[0019] The display device of this invention includes: a gate driving unit that outputs a gate control signal; a data signal generating unit that outputs a data signal; a plurality of gate lines controlled by the gate control signal; a plurality of data lines that output the data signal; and a plurality of pixels connected to each of the plurality of gate lines and each of the plurality of data lines, wherein the plurality of data lines include a first data line and a second data line. The data signal generating unit includes: a grayscale data generating unit that outputs a plurality of data signals including the first data signal and the second data signal; an input data comparison unit that, based on the first data signal and the second data signal, outputs one of a first control signal and a second control signal according to conditions; and a first output unit that receives one of the first control signal and the second control signal and the first data signal. The system comprises: a first output data signal and a second output unit; and a second output unit, which receives one of the first control signal and the second control signal and the second data signal, and outputs a second output data signal to the second data line. The conditions relate to the changes in the first previous data signal and the second previous data signal input from the grayscale data generator to the first data line and the second previous data signal input to the second data line at a previous line time, and the changes in the first data signal and the second data signal input from the grayscale data generator to the first data line and the second data signal input to the second data line at the current line time. The first control signal causes the first output unit and the second output unit to perform a first operation, and the second control signal causes the first output unit and the second output unit to perform the first operation and the second operation.

[0020] Furthermore, the conditions include a first condition for outputting the first control signal and a second condition for outputting the second control signal. The first condition is as follows: the first previous data signal and the second previous data signal correspond to a first grayscale voltage, and the first data signal and the second data signal correspond to a second grayscale voltage, thereby changing from the first grayscale voltage of the previous line time to the second grayscale voltage of the current line time. The second condition is as follows: the first previous data signal and the second previous data signal correspond to the second grayscale voltage, and the first data signal and the second data signal correspond to the first grayscale voltage, thereby changing from the second grayscale voltage of the previous line time to the first grayscale voltage of the current line time.

[0021] Furthermore, the first output section and the second output section respectively include a first buffer and a second buffer, the first buffer and the second buffer each include at least one transistor, the condition includes a first condition and a second condition, based on the satisfaction of the first condition, a first sub-control signal for performing the first operation is output from the input data comparison section, the first operation causes all at least one transistor included in the first buffer and the second buffer to be turned on, and the first control signal includes the first sub-control signal.

[0022] Furthermore, based on the satisfaction of the second condition, the first operation and the second operation are performed, and a second sub-control signal for performing the second operation is output from the input data comparison unit. The second operation causes the first output data signal of the first data line, which is the output line of the first output unit, and the second output data signal of the second data line, which is the output line of the second output unit, to be output at the same voltage level. The second control signal includes the first sub-control signal and the second sub-control signal.

[0023] Furthermore, based on the satisfaction of the second condition, the first operation and the second operation are executed, and the second sub-control signal for executing the second operation is output from the input data comparison unit. The second operation causes the first data line of the first output unit to be connected to the second data line of the second output unit.

[0024] Furthermore, the first control signal includes a first sub-control signal for performing the first operation, the second control signal includes the first sub-control signal and a second sub-control signal for performing the second operation, and the first output unit includes: a first switch group controlled by the first sub-control signal; and a first buffer controlled by the output of the first switch group.

[0025] Furthermore, the second output section includes: a second switch group controlled by the first sub-control signal; and a second buffer controlled by the output of the second switch group.

[0026] Furthermore, it also includes a third switch group for connecting the first output line of the first buffer and the second output line of the second buffer, controlled by the second sub-control signal.

[0027] The data signal generating unit and display device including the present invention reduce the driving current and heat generation of the data driving unit and prevent malfunctions by enabling the data driving unit to perform two types of operations according to the change of grayscale voltage.

[0028] In addition to the above content, the specific effects of the present invention will be explained below in conjunction with specific embodiments. Attached Figure Description

[0029] Figure 1 This is a simplified block diagram of a display device including a data signal generator, according to some embodiments of the present invention.

[0030] Figure 2 For illustrative purposes Figure 1 Diagram of the data signal generation unit.

[0031] Figure 3 and Figure 4 For illustrative purposes Figure 2 A diagram illustrating the operation of the input data comparison section.

[0032] Figure 5 For illustrative purposes Figure 2 The diagram shows the first output section and the second output section.

[0033] Figure 6 For illustrative purposes Figure 2 and Figure 5 A diagram showing the operation of the first and second output sections.

[0034] Figure 7 This diagram illustrates the effect of the data signal generation unit in an embodiment of the present invention.

[0035] Figure 8 For illustrative purposes Figure 2 A diagram illustrating the operation of the input data comparison section.

[0036] Figure 9 For illustrative purposes Figure 2 and Figure 5 A diagram showing the operation of the first and second output sections. Detailed Implementation

[0037] The terms or words used in this specification and the claims of this invention should not be limited to their ordinary or dictionary meanings. In accordance with the principle that inventors can define the concepts of terms or words in order to best describe their own inventions, these terms or words should be interpreted as meanings and concepts consistent with the technical concept of this invention. Furthermore, the embodiments described in this specification and the structures shown in the accompanying drawings are merely one embodiment for implementing this invention and do not represent all the technical concepts of this invention. Therefore, it should be understood that at the time of this application, there may be various equivalent technical solutions and examples of modified applications that can replace them.

[0038] The terms "first," "second," "A," and "B," as used in this specification and the claims of the invention, are only used to describe various structural elements, and the structural elements are not limited to the terms used. These terms are only used to distinguish one structural element from other structural elements. For example, without departing from the scope of the invention, a first structural element may be referred to as a second structural element, and similarly, a second structural element may also be referred to as a first structural element. The term "and / or" includes a combination of multiple related descriptions or any one of multiple related descriptions.

[0039] The terminology used in this specification and the claims is for illustrative purposes only and does not limit the invention. Unless the context clearly indicates otherwise, singular expressions include plural expressions. In this application, terms such as "comprising" or "having" should not be construed as pre-excluding the presence or additional possibilities of features, numbers, steps, operations, structural elements, components, or combinations thereof described in the specification.

[0040] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0041] Terms defined in commonly used dictionaries should be interpreted as having the same meaning as the relevant technical term in context, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this specification. Furthermore, the various embodiments of the present invention may share the included structures, processes, steps, or methods to a extent that they do not conflict with each other at the technical level.

[0042] The following will refer to Figures 1 to 6 The data signal generating unit and the display device including the data signal generating unit of some embodiments of the present invention will be described.

[0043] Figure 1 This is a simplified block diagram of a display device including a data signal generator, according to some embodiments of the present invention.

[0044] Reference Figure 1 The display device 10 may include a panel 100, a signal processing device 200, a gate driving unit 300, and a data signal generating unit 1000.

[0045] Panel 100 (e.g., a liquid crystal panel) may include a plurality of pixels PX. Panel 100 may be connected to a plurality of gate lines G1 to G... n and multiple data lines D1 to D m Connect. Where n and m are natural numbers.

[0046] Multiple gate lines G1 to G can be supplied with nGate signals (e.g., gate on / off voltages (Von, Voff)) output from the gate drive unit 300 are applied respectively.

[0047] Multiple data lines D1 to D2 can be connected. m Data signals output from the data signal generator 1000 are applied respectively. Details of the data signal generator 1000 will be described below.

[0048] Multiple gate lines G1 to G n For example, they can be arranged separately along the row direction. Multiple data lines D1 to D... m For example, they can be arranged separately along the column direction. Pixels PX can be located on multiple gate lines G1 to G... n Each gate line and multiple data lines D1 to D in m The location where each data line intersects.

[0049] For example, a pixel PX can include multiple sub-pixels. For instance, when a pixel PX includes two sub-pixels, signals with opposite phases can be applied to the two sub-pixels respectively.

[0050] For example, the signal processing device 200 may include a timing controller. The signal processing device 200 may receive multiple input control signals from an external source (e.g., a graphics controller) and output a gate control signal C1 and a data control signal C2 based on the received multiple input control signals.

[0051] Multiple input control signals input to the signal processing device 200 may include a horizontal synchronization signal V. sync Vertical synchronization signal H sync Master clock MCLK and data enable signal DE.

[0052] The signal processing device 200 can output the gate control signal C1 to the gate drive unit 300, and can output the data control signal C2 to the data drive unit 400 of the data signal generator unit 1000.

[0053] The operation of the gate drive unit 300 can be controlled by the gate control signal C1. The gate control signal C1 may include, for example, a signal that starts the operation of the gate drive unit 300, a gate clock signal related to the output period of the gate on-voltage, and an output enable signal that determines the pulse width of the gate on-voltage.

[0054] The operation of the data drive unit 400 of the data signal generator 1000 can be controlled by the data control signal C2. The data control signal C2 may include, for example, a signal that initiates the operation of the data drive unit 400.

[0055] The signal processing device 200 can receive image signals R, G, B from an external source (e.g., a graphics controller) and output image data R', G', B' to the data driving unit 400. The image data R', G', B' can be data signals that have been preprocessed from the input image signals R, G, B. For example, the image signals R, G, B can be processed by the signal processing device 200 based on the operating conditions of the panel 100 and input as image data R', G', B' to the data driving unit 400.

[0056] The gate driving unit 300 can output the gate on / off voltages (Von, Voff) sequentially to multiple gate lines G1 to G2 based on the gate control signal C1 provided by the signal processing device 200. n .

[0057] The data driving unit 400 can sequentially receive image data R', G', and B' based on the data control signal C2 provided by the signal processing device 200. The data driving unit 400 can select the data signal corresponding to the image data R', G', and B' from multiple data signals output by the grayscale data generation unit 500.

[0058] The multiple data signals can be grayscale voltages. The multiple data signals can include a first data signal and a second data signal.

[0059] The data drive unit 400 can be connected via the first data line D. m and the second data line D m-1 The first data signal and the second data signal are identified respectively. The data drive unit 400 can, according to conditions, transmit the data through the first data line D. m The first output data signal is output to panel 100 and transmitted via the second data line D. m-1 The second output data signal is output to panel 100. The first output data signal can be a data signal that modifies the first data signal as the condition is met. The second output data signal can be a data signal that modifies the second data signal as the condition is met.

[0060] Figure 2 For illustrative purposes Figure 1 Diagram of the data signal generation unit.

[0061] Reference Figure 1 and Figure 2 The data signal generation unit 1000 may include a grayscale data generation unit 500 and a data driving unit 400. The data driving unit 400 may include an input data comparison unit 410, a first output unit 420, a second output unit 430, and a third switch group 440.

[0062] Among the multiple data signals output from the grayscale data generation unit 500, the first data signal DS1 can be transmitted through the first data line D. m The second data signal DS2 is input to the input data comparison unit 410 and can be transmitted via the second data line D. m-1 Input. Only two output units (first output unit 420 and second output unit 430) are shown in the attached figure, but the number of output units can be the same as the number of data lines.

[0063] The input data comparison unit 410 can output one of a first control signal CONS1 and a second control signal CONS2 based on the first data signal DS1 and the second data signal DS2, according to conditions. Although the accompanying drawings show that the first control signal CONS1 and the second control signal CONS2 are output from the input data comparison unit 410 through different lines, this is not a limitation. For example, one of the first control signal CONS1 and the second control signal CONS2 can be output from the input data comparison unit 410 through a single line.

[0064] Figure 3 and Figure 4 For illustrative purposes Figure 2 A diagram illustrating the operation of the input data comparison section.

[0065] Reference Figure 2 and Figure 3 The input data comparison unit 410 first determines whether a condition is met, and then outputs one of the first control signal CONS1 and the second control signal CONS2. If the first condition is met, the input data comparison unit 410 can output the first control signal CONS1; if the second condition is met, it can output the second control signal CONS2.

[0066] In order to determine whether the conditions are met, the input data comparison unit 410 can compare the data signal of the previous line-time with the data signal of the current line-time (step S100).

[0067] The conditions may involve changes in the previous data signal at the previous line time and the data signal at the current line time. The input data comparison unit 410 can compare data applied to multiple data lines D1 to D2 at the previous line time. m Multiple previous data signals are applied to multiple data lines D1 to D2 at the current line time. m Multiple data signals are compared. For example, the input data comparison unit 410 can compare a first previous data signal and a second previous data signal from a previous timeline with a first data signal and a second data signal from the current timeline. The first previous data signal and the first data signal can be applied to the first data line D. m The signal, the second previous data signal and the second data signal can be applied to the second data line D.m-1 The signal.

[0068] The previous line time may be, for example, a line time that occurs before the current line time, during which the following operation is performed: a gate on-state voltage Von is applied from the gate drive unit 300 to the first gate line G1 of the panel 100, causing a plurality of transistors connected to the first gate line G1 to conduct. The current line time may, for example, relate to the current operation of the display device 10, during which the following operation is performed: a gate on-state voltage Von is applied from the gate drive unit 300 to the second gate line G2 of the panel 100, causing a plurality of transistors connected to the second gate line G2 to conduct.

[0069] Conditions may include a first condition and a second condition.

[0070] The first condition can be a condition that satisfies the following: multiple data lines D1 to D2 are applied at previous time intervals. m Multiple previous data signals are first grayscale voltages, which are applied to multiple data lines D1 to D2 respectively in the current line time. m Multiple data signals are converted into a second grayscale voltage. The first grayscale voltage may be, for example, a voltage corresponding to the black grayscale, which is the lowest grayscale (e.g., grayscale 0). The second grayscale voltage may be, for example, a voltage corresponding to the white grayscale, which is the highest grayscale (e.g., grayscale 255). For example, when the first and second previous data signals correspond to the first grayscale voltage at a previous line time, and the first and second data signals correspond to the second grayscale voltage at the current line time, and the voltage changes from the first grayscale voltage to the second grayscale voltage, the input data comparison unit 410 can determine that the first condition is met.

[0071] The second condition can be one that satisfies the following conditions: multiple data lines D1 to D2 are applied at previous time intervals. m Multiple previous data signals are second grayscale voltages, which are applied to multiple data lines D1 to D2 respectively at the current line time. m Multiple data signals are converted into a first grayscale voltage. For example, when a first previous data signal and a second previous data signal correspond to a second grayscale voltage at a previous line time, and a first data signal and a second data signal correspond to a first grayscale voltage at the current line time, and the second grayscale voltage changes from the second grayscale voltage to the first grayscale voltage, the input data comparison unit 410 can determine that the second condition is satisfied.

[0072] Reference Figure 4 When Line 1 is the previous line time and Line 2 is the current line time, at the previous line time (Line 1), the previous data signal DS m DS m-1DS1, DS2, and DS2 are all first grayscale voltages (e.g., 0 grayscale). At the current line time (line 2), the data signal DS1... m DS m-1 DS1, DS2, and DS2 are all second grayscale voltages (e.g., 255 grayscale). When the previous line time (line 1) changes to the current line time (line 2), the input data comparison unit 410 can determine that the first condition is met based on the change from the first grayscale voltage to the second grayscale voltage.

[0073] When line 2 is the previous line time and line 3 is the current line time, at the previous line time (line 2), the previous data signal DS m DS m-1 DS1, DS2, and DS2 are all second grayscale voltages (e.g., 255 grayscale). At the current line time (line 3), the data signal DS... m DS m-1 DS1, DS2, and DS2 are all first gray level voltages (e.g., 0 gray level). When the previous line time (line 2) changes to the current line time (line 3), the input data comparison unit 410 can determine that the second condition is met based on the change from the second gray level voltage to the third gray level voltage.

[0074] Refer again Figure 2 and Figure 3 The input data comparison unit 410 can determine whether the first condition is met (step S200). Based on the satisfaction of the first condition (example in step S200), the input data comparison unit 410 can output a first control signal containing the first sub-control signal (step S300).

[0075] The first control signal CONS1 can be a signal that causes the first output unit 420 and the second output unit 430 to perform a first operation. The first operation will be explained below. Figure 5 Please provide an explanation.

[0076] The input data comparison unit 410 can output a modified data signal to the data line (step S400). When the first output unit 420 and the second output unit 430 perform a first operation via the first control signal CONS1, the input data comparison unit 410 can output a modified data signal to the data line.

[0077] The data lines for output data signals can be the output lines of each output unit. For example, the output line of the first output unit 420 can be the first data line D. m The output line of the second output unit 430 can be the second data line D. m-1 .

[0078] When the conditions are met, the output data signal can be a modified version of the data signal received from the grayscale data generation unit 500. Alternatively, when the conditions are not met, the output data signal can be the same as the data signal received from the grayscale data generation unit 500.

[0079] For example, the first output data signal DSO1 is transmitted through the first data line D. m The signal applied to pixel PX can be a signal that modifies the first data signal DS1 based on the first control signal CONS1 via the first output unit 420. For example, the second output data signal DSO2 is transmitted via the second data line D. m-1 The signal applied to pixel PX can be a signal that modifies the second data signal DS2 based on the first control signal CONS1 through the second output unit 430.

[0080] If the first condition is not met ("No" in step S200), the input data comparison unit 410 can determine whether the second condition is met (step S500). If the second condition is met ("Yes" in step S500), the input data comparison unit 410 can output a second control signal that includes the first sub-control signal and the second sub-control signal (step S600).

[0081] The second control signal CONS2 can be a signal that causes both the first output unit 420 and the second output unit 430 to perform the first operation and the second operation. The second operation will be referred to below. Figure 5 Please provide an explanation.

[0082] The input data comparison unit 410 can output a modified data signal to the data line (step S400). When the first output unit 420 and the second output unit 430 perform the first operation and the second operation through the second control signal CONS2, the input data comparison unit 410 can output a modified data signal to the data line.

[0083] For example, the first output data signal DSO1 is transmitted through the first data line D. m The signal applied to pixel PX can be a signal that modifies the first data signal DS1 through the first output unit 420 based on the second control signal CONS2. For example, the second output number is transmitted through the second data line D. m-1 The signal applied to pixel PX can be a signal that modifies the second data signal DS2 based on the second control signal CONS2 through the second output unit 430.

[0084] If the second condition is not met ("No" in step S500), the input data comparison unit 410 may output the current line time output data signal to the data line (step S700). In this case, neither the first control signal CONS1 nor the second control signal CONS2 needs to be output.

[0085] The first output data signal DSO1 is transmitted via the first data line D m The signal applied to pixel PX can be the signal of the first data signal DS1 output by the first output unit 420. For example, the second output data signal DS02 is output via the second data line D. m-1 The signal applied to pixel PX can be the signal that outputs the second data signal DS2 through the second output unit 430. In this case, the first data signal DS1 and the second data signal DS2 can be output separately without modification through the first output unit 420 and the second output unit 430.

[0086] Refer again Figure 1 and Figure 2 One of the first control signal CONS1 and the second control signal CONS2 output from the input data comparison unit 410 can be output to the first output unit 420 and the second output unit 430.

[0087] The first output unit 420 may include a first switch group 421 and a first buffer 423. The first output unit 420 may receive one of a first control signal CONS1 and a second control signal CONS2, and a first data signal DS1, and output the first output data signal DS1 to the pixel PX through the first output line of the first buffer 423. The first output line may, for example, be a first data line D. m .

[0088] The second output unit 430 may include a second switch group 431 and a second buffer 433. The second output unit 430 may receive one of a first control signal CONS1 and a second control signal CONS2, and a second data signal DS2, and output the second output data signal DS2 to the pixel PX through the second output line of the second buffer 433. The second output line may, for example, be a second data line D. m-1 .

[0089] Figure 5 For illustrative purposes Figure 2 The diagram shows the first output section and the second output section.

[0090] Reference Figure 2 and Figure 5The first switch group 421 can be controlled by the first sub-control signals SUBC1_R and SUBC1_F. The first switch group 421 can be located between the first power supply and the second power supply. The first switch group 421 can be, for example, a pull-down switch.

[0091] The first sub-control signals SUBC1_R and SUBC1_F can contain two types of sub-control signals. The two types of sub-control signals can be signals that are only opposite in phase and the same in magnitude.

[0092] The first buffer 423 can be controlled by the output of the first switch group 421. The first buffer 423 may include at least one transistor (e.g., TR1, TR2). The output of the first switch group 421 can be applied to the gate of at least one transistor (e.g., TR1, TR2) of the first buffer 423 and control at least one transistor (e.g., TR1, TR2).

[0093] The second switch group 431 can be controlled by the first sub-control signals SUBC1_R and SUBC1_F. The second switch group 431 can be located between the second power supply and the third power supply. The second switch group 431 can be, for example, a pull-up switch.

[0094] The second buffer 433 can be controlled by the output of the second switch group 431. The second buffer 433 may include at least one transistor (e.g., TR3, TR4). The output of the second switch group 431 can be applied to the gate of at least one transistor (e.g., TR3, TR4) of the second buffer 433 and control at least one transistor (e.g., TR3, TR4).

[0095] The third switch group 440 can be connected to the first output line of the first buffer 423 (e.g., the first data line D). m ) and the second output line of the second buffer 433 (e.g., the second data line D) m-1 The third switch group 440 can be set on the first output line of the first buffer 423 (e.g., the first data line D). m ) and the second output line of the second buffer 433 (e.g., the second data line D) m-1 The third switch group 440 can be connected to the common source line (CSline) and to the first output line (e.g., the first data line D). m ) and the second output line of the second buffer 433 (e.g., the second data line D) m-1The third switch group 440 may include at least one transistor (e.g., MUX). At least one transistor (e.g., MUX) in the third switch group 440 may be controlled by the second sub-control signal SUBC2. The third switch group 440 may include at least one additional transistor (e.g., OUTMUX). At least one additional transistor (e.g., OUTMUX) may be disposed between the first buffer 423 and the first output line, or between the second buffer 433 and the second output line.

[0096] The first operation can be performed via the first control signal CONS1. When the first operation is performed, at least one transistor (e.g., TR1, TR2, TR3, TR4) included in the first buffer 423 and the second buffer 433 can be turned on via the first control signal CONS1. For example, when the first condition is met and the first operation is performed via the first control signal CONS1, at least one transistor (e.g., TR1, TR2, TR3, TR4) included in the first buffer 423 and the second buffer 433 is turned on, and the output line (e.g., the first data line D) of each buffer is rapidly driven in a high current and low resistance state. m and the second data line D m-1 As the driving speed increases, the heat generated by the first buffer 423 and the second buffer 433 can be reduced.

[0097] The first and second operations can be performed via the second control signal CONS2. When the second operation is performed, the first output data signal DSO1 output to the first output line and the second output data signal DSO2 output to the second output line can be output at the same voltage level. The second control signal CONS2 may include a first sub-control signal for performing the first operation and a second sub-control signal for performing the second operation.

[0098] According to the second sub-control signal, at least one additional transistor (e.g., OUTMUX) is turned off, and two output lines with different power levels (e.g., the first data line D) are deactivated. m and the second data line D m-1 By short-circuiting each other through the conduction of at least one transistor (e.g., a MUX), charging or discharging operations are performed between the two output lines, thereby sharing charge. According to the second sub-control signal, the first output 420 and the second output 430 are not driven, and the two output lines (e.g., the first data line D) have different voltages. m and the second data line D m-1A short circuit allows the two output lines to charge or discharge without consuming current in the first output section 420 and the second output section 430, thereby reducing the amount of power generated.

[0099] Figure 6 For illustrative purposes Figure 2 and Figure 5 A diagram showing the operation of the first and second output sections.

[0100] Reference Figure 2 , Figure 5 and Figure 6 Within the first interval T1, the input data comparison unit 410 can output a first control signal CONS1, and within the second interval T2, the input data comparison unit 410 can output a second control signal CONS2.

[0101] Within the first interval T1, the first output data signal DSO1, modified from the first data signal DS1, and the second output data signal DSO2, modified from the second data signal DS2, can be output via the first sub-control signals SUBC1_R and SUBC1_F. For example, when the second data signal DS2 changes from a low voltage level to a high voltage level at the falling edge of the clock (CLK), the second output data signal DSO2 can quickly rise to a high voltage level, thereby reducing heat generation.

[0102] Within the second interval T2, the first sub-control signals SUBC1_R and SUBC1_F, and the second sub-control signal SUBC2 can be used to output a first output data signal DSO1 (modified from the first data signal DS1) and a second output data signal DSO2 (modified from the second data signal DS2). For example, when the second data signal DS2 changes from a high voltage level to a low voltage level at the falling edge of the clock (CLK), the second output data signal DSO2 can quickly drop to a low voltage level, reducing the driving range of subsequent operations and thus reducing heat generation.

[0103] Figure 7 This diagram illustrates the effect of the data signal generation unit in an embodiment of the present invention.

[0104] Reference Figure 7 Part (a) shows the output of the output buffer without the input data comparison unit; part (b) shows the output of the output buffer when the input data comparison unit outputs the second sub-control signal at all line times; and part (c) shows the output of the output buffer when the data signal generation unit of the present invention is included. Charging and discharging operations are performed in the common source interval (CS1, CS2, CS3, CS4).

[0105] In part (b), the second operation is performed according to the second sub-control signal at all linear times. As a result, compared to part (a), the driving range increases due to the presence of the first common source (CS) interval CS1, thus increasing heat generation. In part (c), the driving range decreases compared to part (a), thus reducing heat generation. Furthermore, in part (c), the second sub-control signal is output and the second operation (e.g., the fourth common source interval CS4) is performed only when changing from the highest gray level to the lowest gray level (e.g., the second condition), further reducing the driving range and thus reducing heat generation.

[0106] The following will refer to Figure 1 , Figure 2 , Figure 3 , Figure 5 , Figure 8 and Figure 9 The data signal generating unit and the display device including the data signal generating unit according to some embodiments of the present invention will be described. For clarity, content that is repeated in the previous description will be simplified or omitted.

[0107] Figure 8 For illustrative purposes Figure 2 A diagram illustrating the operation of the input data comparison section.

[0108] Reference Figure 2 and Figure 8 When the second condition is met, the input data comparison unit 410 can output a second control signal containing the second sub-control signal (step S800). In some embodiments, when the second condition is met, the first output unit 420 and the second output unit 430 can perform only the second operation.

[0109] Figure 9 For illustrative purposes Figure 2 and Figure 5 A diagram showing the operation of the first and second output sections.

[0110] Reference Figure 2 , Figure 5 and Figure 9 Within the third interval T3, the input data comparison unit 410 can output only the second sub-control signal SUBC2.

[0111] As used herein, the term "unit" can include a unit implemented in hardware, software, or firmware, and is used interchangeably with terms such as logic, logic block, component, or circuit. A "unit" can be a component that is integrally formed or the smallest unit or part of said component that performs more than one function. For example, according to one embodiment, the module can be implemented as an application-specific integrated circuit (ASIC).

[0112] According to various embodiments, each of the aforementioned structural elements (e.g., a unit) may include one or more entities. According to various embodiments, one or more structural elements or operations may be omitted, or one or more other structural elements or operations may be added. Alternatively or further, the multiple structural elements (e.g., units) may be integrated into a single structural element. In this case, the integrated structural element may perform one or more functions of each of the multiple structural elements, in a manner identical or similar to the functions performed by the corresponding structural elements in the multiple structural elements prior to integration. According to various embodiments, the multiple operations performed by a unit or other structural element may be performed sequentially, in parallel, iteratively, or heuristically, or may be performed in different orders, omit one or more of the multiple operations, or add one or more other operations.

[0113] The above description is merely illustrative of the technical concept of the present invention. Those skilled in the art can make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, this embodiment is for illustrative purposes only and does not limit the technical concept of the present invention. The scope of protection of the present invention should be interpreted according to the appended claims, and all technical concepts within the equivalent scope fall within the scope of protection of the present invention.

Claims

1. A data signal generator, characterized in that, include: The grayscale data generation unit outputs multiple data signals, including a first data signal and a second data signal; The input data comparison unit outputs one of a first control signal and a second control signal based on the first data signal and the second data signal, according to a condition. A first output unit receives one of the first control signal and the second control signal, and the first data signal, and outputs a first output data signal to a first data line; and The second output unit receives one of the first control signal and the second control signal, and the second data signal, and outputs a second output data signal to the second data line. The conditions relate to the changes in a first previous data signal input to the first data line from the grayscale data generator and a second previous data signal input to the second data line at a previous line time, and the changes in the first data signal input to the first data line from the grayscale data generator and the second data signal input to the second data line at the current line time. The first control signal causes the first output unit and the second output unit to perform the first operation. The second control signal causes the first output unit and the second output unit to perform the first operation and the second operation.

2. The data signal generator according to claim 1, characterized in that, The conditions include a first condition for outputting the first control signal and a second condition for outputting the second control signal. The first condition is as follows: The first previous data signal and the second previous data signal correspond to a first grayscale voltage, and the first data signal and the second data signal correspond to a second grayscale voltage, thereby changing from the first grayscale voltage in the previous line time to the second grayscale voltage in the current line time. The second condition is as follows: The first previous data signal and the second previous data signal correspond to the second grayscale voltage, and the first data signal and the second data signal correspond to the first grayscale voltage, thereby changing from the second grayscale voltage of the previous line time to the first grayscale voltage of the current line time.

3. The data signal generator according to claim 1, characterized in that, The first output section and the second output section each include a first buffer and a second buffer, and the first buffer and the second buffer each include at least one transistor. The conditions include a first condition and a second condition. Based on the satisfaction of the first condition, a first sub-control signal for performing the first operation is output from the input data comparison unit. The first operation causes all at least one transistor included in each of the first and second buffers to be turned on. The first control signal includes the first sub-control signal.

4. The data signal generator according to claim 3, characterized in that, Based on the fulfillment of the second condition, the first operation and the second operation are executed. A second sub-control signal for performing the second operation is output from the input data comparison unit. The second operation causes the first output data signal of the first data line, which is the output line of the first output unit, and the second output data signal of the second data line, which is the output line of the second output unit, to be output at the same voltage level. The second control signal includes the first sub-control signal and the second sub-control signal.

5. The data signal generator according to claim 4, characterized in that, Based on the fulfillment of the second condition, the first operation and the second operation are executed. The input data comparison unit outputs a second sub-control signal for performing the second operation, the second operation causing the first data line of the first output unit to be connected to the second data line of the second output unit.

6. The data signal generator according to claim 1, characterized in that, The first control signal includes a first sub-control signal for performing the first operation. The second control signal includes the first sub-control signal and a second sub-control signal for performing the second operation. The first output unit includes: The first switch group is controlled by the first sub-control signal; and The first buffer is controlled by the output of the first switch group.

7. The data signal generator according to claim 6, characterized in that, The second output section includes: The second switch group is controlled by the first sub-control signal; and The second buffer is controlled by the output of the second switch group.

8. The data signal generator according to claim 7, characterized in that, It also includes a third switch group for connecting the first output line of the first buffer and the second output line of the second buffer, which is controlled by the second sub-control signal.

9. A display device, characterized in that, include: The gate drive section outputs gate control signals; The data signal generator outputs a data signal. Multiple gate lines are controlled by the gate control signal; Multiple data lines output the data signal; and Multiple pixels, connected to each of the multiple gate lines and each of the multiple data lines. The plurality of data lines includes a first data line and a second data line. The data signal generator includes: The grayscale data generation unit outputs multiple data signals, including a first data signal and a second data signal; The input data comparison unit outputs one of a first control signal and a second control signal based on the first data signal and the second data signal, according to a condition. A first output unit receives one of the first control signal and the second control signal, and the first data signal, and outputs a first output data signal to a first data line; and The second output unit receives one of the first control signal and the second control signal, and the second data signal, and outputs a second output data signal to the second data line. The conditions relate to the changes in a first previous data signal input to the first data line from the grayscale data generator and a second previous data signal input to the second data line at a previous line time, and the changes in the first data signal input to the first data line from the grayscale data generator and the second data signal input to the second data line at the current line time. The first control signal causes the first output unit and the second output unit to perform the first operation. The second control signal causes the first output unit and the second output unit to perform the first operation and the second operation.

10. The display device according to claim 9, characterized in that, The conditions include a first condition for outputting the first control signal and a second condition for outputting the second control signal. The first condition is as follows: The first previous data signal and the second previous data signal correspond to a first grayscale voltage, and the first data signal and the second data signal correspond to a second grayscale voltage, thereby changing from the first grayscale voltage in the previous line time to the second grayscale voltage in the current line time. The second condition is as follows: The first previous data signal and the second previous data signal correspond to the second grayscale voltage, and the first data signal and the second data signal correspond to the first grayscale voltage, thereby changing from the second grayscale voltage of the previous line time to the first grayscale voltage of the current line time.

11. The display device according to claim 9, characterized in that, The first output section and the second output section each include a first buffer and a second buffer, and the first buffer and the second buffer each include at least one transistor. The conditions include a first condition and a second condition. Based on the satisfaction of the first condition, a first sub-control signal for performing the first operation is output from the input data comparison unit. The first operation causes all at least one transistor included in each of the first and second buffers to be turned on. The first control signal includes the first sub-control signal.

12. The display device according to claim 11, characterized in that, Based on the fulfillment of the second condition, the first operation and the second operation are executed. A second sub-control signal for performing the second operation is output from the input data comparison unit. The second operation causes the first output data signal of the first data line, which is the output line of the first output unit, and the second output data signal of the second data line, which is the output line of the second output unit, to be output at the same voltage level. The second control signal includes the first sub-control signal and the second sub-control signal.

13. The display device according to claim 12, characterized in that, Based on the fulfillment of the second condition, the first operation and the second operation are executed. The input data comparison unit outputs a second sub-control signal for performing the second operation, the second operation causing the first data line of the first output unit to be connected to the second data line of the second output unit.

14. The display device according to claim 9, characterized in that, The first control signal includes a first sub-control signal for performing the first operation. The second control signal includes the first sub-control signal and a second sub-control signal for performing the second operation. The first output unit includes: The first switch group is controlled by the first sub-control signal; and The first buffer is controlled by the output of the first switch group.

15. The display device according to claim 14, characterized in that, The second output section includes: The second switch group is controlled by the first sub-control signal; and The second buffer is controlled by the output of the second switch group.

16. The display device according to claim 15, characterized in that, It also includes a third switch group for connecting the first output line of the first buffer and the second output line of the second buffer, which is controlled by the second sub-control signal.

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