Display panel and display device comprising the same

Abstract

The disclosure relates to a display panel and a display device including the same. A display panel includes a display area in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are disposed, and a gate driver connected to the gate lines. The gate driver includes a rendering signal generator sequentially outputting a rendering signal, a gate signal output circuit sequentially outputting a gate signal, and an output controller receiving the rendering signal, the gate signal, and a frequency control signal to output a pulse of the gate signal to a corresponding gate line or maintain a voltage of the corresponding gate line at a first gate voltage. A display device is also disclosed.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, for example, but not limited to, a display panel and a display apparatus including the display panel. Background Technology

[0002] Electroluminescent display devices include self-emissive elements, such as organic light-emitting diodes (OLEDs), arranged in corresponding sub-pixels. These devices offer fast response times, high luminous efficiency, high brightness, and wide viewing angles. Furthermore, they can represent black grayscale as true black, thereby improving contrast and color reproduction.

[0003] Electroluminescent display devices do not require a backlight unit and can be formed on plastic substrates, thin glass substrates, and / or metal substrates, including flexible materials.

[0004] Various methods have been investigated to further reduce the power consumption of electroluminescent display devices. For example, variable refresh rate (VRR) technology can be applied to electroluminescent display devices. However, the implementation of VRR technology may increase the size and complexity of the gating drive circuit, which can reduce the yield of the display panel and increase the non-display area of ​​the display panel.

[0005] The description of related technologies should not be considered prior art simply because it is mentioned or associated with in the related technologies section. The description of related technologies includes information describing one or more aspects of the subject matter technology, and the description in this section does not limit the scope of this disclosure. Summary of the Invention

[0006] This disclosure aims to overcome the limitations and shortcomings of related technologies, including the problems mentioned above.

[0007] One or more aspects of this disclosure are intended to provide a display panel capable of reducing power consumption and a display device including the display panel.

[0008] Other aspects, features and advantages of this disclosure are set forth herein and will also be apparent from this disclosure, or may be learned by practicing the inventive concepts provided herein.

[0009] A display panel according to one or more exemplary embodiments includes: a display area having a plurality of data lines, a plurality of gating lines, a plurality of power lines, and a plurality of sub-pixels disposed therein; and a gating driver connected to the plurality of gating lines. The gating driver includes: a rendering signal generator configured to sequentially output rendering signals; a gating signal output circuit configured to sequentially output gating signals; and an output controller configured to receive the rendering signals, the gating signals, and a frequency control signal to output pulses of the gating signals to corresponding gating lines or to maintain the voltage of the corresponding gating lines at a first gating voltage.

[0010] The gating signal output circuit may include multiple signal transmission stages connected to one or more clock lines, to which one or more clock signals are applied. The multiple signal transmission stages are sequentially connected via carry signal lines that propagate carry signals from one stage to the next. Each of the multiple signal transmission stages is configured to output a corresponding gating signal to a corresponding first output node. The output controller may include multiple controllers connected to a corresponding stage of the gating signal output circuit. Each controller is configured to receive a corresponding gating signal from a corresponding signal transmission stage, receive the frequency control signal, and output a corresponding final gating signal to a corresponding second output node connected to the corresponding gating line. The corresponding final gating signal may include a pulse of the corresponding gating signal or a signal maintained at the first gating voltage.

[0011] The strobe signal output circuit may include: a first signal transmission stage configured to output a pulse of a first strobe signal; and a second signal transmission stage configured to receive the pulse of the first strobe signal as a carry signal and output a pulse of a second strobe signal following the pulse of the first strobe signal. The output controller may include: a first controller configured to receive the pulse of the first strobe signal, a pulse of a first rendering signal, and the frequency control signal; and a second controller configured to receive the pulse of the second strobe signal, a pulse of a second rendering signal generated following the pulse of the first rendering signal, and the frequency control signal.

[0012] The Nth (N is a natural number) signal transmission stage can output the Nth gating signal to the first output node in response to the voltage of the Q node. The Nth controller can share the Q node and output the Nth final gating signal to the second output node in response to the Nth rendering signal, the Nth gating signal, and the frequency control signal.

[0013] The Nth signal transmission stage may include: a first transistor comprising a gate electrode connected to a clock node, a first electrode connected to a VST node, and a second electrode connected to a Q2 node, wherein a clock signal is applied to the clock node and a start signal or carry signal is input to the VST node; a second transistor comprising a gate electrode connected to the VST node, a first electrode connected to a buffer node, and a second electrode connected to a VEH node, wherein a second gate voltage is applied to the VEH node; a first capacitor connected between the buffer node and the clock node; a third transistor comprising a gate electrode connected to the buffer node, a first electrode connected to the clock node, and a second electrode connected to a QB node; and a fourth transistor comprising a gate electrode connected to the Q2 node, a first electrode connected to a QB node, and a second electrode connected to a QB node. The first electrode of the QB node and the second electrode connected to the VEH node; a fifth transistor, which includes a gate electrode connected to the VEL node, a first electrode connected to the Q2 node, and a second electrode connected to the Q node, wherein the first gate voltage is applied to the VEL node; a sixth first transistor, which includes a gate electrode connected to the Q node, a first electrode connected to the VEL node, and a second electrode connected to the first output node; a second capacitor connected between the Q node and the first output node; a seventh transistor, which includes a gate electrode connected to the QB node, a first electrode connected to the first output node, and a second electrode connected to the VEH node; and a third capacitor connected between the QB node and the VEH node.

[0014] The Nth controller may further include: a sixth-second transistor comprising a gate electrode connected to the Q node, a first electrode connected to the VEL node, and a second electrode connected to the second output node; a fourth capacitor into which the voltage of the frequency control signal is charged; an eighth transistor comprising a gate electrode to which the Nth rendering signal is applied, the eighth transistor comprising a first electrode connected to the fourth capacitor and a second electrode to which the frequency control signal is applied; and a ninth transistor comprising a gate electrode connected to the fourth capacitor, a first electrode connected to the first output node, and a second electrode connected to the second output node.

[0015] The Nth controller may include: a first control transistor including a gate electrode connected to the Q node, a first electrode connected to the VEL node, and a second electrode connected to the second output node, wherein the first gating voltage is applied to the VEL node; a capacitor into which the voltage of the frequency control signal is charged; a second control transistor including a gate electrode to which the Nth rendering signal is applied, wherein the second control transistor includes a first electrode connected to the capacitor and a second electrode to which the frequency control signal is applied; and a third control transistor including a gate electrode connected to the capacitor, a first electrode connected to the first output node, and a second electrode connected to the second output node.

[0016] Each of the sub-pixels may include: a light-emitting device; a driving circuit configured to drive the light-emitting device; a capacitor connected to the driving circuit; and one or more switching circuits connected to the capacitor.

[0017] Each of the one or more switching circuits may include a transistor. A pulse of the first gating voltage or the gating signal output from the output controller may be applied to a corresponding gating line. The corresponding gating line may be connected to the gate electrode of the transistor.

[0018] Each of the plurality of sub-pixels may include: a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a light-emitting device including an anode electrode connected to a fourth node and a cathode electrode to which a cathode voltage is applied; a capacitor connected between the node to which the pixel driving voltage is applied and the first node; a first switching transistor including a gate electrode to which a first strobe signal is applied, the first switching transistor including a first electrode connected to the first node and a second electrode connected to the third node; and a second switching transistor including a gate electrode to which a second strobe signal is applied, the second switching transistor including a first electrode connected to a data line. The output controller includes an electrode and a second electrode connected to the second node; a third switching transistor including a gate electrode to which a fifth strobe signal is applied, the third switching transistor including a first electrode connected to the node to which the pixel driving voltage is applied and a second electrode connected to the second node; a fourth switching transistor including a gate electrode to which the fifth strobe signal is applied, the fourth switching transistor including a first electrode connected to the third node and a second electrode connected to the fourth node; and a fifth switching transistor including a gate electrode to which a fourth strobe signal is applied, the fifth switching transistor including a first electrode connected to the first node and a second electrode to which an initialization voltage is applied. The pulse of the strobe signal output from the output controller or the first strobe voltage may be at least one of the first strobe signal and the fourth strobe signal.

[0019] Each of the plurality of sub-pixels may further include: a sixth switching transistor including a gate electrode to which a third strobe signal is applied, the sixth switching transistor including a first electrode connected to the fourth node and a second electrode to which an anode reset voltage is applied; and a seventh switching transistor including a gate electrode to which the third strobe signal is applied, the seventh switching transistor including a first electrode connected to the second node and a second electrode to which an on-bias voltage is applied.

[0020] A display device according to one or more exemplary embodiments includes: a display panel including a display area, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels are disposed in the display area; a gate driver connected to the gate lines; and a data driver connected to the data lines. The gate driver includes: a rendering signal generator configured to sequentially output rendering signals; a gate signal output circuit configured to sequentially output gate signals; and an output controller configured to receive the rendering signals, the gate signals, and a frequency control signal to output pulses of the gate signals to corresponding gate lines or to maintain the voltage of the corresponding gate lines at a first gate voltage. Each of a first sub-pixel to which pulses of the gate signals from the output controller are applied is charged with a data voltage from the data driver to update pixel data. Each of a second sub-pixel to which pulses of the gate signals from the output controller are applied and maintained at the first gate voltage is driven with a previously charged data voltage. The plurality of sub-pixels includes the first sub-pixels and the second sub-pixels.

[0021] The display panel may include: a refresh pixel region, in which pixel data is updated within a frame period; and a skip pixel region, in which pixel data is not updated. The refresh pixel region may include a first sub-pixel that is pulsed with the strobe signal from the output controller. The skip pixel region may include a second sub-pixel that is pulsed with the voltage maintained at the first strobe voltage from the output controller.

[0022] A display device according to one or more exemplary embodiments includes: a display area including a plurality of gate lines and a plurality of sub-pixels; and one or more controllers configured to control the plurality of sub-pixels to selectively assign refresh sub-pixels and skip sub-pixels among the plurality of sub-pixels. Pixel data of the refresh sub-pixels is updated during a frame period, and pixel data of the skip sub-pixels is not updated during the frame period. The one or more controllers include gate drivers connected to the plurality of gate lines. The gate driver is configured to: output a pulse of the first gate signal to the first gate line corresponding to the refresh sub-pixel based on the first rendering signal, the first gate signal, and the frequency control signal; and maintain the second gate line corresponding to the skip sub-pixel at a first gate voltage based on the second rendering signal and the frequency control signal.

[0023] A subpixel selectively assigned to refresh at a first time point may be different from a subpixel selectively assigned to refresh at a second time point. Similarly, a subpixel selectively assigned to skip at the first time point may be different from a subpixel selectively assigned to skip at the second time point. During operation of the display device, the first time point may be before a given frame period, and the second time point may be after the given frame period.

[0024] The gating driver may include a rendering signal generator, a gating signal output circuit, and an output controller.

[0025] The rendering signal generator may include a first transmission stage and a second transmission stage. The first transmission stage may be configured to output the first rendering signal, and the second transmission stage may be configured to receive the first rendering signal as a carry signal and output the second rendering signal.

[0026] The strobe signal output circuit may include a first signal transmission stage and a second signal transmission stage. The first signal transmission stage may be configured to output the first strobe signal, and the second signal transmission stage may be configured to receive the first strobe signal as a carry signal and output a second strobe signal.

[0027] The output controller may include a first controller and a second controller. The first controller may be configured to receive the first rendering signal from the first transmission stage, receive the first gating signal from the first signal transmission stage, and receive the frequency control signal, and may output a pulse of the first gating signal to the first gating line corresponding to the refresh sub-pixel. The second controller may be configured to receive the second rendering signal and the frequency control signal from the second transmission stage but not the second gating signal from the second signal transmission stage, and may output the first gating voltage to the second gating line corresponding to the skip sub-pixel.

[0028] The first transmission stage and the second transmission stage can be cascaded, and the first signal transmission stage and the second signal transmission stage can be cascaded, while the first controller and the second controller are not cascaded.

[0029] The first transmission stage can be directly connected to the first controller, but is not directly connected to the first signal transmission stage. The second transmission stage can be directly connected to the second controller, but is not directly connected to the second signal transmission stage.

[0030] The one or more controllers may include a timing controller, or may include both a timing controller and a host system.

[0031] The one or more controllers can be configured to selectively assign refresh subpixels and skip subpixels among the plurality of subpixels in real time.

[0032] In one or more aspects, the present invention can reduce or minimize power consumption without degrading image quality by changing the pixel refresh rate according to the position within the display area, and can achieve low-power driving and improved operating life of the display device.

[0033] In one or more aspects, the present invention can reduce power consumption without degrading image quality by displaying images in different areas of a display panel at different refresh rates or by driving different areas of a display panel at different refresh rates.

[0034] In one or more aspects, the techniques of this subject can change the pixel driving frequency without degrading image quality by selectively controlling refresh and skip operations (or selectively controlling refresh pixels and skip pixels) on a pixel-by-pixel basis.

[0035] In one or more aspects, the techniques of this subject can lead to a reduction in the size of the non-display area of ​​the display panel due to the limited addition of circuitry and signal lines for controlling the variable refresh rate, and can facilitate a narrow bezel design for the display panel.

[0036] The effects of this subject matter are not limited to those described above, and those skilled in the art will clearly understand from this disclosure other effects not mentioned.

[0037] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon review of the accompanying drawings and the following detailed description. All such additional systems, methods, features, and advantages are intended to be included within the scope of this description, the disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0038] It should be understood that the above and following descriptions of this disclosure are exemplary and intended to provide further explanation of the claimed disclosure. Nothing in this section should be construed as limiting the claims. Further details, advantages, and aspects are discussed below in conjunction with embodiments of this disclosure. Attached Figure Description

[0039] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles and examples of this disclosure. In the drawings: Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure; Figure 2A and Figure 2B This is an exemplary view showing a plurality of pixel regions in an exemplary embodiment of the present disclosure, wherein the driving frequency of a pixel is independently controlled; Figure 3 This is a circuit diagram illustrating a pixel circuit according to a first exemplary embodiment of the present disclosure; Figure 4A and Figure 4B This illustrates the application of a first exemplary embodiment of the present disclosure to the refresh period and the skip period during which the refresh period is performed. Figure 3 The waveform diagram of an example of the gating signal for the pixel circuit shown; Figure 5 This illustrates a first exemplary embodiment of a device for driving according to the present disclosure. Figure 3 An exemplary view of the gating driver of the pixel circuit shown; Figure 6 This is an exemplary view illustrating the configuration of a gating driver capable of changing the driving frequency of pixels according to an exemplary embodiment of the present disclosure. Figure 7 This illustrates in detail exemplary embodiments according to this disclosure. Figure 6 The circuit diagram shown is an example of a strobe driver; Figures 8A to 13B This illustrates an exemplary embodiment according to the present disclosure. Figure 7 An exemplary view of the operation of the output controller is shown; and Figure 14 This is a cross-sectional view showing the cross-sectional structure of a display panel according to an exemplary embodiment of the present disclosure.

[0040] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and depictions of these elements may be exaggerated. Detailed Implementation

[0041] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known methods, functions, structures, or configurations may be omitted for brevity where such descriptions might unnecessarily obscure aspects of this disclosure. Furthermore, repeated descriptions may be omitted for brevity. The described processing steps and / or the progression of operations are non-limiting examples.

[0042] The order of steps and / or operations is not limited to the order set forth herein and may be altered to occur in a different order than that described herein, except for steps and / or operations that must occur in a specific order. In one or more examples, two consecutive operations may be performed substantially simultaneously, or the two operations may be performed in reverse order or in a different order depending on the functions or operations involved.

[0043] Unless otherwise stated, the same reference numerals may refer to the same elements throughout the specification, even when shown in different figures. Unless otherwise stated, the same reference numerals may be used to refer to the same or substantially the same elements throughout the specification and figures. In one or more aspects, the same elements (or elements with the same name) in different figures may have the same or substantially the same function and properties, unless otherwise stated. The names of the various elements used in the following explanation are chosen for convenience only and may therefore differ from those used in the actual product.

[0044] The advantages and features of this disclosure, and its implementation methods, are illustrated by the embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are examples and are provided to make this disclosure thorough and complete, to assist those skilled in the art in understanding the inventive concept, without limiting the scope of protection of this disclosure.

[0045] The shapes, dimensions (e.g., size, length, width, height, thickness, position, radius, diameter, and area), proportions, ratios, angles, quantities, number of elements, etc., disclosed herein (including those shown in the accompanying drawings) are merely examples, and therefore, this disclosure is not limited to the details shown. However, it should be noted that the relative dimensions of the components shown in the accompanying drawings are part of this disclosure.

[0046] When the terms “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “comprising,” “composed of,” etc., are used with respect to one or more elements (e.g., layers, films, components, electrodes, structures, transistors, parts, members, parts, regions, areas, sections, steps, operations, etc.), one or more additional elements may be added unless a term such as “only” is used. The terminology used in this disclosure is for describing particular exemplary embodiments only and is not intended to limit the scope of this disclosure. Unless expressly stated otherwise, any reference to the singular may include the plural, and vice versa. In one or more examples, unless expressly stated otherwise, an element may be one or more elements; and an element may include multiple elements. The word “exemplary” is used to indicate as an example or illustration. An implementation is an exemplary implementation. An aspect is an exemplary aspect. In one or more implementations, “implementation,” “example,” “aspect,” etc., should not be construed as preferred or advantageous relative to other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc. Furthermore, the term “can” encompasses all the meanings of the term “able to”.

[0047] In one or more aspects, unless otherwise expressly stated, components, features, or corresponding information (e.g., levels, ranges, dimensions, sizes, etc.) are interpreted as including a range of errors or tolerances, even if no explicit description of such an error or tolerance range is provided. An error or tolerance range may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.). When interpreting numerical values, unless otherwise expressly stated, the value is interpreted as including the error range.

[0048] When using any term indicating location or position, such as “on,” “on top of,” “above,” “directly above,” “above,” “below,” “above,” “above,” “below,” “under,” “under,” “near,” “close to,” “adjacent to,” “next to,” “right next to,” “on one side of,” etc., to describe the positional relationship between two elements (e.g., layers, films, components, electrodes, structures, transistors, parts, components, components, areas, zones, sections, etc.), one or more additional elements may be located between the two elements, unless more restrictive terms such as “closely to,” “directly,” or “tightly” are used. For example, when using any of the foregoing terms to describe one element and another element, the description should be interpreted to include cases where the elements are in direct contact with each other and cases where one or more additional elements are disposed or inserted between them. Furthermore, spatial relative terms such as the foregoing terms and other terms such as “front,” “back,” “back,” “left,” “right,” “top,” “bottom,” “up,” “down,” “downward,” “upward,” “upward,” “column,” “row,” “vertical,” “horizontal,” and “diagonal” refer to any frame of reference. For example, these terms can be used to exemplarily understand the relative relationships between elements, including any correlations shown in the accompanying drawings. However, embodiments of this disclosure are not limited thereto. Spatial relative terms should be understood to include terms for different orientations of elements in use or operation, other than those depicted in the drawings or described herein. For example, if an element located below or under another element is flipped, that element can be referred to as an element above or above the other element. Thus, for example, the terms “below” or “under” can, in meaning, include the terms “above” or “on top.” Exemplary terms such as “below” can include all directions, including “below,” “above,” and diagonal directions. Similarly, exemplary terms such as “above”, “on”, etc. can include all directions, including “above”, “on”, “below”, and diagonal directions.

[0049] When describing temporal relationships, when the temporal order is described as such as "after", "following", "subsequent", "next", "before", "in front", "before", etc., it may include discontinuous or out-of-order situations, and therefore one or more other events may occur in between, unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0050] It should be understood that although the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used herein to describe various elements (e.g., layers, films, components, electrodes, structures, transistors, parts, components, parts, regions, areas, sections, steps, operations, etc.), these elements should not be limited by these terms, for example, not by any particular order, priority, or number of elements. Furthermore, these are not used to define the nature or basis of an element. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may refer to a second element, and similarly, a second element may refer to a first element. Furthermore, without departing from the scope of this disclosure, first elements, second elements, etc., may be named arbitrarily by those skilled in the art as conveniently as possible. For clarity, the function or structure of these elements (e.g., first elements, second elements, etc.) is not limited by ordinal numbers or names preceding the element. Furthermore, a first element may include one or more first elements. Similarly, a second element, etc., may include one or more second elements, etc.

[0051] The term "joined" to another element (e.g., layer, film, component, electrode, structure, transistor, part, component, area, region, section, etc.) can be understood as, for example, the element can be joined directly or indirectly to the other element. The term "joined" or similar expressions can refer to terms such as "in contact," "contact," "overlapping," "crossing," "intersecting," "connected," "linked," "combined," "associated," "set up," "arranged," "interacting," etc. Unless otherwise stated, the joining can involve the insertion or interposition of one or more intermediate elements between the element and another element. Furthermore, unless otherwise stated, an element can be joined to another element at least partially or completely (or entirely). Additionally, an element can be included in at least one of two or more elements joined to each other. Similarly, another element can be included in at least one of two or more elements joined to each other. When an element is joined to another element, at least a portion of the element can be joined to at least a portion of the other element. The term "together with another element" or similar expressions can be understood, depending on the context, as "the other element" or "with another element, to another element, in another element, or on another element." Similarly, the term “each other” can be understood in context as “each other” or “with each other, to each other, or on each other”.

[0052] Terms such as “line” or “direction” should not be interpreted solely based on the geometric relationship that the respective lines or directions are parallel, perpendicular, diagonal, or inclined to each other, but may mean a line or direction with a wider range of directional characteristics within which the components of this disclosure can be functionally operated. For example, the terms “first direction,” “second direction,” etc., should not be interpreted solely based on the geometric relationship that the respective directions are parallel, perpendicular, diagonal, or inclined to each other, but may mean a direction with a wider range of directional characteristics within which the components of this disclosure can be functionally operated.

[0053] The term “at least one” should be understood to include any and all combinations of one or more related listed items. For example, unless otherwise stated, each of the phrases “at least one of the first, second, or third items” and “at least one of the first, second, and third items” can mean (i) a combination of items provided by two or more of the first, second, and third items or (ii) only one of the first, second, or third items. Furthermore, unless otherwise stated, at least one of a plurality of elements can mean (i) one element of a plurality of elements, (ii) some elements of a plurality of elements, or (iii) all elements of a plurality of elements. Furthermore, unless otherwise stated, “at least some,” “some,” “at least some parts,” “at least some components,” “at least a portion,” “at least one or more parts,” “at least one component,” “at least one or more components,” “at least some elements,” “one or more,” etc., in the context of a plurality of elements can mean (i) one element of a plurality of elements, (ii) a portion (or a part) of a plurality of elements, (iii) one or more portions (or components) of a plurality of elements, (iv) one or more elements of a plurality of elements, (v) a plurality of elements of a plurality of elements, or (vi) all elements of a plurality of elements. In addition, unless otherwise stated, “at least some,” “some,” “at least some parts,” “at least some components,” “at least a portion,” “at least one or more parts,” “at least one component,” “at least one or more components,” etc., can mean (i) a part (or a portion) of an element, (ii) one or more parts (or components) of an element, (iii) an element, or (iv) all parts of an element.

[0054] The expression "first element," "second element," and " / or" "third element" should be understood as any one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. A similar interpretation applies to "and / or" used with two elements or with three or more elements. For example, A, B, and / or C can refer to only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. Furthermore, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to only A; only B; A or B; or A and B.

[0055] In one or more aspects, unless otherwise stated, the terms "between" and "among" may be used interchangeably for convenience only. For example, the expression "between multiple elements" can be understood as "among multiple elements." In another example, the expression "among multiple elements" can be understood as "between multiple elements." In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. Furthermore, when an element is referred to as being "between" at least two elements, the element may be the only element among the at least two elements, or there may be one or more intermediate elements.

[0056] In one or more aspects, unless otherwise stated, the phrases “each other” and “mutually” may be used interchangeably for convenience only. For example, the expression “different from each other” can be understood as “different from each other”. In another example, the expression “different from each other” can be understood as “different from each other”. In one or more examples, the number of elements involved in the foregoing expression may be two. In one or more examples, the number of elements involved in the foregoing expression may be more than two.

[0057] In one or more aspects, unless otherwise stated, the phrases “one or more of…” and “at least one of…” may be used interchangeably for convenience only. In one or more aspects, unless otherwise stated, the term “nth” may refer to “nth” (e.g., the second when n is 2, or the third when n is 3), and n may be a natural number or an integer.

[0058] The term "or" means "inclusive or" rather than "exclusive or". That is, unless otherwise stated or clearly determined by the context, the statement "x uses a or b" means any natural inclusive permutation. For example, "a or b" can mean "a", "b", or "a and b". For example, "a, b, or c" can mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0059] The phrases “substantially identical” or “nearly identical” can indicate the degree to which they are considered equivalent, taking into account minor differences caused by errors in the manufacturing process.

[0060] Features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, may be technically related to each other, and may be operated, associated, or driven together in various ways. Embodiments of this disclosure may be implemented or performed independently of each other, or may be implemented or performed together in a mutually dependent or related relationship. In one or more aspects, components of each device and apparatus according to the various embodiments of this disclosure are operatively linked and configured.

[0061] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, unless otherwise stated, the terms “part,” “unit,” or “module” can refer to, for example, a circuit, component, integrated circuit, computational block of a circuit device, or structure configured to perform the described functions, as understood by one of ordinary skill in the art.

[0062] The terminology used herein has been selected as that commonly used in the relevant technical field; however, other terms may exist depending on the development / changes in technology and / or conventions, the preferences of those skilled in the art, etc. Therefore, the terminology used herein should not be construed as limiting the technical concept, but rather as examples of terms describing exemplary embodiments.

[0063] Furthermore, in certain circumstances, terms may be arbitrarily chosen by the applicant, and in such cases, their detailed meanings are described herein. Therefore, the terms used herein should be understood based on their meanings and the content of this document, and not merely on their names.

[0064] In the following description, various exemplary embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. Regarding the reference numerals for elements in each drawing, unless otherwise stated, the same or similar elements may be shown in other drawings, and the same reference numerals may refer to the same or similar elements. Even if depicted in different drawings, the same or similar elements may be represented by the same reference numerals. For the sake of brevity, repeated descriptions of the same or similar elements may be omitted. Unless otherwise stated, elements designated by the same or similar reference numerals in different drawings should be understood to have the same description. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness; therefore, embodiments of the present disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0065] When describing the flow of a signal, for example, when a signal is provided (e.g., passed or sent) from node A to node B, this may include situations where the signal is provided from node A to node B via one or more nodes, unless phrases such as “provided immediately” or “provided directly” are used.

[0066] Each of the pixel circuits and gating drive circuits in the display device may include multiple transistors. The transistors may be implemented as thin-film transistors (TFTs). The transistors may be implemented as oxide thin-film transistors (Oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs (LTPS TFTs) including low-temperature polycrystalline silicon, etc.

[0067] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor, and the drain is the electrode through which charge carriers leave the transistor. Therefore, during operation, charge carriers flow between the source and drain. In an n-channel transistor, the charge carriers are electrons. The source is at a lower potential (or voltage) than the drain, causing electrons to flow from the source to the drain, while conventional current flows from the drain to the source. In a p-channel transistor (e.g., a p-channel metal-oxide-semiconductor), the charge carriers are holes. The source is at a higher potential (or voltage) than the drain, causing holes to flow from the source to the drain, while conventional current flows from the source to the drain.

[0068] The designation of the source and drain terminals is not fixed and can vary depending on the applied voltage and operating conditions. Therefore, this disclosure is not limited to the labeling of the source and drain terminals. In exemplary embodiments of this disclosure, for ease of description, the source and drain electrodes are distinguished and interchangeable. That is, an electrode described as a source electrode can be used as a drain electrode, and vice versa. In the following description, the source and drain of the transistor may also be referred to as the first electrode and the second electrode.

[0069] The gating signal oscillates between a gating on voltage and a gating off voltage. The transistor turns on in response to the gating on voltage and turns off in response to the gating off voltage. In the case of an n-channel transistor, the gating on voltage can be a high gating voltage VGH, and the gating off voltage can be a low gating voltage VGL. In the case of a p-channel transistor, the gating on voltage can be a low gating voltage VGL, and the gating off voltage can be a high gating voltage VGH.

[0070] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0071] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0072] Reference Figure 1 The display device 10 according to an exemplary embodiment of the present disclosure includes a display panel 100, a display panel driving circuit configured to write data to the pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0073] The display panel 100 may include a display area AA for displaying an input image on the screen. A non-display area NA may be disposed outside the display area AA. The substrate of the display panel 100 may be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. The non-display area NA outside the display area AA can be understood as a border area. The display panel 100 may be a rectangular panel having a length along the X-axis direction (or a first direction), a width along the Y-axis direction (or a second direction), and a thickness along the Z-axis direction (or a third direction), but is not limited thereto. For example, at least a portion of the display panel 100 may have a curved outer portion.

[0074] Display panel 100 includes lines such as multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and multiple power lines. The gate lines GL can be arranged parallel to a first direction X on display panel 100, and the data lines DL can be arranged parallel to a second direction Y on display panel 100. Pixel PXL of display area AA is connected to the data lines DL, gate lines GL, power lines, etc. The power lines can be collectively connected to pixel PXL and supply the constant voltage required to drive pixel PXL. The power lines can be implemented on display panel 100 as long strips along the first or second direction, or as a grid of lines where the lines in the first and second directions are electrically connected.

[0075] The display area AA comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of sub-pixels positioned along a first direction X of the display panel 100. Pixels positioned in a pixel row can share a gating line GL. Sub-pixels in a column positioned along a second direction Y share the same data line DL. A horizontal time period 1H is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0076] The display panel 100 can be implemented as a non-transmissive or transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and a real object in the background is visible. The display panel 100 can be made as a flexible display panel. The screen of a foldable display can be implemented as a flexible display panel. The flexible display panel can be folded around a foldable axis spanning the display area AA. The foldable axis can exist along a first direction X in the display area AA and the gating driver 120 of the flexible display panel, but is not limited thereto.

[0077] Each pixel PXL can be divided into red, green, and blue subpixels for color implementation. Each pixel may further include a white subpixel. Each subpixel may include pixel circuitry configured to drive a light-emitting element. Each pixel circuitry may be connected to data lines, gating lines, and power lines. In the following text, "pixel" may be understood as "subpixel." Each subpixel includes pixel circuitry that drives a light-emitting element such as an OLED.

[0078] The display panel driving circuit may include a data driver 110, a gating driver 120, a timing controller 130, a power supply 140, and a level shifter 150. The driving circuit of the display panel 100 may further include a touch sensor driver. The data driver 110 and the touch sensor driver can be integrated into a single driver integrated circuit (IC). In mobile terminals or wearable terminals, the timing controller 130, power supply 140, level shifter 150, data driver 110, touch sensor driver, etc., can be integrated into a single driver IC.

[0079] The display panel driving circuit can drive the pixel PXL at a variable refresh rate (VRR) under the control of the timing controller 130. For example, the timing controller 130 can analyze the input image and reduce the refresh rate when the input image does not change within a predetermined (or preset) time, thereby reducing the power consumption of the display device. In this case, the driving circuit of the display panel 100 can, under the control of the timing controller 130, control the data write cycle of the pixel PXL to be longer by reducing the refresh rate of the pixel PXL when a still image is input for a given time or longer, thereby reducing the power consumption of the display device. The refresh rate of the display panel driving circuit can be reduced when the display device operates in standby mode or in response to a user command. In addition, the refresh rate can be reduced on an always-on display (AOD) screen. The AOD screen is a portion of the pixel area of ​​the display area AA, in which preset information, such as brief information such as remaining battery power and time, is displayed in standby mode. In one or more aspects, the refresh rate can represent the driving frequency at which the data of the pixel PXL is updated. Figure 2A and Figure 2B As shown, the display panel driving circuit can change the refresh rate for different areas within the display panel (e.g., divided pixel areas), thereby reducing power consumption without degrading image quality.

[0080] The timing controller 130 sends pixel data of the input image to the data driver 110. The timing controller 130 can synchronize the data driver 110 and the gating driver 120 based on timing signals received synchronously with the input image, and control the operating timing of each of the data driver 110 and the gating driver 120. Timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, a data enable signal DE, etc. One period of the vertical synchronization signal Vsync can be a frame period. One period of the horizontal synchronization signal Hsync and the data enable signal DE can be a horizontal period 1H. The data enable signal DE defines the effective data interval of the input image. Since the frame period and horizontal period can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0081] The gating timing control signal generated from the timing controller 130 can be input to the gating driver 120 via a level shifter 150. The level shifter 150 receives the gating timing control signal and outputs a start signal, a clock signal, and a frequency control signal. The input signal to the level shifter 150 is a signal with a digital signal voltage level, and the output signal of the level shifter 150 can be an analog voltage signal that swings between a gating high voltage and a gating low voltage. The level shifter 150 can convert a low-level voltage of the gating timing signal output from the timing controller 130 to a gating low voltage and a high-level voltage to a gating high voltage. The output signal of the level shifter 150 is input to the gating driver 120.

[0082] The timing controller 130 controls the display panel driving circuit to reduce the driving frequency of pixels PXL displaying still images by comparing pixel data between frames of the input image. In another exemplary embodiment, the host system 200 sends pixel region information indicating pixel regions with low refresh rates to the timing controller 130, and the timing controller 130 can control the display panel driving circuit to reduce the driving frequency of pixels displaying still images therein in response to the pixel region information.

[0083] The output signal of the level shifter 150 can be input to the gating driver 120 via signal line 129. Signal line 129 may include a clock line through which start and clock signals are transmitted, and a line through which frequency control signals are transmitted.

[0084] Data driver 110 can receive pixel data of an input image received as a digital signal from timing controller 130 and output a data voltage. Data driver 110 can use a digital-to-analog converter (hereinafter referred to as "DAC") to convert the image data of the input image into a gamma-compensated voltage and output the data voltage. The gamma reference voltage GMA output from power supply 140 can be divided into gamma-compensated voltages for each grayscale level by a voltage divider circuit of data driver 110 and provided to the DAC. The DAC can output a data voltage as a gamma-compensated voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC can be output to data line DL through an output buffer in each of the data output channels of data driver 110.

[0085] The gating driver 120 can be disposed on the display panel 100. The gating driver 120 can be disposed in a non-display area NA outside the display area AA of the display panel 100, or at least a portion thereof can be disposed within the display area AA. The gating driver 120 can supply a gating signal to the gating line GL using a single-feed method or a dual-feed method. In a single-feed method, the gating signal can be applied to one end of the gating line GL. In a dual-feed method, the gating signal can be applied to both ends of the gating line GL simultaneously.

[0086] The strobe driver 120 may include one or more shift registers and / or edge-triggered flip-flops. For example... Figure 3 In the pixel circuit shown, gating signals with different waveforms can be applied to pixel PXL. In this case, as... Figure 5 As shown, the gating driver 120 may include multiple gating drivers that output gating signals with different waveforms. The gating driver 120 can control each of the pixel rows L1 to LN to be a pixel row in a pixel region with a high refresh rate or a pixel row in a pixel region with a low refresh rate by changing the frequency of the gating signal applied to the gating line under the control of the timing controller 130.

[0087] Power supply 140 may include a charge pump, regulator, buck converter, boost converter, etc., but the embodiments described herein are not limited thereto. Power supply 140 may receive a DC input voltage from host system 200 and generate the power required to drive the driver of display panel 100 and display panel 100. Power supply 140 may output a constant voltage (or DC voltage) such as a gamma reference voltage, a gating high voltage, and a gating low voltage. In addition, power supply 140 may output a constant voltage to be supplied to pixel circuitry. Gamma reference voltage GMA may be supplied to data driver 110. Gating high voltage and gating low voltage may be supplied to level shifter 150 and gating driver 120. The constant voltage input to pixel circuitry may be supplied to the pixel via a power line commonly connected to pixel PXL.

[0088] Figure 2A and Figure 2B This is an exemplary view showing multiple pixel regions in which the driving frequency of pixels is independently controlled. Figure 2B In this context, FR(N) to FR(N+3) represent the time interval from frame N (where N is a natural number) to frame N+3. Figure 2B In the image, the thick vertical lines represent data update periods that vary depending on the refresh rate. Note that... Figure 2A The pixel regions A, B, and C shown are... Figure 2B The refresh rates shown are merely examples and are not limited to these examples. Figure 2A and Figure 2B .

[0089] Reference Figure 2A and Figure 2B Regarding the pixel driving frequency, the display area AA can be divided into two or more pixel areas A, B, and C. Each of pixel areas A, B, and C may include one or more pixel rows. The timing controller 130 can control the data driver 110 and the strobe driver 120 to independently control the pixel driving frequency for each pixel area. The timing controller 130 can increase the driving frequency of pixel areas that require high scan rate data updates, while decreasing the driving frequency of pixel areas where image quality degradation is not visually noticeable even when updating data at a low refresh rate. The pixel driving frequency is proportional to the refresh rate. For example, as... Figure 2A and Figure 2B As shown, the refresh rate of the first pixel region A at 120Hz is higher than that of the second pixel region B at 60Hz and the third pixel region C at 30Hz.

[0090] Figure 3 This is a circuit diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure. The pixel circuit may be a pixel circuit for a sub-pixel present in the Nth pixel row. The Nth pixel row may be operated as a skip pixel row or a refresh pixel row based on the operating conditions of the display panel or in response to one or more control signals of the display panel (e.g., rendering signals, strobe signals, and frequency control signals, which will be described in more detail later). The pixel circuit of this disclosure is not limited to... Figure 3 . Figure 4A and Figure 4B It is shown in Figure 4A The refresh period RF and shown Figure 4B The skip period SF shown is applied to Figure 3 A waveform diagram of an example of the gating signal for a pixel circuit.

[0091] Reference Figure 3 , Figure 4A and Figure 4B The pixel circuit 101 includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M01 to M07, and a capacitor Cst. Each of the first switching element M01 and the fifth switching element M05 can be implemented as an n-channel oxide TFT with low cutoff current. Cutoff current is the leakage current flowing through the semiconductor channel of the transistor in the off state. Each of the second switching element M02, the third switching element M03, the fourth switching element M04, the sixth switching element M06, and the seventh switching element M07, as well as the driving element DT, can be implemented as a p-channel LTPS TFT with high on-state current.

[0092] The driving element DT generates current based on the gate-source voltage Vgs to drive the light-emitting element EL. The driving element DT includes a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3. The light-emitting element EL can be implemented as an OLED, but is not limited thereto. The anode electrode of the light-emitting element EL is connected to a fourth node n4. A cathode voltage ELVSS is applied to the cathode electrode of the light-emitting element EL. A capacitor Cst is connected between the first constant voltage node PL1, where the pixel driving voltage ELVDD is applied, and the first node n1.

[0093] A first switching element M01 is connected between a first node n1 and a third node n3. The first switching element M01 can be turned on in response to a high-voltage (H) gate applied by a first gating signal SC1(n). When the first switching element M01 is turned on, the first node n1 is electrically connected to the third node n3. The first switching element M01 includes: a gate electrode connected to a first gating line GL1 to which the first gating signal SC1(n) is applied; a first electrode connected to the first node n1; and a second electrode connected to the third node n3.

[0094] A second switching element M02 is connected between the data line DL and the second node n2. The second switching element M02 can be turned on in response to a low-voltage (L) gate of the second strobe signal SC2(n). When the second switching element M02 is turned on, the data line DL, to which pixel data data Vdata is applied, is electrically connected to the second node n2, and the data voltage Vdata is applied to the second node n2. The second switching element M02 includes: a gate electrode connected to a second strobe line GL2 to which the second strobe signal SC2(n) is applied; a first electrode connected to the data line DL; and a second electrode connected to the second node n2.

[0095] A third switching element M03 is connected between a first constant voltage node PL1 and a second node n2 to which the pixel driving voltage ELVDD is applied. The third switching element M03 can be turned on in response to a low-voltage (L) gate of the fifth strobe signal EM(n). When the third switching element M03 is turned on, the first constant voltage node PL1 is electrically connected to the second node n2. The third switching element M03 includes: a gate electrode connected to a fifth strobe line GL5 to which the fifth strobe signal EM(n) is applied; a first electrode connected to the first constant voltage node PL1; and a second electrode connected to the second node n2.

[0096] A fourth switching element M04 is connected between the third node n3 and the fourth node n4. The fourth switching element M04 can be turned on in response to a low-voltage (L) gate of the fifth gating signal EM(n). When the fourth switching element M04 is turned on, the third node n3 is electrically connected to the fourth node n4. The fourth switching element M04 includes a gate electrode connected to the fifth gating line GL5, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0097] A fifth switching element M05 is connected between the first node n1 and the third constant voltage node PL3, to which an initialization voltage Vini is applied. The fifth switching element M05 can be turned on in response to a high-voltage (H) gate of the fourth gating signal SC4(n). When the fifth switching element M05 is on, the first node n1 is electrically connected to the third constant voltage node PL3. The fifth switching element M05 includes: a gate electrode connected to the fourth gating line GL4 to which the fourth gating signal SC4(n) is applied; a first electrode connected to the first node n1; and a second electrode connected to the third constant voltage node PL3.

[0098] A sixth switching element M06 is connected between the fourth node n4 and the fourth constant voltage node PL4 to which the anode reset voltage VAR is applied. The sixth switching element M06 can be turned on in response to a low-voltage (L) gate of the third gating signal SC3(n). When the sixth switching element M06 is turned on, the fourth node n4 is electrically connected to the fourth constant voltage node PL4, and the anode reset voltage VAR is applied to the fourth node n4. The sixth switching element M06 includes: a gate electrode connected to the third gating line GL3 to which the third gating signal SC3(n) is applied; a first electrode connected to the fourth node n4; and a second electrode connected to the fourth constant voltage node PL4.

[0099] A seventh switching element M07 is connected between the second node n2 and the fifth constant voltage node PL5, to which a conduction bias voltage VOBS is applied. The seventh switching element M07 can be turned on in response to a low-voltage (L) gate of the third gating signal SC3(n). When the seventh switching element M07 is turned on, the conduction bias voltage VOBS is applied to the second node n2. The seventh switching element M07 includes: a gate electrode connected to a third gating line GL3 to which the third gating signal SC3(n) is applied; a first electrode connected to the second node n2; and a second electrode connected to the fifth constant voltage node PL5.

[0100] A frame period in a display device may include one or more refresh periods in which pixel data is updated to pixels, and one or more frame skip periods in which pixel data is not updated to pixels. Refreshed pixel regions include pixels in which pixel data is written during a refresh period by scanning with a strobe signal synchronized with the data voltage. Skipped pixel regions include pixels in which pixel data is not written during a skip period and which maintain the previous data voltage. Figure 2A and Figure 2B In the example, the (N+1)th frame time period FR(N+1) includes a refresh period in which data voltage is charged to the pixels of the first pixel region A and the pixel data is updated, and a skip period in which the second pixel region B and the third pixel region C are driven without data updates. The (N+2)th frame time period FR(N+2) includes a refresh period in which the first pixel region A and the second pixel region B are driven, and a skip period in which the third pixel region C is driven.

[0101] Figure 4A The refresh period RF shown may include a first period P1, a second period P2, a third period P3, a fourth period P4, and a fifth period P5.

[0102] During the first time period P1, the first switching element M01, the sixth switching element M06, and the seventh switching element M07 are turned on. When the conduction bias voltage VOBS is applied to the second node n2 during the first time period P1, the drive element DT is turned on, and the conduction bias voltage VOBS is applied to the first node n1 and the second node n2 through the drive element DT and the first switching element M01. Simultaneously, during the first time period P1, the anode reset voltage VAR is applied to the fourth node n4.

[0103] During the second time period P2, the first switching element M01 and the fifth switching element M05 are turned on. At the end of the second time period P2, the threshold voltage of the driving element DT is sampled into the capacitor Cst.

[0104] During the third time period P3, the first switching element M01 and the second switching element M02 are turned on. Here, the data voltage Vdata is applied to the gate electrode of the driving element DT and the capacitor Cst through the second node n2 and the third node n3, and the data voltage Vdata compensated by the threshold voltage of the driving element DT is stored in the capacitor Cst. During the fourth time period P4, the sixth switching element M06 and the seventh switching element M07 are turned on. In the fourth time period P4, the on-bias voltage VOBS is applied to the second node n2, and simultaneously, the anode reset voltage VAR is applied to the fourth node n4. During the fifth time period P5, the third switching element M03 and the fourth switching element M04 are turned on, and the light-emitting element EL is driven by the current from the driving element DT, and the light-emitting element EL can emit light with a brightness corresponding to the gray level value of the pixel data.

[0105] Figure 4B The skip period SF shown includes periods P1 and P4 in which the conduction bias voltage and anode reset voltage are applied to the pixel circuit, and a light-emitting period P5 in which the light-emitting element EL emits light. The data driver 110 stops driving and does not output a data voltage during the skip period. During the skip period, a pulse of the second strobe signal SC2(n) can be applied, but since the data voltage Vdata is not output from the data driver 110, it is not applied to the pixel circuit. The driving element DT of the pixel circuit can drive the light-emitting element EL by generating current using the voltage of the capacitor Cst charged with the data voltage Vdata from the previous refresh period.

[0106] As described above, the first gating signal SC1(n) and the fourth gating signal SC4(n) control the switching elements M01 and M05 connected to the capacitor Cst. In one or more examples, during the skip period, the first gating signal SC1(n) and the fourth gating signal SC4(n) must maintain the gating cutoff voltage, i.e., the gating low voltage (L), so that the voltage of the capacitor Cst does not change.

[0107] In one or more aspects, the strobe signals SC1(n) to SC4(n) may be referred to as SC1 to SC4, respectively.

[0108] Figure 5 This shows the drive. Figure 3 A view of an example of a gating driver for a pixel circuit. Figure 5 In this context, "GIP" refers to the gating drive circuit area that exists in the non-display area.

[0109] Reference Figure 1 , Figure 3 and Figure 5The gating driver 120 may include a first gating driver 121 that sequentially outputs pulses of a first gating signal SC1, a second gating driver 122 that sequentially outputs pulses of a second gating signal SC2, a third gating driver 123 that sequentially outputs pulses of a third gating signal SC3, a fourth gating driver 124 that sequentially outputs pulses of a fourth gating signal SC4, and a fifth gating driver 125 that sequentially outputs pulses of a fifth gating signal EM. The second gating driver 122 may be implemented as a shift register, and the other gating drivers 121, 123, 124, and 125 may be implemented as edge-triggered flip-flops, but are not limited thereto.

[0110] Each of the strobe drivers 121 to 125 can receive a start signal and a clock signal with a phase i (i is a natural number of 2 or greater) having a different phase. The pulse and phase of the strobe signal can be controlled according to the pulses of the start signal and the clock signal.

[0111] The gating driver 120 further includes a rendering signal generator 126 and output controllers 121C and 124C to change the driving frequency of pixels according to the refresh rate. The rendering signal generator 126 can be implemented as a shift register. The output controllers 121C and 124C include an output controller 121C connected to the output node of the first gating driver 121, and an output controller 124C connected to the output node of the fourth gating driver 124.

[0112] Figure 6 This is a view illustrating an example configuration of a gating driver capable of changing the driving frequency of pixels according to the refresh rate. Each of the first gating driver 121 and the fourth gating driver 124 can be configured as follows: Figure 6 The shown diagram shows a gating driver. Reference numeral "1211" indicates a line to which a clock signal is applied, and "1212" indicates a line to which a frequency control signal FD is applied. Figure 6 In the diagram, L(N) to L(N+4) represent the Nth pixel row to the (N+4)th pixel row.

[0113] Reference Figure 6 Each of the first gating driver 121 and the fourth gating driver 124 includes a rendering signal generator RSS, a gating signal output circuit OSS, and an output controller CS. The rendering signal generator RSS and... Figure 5 The rendering signal generator 126 shown is the same, and the output controller CS is the same as... Figure 5 The output controllers 121C and 124C shown are identical. The strobe signal output circuit OSS can be... Figure 5 The first strobe driver 121 or the fourth strobe driver 124 shown.

[0114] The rendering signal generator RSS includes multiple signal transmission stages 510(N) to 510(N+4) connected dependently via clock line 1211 and carry signal line. The rendering signal generator RSS receives a start signal RVST and clock signals RCLK1 to RCLK4, and sequentially outputs pulses of rendering signals RS(N) to RS(N+4). The rendering signal generator 126 can be implemented as follows: Figure 7 The shift registers shown are not limited to these. Each of the signal transmission stages 510(N) to 510(N+4) includes a VST node, clock nodes CLK(N-1), CLK(N), and CLK(N+2), and an output node OUT. The start signal RVST or carry signal CAR is input to the VST node, and the corresponding clock signals among the clock signals RCLK1 to RCLK4 are input to the clock nodes CLK(N-1), CLK(N), and CLK(N+2). The render signal RS is output from the output node OUT. The start signal RVST is input to the first signal transmission stage. Figure 7 In the example, the Nth signal transmission stage 510(N) can be the first signal transmission stage to which the start signal RVST is input, but is not limited to this. In the render signal generator RSS, the carry signal input to the VST node of the next signal transmission stage is the render signal RS output from the previous signal transmission stage.

[0115] The strobe signal output circuit OSS includes multiple signal transmission stages 520(N) to 520(N+4) connected dependently via clock line 1211 and carry signal lines. The strobe signal output circuit OSS receives a start signal GVST and clock signals GCLK1 and GCLK2, and sequentially outputs strobe signals. The strobe signal output circuit OSS can be implemented as follows: Figure 7 The edge-triggered triggers shown are not limited to these. Each of the signal transmission stages 520(N) to 520(N+4) includes a VST node, a clock node CLK(N), and an output node OUT. A start signal GVST or a carry signal CAR is input to the VST node, a clock signal GCLK1 or a clock signal GCLK2 is input to the clock node CLK(N), and a strobe signal is output from the output node OUT. The start signal GVST is input to the first signal transmission stage. Figure 7 In the example, the Nth signal transmission stage 520(N) can be the first signal transmission stage to which the start signal GVST is input, but is not limited thereto. In the strobe output circuit OSS, the carry signal input to the VST node of the next signal transmission stage is a strobe signal output from the previous signal transmission stage (e.g., from the output node OUT of the previous signal transmission stage).

[0116] The output controller CS includes multiple controllers 530(N) to 530(N+4) connected to the output nodes OUT of the corresponding signal transmission stages 520(N) to 520(N+4). Each of the controllers 530(N) to 530(N+4) receives: a rendering signal (one of RS(N) to RS(N+4)) input from the corresponding signal transmission stage (one of 510(N) to 510(N+4)) of the rendering signal generator RSS; a gating signal input from the corresponding signal transmission stage (one of 520(N) to 520(N+4)) of the gating signal output circuit OSS; and a frequency control signal FD.

[0117] Each of controllers 530(N) to 530(N+4) outputs a final gating signal. The final gating signal is output as a pulse of the gating signal or as a gating low voltage VEL, depending on the variable refresh rate or the drive frequency of the pixel PXL. The gating low voltage VEL can be equal to... Figure 3 The turn-on low voltage of the first switching element M01 and the fifth switching element M05 of the cut-off pixel circuit shown.

[0118] Each of the controllers 530(N) to 530(N+4) of the output controller CS shares the output node OUT of the corresponding signal transmission stage 520(N) to 520(N+4) to receive the strobe signal as a carry signal CAR, and shares the control node T6Q of the corresponding signal transmission stage (one of 520(N) to 520(N+4)). Each of the controllers 530(N) to 530(N+4) includes a node OS with a strobe low voltage VEL applied, a node with a frequency control signal FD applied, and an output node OUT from which the final strobe signal is output.

[0119] Figure 7 It is shown in detail Figure 6 The circuit diagram shown is an example of a strobe driver. Figure 7 In this context, VGL and VEL are low-gating voltages and can be understood as the gating cutoff voltages or first gating voltages for the first switching element M01 and the fifth switching element M05 in the pixel circuit. VGH and VEH are high-gating voltages and can be understood as the gating on voltages or second gating voltages for the first switching element M01 and the fifth switching element M05 in the pixel circuit.

[0120] Reference Figure 7Each of the signal transmission stages 510(N) and 510(N+1) of the rendering signal generator RSS includes a first-first control node (hereinafter referred to as the "Q01 node"), a first-second control node (hereinafter referred to as the "Q02 node"), a second control node (hereinafter referred to as the "QB01 node"), and a plurality of transistors T01 to T08. Each of transistors T01 to T08 may be implemented as a p-channel LTPS TFT, but is not limited thereto.

[0121] Signal transmission stages 510(N) and 510(N+1) can be implemented using essentially the same circuitry. The Nth signal transmission stage 510(N) receives the start signal RVST and clock signals RCLK(N-1), RCLK(N), and RCLK(N+2), and outputs a pulse of the first rendering signal RS1. The pulse of the first rendering signal RS1 is input to the Nth controller 530(N) of the output controller CS, and simultaneously input as a carry signal to the (N+1)th signal transmission stage 510(N+1). The (N+1)th signal transmission stage 510(N+1) receives the carry signal RS1 and clock signals RCLK(N), RCLK(N+1), and RCLK(N+3) from the Nth signal transmission stage 510(N), and outputs a pulse of the second rendering signal RS2. The pulse of the second rendering signal RS2 is input to the (N+1)th controller 530 (N+1) of the output controller CS, and simultaneously input as a carry signal to the (N+2)th signal transmission stage 510 (N+2). For simplicity, the (N+2)th signal transmission stage 510 (N+2) is not shown in the diagram. Figure 7 As shown in the figure, the Nth signal transmission stage 510(N) and the (N+1)th signal transmission stage 510(N+1) can be understood as the first signal transmission stage and the second signal transmission stage, respectively.

[0122] In the following text, the circuit configurations of signal transmission stages 510(N) and 510(N+1) will be described primarily with reference to the Nth signal transmission stage 510(N).

[0123] A first transistor T01 is connected between nodes VST 71 and Q02 and can be turned on in response to a clock signal RCLK(N-1) input to a first clock node 72 to electrically connect VST node 71 to node Q02. The first transistor T01 includes a gate electrode connected to the first clock node 72, a first electrode connected to VST node 71, and a second electrode connected to node Q02. A second transistor T02 can be turned on in response to a voltage at node QB01 to electrically connect node VGH 76, to node Q02, to which a gate high voltage is applied. The second transistor T02 includes a gate electrode connected to node QB01, a first electrode connected to node Q02, and a second electrode connected to node VGH 76.

[0124] A third transistor T03 is connected between node VGL 74, to which a gate low voltage is applied, and node QB01. It is turned on in response to a clock signal RCLK(N+2) input to the second clock node 73, electrically connecting node VGL 74 to node QB01. The third transistor T03 includes a gate electrode connected to the second clock node 73, a first electrode connected to node VGL 74, and a second electrode connected to node QB01. A fourth transistor T04 is connected between node QB01 and node VGH 76, and is turned on in response to a voltage at node VST 71, electrically connecting node QB01 to node VGH 76. The fourth transistor T04 includes a gate electrode connected to node VST 71, a first electrode connected to node QB01, and a second electrode connected to node VGH 76. A fifth transistor T05 is connected between node QB01 and node VGH 76, and is turned on in response to a voltage at node Q02, electrically connecting node QB01 to node VGH 76. The fifth transistor T05 includes a gate electrode connected to node Q02, a first electrode connected to node QB01, and a second electrode connected to node VGH76.

[0125] A sixth transistor T06 is connected between the third clock node 75 and the output node 77, and can be turned on in response to the voltage of node Q01 to electrically connect the third clock node 75 to the output node 77. The sixth transistor T06 can be understood as a pull-up transistor. The sixth transistor T06 includes a gate electrode connected to node Q01, a first electrode connected to the third clock node 75, and a second electrode connected to the output node 77. A capacitor CQ1 is connected between node Q01 and the output node 77. When the voltage of the third clock node 75 rises, capacitor CQ1, through capacitive coupling between the output node 77 and node Q01, bootstraps the voltage of node Q01.

[0126] The seventh transistor T07 is connected between the output node 77 and the VGH node 76 and is turned on in response to the voltage at the QB01 node. The seventh transistor T07 can be understood as a pull-down transistor. The seventh transistor T07 includes a gate electrode connected to the QB01 node, a first electrode connected to the output node 77, and a second electrode connected to the VGH node 76. A capacitor CQB1 is connected between the QB01 node and the VGH node 76 to reduce the gate-source voltage variation of the seventh transistor T07.

[0127] The eighth transistor T08 is connected between nodes Q01 and Q02, and electrically isolates nodes Q01 and Q02 when node Q01 is bootstrapping to reduce stress on the first transistor T01. The eighth transistor T08 includes a gate electrode connected to node VGL 74, a first electrode connected to node Q02, and a second electrode connected to node Q01.

[0128] Each of the signal transmission stages 520(N) and 520(N+1) of the OSS gating signal output circuit includes a first-first control node (hereinafter referred to as the "T6Q node"), a first-second control node (hereinafter referred to as the "Q2 node"), a second control node (hereinafter referred to as the "QB node"), and a plurality of transistors T1 to T7. Each of transistors T1 to T7 may be implemented as a p-channel LTPS TFT, but is not limited thereto.

[0129] Signal transmission stages 520(N) and 520(N+1) can be implemented using essentially the same circuitry. The Nth signal transmission stage 520(N) receives a start signal GVST and a clock signal GCLK1, and outputs a pulse of the first strobe signal to the first output node 85. The first output node 85 is shared by the Nth signal transmission stage 520(N) and the Nth controller 530(N). The pulse of the first strobe signal is input to the Nth controller 530(N) and simultaneously input as a carry signal CAR to the (N+1)th signal transmission stage 520(N+1). The (N+1)th signal transmission stage 520(N+1) receives the carry signal CAR and the clock signal GCLK2 from the Nth signal transmission stage 520(N), and outputs a pulse of the first strobe signal to the first output node. The first output node of the (N+1)th signal transmission stage 520(N+1) is shared by the (N+1)th controller 530(N+1). The pulse of the second strobe signal is input to the (N+1)th controller 530 (N+1), and simultaneously input as a carry signal CAR to the (N+2)th signal transmission stage 520 (N+2). For simplicity, the (N+2)th signal transmission stage 520 (N+2) is not shown in the diagram. Figure 7 As shown in the figure, the Nth signal transmission stage 520(N) and the (N+1)th signal transmission stage 520(N+1) can be understood as the first signal transmission stage and the second signal transmission stage, respectively.

[0130] In the following text, the circuit configurations of signal transmission stages 520(N) and 520(N+1) will be described primarily with reference to the Nth signal transmission stage 520(N).

[0131] A first transistor T1 is connected between VST node 81 and Q2 node, and can be turned on in response to a clock signal GCLK1 input to clock node 88 connected to clock line 1211, to electrically connect VST node 81 to Q2 node. The first transistor T1 includes a gate electrode connected to clock node 88, a first electrode connected to VST node 81, and a second electrode connected to Q2 node. A second transistor T2 can be turned on in response to a start signal GVST, to electrically connect buffer node 87 to VEH node 82, to which a gate high voltage is applied. The second transistor T2 includes a gate electrode connected to VST node 81, a first electrode connected to buffer node 87, and a second electrode connected to VEH node 82. A capacitor CON is connected between buffer node 87 and clock node 88.

[0132] The third transistor T3 is connected between the clock node 88 and the QB node, and can be turned on in response to the voltage of the buffer node 87 to electrically connect the clock node 88 to the QB node. The third transistor T3 includes a gate electrode connected to the buffer node 87, a first electrode connected to the clock node 88, and a second electrode connected to the QB node. The third transistor T3 may consist of two transistors connected in series between the clock node 88 and the QB node, but is not limited thereto.

[0133] A fourth transistor T4 is connected between the QB node and the VEH node 82 to which a high gate voltage is applied, and can be turned on in response to the voltage of the Q2 node to electrically connect the QB node to the VEH node 82. The fourth transistor T4 includes a gate electrode connected to the Q2 node, a first electrode connected to the QB node, and a second electrode connected to the VEH node 82. A fifth transistor T5 is connected between the T6Q node and the Q2 node, and is turned on when the voltage of the Q2 node rises, and electrically isolates the T6Q node and the Q2 node when the T6Q node is bootstrapping. The fifth transistor T5 includes a gate electrode connected to the VEL node 84 to which a low gate voltage is applied, a first electrode connected to the Q2 node, and a second electrode connected to the T6Q node.

[0134] The sixth-first transistor T6C is connected between VEL node 84 and the first output node 85, and can be turned on in response to the voltage of node T6Q to electrically connect VEL node 84 to the first output node 85. The sixth-first transistor T6C can be understood as a first pull-up transistor. The sixth-first transistor T6C includes a gate electrode connected to node T6Q, a first electrode connected to VEL node 84, and a second electrode connected to the first output node 85. A capacitor CQ2 is connected between node T6Q and the first output node 85.

[0135] A seventh transistor T7 is connected between the first output node 85 and the VEH node 82, and is turned on in response to the voltage at the QB node. The seventh transistor T7 can be understood as a pull-down transistor. The seventh transistor T7 includes a gate electrode connected to the QB node, a first electrode connected to the first output node 85, and a second electrode connected to the VEH node 82. A capacitor CQB2 is connected between the QB node and the VEH node 82.

[0136] Each of the controllers 530(N) and 530(N+1) in the output controller CS includes a sixth-second transistor T60, an eighth transistor T8, a ninth transistor T9, and a capacitor Cf. Each of transistors T60, T8, and T9 can be implemented as a p-channel LTPS TFT, but is not limited thereto. Each of the sixth-second transistor T60, the eighth transistor T8, and the ninth transistor T9 can be understood as a control transistor.

[0137] Controllers 530(N) and 530(N+1) can be implemented using essentially the same circuitry. The Nth controller 530(N) samples the voltage of the frequency control signal FD in response to a pulse of the first rendering signal RS1 and stores it in capacitor Cf. The (N+1)th controller 530(N+1) samples the voltage of the frequency control signal FD in response to a pulse of the second rendering signal RS2 generated following the pulse of the first rendering signal RS1 and stores it in capacitor Cf. The capacitance of capacitor Cf can be equal to or similar to the capacitance of capacitor Cst disposed in the pixel circuitry.

[0138] Controllers 530(N) and 530(N+1) are connected to signal transmission stages 520(N) and 520(N+1) in a one-to-one (1:1) manner. The Nth controller 530(N) is connected to the Nth signal transmission stage 520(N), receives the Nth strobe signal from the Nth signal transmission stage 520(N), and shares the T6Q node with the Nth signal transmission stage 520(N). The (N+1)th controller 530(N+1) is connected to the (N+1)th signal transmission stage 520(N+1), receives the (N+1)th strobe signal from the (N+1)th signal transmission stage 520(N+1), and shares the T6Q node with the (N+1)th signal transmission stage 520(N+1).

[0139] Each of controllers 530(N) and 530(N+1) can control the first voltage of the frequency control signal FD stored in capacitor Cf, and output the pulses of the gating signals input from signal transmission stages 520(N) and 520(N+1) as final gating signals SRO1 and SRO2 to the second output node 86. Each of controllers 530(N) and 530(N+1) can control the second voltage of the frequency control signal FD stored in capacitor Cf, and block the pulses of the gating signals input from signal transmission stages 520(N) and 520(N+1), and supply a gating low voltage VEL to the second output node 86, or maintain the voltage of the second output node 86 at the gating low voltage VEL. The second output node 86 can be connected to... Figure 3 The first gating line GL1 or the fourth gating line GL4 are shown. The first voltage of the frequency control signal FD can be a low gating voltage, and the second voltage of the frequency control signal FD can be a high gating voltage, but is not limited thereto. The Nth controller 530(N) and the (N+1)th controller 530(N+1) can be understood as the first controller and the second controller, respectively.

[0140] The sixth-second transistor T6O is connected between VEL node 84 and the second output node 86, and can be turned on in response to the voltage of node T6Q to electrically connect VEL node 84 to the second output node 86. The sixth-second transistor T6O can be understood as a second pull-up transistor. The sixth-second transistor T6O includes a gate electrode connected to node T6Q, a first electrode connected to VEL node 84, and a second electrode connected to the second output node 86.

[0141] The eighth transistor T8 is connected between node 83, which is connected to capacitor Cf, and line 1212, to which the frequency control signal FD is applied, and is turned on in response to rendering signals RS1 (for controller 530(N)) or RS2 (for controller 530(N+1)). The eighth transistor T8 includes a gate electrode connected to the output node 77 of the rendering signal generator RSS (to which rendering signals RS1 (for controller 530(N)) or RS2 (for controller 530(N+1)) are applied), a first electrode connected to capacitor Cf, and a second electrode to which the frequency control signal FD is applied. One electrode of capacitor Cf is connected to node 83, and the other electrode is connected to a ground voltage source or a separate reference voltage source.

[0142] The ninth transistor T9 is connected between the first output node 85 and the second output node 86, and is turned on in response to the voltage of the capacitor Cf. The ninth transistor T9 includes a gate electrode connected to the capacitor Cf, a first electrode connected to the first output node 85, and a second electrode connected to the second output node 86.

[0143] Notice, Figure 7 The clock signals RCLK(N-1), RCLK(N), and RCLK(N+2) can respectively correspond to Figure 6 The clock signals are input to clock nodes CLK(N-1), CLK(N), and CLK(N+2). Figure 7 The first rendering signal RS1 and the second rendering signal RS2 can respectively correspond to Figure 6 The rendering signals RS(N) and RS(N+1). Figure 7 The clock node 88 of the signal transmission stage 520(N) can correspond to Figure 6 The clock node CLK(N) of the signal transmission stage 520(N).

[0144] Figures 8A to 13B It is shown Figure 7 The image shows an exemplary view of the operation of the output controller. Figure 8B , Figure 9B , Figure 10B and Figure 11B In the circuit, GVST, GCLK1, and GCLK2 are the start and clock signals input to the signal transmission stages 520(N) and 520(N+1) of the strobe signal output circuit OSS. SRO1 to SRO4 are the final strobe signals output under the control of controllers 530(N) and 530(N+1). The final strobe signal can correspond to... Figure 3 The first strobe signal SC1 or the fourth strobe signal SC4. RVST and RCLK1 to RCLK4 are the start and clock signals input to the signal transmission stages 510(N) and 510(N+1) of the render signal generator RSS. RS1 to RS4 are the render signals sequentially output from the signal transmission stages 510(N) and 510(N+1) of the render signal generator RSS. Figure 8B , Figure 9B , Figure 10B and Figure 11B In this code, "L" selects the low voltage and "H" selects the high voltage. The low voltage selection L and... Figure 7 The low-gating voltages VGL and VEL shown are essentially the same voltage. The high-gating voltage H is... Figure 7 The high-voltage gates VGH and VEH shown are essentially the same voltage.

[0145] Figures 8A to 11BThe illustrated implementation is an example where the Nth controller 530(N) controls the voltages of the gating signals SC1 and SC4 applied to pixels in skipped pixel rows, while the (N+1)th controller 530(N+1) controls the voltages of the gating signals SC1 and SC4 applied to pixels in refreshed pixel rows. According to the frequency control signal FD, the Nth controller 530(N) can control pixels in refreshed pixel rows, while the (N+1)th controller 530(N+1) can control pixels in skipped pixel rows. Refreshed pixel rows include pixels that update data using the data voltage Vdata of the charging pixel data. Skipped pixel rows include pixels that do not update data by maintaining the first gating signal SC1 and the fourth gating signal SC4 at the gating cutoff voltage (i.e., the gating low voltage L).

[0146] Reference Figure 8A and Figure 8B At time t1, the low gate voltage L of the first rendering signal RS1 is applied to the gate electrode of the eighth transistor T8, and simultaneously, the high gate voltage H of the frequency control signal FD is applied to the eighth transistor T8. As a result, when the eighth transistor T8 of the Nth controller 530(N) is turned on at time t1, the high gate voltage H of the frequency control signal FD is charged into the capacitor Cf. At time t1, since no rendering signal equal to or lower than the second rendering signal RS2 is generated, the (N+1)th controller 530(N+1) with the second rendering signal RS2 applied maintains its previous state.

[0147] Reference Figure 9A and Figure 9B At time t2, the low gate voltage L of the second rendering signal RS2 is applied to the gate electrode of the eighth transistor T8, and simultaneously, the low gate voltage L of the frequency control signal FD is applied to the eighth transistor T8. As a result, when the eighth transistor T8 of the (N+1)th controller 530 (N+1) is turned on at time t2, the low gate voltage H of the frequency control signal FD is charged into the capacitor Cf. At time t2, since the first rendering signal RS1 is at the high gate voltage H, the capacitor voltage of the Nth controller 530 (N) is maintained at the high gate voltage H.

[0148] Reference Figures 10A to 11B At times t3 and t4, rendering signals RS1 to RS4 are maintained at the high gate voltage, and the eighth transistor T8 of controllers 530(N) and 530(N+1) is in the off state. At time t3, the voltage charging in capacitor Cf of the Nth controller 530(N) is the high gate voltage H. At time t4, the voltage charging in capacitor Cf of the (N+1)th controller 530(N+1) is the low gate voltage L.

[0149] At time point t3, such as Figure 10AAs shown, the pulse of the gating signal output from the Nth signal transmission stage 520(N) is blocked by the ninth transistor T9, which is turned off by the gating high voltage H charged in the capacitor Cf of the Nth controller 530(N). Here, the gating signal SRO1 output from the Nth controller 530(N) is maintained at the gating low voltage L and is applied to the pixels skipping the pixel row.

[0150] At time t4, such as Figure 11A As shown, the pulse of the gating signal output from the (N+1)th signal transmission stage 520 (N+1) is output as gating signal SRO2 through the ninth transistor T9, which is turned on by the gating low voltage L charged in the capacitor Cf of the (N+1)th controller 530 (N+1). Here, the pulse of the gating signal SRO2 output from the (N+1)th controller 530 (N+1) is applied to the pixels of the refresh pixel row.

[0151] Figure 12A and Figure 12B yes Figure 7 The circuit diagram shown is a portion of the strobe driver used to apply strobe signals to the pixels of a refresh pixel row.

[0152] Reference Figure 12A When the VST node voltage of signal transmission stage 520(N) changes from gating low voltage to gating high voltage, the voltage of node T6Q rises, and the sixth-first transistor T6C and the sixth-second transistor T6O are turned off. Here, the voltage of gating signal SRO1 can be increased from gating low voltage L to gating high voltage H by the gating high voltage VEH output via the seventh transistor T7 and the ninth transistor T9.

[0153] Reference Figure 12B When the VST node voltage of signal transmission stage 520(N) changes from gating high voltage to gating low voltage, the voltage of T6Q drops, and the sixth-first transistor T6C and the sixth-second transistor T6O turn on. Here, the voltage of the gating signal SRO1 is reduced from the gating high voltage H to the gating low voltage L by the gating low voltage VEL output via the sixth-first transistor T6C and the sixth-second transistor T6O.

[0154] In a structure where the sixth-first transistor T6C and the sixth-second transistor T6O share the T6Q node, if the sixth-second transistor T6O is absent, the low voltage L of the gating signal SRO may rise to VEL+a. Here, a is the threshold voltage of each of the eighth transistor T8 and the ninth transistor T9. In this case, the transistors in the pixel circuit controlled by the gating signal SRO (e.g., Figure 3Leakage current may occur in the first transistor M01 or the fifth transistor M05 shown, or the pixel circuit may not be able to drive properly because it is not turned off.

[0155] When the voltage at node T6Q changes from gate high to gate low, it is boosted to a voltage below VEL through the bootstrapping of capacitor CQ2. The sixth-second transistor T6O is quickly turned on by the gate low voltage at node T6Q, exhibiting low on-resistance, and its rise in gate low voltage L is prevented or reduced when the pulse of the gate signal SRO1 decreases from gate high voltage H to gate low voltage L.

[0156] Figure 13A and Figure 13B yes Figure 7 The circuit diagram shown is a portion of the strobe driver used to apply a strobe signal to the pixels in the skip pixel row.

[0157] Reference Figure 13A and Figure 13B When the voltage charging in capacitor Cf of controller 530(N) is the high gate voltage, the ninth transistor T9 is in the off state. Here, the pulse of the gate signal applied to the first output node 85 is blocked by the ninth transistor T9, which is in the off state, and the low gate voltage VEL is applied to the second output node 86 through the conducting sixth-second transistor T6O, and the voltage of the gate signal SRO can be maintained at the low gate voltage VEL.

[0158] Figure 14 This is a cross-sectional view showing the cross-sectional structure of a display panel according to an exemplary embodiment of the present disclosure.

[0159] Reference Figure 14 The cross-sectional structure of the display panel 100 may include a circuit layer POT, a package layer POC, a touch sensor layer TOE, a color filter layer COE, etc.

[0160] The circuit layer POT can have a structure in which light-emitting elements are disposed on the pixel circuitry and a gating driver is disposed on the substrate. The substrate of the display panel 100 can be manufactured in a structure in which a first polyimide (hereinafter referred to as "PI") substrate PI1, an inorganic layer IPD, and a second PI substrate PI2 are stacked, but is not limited thereto. The inorganic layer IPD blocks moisture penetration.

[0161] The circuit layer POT can be divided into a pixel circuit layer and a light-emitting element layer. The pixel circuit layer includes a first insulating layer BUF1, a first metal layer BSM disposed on the first insulating layer BUF1, a second insulating layer BUF2 covering the first metal layer BSM and the first insulating layer BUF1, a first semiconductor layer ACT1 disposed on the second insulating layer BUF2, a third insulating layer GI1 covering the first semiconductor layer ACT1 and the second insulating layer BUF2, a second metal layer GAT1 disposed on the third insulating layer GI1, a fourth insulating layer ILD1 covering the second metal layer GAT1 and the third insulating layer GI1, a third metal layer GAT2 disposed on the fourth insulating layer ILD1, a fifth insulating layer BUF3 covering the third metal layer GAT2 and the fourth insulating layer ILD1, a fourth metal layer LOGAT disposed on the fifth insulating layer BUF3, and a fourth metal layer LOGAT disposed on the fifth insulating layer BUF3. The structure includes: a sixth insulating layer BUF4 (part of the fifth insulating layer BUF3), a second semiconductor layer ACT2 disposed on the sixth insulating layer BUF4, a seventh insulating layer GI2 covering the second semiconductor layer ACT2 and the sixth insulating layer BUF4, a fifth metal layer OGA disposed on the seventh insulating layer GI2, an eighth insulating layer ILD2 covering the fifth metal layer OGA and the seventh insulating layer GI2, a sixth metal layer SD1 disposed on the eighth insulating layer ILD2, a ninth insulating layer PLN1 covering the sixth metal layer SD1 and the eighth insulating layer ILD2, a seventh metal layer SD2 disposed on the ninth insulating layer PLN1, a tenth insulating layer PLN2 covering the seventh metal layer SD2 and the ninth insulating layer PLN1, and an eleventh insulating layer PLN3 covering the tenth insulating layer PLN2. The first to eighth insulating layers BUF1 to ILD2 can be inorganic layers. The ninth to eleventh insulating layers PLN1, PLN2, and PLN3 can be organic layers.

[0162] The metal layer of the circuit layer POT can be used as electrodes for transistors and wires connected to the transistors. The first transistor TR1, the second transistor TR2, the third transistor TR3, and the capacitor Cst can be components of the pixel circuit disposed in the display area AA. The fourth transistor TR4 and the capacitor Cf can be components of the gating drive circuit area GIP disposed in the non-display area NA. Although in Figure 14Transistors, omitted in the text but having substantially the same structure as the second transistor TR2 and / or the third transistor TR3, can be disposed in the gated drive circuit region GIP. The first semiconductor layer ACT1 may include a polysilicon semiconductor layer. The second semiconductor layer may include an oxide semiconductor layer. The first transistor TR1 may be a transistor implemented as an LTPS TFT in the pixel circuit. The second transistor TR2 and the third transistor TR3 may be transistors implemented as oxide TFTs in the pixel circuit. A metal pattern formed by a selected metal layer may be disposed beneath the semiconductor layers ACT1 and ACT2 of the transistors. The thickness of the insulating layer between the semiconductor layers ACT1 and ACT2 and the metal pattern can be appropriately selected.

[0163] The light-emitting element layer includes an anode AND connected to the first transistor TR1 through contact holes passing through insulating layers PLN2 and PLN3, a cathode CAT connected to a power line VSS to which a cathode voltage ELVSS is applied, a light-emitting layer disposed between the anode AND and the cathode CAT, a black dam BBNK separating sub-pixels, a transparent dam BNK, etc. The anode AND can be disposed in a light-emitting region separated below the dams BBNK and BNK and defined by the dams BBNK and BNK. The surface of the black dam BBNK can be recessed, and trenches can be formed at the boundaries of adjacent sub-pixels. The trenches can extend the current path between adjacent sub-pixels in the lateral direction in the light-emitting element layer, thereby reducing leakage current flowing in the lateral direction.

[0164] The encapsulation layer POC covers the circuit layer POT. The encapsulation layer POC can be a multi-insulating film structure in which an organic film PCL and inorganic films EPAS1 and EPAS2 are stacked. The inorganic films EPAS1 and EPAS2 block moisture penetration. The organic film PCL flattens the surface of the encapsulation layer POC. The barrier layer DAM can be disposed on the outermost side of the display panel 100. The barrier layer DAM has a thick structure in which organic films PLN1 and PLN2 are stacked. The barrier layer DAM can extend the moisture penetration path and suppress the phenomenon of organic film flowing to the outermost side of the display panel 100 when the organic film of the encapsulation layer POC is applied.

[0165] The touch sensor layer TOE covers the packaging layer POC. The touch sensor layer TOE includes a touch sensor TS disposed on the display area AA. The touch sensor TS can be an electrostatic capacitive touch sensor that senses touch input based on the change in capacitance before and after touch input. The touch sensor layer TOE may include a metal layer serving as electrodes for the touch sensor, an organic film TILD, and inorganic insulating films SBUF1, SBUF2, and CBUF.

[0166] The color filter layer COE covers the touch sensor layer TOE. The color filter layer COE includes color filters R / G / B, a black matrix BM, and an organic film OC covering the color filters R / G / B and the black matrix BM. The color filter layer COE improves the color reproduction of pixels and reduces the transmittance of light reflected by the metal of the touch sensor layer TOE and the circuit layer POT, thereby improving visibility and contrast. The organic film OC protects the color filters R / G / B and the black matrix BM and flattens the surface of the color filter layer COE. The black matrix BM can be placed at the boundaries of adjacent sub-pixels to reduce optical crosstalk between adjacent sub-pixels. The black matrix BM can be placed in the gating drive circuit area GIP of the non-display area NA and covers the underlying circuit elements.

[0167] In one or more examples, unless otherwise explicitly stated, an element may refer to a device or circuit. In one example, a light-emitting element may refer to a light-emitting device. In one example, a driving element may refer to a driving circuit. In one example, a switching element may refer to a switching circuit.

[0168] According to one or more embodiments of this disclosure, the display device may be included in or applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop computers, netbook computers, workstations, navigators, vehicle navigators, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, video cameras, and home appliances, etc. Furthermore, the display device according to one or more embodiments of this disclosure may be included in or applied to organic light-emitting devices or inorganic light-emitting devices.

[0169] The purpose of this disclosure, the means to achieve the purpose, and the effects of this disclosure do not specify the essential features of the claims; therefore, the scope of the claims is not limited to the content of this disclosure.

[0170] Although one or more exemplary embodiments of this disclosure have been described in more detail with reference to the accompanying drawings, this disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of this disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and do not limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and not limiting of this disclosure. Therefore, this disclosure covers modifications and variations of this disclosure, provided they fall within the scope of the claims or their equivalents.

[0171] Cross-references to related applications

[0172] This application claims priority to Korean Patent Application No. 10-2025-0056428, filed on April 29, 2025, the entire contents of which are incorporated herein by reference for all purposes.

Claims

1. A display panel, the display panel comprising: The display area includes multiple data lines, multiple gating lines, multiple power lines, and multiple sub-pixels. as well as A gating driver, the gating driver being connected to the plurality of gating lines. The gating driver includes: A rendering signal generator configured to sequentially output rendering signals; A gating signal output circuit, the gating signal output circuit being configured to sequentially output gating signals; and An output controller is configured to receive the rendering signal, the gating signal, and a frequency control signal to output a pulse of the gating signal to a corresponding gating line or to maintain the voltage of the corresponding gating line at a first gating voltage.

2. The display panel according to claim 1, wherein, The gating signal output circuit includes: Multiple signal transmission stages are connected to one or more clock lines, one or more clock signals are applied to the clock lines, the multiple signal transmission stages are sequentially connected via carry signal lines that propagate carry signals from the previous stage to the next stage, and each of the multiple signal transmission stages is configured to output a corresponding strobe signal to a corresponding first output node. The output controller includes: Multiple controllers, each connected to a corresponding signal transmission stage among the multiple signal transmission stages of the gating signal output circuit, each controller is configured to receive the corresponding gating signal from the corresponding signal transmission stage, each controller is configured to receive the frequency control signal, and each controller is configured to output the corresponding final gating signal to a corresponding second output node connected to the corresponding gating line. The corresponding final gating signal includes a pulse of the corresponding gating signal or a signal maintained at the first gating voltage.

3. The display panel according to claim 1, wherein, The gating signal output circuit includes: A first signal transmission stage, configured to output a pulse of a first strobe signal; and A second signal transmission stage is configured to receive the pulse of the first strobe signal as a carry signal, and the second signal transmission stage outputs a pulse of a second strobe signal that follows the pulse of the first strobe signal. The output controller includes: A first controller, configured to receive the pulse of the first strobe signal, the pulse of the first rendering signal, and the frequency control signal; and A second controller is configured to receive the pulse of the second strobe signal, the pulse of a second rendering signal generated following the pulse of the first rendering signal, and the frequency control signal.

4. The display panel according to claim 1, wherein, The gating signal output circuit includes multiple signal transmission stages; The output controller includes multiple controllers; The Nth signal transmission stage among the plurality of signal transmission stages is configured to output the Nth gating signal to the first output node in response to the voltage of the Q node; The Nth controller of the plurality of controllers is configured to share the Q node and, in response to the Nth rendering signal, the Nth strobe signal, and the frequency control signal, output the Nth final strobe signal to the second output node; and N is a natural number.

5. The display panel according to claim 4, wherein, The Nth controller includes: A first control transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the Q node, the first electrode is connected to a VEL node to which the first gate voltage is applied, and the second electrode is connected to the second output node; A capacitor into which the voltage of the frequency control signal is charged; A second control transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the Nth rendering signal is applied to the gate electrode, the first electrode is connected to the capacitor, and the frequency control signal is applied to the second electrode; and A third control transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the capacitor, the first electrode is connected to the first output node, and the second electrode is connected to the second output node.

6. The display panel according to claim 1, wherein, The gating signal output circuit includes multiple signal transmission stages. The Nth signal transmission stage among the plurality of signal transmission stages includes: A first transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to a clock node to which a clock signal is applied, the first electrode is connected to a VST node to which a start signal or carry signal is input, and the second electrode is connected to a Q2 node. The second transistor includes a gate electrode, a first electrode, and a second electrode, the gate electrode being connected to the VST node, the first electrode being connected to a buffer node, and the second electrode being connected to a VEH node to which a second gate voltage is applied; A first capacitor is located between the buffer node and the clock node; A third transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the buffer node, the first electrode is connected to the clock node, and the second electrode is connected to the QB node; A fourth transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the Q2 node, the first electrode is connected to the QB node, and the second electrode is connected to the VEH node; A fifth transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to a VEL node to which the first gate voltage is applied, the first electrode is connected to the Q2 node, and the second electrode is connected to the Q node; The sixth-first transistor includes a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the Q node, the first electrode is connected to the VEL node, and the second electrode is connected to the first output node; A second capacitor is connected between the Q node and the first output node; A seventh transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the QB node, the first electrode is connected to the first output node, and the second electrode is connected to the VEH node; and A third capacitor is connected between the QB node and the VEH node, and The Nth signal transmission stage is configured to output the Nth strobe signal to the first output node.

7. The display panel according to claim 6, wherein, The output controller includes multiple controllers. The Nth controller among the plurality of controllers includes: The sixth-second transistor includes a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the Q node, the first electrode is connected to the VEL node, and the second electrode is connected to the second output node; The fourth capacitor is into which the voltage of the frequency control signal is charged; An eighth transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein an Nth rendering signal is applied to the gate electrode, the first electrode is connected to the fourth capacitor, and the frequency control signal is applied to the second electrode; and A ninth transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the fourth capacitor, the first electrode is connected to the first output node, and the second electrode is connected to the second output node. The Nth controller is configured to output the Nth final strobe signal to the second output node.

8. The display panel according to claim 1, wherein, Each of the plurality of sub-pixels includes: Light-emitting devices; A driving circuit, configured to drive the light-emitting device; A capacitor, the capacitor being connected to the drive circuit; and One or more switching circuits connected to the capacitor.

9. The display panel according to claim 8, wherein, Each of the one or more switching circuits includes a transistor; The pulse of the first gating voltage or the gating signal output from the output controller is applied to the corresponding gating line; and The corresponding gate line is connected to the gate electrode of the transistor.

10. The display panel according to claim 1, wherein, Each of the plurality of sub-pixels includes: A driving transistor, the driving transistor including a gate electrode, a first electrode and a second electrode, the gate electrode being connected to a first node, the first electrode being connected to a second node and the second electrode being connected to a third node; A light-emitting device, comprising an anode electrode and a cathode electrode, the anode electrode being connected to a fourth node, and a cathode voltage being applied to the cathode electrode; A capacitor is connected between the node to which the pixel driving voltage is applied and the first node; A first switching transistor includes a gate electrode, a first electrode, and a second electrode. A first strobe signal is applied to the gate electrode. The first electrode is connected to the first node, and the second electrode is connected to the third node. The second switching transistor includes a gate electrode, a first electrode, and a second electrode. A second strobe signal is applied to the gate electrode, the first electrode is connected to a data line, and the second electrode is connected to the second node. A third switching transistor includes a gate electrode, a first electrode, and a second electrode. A fifth strobe signal is applied to the gate electrode. The first electrode is connected to the node to which the pixel driving voltage is applied, and the second electrode is connected to the second node. A fourth switching transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein a fifth strobe signal is applied to the gate electrode, the first electrode is connected to the third node, and the second electrode is connected to the fourth node; and A fifth switching transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein a fourth strobe signal is applied to the gate electrode, the first electrode is connected to the first node, and an initialization voltage is applied to the second electrode. Wherein, the pulse of the gating signal output from the output controller or the first gating voltage is at least one of the first gating signal and the fourth gating signal.

11. The display panel according to claim 10, wherein, Each of the plurality of sub-pixels also includes: A sixth switching transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein a third strobe signal is applied to the gate electrode, the first electrode is connected to the fourth node, and an anode reset voltage is applied to the second electrode; and A seventh switching transistor includes a gate electrode, a first electrode, and a second electrode. A third strobe signal is applied to the gate electrode, the first electrode is connected to the second node, and a conduction bias voltage is applied to the second electrode.

12. A display device, the display device comprising: The display panel includes: a display area, wherein multiple data lines, multiple gating lines, multiple power lines, and multiple sub-pixels are disposed in the display area; a gating driver connected to the multiple gating lines; and a data driver connected to the data lines. The gating driver includes: A rendering signal generator configured to sequentially output rendering signals; A gating signal output circuit, the gating signal output circuit being configured to sequentially output gating signals; and An output controller configured to receive the rendering signal, the gating signal, and a frequency control signal, to output a pulse of the gating signal to a corresponding gating line or to maintain the voltage of the corresponding gating line at a first gating voltage. Each of the first sub-pixels to which the pulse of the gating signal from the output controller is applied is charged with a data voltage from the data driver to update the pixel data. Each of the second sub-pixels, which is subjected to a voltage maintained at the first gating voltage from the output controller, is driven by the previously charged data voltage, and The plurality of sub-pixels includes the first sub-pixel and the second sub-pixel.

13. The display device according to claim 12, wherein, The display panel includes: Refresh pixel regions, where pixel data is updated within a frame period; and Skip pixel regions, where pixel data is not updated. Wherein, the refreshed pixel region includes the first sub-pixel to which the pulse of the strobe signal from the output controller is applied, and The skipped pixel region includes the second sub-pixel that is subjected to a voltage maintained at the first gating voltage by the output controller.

14. The display device according to claim 12, wherein, The gating signal output circuit includes: Multiple signal transmission stages are connected to one or more clock lines, one or more clock signals are applied to the clock lines, the multiple signal transmission stages are sequentially connected via carry signal lines that provide carry signals from the previous stage to the next stage, and each of the multiple signal transmission stages is configured to output a corresponding strobe signal to a corresponding first output node. The output controller includes: Multiple controllers, each connected to a corresponding signal transmission stage among the multiple signal transmission stages of the gating signal output circuit, each controller is configured to receive the corresponding gating signal from the corresponding signal transmission stage, each controller is configured to receive the frequency control signal, and each controller is configured to output the corresponding final gating signal to a corresponding second output node connected to the corresponding gating line. The corresponding final gating signal includes a pulse of the corresponding gating signal or a signal maintained at the first gating voltage.

15. The display device according to claim 12, wherein, The gating signal output circuit includes multiple signal transmission stages; The output controller includes multiple controllers; The Nth signal transmission stage among the plurality of signal transmission stages is configured to output the Nth gating signal to the first output node in response to the voltage of the Q node; The Nth controller of the plurality of controllers is configured to share the Q node and, in response to the Nth rendering signal, the Nth strobe signal, and the frequency control signal, output the Nth final strobe signal to the second output node; and N is a natural number.

16. The display device according to claim 15, wherein, The Nth controller includes: A first transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the Q node, the first electrode is connected to a VEL node to which the first gating voltage is applied, and the second electrode is connected to the second output node; A capacitor into which the voltage of the frequency control signal is charged; A second transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the Nth rendering signal is applied to the gate electrode, the first electrode is connected to the capacitor, and the frequency control signal is applied to the second electrode; and A third transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein the gate electrode is connected to the capacitor, the first electrode is connected to the first output node, and the second electrode is connected to the second output node.

17. The display device according to claim 12, wherein, Each of the plurality of sub-pixels includes: Light-emitting devices; A driving circuit, configured to drive the light-emitting device; A capacitor, the capacitor being connected to the drive circuit; and One or more switching circuits connected to the capacitor.

18. The display device according to claim 17, wherein, Each of the one or more switching circuits includes a transistor; and The pulse of the gating signal output from the output controller or the first gating voltage is applied to the gate electrode of the transistor.

19. The display device according to claim 12, wherein, Each of the plurality of sub-pixels includes: A driving transistor, the driving transistor including a gate electrode, a first electrode and a second electrode, the gate electrode being connected to a first node, the first electrode being connected to a second node and the second electrode being connected to a third node; A light-emitting device, comprising an anode electrode and a cathode electrode, the anode electrode being connected to a fourth node, and a cathode voltage being applied to the cathode electrode; A capacitor is connected between the node to which the pixel driving voltage is applied and the first node; A first switching transistor includes a gate electrode, a first electrode, and a second electrode. A first strobe signal is applied to the gate electrode. The first electrode is connected to the first node, and the second electrode is connected to the third node. The second switching transistor includes a gate electrode, a first electrode, and a second electrode. A second strobe signal is applied to the gate electrode, the first electrode is connected to a data line, and the second electrode is connected to the second node. A third switching transistor includes a gate electrode, a first electrode, and a second electrode. A fifth strobe signal is applied to the gate electrode. The first electrode is connected to the node to which the pixel driving voltage is applied, and the second electrode is connected to the second node. A fourth switching transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein a fifth strobe signal is applied to the gate electrode, the first electrode is connected to the third node, and the second electrode is connected to the fourth node; and A fifth switching transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein a fourth strobe signal is applied to the gate electrode, the first electrode is connected to the first node, and an initialization voltage is applied to the second electrode. Wherein, the pulse of the gating signal output from the output controller or the first gating voltage is at least one of the first gating signal and the fourth gating signal.

20. The display device according to claim 19, wherein, Each of the plurality of sub-pixels includes: A sixth switching transistor, comprising a gate electrode, a first electrode, and a second electrode, wherein a third strobe signal is applied to the gate electrode, the first electrode is connected to the fourth node, and an anode reset voltage is applied to the second electrode; and A seventh switching transistor includes a gate electrode, a first electrode, and a second electrode. A third strobe signal is applied to the gate electrode, the first electrode is connected to the second node, and a conduction bias voltage is applied to the second electrode.

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