A shift register unit, a gate driving circuit, a display panel and a display device

Abstract

The application provides a shift register unit, a gate drive circuit, a display panel and a display device. The shift register unit comprises a first module, a second module, an output module, a pull-up node, a pull-down node and a signal output end. The first module is connected with a first input signal, a first control signal, a second control signal, the pull-up node and the pull-down node. The second module is connected with a second input signal, the first control signal, the second control signal, the pull-up node and the pull-down node. The output module is connected with a first clock signal end CLK, the pull-up node and the signal output end. The application can improve the problem of abnormal output of the gate drive circuit supporting forward and reverse scanning.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, display panels are showing a trend towards high integration and low cost. Among these technologies, GOA (Gate Driver on Array) integrates the TFT (Thin Film Transistor) gate driving circuitry onto the array substrate of the display panel to form a scanning drive for the display panel. Currently, GOA circuits typically consist of multiple cascaded shift register units, with each shift register unit's signal output corresponding to a gate line, used to sequentially input scan signals to the connected gate lines.

[0003] However, there is a problem in the GOA circuit where the pull-up node PU and the pull-down node PD compete with each other (i.e., they affect each other), especially in GOA circuits that support both forward and reverse scanning, which causes abnormal GOA output. Summary of the Invention

[0004] This application provides a shift register unit, a gate drive circuit, a display panel, and a display device to improve the problem of abnormal output of the gate drive circuit supporting forward and reverse scanning.

[0005] In a first aspect, embodiments of this application provide a shift register unit, characterized by comprising a first module, a second module, an output module, a pull-up node, a pull-down node, and a signal output terminal; the first module is connected to a first input signal, a first control signal, a second control signal, the pull-up node, and the pull-down node; the second module is connected to a second input signal, the first control signal, the second control signal, the pull-up node, and the pull-down node; and the output module is connected to a first clock signal terminal CLK, the pull-up node, and the signal output terminal.

[0006] Secondly, embodiments of this application provide a gate driving circuit, including the shift register unit described in any embodiment of the first aspect.

[0007] Thirdly, embodiments of this application provide a display panel including the gate driving circuit described in the second aspect embodiment.

[0008] Fourthly, embodiments of this application provide a display device, including the display panel described in the third aspect embodiment.

[0009] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application may be realized and obtained by means of the embodiments described in the description, claims, and drawings. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a shift register unit in related technologies;

[0012] Figure 2 for Figure 1 The circuit timing diagram of the shift register unit is shown;

[0013] Figure 3 This is a schematic diagram of the module structure of the shift register unit in one embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of the structure of a shift register unit in one embodiment of the present invention;

[0015] Figure 5 for Figure 4 The circuit timing diagram of the shift register unit is shown;

[0016] Figure 6 This is a schematic diagram of the shift register unit in another embodiment of the present invention;

[0017] Figure 7 This is a timing diagram of two voltage terminals;

[0018] Figure 8 This is a schematic diagram of the gate driving circuit according to an embodiment of the present invention;

[0019] Figure 9 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0020] Figure 10 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the specific embodiments of the gate driving circuit, display panel, and display device provided by the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are for illustration and explanation only and are not intended to limit the present invention. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict. It should be noted that the figures and shapes in the drawings do not reflect actual proportions and are only intended to illustrate the content of the present invention. And throughout the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions.

[0022] like Figure 1 As shown, the shift register unit may include thin-film transistors T0 to T10 and capacitor C1. Figure 1 The timing diagram for the shift register shown during forward scanning is as follows: Figure 2 As shown. Specifically, in the input stage T1, since the signal INB is a low-level signal, thin-film transistor T1 is turned off. The input signal INF is a high-level signal, so thin-film transistor T0 is turned on, and provides the high-level signal U2D to the pull-up node PU, so that the signal of the pull-up node PU is a high-level signal, thereby controlling thin-film transistors T3, T4, and T6 to turn on. The turned-on thin-film transistor T3 provides the low-level signal VGL to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal, thereby controlling thin-film transistors T2 and T5 to turn off. The turned-on thin-film transistor T6 provides the low-level signal VGL to the gate of T7, thereby controlling thin-film transistor T7 to turn off. The turned-on thin-film transistor T4 provides the low-level clock signal CLK to the signal output terminal Gout, so that the signal output terminal Gout outputs a low-level signal.

[0023] In the output phase T2, since the signal INB is low, thin-film transistor T1 is off. The input signal INF is low, so thin-film transistor T0 is off. Capacitor C1 keeps the signal at the pull-up node PU high, thus controlling thin-film transistors T3, T4, and T6 to conduct. The conducting thin-film transistor T4 provides a high-level clock signal CLK to the signal output terminal Gout, causing Gout to output a high-level signal. Furthermore, due to the effect of capacitor C1, the pull-up node PU is further pulled high, causing the conducting thin-film transistor T4 to provide a high-level clock signal CLK to the signal output terminal Gout. The conducting thin-film transistor T3 provides a low-level signal VGL to the pull-down node PD, causing the signal at the pull-down node PD to be low, thus controlling thin-film transistors T2 and T5 to turn off. The conducting thin-film transistor T6 provides a low-level signal VGL to the gate of T7, thus controlling thin-film transistor T7 to turn off.

[0024] During the reset phase T3, since the input signal INF is low, thin-film transistor T0 is turned off. Since the signal INB is high, thin-film transistor T1 is turned on and provides the low-level signal D2U to the pull-up node PU, so that the signal of the pull-up node PU is low, thereby controlling thin-film transistors T3, T4, and T6 to be turned off.

[0025] exist Figure 1 When the shift register unit shown performs a reverse scan, the functions of thin-film transistors T0 and T1 are interchanged. That is, in the input phase T1 of the reverse scan, thin-film transistor T1 is used to pull the pull-up node PU high, and in the reset phase T3, thin-film transistor T0 is used to pull the pull-up node PU low. However, in the gate drive circuit, its normal operation depends on the precise control of the critical node level, among which the potential rise of the pull-up node PU is the core link to realize the gate signal output. In practical applications, especially under long-term continuous operation and low-temperature environments, gate drive circuits often fail. The root cause is usually attributed to whether the pull-up node PU can be effectively raised to a high level under the drive of the input signal INF or INB. However, the typical failure mode of the GOA circuit often stems from the PU point's inability to "compete" with the pull-down node PD. That is, during the charging phase of the pull-up node PU, the pull-down node PD remains at a high level, preventing the pull-up node PU potential from rising normally and affecting the signal output Gout. Especially under long-term operation and low-temperature environments, the abnormal output problem of the gate drive circuit supporting forward and reverse scans is particularly prominent.

[0026] Based on this, embodiments of the present invention provide a gate driving circuit to improve the problem of abnormal output of gate driving circuits supporting forward and reverse scanning.

[0027] Figure 3 This is a schematic diagram of the structure of a shift register unit in one embodiment of the present invention; Figure 4 This is a schematic diagram of the specific structure of a shift register unit in one embodiment of the present invention. Figure 3 As shown, this embodiment of the invention provides a shift register unit, which includes a first module 110, a second module 120, an output module 140, a pull-up node PU, a pull-down node PD, and a signal output terminal OUT.

[0028] The first module 110 is connected to the first input signal INF, the first control signal U2D, the second control signal D2U, the pull-up node PU, and the pull-down node PD, respectively. The first module 110 is used to control the level signal of the first control signal U2D to be provided to the pull-up node PU and to control the level signal of the second control signal D2U to be provided to the pull-down node PD according to the level of the first input signal INF.

[0029] The second module 120 is connected to the second input signal INB, the first control signal U2D, the second control signal D2U, the pull-up node PU, and the pull-down node PD, respectively. The second module 120 is used to control the level signal of the second control signal D2U to be provided to the pull-up node PU and to control the level signal of the first control signal U2D to be provided to the pull-down node PD according to the level of the second input signal INB.

[0030] The output module 140 is connected to the first clock signal terminal CLK, the pull-up node PU, and the signal output terminal OUT, respectively. The output module 140 is used to control the level signal of the first clock signal terminal CLK to be provided to the signal output terminal OUT according to the level of the pull-up node PU.

[0031] This invention provides a shift register unit. When performing a forward scan of the display panel, a first module 110 can input a first control signal U2D and a second control signal D2U to the pull-up node PU and pull-down node PD. When performing a reverse scan of the display panel, a second module 120 can input the first control signal U2D and the second control signal D2U to the pull-up node PU and pull-down node PD. Thus, during both forward and reverse scans of the display panel, when either the first input signal INF or the second input signal INB is valid, the pull-down node PD can be actively pulled down. Furthermore, after the current row shift register unit's signal output terminal OUT finishes outputting the signal, the level signal of the pull-down node PD is actively pulled high. This avoids output abnormalities caused by the pull-up node PU failing to compete with the pull-down node PD.

[0032] The above are merely examples illustrating the specific structure of each module in the shift register unit. In actual implementation, the specific structure of each module is not limited to the structure provided in the embodiments of the present invention, but may be other structures known to those skilled in the art, and are not limited here.

[0033] In one alternative implementation, such as Figure 3 As shown, the shift register unit provided in this embodiment of the invention further includes: a pull-down module 130, which is connected to a pull-up node PU, a pull-down node PD, a first voltage signal terminal VGL, and a signal output terminal OUT, respectively; the pull-down module 130 is used to control the level signal of the first voltage signal terminal VGL to be provided to the pull-up node PU and the signal output terminal OUT according to the level signal of the pull-down node PD.

[0034] In one alternative implementation, such as Figure 3As shown, the shift register unit provided in this embodiment of the invention further includes: a pull-down control module 150, which is connected to the pull-down node PD and the second voltage signal terminal VGH respectively; the pull-down control module 150 is used to control the level signal of the second voltage signal terminal VGH to be provided to the pull-down node PD according to the level signal of the second voltage signal terminal VGH.

[0035] In one alternative implementation, such as Figure 3 As shown, the shift register unit provided in this embodiment of the invention further includes: a pull-up module 160, which is connected to a pull-up node PU, a pull-down node PD, a pull-down control module 150 and a first voltage signal terminal VGL; the pull-up module 160 is used to control the level signal of the first voltage signal terminal VGL to be provided to the pull-down node PD and the pull-down control module 150 according to the level signal of the pull-up node PU.

[0036] In one alternative implementation, such as Figure 3 As shown, the shift register unit provided in this embodiment of the invention further includes: a second reset module 170, which is connected to the pull-up node PU, the signal output terminal OUT, the first voltage signal terminal VGL, and the second reset signal terminal T-reset respectively; the second reset module 170 is used to control the level signal of the first voltage signal terminal VGL to be provided to the pull-up node PU and the signal output terminal OUT according to the level signal of the second reset signal terminal T-reset.

[0037] In specific implementations, in the embodiments of the present invention, the transistors mentioned above are generally made of the same material. In specific implementations, the transistors in the shift register unit can be N-type transistors. In the embodiments of the present invention, during forward scanning, the effective pulse signal of the first input signal INF can be a high-level signal, the first control signal U2D can be a high-level signal, and the second control signal D2U can be a low-level signal. During reverse scanning, the effective pulse signal of the second input signal INB can be a high-level signal, the first control signal U2D can be a low-level signal, and the second control signal D2U can be a high-level signal.

[0038] In specific implementations, the transistors in the shift register unit can also be P-type transistors. In this embodiment of the invention, during forward scanning, the effective pulse signal of the first input signal INF can be a low-level signal, the first control signal U2D can be a low-level signal, and the second control signal D2U can be a high-level signal. During reverse scanning, the effective pulse signal of the second input signal INB can be a low-level signal, the first control signal U2D can be a high-level signal, and the second control signal D2U can be a low-level signal.

[0039] In practice, N-type transistors are turned on under high-level signals and turned off under low-level signals; P-type transistors are turned off under high-level signals and turned on under low-level signals.

[0040] In practical implementation, the first voltage signal terminal VGL can continuously provide a high-level signal, and the second voltage signal terminal VGH can continuously provide a low-level signal. The schematic diagram in this invention uses an N-type transistor in the shift register unit. If a P-type transistor is used in the shift register unit, the positions of the first voltage signal terminal VGL and the second voltage signal terminal VGH are interchanged in the schematic diagram.

[0041] It should be noted that the transistors mentioned in the above embodiments of the present invention can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), and are not limited thereto. In specific implementations, depending on the type of transistor and the received signal, the first terminal of these transistors can be used as the source and the second terminal as the drain, or vice versa; no specific distinction is made here.

[0042] The present invention will now be described in detail with reference to specific embodiments. It should be noted that these embodiments are for better explanation of the present invention and do not limit the scope of the invention.

[0043] like Figure 4 As shown, the first module 110 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the first input signal INF, the first terminal is connected to the first control signal U2D, and the second terminal is connected to the pull-up node PU. The gate of the second transistor T2 is connected to the first input signal INF, the first terminal is connected to the second control signal D2U, and the second terminal is connected to the pull-down node PD.

[0044] Specifically, when the first transistor T1 is in the on state under the control of the first input signal INF, it can provide the level signal of the first control signal U2D to the pull-up node PU. When the second transistor T2 is in the on state under the control of the first input signal INF, it can provide the level signal of the second control signal D2U to the pull-down node PD.

[0045] The second module 120 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is connected to the second input signal INB, the first terminal is connected to the second control signal D2U, and the second terminal is connected to the pull-up node PU. The gate of the fourth transistor T4 is connected to the second input signal INB, the first terminal is connected to the first control signal U2D, and the second terminal is connected to the pull-down node PD.

[0046] Specifically, when the third transistor T3 is in the ON state under the control of the second input signal INB, it can provide the level signal of the second control signal D2U to the pull-up node PU. When the fourth transistor T4 is in the ON state under the control of the second input signal INB, it can provide the level signal of the first control signal U2D to the pull-down node PD.

[0047] The output module 140 includes a seventh transistor T7 and a first capacitor C1. The gate of the seventh transistor T7 is connected to the pull-up node PU, the first terminal is connected to the first clock signal terminal CLK, and the second terminal is connected to the signal output terminal OUT. The first capacitor is connected between the pull-up node PU and the signal output terminal OUT.

[0048] Specifically, when the seventh transistor T7 is in the on state under the control of the pull-up node PU, it can provide the level signal of the first clock signal terminal CLK to the signal output terminal OUT. The first capacitor C1 can store the voltage input between the pull-up node PU and the signal output terminal OUT. Furthermore, when the pull-up node PU is in the floating state, the first capacitor C1 can also keep the voltage difference between the pull-up node PU and the signal output terminal OUT stable.

[0049] The pull-down module 130 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is connected to the pull-down node PD, the first terminal is connected to the first voltage signal terminal VGL, and the second terminal is connected to the pull-up node PU. The gate of the sixth transistor T6 is connected to the pull-down node PD, the first terminal is connected to the first voltage signal terminal VGL, and the second terminal is connected to the signal output terminal OUT.

[0050] Specifically, when the fifth transistor T5 is in the ON state under the control of the pull-down node PD, it can provide the level signal of the first voltage signal terminal VGL to the pull-up node PU. When the sixth transistor T6 is in the ON state under the control of the pull-down node PD, it can provide the level signal of the first voltage signal terminal VGL to the signal output terminal OUT.

[0051] The pull-down control module 150 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is connected to the second voltage signal terminal VGH, the first terminal is connected to the second voltage signal terminal VGH, and the second terminal is connected to the gate of the ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the second voltage signal terminal VGH, and the second terminal is connected to the pull-down node PD.

[0052] Specifically, when the second voltage signal terminal VGH is a high-level signal, the eighth transistor T8 is in the conducting state under the control of the high-level signal of the second voltage signal terminal VGH, and provides the high-level signal of the second voltage signal terminal VGH to the gate of the ninth transistor T9, so that the ninth transistor T9 is turned on, thereby providing the high-level signal of the second voltage signal terminal VGH to the pull-down node PD.

[0053] The pull-up module 160 includes a tenth transistor T10 and an eleventh transistor T11. The gate of the tenth transistor T10 is connected to the pull-up node PU, the first terminal is connected to the first voltage signal terminal VGL, and the second terminal is connected to the pull-down node PD. The gate of the eleventh transistor T11 is connected to the pull-up node PU, the first terminal is connected to the first voltage signal terminal VGL, and the second terminal is connected to the gate of the ninth transistor T9.

[0054] Specifically, when the first voltage signal terminal VGL is low, the tenth transistor T10 is in the on state under the control of the pull-up node PU, and provides the low-level signal of the first voltage signal terminal VGL to the pull-down node PD; when the eleventh transistor T11 is in the on state under the control of the pull-up node PU, it provides the low-level signal of the first voltage signal terminal VGL to the gate of the ninth transistor T9, and the ninth transistor T9 is turned off.

[0055] The second reset module 170 includes a twelfth transistor T12 and a thirteenth transistor T13. The gate of the twelfth transistor T12 is connected to the second reset signal terminal T-reset, the first terminal is connected to the first voltage signal terminal VGL, and the second terminal is connected to the pull-up node PU. The gate of the thirteenth transistor T13 is connected to the second reset signal terminal T-reset, the first terminal is connected to the first voltage signal terminal VGL, and the second terminal is connected to the signal output terminal OUT.

[0056] Specifically, when the twelfth transistor T12 is in the on state under the control of the second reset signal terminal T-reset, it provides the low-level signal of the first voltage signal terminal VGL to the pull-up node PU; when the thirteenth transistor T13 is in the on state under the control of the second reset signal terminal T-reset, it provides the low-level signal of the first voltage signal terminal VGL to the signal output terminal OUT.

[0057] The following is based on Figure 4 Taking the structure shown as an example, combined with Figure 5 The circuit timing diagram shown describes the operation of the shift register unit provided in the embodiment of the present invention.

[0058] like Figure 5As shown, T10 represents the forward scan time period, and T20 represents the reverse scan time period. T11 represents the input phase of the forward scan time period, T12 represents the output phase of the forward scan time period, T13 represents the first reset phase of the forward scan time period, T14 represents the sustain phase of the forward scan time period, and T15 represents the second reset phase of the forward scan time period. T21 represents the input phase of the reverse scan time period, T22 represents the output phase of the reverse scan time period, T23 represents the reset phase of the reverse scan time period, T24 represents the sustain phase of the reverse scan time period, and T25 represents the second reset phase of the reverse scan time period. Specifically, during the forward scan time period T10, the first control signal U2D is a high-level signal, and the second control signal D2U is a low-level signal; and during the reverse scan time period T20, the first control signal U2D is a low-level signal, and the second control signal D2U is a high-level signal.

[0059] During the forward scan input phase T11, the first input signal INF is high, and the first transistor T1 and the second transistor T2 are simultaneously turned on. The turned-on first transistor T1 provides the high-level first control signal U2D to the pull-up node PU, thereby pulling the level of the pull-up node PU high and storing the high level in the first capacitor C1. At this time, the seventh transistor T7 is turned on under the drive of the high level of the pull-up node PU. Since the first clock signal terminal CLK is low, the low level of the first clock signal terminal CLK is provided to the signal output terminal OUT through the seventh transistor T7. Therefore, the signal output terminal OUT outputs a low-level signal. The turned-on second transistor T2 provides the low-level second control signal D2U to the pull-down node PD, thereby directly pulling the level on the pull-down node PD low. Therefore, the first module 110 can directly pull down the pull-down node PD when charging the pull-up node PU, which can avoid the pull-up node PU being unable to compete with the pull-down node PD, resulting in the pull-up node PU being unable to rise normally; even if the gate drive circuit has been working for a long time or under low temperature environment, causing the conduction current Ion to decay and the charging current to be insufficient, the pull-up node PU can still achieve normal potential rise, and the stability of the circuit operation is guaranteed.

[0060] During this stage, the second input signal INB is low, and the third transistor T3 and the fourth transistor T4 are turned off.

[0061] During this phase, the pull-down node PD is at a low level, and the fifth transistor T5 and the sixth transistor T6 are off. The fifth transistor T5 being off prevents the pull-up node PU from being pulled low to the low level of the first voltage signal terminal VGL; the sixth transistor T6 being off prevents the signal output terminal OUT from being pulled low to the low level of the first voltage signal terminal VGL.

[0062] In this phase, the pull-up node PU is at a high level, and the tenth transistor T10 and the eleventh transistor T11 are turned on. The turned-on tenth transistor T10 provides the low-level signal of the first voltage signal terminal VGL to the pull-down node PD, and together with the turned-on second transistor T2, pulls down the level of the pull-down node PD. The turned-on eleventh transistor T11 provides the low-level signal of the first voltage signal terminal VGL to the ninth transistor T9, and the ninth transistor T9 is turned off. The turned-off ninth transistor T9 will no longer charge the pull-down node PD.

[0063] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0064] In the forward scan output stage T12, the first input signal INF is low, and the first transistor T1 and the second transistor T2 are off. However, since the first capacitor C1 has already stored the high-level signal of the first input signal INF from the forward scan input stage T11, the pull-up node PU remains high. The high-level pull-up node PU keeps the seventh transistor T7 on. The input signal of the first clock signal terminal CLK becomes high. Due to the bootstrap effect of the transistor, the level of the pull-up node PU continues to be pulled high, amplifying the level of the pull-up node PU. The signal output terminal OUT outputs a high-level gate drive signal. The increase in the level of the pull-up node PU improves the charging capability of the seventh transistor T7, ensuring the pixel charging level.

[0065] During this stage, the second input signal INB is low, and the third transistor T3 and the fourth transistor T4 are turned off.

[0066] During this phase, the pull-down node PD is at a low level, and the fifth transistor T5 and the sixth transistor T6 are off. The fifth transistor T5 being off prevents the pull-up node PU from being pulled low to the low level of the first voltage signal terminal VGL; the sixth transistor T6 being off prevents the signal output terminal OUT from being pulled low to the low level of the first voltage signal terminal VGL.

[0067] In this phase, the voltage level of the pull-up node PU is further increased, and the tenth transistor T10 and the eleventh transistor T11 remain on. The on-state tenth transistor T10 provides a low-level signal from the first voltage signal terminal VGL to the pull-down node PD. The on-state eleventh transistor T11 provides a low-level signal from the first voltage signal terminal VGL to the ninth transistor T9, which is then off. The off-state ninth transistor T9 will no longer charge the pull-down node PD.

[0068] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0069] In the first reset phase T13 of the forward scan, the second input signal INB is high, and the third transistor T3 and the fourth transistor T4 are simultaneously turned on. The turned-on third transistor T3 provides the low-level second control signal D2U to the pull-up node PU, thereby pulling the level of the pull-up node PU down to a low level. The turned-on fourth transistor T4 provides the high-level first control signal U2D to the pull-down node PD, pulling the level of the pull-down node PD up to a high level. Therefore, after the signal output Gout of the current row shift register unit ends, the second module 120 can actively pull down the pull-up node PU and simultaneously pull up the potential of the pull-down node PD; this can improve the problem of the slow rise rate of the pull-down node PD level during the operation of the gate drive circuit; if the pull-down node PD level rises slowly, the display panel is very susceptible to electrostatic disturbances during this phase, resulting in display defects. Therefore, the second module 120 can optimize the node charging speed, suppress the risk of electrostatic interference, and thus effectively improve the reliability of the display panel.

[0070] During this stage, the first input signal INF is low, and the first transistor T1 and the second transistor T2 are turned off. Therefore, the seventh transistor T7 is also turned off.

[0071] During this phase, since the pull-down node PD is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned on. The turned-on sixth transistor T6 provides the low-level signal from the first voltage signal terminal VGL to the signal output terminal OUT, and the signal output terminal OUT outputs a low-level signal.

[0072] During this phase, since the pull-up node PU is at a low level, the tenth transistor T10 and the eleventh transistor T11 are turned off. With the tenth transistor T10 off, it will not pull the pull-down node PD low to the low level of the first voltage signal terminal VGL; with the eleventh transistor T11 off, it will not provide the low level of the first voltage signal terminal VGL to the ninth transistor T9.

[0073] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0074] During the forward scan sustain phase T14, both the first input signal INF and the second input signal INB are at a low level, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. Therefore, the seventh transistor T7 is also turned off.

[0075] During this stage, the input signal of the second voltage signal terminal VGH is at a high level, and the eighth transistor T8 and the ninth transistor T9 are turned on, so that the pull-down node PD is always at a high level.

[0076] During this phase, since the pull-down node PD is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned on. The turned-on fifth transistor T5 provides the low-level signal of the first voltage signal terminal VGL to the pull-up node PU, maintaining the level of the pull-up node PU at a low potential. The turned-on sixth transistor T6 provides the low-level signal of the first voltage signal terminal VGL to the signal output terminal OUT, and the signal output terminal OUT outputs a low-level signal.

[0077] During this phase, since the pull-up node PU is at a low level, the tenth transistor T10 and the eleventh transistor T11 are turned off. With the tenth transistor T10 off, it will not pull the pull-down node PD low to the low level of the first voltage signal terminal VGL; with the eleventh transistor T11 off, it will not provide the low level of the first voltage signal terminal VGL to the ninth transistor T9.

[0078] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0079] During the second reset phase T15 of the forward scan, i.e. during the idle period, the input signal of the second reset signal terminal T-reset becomes high level, and the twelfth transistor T12 and the thirteenth transistor T13 are turned on to reduce noise for the first capacitor C1 and the signal output terminal OUT, so as to keep the pull-up node PU and the signal output terminal OUT pulled low to the low level signal of the first voltage signal terminal VGL.

[0080] After the forward scan sustain phase T14, the first clock signal terminal CLK remains low until the first input signal INF goes high, then the forward scan input phase T11 restarts. The time from when the first clock signal terminal CLK stops outputting a high level to the restart of the next first phase can be called the blanking time. When the display panel is working normally, gate drive signals need to be output sequentially from the first row of gate lines to the last row. After the gate drive signal for a certain row of gate lines finishes outputting, the shift register enters the blanking time period for clock signal input. This embodiment introduces a second reset signal terminal T-reset into the shift register unit to keep the pull-up node PU and the signal output terminal OUT at a low level on the first voltage signal terminal VGL during the blanking time period. This avoids problems such as transistor characteristic drift caused by bias voltage under high temperature and high humidity environments, and end-line defects caused by charge accumulation on the pull-up node PU.

[0081] During the reverse scan input phase T21, the second input signal INB is high, and the third transistor T3 and the fourth transistor T4 are simultaneously turned on. The turned-on third transistor T3 provides the high-level second control signal D2U to the pull-up node PU, thereby pulling the level of the pull-up node PU high and storing the high level in the first capacitor C1. At this time, the seventh transistor T7 is turned on under the drive of the high level of the pull-up node PU. Since the first clock signal terminal CLK is low, the low level of the first clock signal terminal CLK is provided to the signal output terminal OUT through the seventh transistor T7. Therefore, the signal output terminal OUT outputs a low-level signal. The turned-on fourth transistor T4 provides the low-level first control signal U2D to the pull-down node PD, thereby pulling the level on the pull-down node PD low. Therefore, the second module 120 can directly pull down the pull-down node PD when charging the pull-up node PU, which can avoid the pull-up node PU being unable to compete with the pull-down node PD, thus preventing the pull-up node PU from rising normally. Even if the gate drive circuit has been working for a long time or under low temperature conditions, causing the conduction current Ion to decay and the charging current to be insufficient, the pull-up node PU can still achieve normal potential rise, and the stability of the circuit operation is guaranteed.

[0082] During this stage, the first input signal INF is low, and the first transistor T1 and the second transistor T2 are turned off.

[0083] During this phase, the pull-down node PD is at a low level, and the fifth transistor T5 and the sixth transistor T6 are off. The fifth transistor T5 being off prevents the pull-up node PU from being pulled low to the low level of the first voltage signal terminal VGL; the sixth transistor T6 being off prevents the signal output terminal OUT from being pulled low to the low level of the first voltage signal terminal VGL.

[0084] In this phase, the pull-up node PU is at a high level, and the tenth transistor T10 and the eleventh transistor T11 are turned on. The turned-on tenth transistor T10 provides the low-level signal of the first voltage signal terminal VGL to the pull-down node PD, and together with the turned-on second transistor T2, pulls down the level of the pull-down node PD. The turned-on eleventh transistor T11 provides the low-level signal of the first voltage signal terminal VGL to the ninth transistor T9, and the ninth transistor T9 is turned off. The turned-off ninth transistor T9 will no longer charge the pull-down node PD.

[0085] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0086] In the reverse scan output stage T22, the second input signal INB is low, and the third transistor T3 and the fourth transistor T4 are off. However, since the first capacitor C1 has already stored the high-level signal of the second input signal INB from the reverse scan input stage T21, the potential of the pull-up node PU remains high. The first clock signal terminal CLK inputs a high-level signal, and the level of the pull-up node PU further increases due to the bootstrap effect, keeping the seventh transistor T7 on. Therefore, the high-level signal input to the first clock signal terminal CLK is provided to the signal output terminal OUT through the seventh transistor T7.

[0087] During this stage, the first input signal INF is low, and the first transistor T1 and the second transistor T2 are turned off.

[0088] During this phase, the pull-down node PD is at a low level, and the fifth transistor T5 and the sixth transistor T6 are off. The fifth transistor T5 being off prevents the pull-up node PU from being pulled low to the low level of the first voltage signal terminal VGL; the sixth transistor T6 being off prevents the signal output terminal OUT from being pulled low to the low level of the first voltage signal terminal VGL.

[0089] In this phase, the voltage level of the pull-up node PU is further increased, and the tenth transistor T10 and the eleventh transistor T11 remain on. The on-state tenth transistor T10 provides a low-level signal from the first voltage signal terminal VGL to the pull-down node PD. The on-state eleventh transistor T11 provides a low-level signal from the first voltage signal terminal VGL to the ninth transistor T9, which is then off. The off-state ninth transistor T9 will no longer charge the pull-down node PD.

[0090] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0091] In the first reset stage T23 of the reverse scan, the first input signal INF is high. The first transistor T1 and the second transistor T2 are simultaneously turned on. The turned-on first transistor T1 provides a low-level first control signal U2D to the pull-up node PU, thereby pulling the level of the pull-up node PU down to a low level. The turned-on second transistor T2 provides a high-level second control signal D2U to the pull-down node PD, thereby pulling the level on the pull-down node PD up to a high level. Therefore, after the output signal Gout of the current row shift register unit ends, the first module 110 can actively pull down the pull-up node PU and simultaneously pull up the potential of the pull-down node PD; this can improve the problem of the slow rise rate of the pull-down node PD level during the operation of the gate drive circuit; if the pull-down node PD level rises slowly, the display panel is easily affected by electrostatic discharge during this stage, resulting in display defects. Therefore, the first module 110 can optimize the node charging speed, suppress the risk of electrostatic interference, and thus effectively improve the reliability of the display panel.

[0092] During this stage, the second input signal INB is low, and the third transistor T3 and the fourth transistor T4 are turned off. Therefore, the seventh transistor T7 is also turned off.

[0093] During this phase, since the pull-down node PD is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned on. The turned-on sixth transistor T6 provides the low-level signal from the first voltage signal terminal VGL to the signal output terminal OUT, and the signal output terminal OUT outputs a low-level signal.

[0094] During this phase, since the pull-up node PU is at a low level, the tenth transistor T10 and the eleventh transistor T11 are turned off. With the tenth transistor T10 off, it will not pull the pull-down node PD low to the low level of the first voltage signal terminal VGL; with the eleventh transistor T11 off, it will not provide the low level of the first voltage signal terminal VGL to the ninth transistor T9.

[0095] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0096] During the reverse scan sustain phase T24, both the first input signal INF and the second input signal INB are at a low level, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. Therefore, the seventh transistor T7 is also turned off.

[0097] During this stage, the input signal of the second voltage signal terminal VGH is at a high level, and the eighth transistor T8 and the ninth transistor T9 are turned on, so that the pull-down node PD is always at a high level.

[0098] During this phase, since the pull-down node PD is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned on. The turned-on fifth transistor T5 provides the low-level signal of the first voltage signal terminal VGL to the pull-up node PU, maintaining the level of the pull-up node PU at a low potential. The turned-on sixth transistor T6 provides the low-level signal of the first voltage signal terminal VGL to the signal output terminal OUT, and the signal output terminal OUT outputs a low-level signal.

[0099] During this phase, since the pull-up node PU is at a low level, the tenth transistor T10 and the eleventh transistor T11 are turned off. With the tenth transistor T10 off, it will not pull the pull-down node PD low to the low level of the first voltage signal terminal VGL; with the eleventh transistor T11 off, it will not provide the low level of the first voltage signal terminal VGL to the ninth transistor T9.

[0100] During this stage, the input signal of the second reset signal terminal T-reset is low, and the twelfth transistor T12 and the thirteenth transistor T13 are turned off, so the pull-up node PU and the signal output terminal OUT will not be pulled down to the low level of the first voltage signal terminal VGL.

[0101] In the second reset phase T25 of the reverse scan, the input signal of the second reset signal terminal T-reset becomes high level, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the first capacitor C1 and the signal output terminal OUT are noise-damped to keep the pull-up node PU and the signal output terminal OUT pulled low to the low level signal of the first voltage signal terminal VGL.

[0102] After the reverse scan sustain phase T24, the first clock signal CLK remains low until the second input signal INB is high, at which point the reverse scan input phase T21 restarts.

[0103] In practice, the forward scanning time period can be at least the display time of one frame. For example, it can be the display time of one frame. Alternatively, it can be the display time of five frames. Of course, in practical applications, different application environments have different requirements for the length of the forward scanning time period. Therefore, the specific length of the forward scanning time period can be designed and determined according to the actual application environment, and is not limited here.

[0104] In practice, the reverse scan time period can be at least the display time of one frame. For example, it can be the display time of one frame, or it can be the display time of five frames. Of course, in practical applications, different application environments have different requirements for the duration of the reverse scan time period. Therefore, the specific duration of the reverse scan time period can be designed and determined according to the actual application environment, and is not limited here.

[0105] It should be noted that the forward scan period can be performed after the forward scan period is completed, or vice versa. Therefore, the order of the forward and reverse scan periods can be determined based on the actual application environment and is not limited here.

[0106] The shift register unit provided in this embodiment of the invention, when performing forward scanning of the display panel in the display device, can utilize the thin-film transistor in the first module 110 to actively pull up the level signal of the pull-up node PU and actively pull down the level signal of the pull-down node PD in response to the first input signal INF during the input phase T11; and utilize the thin-film transistor in the second module 120 to actively pull down the level signal of the pull-up node PU and actively pull up the level signal of the pull-down node PD in response to the second input signal INB during the reset phase T13 to reset. When performing reverse scanning of the display panel, the thin-film transistor in the second module 120 can utilize the thin-film transistor in the second module 120 to actively pull up the level signal of the pull-up node PU and actively pull down the level signal of the pull-down node PD in response to the second input signal INB during the input phase T21; and utilize the thin-film transistor in the first module 110 to actively pull down the level signal of the pull-up node PU and actively pull up the level signal of the pull-down node PD in response to the first input signal INF during the reset phase T23 to reset. In this way, during forward or reverse scanning of the display panel, the pull-down node PD can be pulled down directly while charging the pull-up node PU during the input phase. This avoids the pull-up node PU failing to compete with the pull-down node PD, preventing it from rising properly. Even if the gate drive circuit experiences a decrease in conduction current Ion or insufficient charging current due to long-term operation or low-temperature environments, the pull-up node PU can still achieve normal potential rise, ensuring circuit stability. During the first reset phase, after the output signal of the previous row shift register unit Gout ends, the pull-up node PU can be actively pulled down, and the pull-down node PD can be pulled up simultaneously. This improves the problem of slow rise rate of the pull-down node PD level during gate drive circuit operation. If the pull-down node PD level rises slowly, the display panel is highly susceptible to electrostatic disturbances during this phase, resulting in display defects. Therefore, the second module 120 can optimize node charging speed, suppress electrostatic interference risks, and effectively improve the reliability of the display panel.

[0107] In one alternative implementation, Figure 6 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Figure 6As shown, this embodiment of the invention provides a shift register unit, including a first module 110, a second module 120, a pull-down module, an output module 140, a pull-down control module, a pull-up module, a second reset module 170, a pull-up node PU, a pull-down node PD, and a signal output terminal. This shift register unit includes two structurally identical parts that operate in a time-division multiplexing manner. For example, the pull-down module includes a first pull-down module 131 and a second pull-down module 132; the pull-down control module includes a first pull-down control module 151 and a second pull-down control module 152; the pull-up module includes a first pull-up module 161 and a second pull-up module 162; and the pull-down node PD includes a first pull-down node PD1 and a second pull-down node PD2.

[0108] The first pull-down control module 151 is connected to the second voltage signal terminal 1 VGH1, and the second pull-down control module 152 is connected to the second voltage signal terminal 2 VGH2. For example... Figure 7 As shown, the signals on the second voltage signal terminal 1 VGH1 and the second voltage signal terminal 2 VGH2 can alternately be on-level (e.g., high-level). When the second voltage signal terminal 1 VGH1 provides an on-level, the second voltage signal terminal 2 VGH2 provides an off-level; or, when the second voltage signal terminal 1 VGH1 provides an off-level, the second voltage signal terminal 2 VGH2 provides an on-level. This allows one of the first pull-down control module 151 and the second pull-down control module 152 to be in an active state while the other is in an inactive state. Similarly, it allows one of the first pull-down control module 151 and the second pull-down control module 152 to be in an active state while the other is in an inactive state. This is equivalent to reducing the working time of any pull-down control module, pull-up module, and pull-down module, and reducing the time that the transistors electrically connected to them are in a biased state, thereby improving the threshold drift problem.

[0109] The signal output terminals include a scan signal output terminal Gout and a cascade signal output terminal Cout. Because the load on the output terminal OUT of the shift register unit is relatively large and the signal is delayed when connected to the scan line SL in the display panel, the signal output terminals of the shift register unit can include a scan signal output terminal Gout and a cascade signal output terminal Cout to provide a more effective trigger signal for the next-stage shift register unit, in order to ensure that the enable signal output by the shift register unit can provide a more effective trigger signal for the next-stage shift register unit. The scan signal output terminal Gout can be electrically connected to the scan line SL, and the cascade signal output terminal Cout can be electrically connected to the first input signal INF or the second input signal INB of the trigger terminal of the next-stage shift register unit.

[0110] The first module 110 is connected to the first input signal INF, the first control signal U2D, the second control signal D2U, the pull-up node PU, the first pull-down node PD1, and the second pull-down node PD2. The first module 110 is used to control the level signal of the first control signal U2D to be provided to the pull-up node PU and to control the level signal of the second control signal D2U to be provided to the pull-down node PD according to the level of the first input signal INF.

[0111] The first module 110 includes a first transistor T1, a second transistor T2, and a fourteenth transistor T14. The gate of the first transistor T1 is connected to the first input signal INF, its first terminal is connected to the first control signal U2D, and its second terminal is connected to the pull-up node PU. The gate of the second transistor T2 is connected to the first input signal INF, its first terminal is connected to the second control signal D2U, and its second terminal is connected to the first pull-down node PD1. The gate of the fourteenth transistor T14 is connected to the first input signal INF, its first terminal is connected to the second control signal D2U, and its second terminal is connected to the second pull-down node PD2.

[0112] Specifically, when the first transistor T1 is in the ON state under the control of the first input signal INF, it can provide the level signal of the first control signal U2D to the pull-up node PU. When the second transistor T2 is in the ON state under the control of the first input signal INF, it can provide the level signal of the second control signal D2U to the first pull-down node PD1. When the fourteenth transistor T14 is in the ON state under the control of the first input signal INF, it can provide the level signal of the second control signal D2U to the second pull-down node PD2.

[0113] The second module 120 is connected to the second input signal INB, the first control signal U2D, the second control signal D2U, the pull-up node PU, the first pull-down node PD1, and the second pull-down node PD2. The second module 120 is used to control the level signal of the second control signal D2U to be provided to the pull-up node PU and to control the level signal of the first control signal U2D to be provided to the pull-down node PD according to the level of the second input signal INB.

[0114] The second module 120 includes a third transistor T3, a fourth transistor T4, and a fifteenth transistor T15. The gate of the third transistor T3 is connected to the second input signal INB, its first terminal is connected to the second control signal D2U, and its second terminal is connected to the pull-up node PU. The gate of the fourth transistor T4 is connected to the second input signal INB, its first terminal is connected to the first control signal U2D, and its second terminal is connected to the first pull-down node PD1. The gate of the fifteenth transistor T15 is connected to the second input signal INB, its first terminal is connected to the first control signal U2D, and its second terminal is connected to the second pull-down node PD2.

[0115] Specifically, when the third transistor T3 is in the ON state under the control of the second input signal INB, it can provide the level signal of the second control signal D2U to the pull-up node PU. When the fourth transistor T4 is in the ON state under the control of the second input signal INB, it can provide the level signal of the first control signal U2D to the first pull-down node PD1. When the fifteenth transistor T15 is in the ON state under the control of the second input signal INB, it can provide the level signal of the first control signal U2D to the second pull-down node PD2.

[0116] The output module 140 is connected to the pull-up node PU, the first clock signal terminal CLK, the scan signal output terminal Gout, and the cascade signal output terminal Cout, respectively.

[0117] Output module 140 includes a seventh transistor T7, a seventeenth transistor T17, and a first capacitor C1. The gate of the seventh transistor T7 is connected to the pull-up node PU, its first terminal is connected to the first clock signal terminal CLK, and its second terminal is connected to the scan signal output terminal Gout. The gate of the seventeenth transistor T17 is connected to the pull-up node PU, its first terminal is connected to the first clock signal terminal CLK, and its second terminal is connected to the cascaded signal output terminal Cout. The first capacitor C1 stores the voltage input between the pull-up node PU and the scan signal output terminal Gout. Furthermore, when the pull-up node PU is in a floating state, the first capacitor C1 also stabilizes the voltage difference between the pull-up node PU and the scan signal output terminal Gout.

[0118] Specifically, when the seventh transistor T7 is in the ON state under the control of the pull-up node PU, it can provide the level signal of the first clock signal terminal CLK to the scan signal output terminal Gout. When the seventeenth transistor T17 is in the ON state under the control of the pull-up node PU, it can provide the level signal of the first clock signal terminal CLK to the cascaded signal output terminal Cout.

[0119] The first pull-down module 131 is connected to the pull-up node PU, the first pull-down node PD1, the first voltage signal terminal VGL, the third voltage signal terminal LVGL, the cascaded signal output terminal Cout, and the scan signal output terminal Gout. The first pull-down module 131 is used to control the level signals of the third voltage signal terminal LVGL and the first voltage signal terminal VGL to be provided to the pull-up node PU, the cascaded signal output terminal Cout, and the scan signal output terminal Gout based on the level signal of the first pull-down node PD1.

[0120] The first pull-down module 131 includes a fifth transistor T5, a sixteenth transistor T16, and a sixth transistor T6. The gate of the fifth transistor T5 is connected to the first pull-down node PD1, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the pull-up node PU. The gate of the sixteenth transistor T16 is connected to the first pull-down node PD1, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the cascaded signal output terminal Cout. The gate of the sixth transistor T6 is connected to the first pull-down node PD1, its first terminal is connected to the first voltage signal terminal VGL, and its second terminal is connected to the scan signal output terminal Gout.

[0121] Specifically, when the fifth transistor T5 is in the ON state under the control of the first pull-down node PD1, it can provide the level signal of the third voltage signal terminal LVGL to the pull-up node PU. When the sixteenth transistor T16 is in the ON state under the control of the first pull-down node PD1, it can provide the level signal of the third voltage signal terminal LVGL to the cascaded signal output terminal Cout. When the sixth transistor T6 is in the ON state under the control of the first pull-down node PD1, it can provide the level signal of the third voltage signal terminal LVGL to the scan signal output terminal Gout.

[0122] The first pull-down control module 151 is connected to the second voltage signal terminal 1VGH1 and the first pull-down node PD1, respectively. The first pull-down control module 151 is used to control the level signal of the second voltage signal terminal 1VGH1 to be provided to the first pull-down node PD1 according to the level signal of the second voltage signal terminal 1VGH1.

[0123] The first pull-down control module 151 includes an eighth transistor T8 and a ninth transistor T9. The gate of the eighth transistor T8 is connected to the second voltage signal terminal 1 VGH1, the first terminal is connected to the second voltage signal terminal 1 VGH1, and the second terminal is connected to the gate of the ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the second voltage signal terminal 1 VGH1, and the second terminal is connected to the first pull-down node PD1.

[0124] Specifically, when the second voltage signal terminal 1VGH1 is a high-level signal, the eighth transistor T8 is in the conducting state under the control of the high-level signal of the second voltage signal terminal 1VGH1, and provides the high-level signal of the second voltage signal terminal 1VGH1 to the gate of the ninth transistor T9, so that the ninth transistor T9 is turned on, thereby providing the high-level signal of the second voltage signal terminal 1VGH1 to the first pull-down node PD1.

[0125] The first pull-up module 161 is connected to the pull-up node PU, the first pull-down node PD1, and the third voltage signal terminal LVGL. The first pull-up module 161 is used to control the level signal of the third voltage signal terminal LVGL to be provided to the first pull-down node PD1 and the first pull-down control module 151 according to the level signal of the pull-up node PU.

[0126] The first pull-up module 161 includes a tenth transistor T10 and an eleventh transistor T11. The gate of the tenth transistor T10 is connected to the pull-up node PU, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the first pull-down node PD1. The gate of the eleventh transistor T11 is connected to the pull-up node PU, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the gate of the ninth transistor T9.

[0127] Specifically, when the third voltage signal terminal LVGL is low, the tenth transistor T10 is in the on state under the control of the pull-up node PU, and provides the low-level signal of the third voltage signal terminal LVGL to the first pull-down node PD1; when the eleventh transistor T11 is in the on state under the control of the pull-up node PU, it provides the low-level signal of the third voltage signal terminal LVGL to the gate of the ninth transistor T9, and the ninth transistor T9 is turned off.

[0128] The second reset module 170 is connected to the pull-up node PU, the second reset signal terminal T-reset, and the third voltage signal terminal LVGL. The second reset module 170 is used to control the level signal of the third voltage signal terminal LVGL to be provided to the pull-up node PU according to the level signal of the second reset signal terminal T-reset.

[0129] The second reset module 170 includes a twelfth transistor T12. The gate of the twelfth transistor T12 is connected to the second reset signal terminal T-reset, the first terminal is connected to the third voltage signal terminal LVGL, and the second terminal is connected to the pull-up node PU.

[0130] Specifically, when the twelfth transistor T12 is in the on state under the control of the second reset signal terminal T-reset, it provides the low-level signal of the third voltage signal terminal LVGL to the pull-up node PU.

[0131] During the forward scan input phase, the first input signal INF is high, and the first transistor T1, the second transistor T2, and the fourteenth transistor T14 are simultaneously turned on. The turned-on first transistor T1 provides a high-level first control signal U2D to the pull-up node PU, thereby pulling the level of the pull-up node PU high and storing the high level in the first capacitor C1. At this time, the seventh transistor T7 and the seventeenth transistor T17 are turned on under the drive of the high level of the pull-up node PU. Since the first clock signal terminal CLK is low, the low level of the first clock signal terminal CLK is provided to the scan signal output terminal Gout and the cascade signal output terminal Cout through the seventh transistor T7 and the seventeenth transistor T17, respectively. Therefore, both the scan signal output terminal Gout and the cascade signal output terminal Cout output low-level signals. The turned-on second transistor T2 provides a low-level second control signal D2U to the first pull-down node PD1, thereby directly pulling the level on the first pull-down node PD1 low. Therefore, the first module 110 can directly pull down the first pull-down node PD1 when charging the pull-up node PU, which can avoid the pull-up node PU failing to compete with the first pull-down node PD1, causing the pull-up node PU to fail to rise normally; even if the gate drive circuit has been working for a long time or under low temperature environment, causing the conduction current Ion to decay and the charging current to be insufficient, the pull-up node PU can still achieve normal potential rise, and the stability of the circuit operation is guaranteed.

[0132] During the forward scan output phase, the first input signal INF is low, and the first transistor T1, the second transistor T2, and the fourteenth transistor T14 are cut off. However, since the first capacitor C1 has already stored the high-level signal of the first input signal INF from the forward scan input phase, the pull-up node PU remains high. The high-level pull-up node PU keeps the seventh transistor T7 and the seventeenth transistor T17 conducting. The input signal of the first clock signal terminal CLK becomes high. Due to the bootstrap effect of the transistors, the level of the pull-up node PU continues to be pulled high, amplifying the level of the pull-up node PU. Both the scan signal output terminal Gout and the cascade signal output terminal Cout output high-level gate drive signals. The increase in the level of the pull-up node PU improves the charging capability of the seventh transistor T7 and the seventeenth transistor T17, ensuring the pixel charging level.

[0133] During the first reset phase of the forward scan, the second input signal INB is high, and the third transistor T3, the fourth transistor T4, and the fifteenth transistor T15 are simultaneously turned on. The turned-on third transistor T3 provides the low-level second control signal D2U to the pull-up node PU, thereby pulling the level of the pull-up node PU down to a low level. The turned-on fourth transistor T4 provides the high-level first control signal U2D to the first pull-down node PD1, pulling the level of the first pull-down node PD1 up to a high level. Therefore, after the signal output of the current row shift register unit ends, the second module 120 can actively pull down the pull-up node PU and simultaneously pull up the potential of the first pull-down node PD1; this can improve the problem of the slow rise rate of the first pull-down node PD1 level during the operation of the gate drive circuit; if the rise rate of the first pull-down node PD1 level is slow, the display panel is very susceptible to electrostatic disturbances during this phase, resulting in display defects. Therefore, the second module 120 can optimize the node charging speed, suppress the risk of electrostatic interference, and thus effectively improve the reliability of the display panel.

[0134] Similarly, in reverse scan mode, the second module 120 can directly pull down the first pull-down node PD1 while charging the pull-up node PU, avoiding the situation where the pull-up node PU cannot compete with the first pull-down node PD1, thus preventing the pull-up node PU from rising normally. Even if the gate drive circuit experiences a decrease in conduction current Ion or insufficient charging current due to long-term operation or low-temperature environment, the pull-up node PU can still achieve normal potential rise, ensuring the stability of the circuit operation. After the signal output terminal of the current row shift register unit finishes outputting the signal, the first module 110 can actively pull down the pull-up node PU and simultaneously pull up the potential of the first pull-down node PD1. This can improve the problem of the slow rise rate of the first pull-down node PD1 level during the operation of the gate drive circuit. If the rise rate of the first pull-down node PD1 level is slow, the display panel is very susceptible to electrostatic disturbances during this stage, resulting in display defects. Therefore, the first module 110 can optimize the node charging speed, suppress the risk of electrostatic interference, and thus effectively improve the reliability of the display panel.

[0135] Similarly, the second pull-down module 132, the second pull-down control module 152, and the second pull-up module 162 have the same structure as the first pull-down module 131, the first pull-down control module 151, and the first pull-up module 161 and operate in a time-sharing manner.

[0136] The second pull-down module 132 is connected to the pull-up node PU, the second pull-down node PD2, the first voltage signal terminal VGL, the third voltage signal terminal LVGL, the cascaded signal output terminal Cout, and the scan signal output terminal Gout, respectively.

[0137] Specifically, the second pull-down module 132 includes an eighth transistor T8, a twentieth transistor T20, and a nineteenth transistor T19. The gate of the eighth transistor T8 is connected to the second pull-down node PD2, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the pull-up node PU. The gate of the twentieth transistor T20 is connected to the second pull-down node PD2, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the cascaded signal output terminal Cout. The gate of the nineteenth transistor T19 is connected to the second pull-down node PD2, its first terminal is connected to the first voltage signal terminal VGL, and its second terminal is connected to the scan signal output terminal Gout.

[0138] The second pull-down control module 152 is connected to the second voltage signal terminal 2 VGH2 and the second pull-down node PD2, respectively.

[0139] Specifically, the second pull-down control module 152 includes a twenty-first transistor T21 and a twenty-second transistor T22. The gate of the twenty-second transistor T22 is connected to the second voltage signal terminal 2 VGH2, the first terminal is connected to the second voltage signal terminal 2 VGH2, and the second terminal is connected to the gate of the twenty-second transistor T22. The first terminal of the twenty-second transistor T22 is connected to the second voltage signal terminal 2 VGH2, and the second terminal is connected to the second pull-down node PD2.

[0140] The second pull-up module 162 is connected to the pull-up node PU, the second pull-down node PD2, and the third voltage signal terminal LVGL.

[0141] Specifically, the second pull-up module 162 includes a twenty-third transistor T23 and a twenty-fourth transistor T24. The gate of the twenty-third transistor T23 is connected to the pull-up node PU, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the second pull-down node PD2. The gate of the twenty-fourth transistor T24 is connected to the pull-up node PU, its first terminal is connected to the third voltage signal terminal LVGL, and its second terminal is connected to the gate of the twenty-second transistor T22.

[0142] Similarly, this module, in conjunction with the first module 110, the second module 120, the output module 140, and the second reset module 170, can also directly pull down the second pull-down node PD2 while charging the pull-up node PU in either forward or reverse scanning mode. This avoids the pull-up node PU failing to rise properly due to competition with the second pull-down node PD2. Furthermore, after the signal output of the current row shift register unit ends, the second module 120 or the first module 110 can actively pull down the pull-up node PU and simultaneously pull up the potential of the second pull-down node PD2. This can improve the problem of the slow rise rate of the second pull-down node PD2 level during the operation of the gate drive circuit. If the rise rate of the second pull-down node PD2 level is slow, the display panel is easily affected by electrostatic disturbances during this stage, resulting in display defects.

[0143] The shift register unit provided in this embodiment of the invention, when performing forward scanning of the display panel in the display device, can use the thin-film transistor in the first module 110 to actively pull up the level signal of the pull-up node PU and actively pull down the level signals of the first pull-down node PD1 and the second pull-down node PD2 in response to the first input signal INF during the input phase; and use the thin-film transistor in the second module 120 to actively pull down the level signal of the pull-up node PU and actively pull up the level signals of the first pull-down node PD1 and the second pull-down node PD2 in response to the second input signal INB during the reset phase to reset. When performing a reverse scan of the display panel, the thin-film transistor in the second module 120 can actively pull up the level signal of the pull-up node PU and actively pull down the level signals of the first pull-down node PD1 and the second pull-down node PD2 in response to the second input signal INB during the input phase. Similarly, the thin-film transistor in the first module 110 can actively pull down the level signal of the pull-up node PU and actively pull up the level signals of the first pull-down node PD1 and the second pull-down node PD2 to reset the display panel during the reset phase, in response to the first input signal INF. This allows for forward or reverse scanning of the display panel, where the first pull-down node PD1 or the second pull-down node PD2 can be pulled down directly during the input phase while charging the pull-up node PU. This prevents the pull-up node PU from failing to rise properly due to competition with the first pull-down node PD1 or the second pull-down node PD2. Even if the gate drive circuit experiences a decrease in conduction current Ion or insufficient charging current due to long-term operation or low-temperature environments, the pull-up node PU can still achieve a normal potential rise, ensuring circuit stability. During the first reset phase, i.e., after the output signal of the current row shift register unit's signal output terminal Gout ends, the pull-up node PU can be actively pulled down, and the potential of the first pull-down node PD1 or the second pull-down node PD2 can be pulled up simultaneously. This can improve the problem of the slow rise rate of the first pull-down node PD1 or the second pull-down node PD2 level during the operation of the gate drive circuit. If the rise rate of the first pull-down node PD1 or the second pull-down node PD2 level is slow, the display panel is very susceptible to electrostatic disturbances during this phase, resulting in display defects. Therefore, the second module 120 can optimize the node charging speed, suppress the risk of electrostatic interference, and thus effectively improve the reliability of the display panel.

[0144] Furthermore, because this gate drive circuit can actively control the pull-up or pull-down levels of the pull-up node PU and the pull-down node PD, the size of the transistors involved in the level competition between the pull-up node PU and the pull-down node PD can be optimized and adjusted significantly. Especially in narrow-bezel display panel products, the device size of these transistors can be further reduced, which is beneficial for achieving miniaturized circuit design.

[0145] Based on the same inventive concept, embodiments of the present invention also provide a gate driving circuit, such as... Figure 8 As shown, the gate drive circuit 10 provided in this embodiment includes multiple cascaded shift register units (VSRs). Each shift register unit (VSR) is any of the shift register units (VSRs) provided in this embodiment of the invention. Their implementation principles and effects are similar, so they will not be described in detail here.

[0146] The signal output terminal OUT(n) of the nth-stage shift register unit VSR outputs a gate drive signal to the nth row scan line SL of the display area. The first input signal INF of the nth-stage shift register unit VSR is connected to the signal output terminal OUT(nj) of the nj-th-stage shift register unit, where j is a natural number greater than 0. The second input signal INB of the nth-stage shift register unit is connected to the signal output terminal OUT(n+h) of the (n+h)-th-stage shift register unit, where h is a natural number greater than 0.

[0147] Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, such as... Figure 9 As shown, the display panel 100 includes a gate driving circuit 10 provided in any embodiment of the present invention.

[0148] The display panel 100 has two operating modes: forward scanning mode and reverse scanning mode. In forward scanning mode, the first control signal U2D is active and the second control signal D2U is inactive; in reverse scanning mode, the first control signal U2D is inactive and the second control signal D2U is active.

[0149] It should be noted that when the gate driving circuit 10 provided in the embodiments of the present invention is applied to the display panel 100, it can be located in the display area (not shown in the figure) of the display panel 100 or in the non-display area (not shown in the figure) of the display panel 100. When the gate driving circuit 10 is located in the non-display area, the gate driving circuit 10 can be located on any one side, two sides, three sides or four sides of the display area. The embodiments of the present invention do not limit the position of the gate driving circuit 10 in the display panel 100.

[0150] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 10 As shown, the display device 1000 includes a display panel 100 provided in any embodiment of the present invention. The display device 1000 provided in the embodiments of the present invention can be... Figure 10The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0151] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register unit, characterized in that, include: First module, second module, output module, pull-up node, pull-down node, and signal output terminal; The first module is connected to the first input signal, the first control signal, the second control signal, the pull-up node, and the pull-down node. The second module is connected to the second input signal, the first control signal, the second control signal, the pull-up node, and the pull-down node. The output module is connected to the first clock signal terminal CLK, the pull-up node, and the signal output terminal.

2. The shift register unit according to claim 1, characterized in that, The first module includes a first transistor and a second transistor. The gate of the first transistor is connected to the first input signal, the first terminal of the first transistor is connected to the first control signal, and the second terminal of the first transistor is connected to the pull-up node. The gate of the second transistor is connected to the first input signal, the first terminal of the second transistor is connected to the second control signal, and the second terminal of the second transistor is connected to the pull-down node. The second module includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the second input signal, the first terminal of the third transistor is connected to the second control signal, and the second terminal of the third transistor is connected to the pull-up node. The gate of the fourth transistor is connected to the second input signal, the first terminal of the fourth transistor is connected to the first control signal, and the second terminal of the fourth transistor is connected to the pull-down node.

3. The shift register unit according to claim 1, characterized in that, The output module includes a seventh transistor and a first capacitor; the gate of the seventh transistor is connected to the pull-up node, the first terminal is connected to the first clock signal terminal, and the second terminal is connected to the signal output terminal; the first capacitor is connected between the pull-up node and the signal output terminal.

4. The shift register unit according to claim 1, characterized in that, It also includes a pull-down module, a pull-down control module, a pull-up module, and a second reset module; the pull-down module is connected to the pull-up node, the pull-down node, the signal output terminal, and the first voltage signal terminal; the pull-down control module is connected to the second voltage signal terminal and the pull-down node; the pull-up module is connected to the pull-up node, the pull-down node, the pull-down control module, and the first voltage signal terminal; the second reset module is connected to the second reset signal terminal, the pull-up node, the first voltage signal terminal, and the signal output terminal.

5. The shift register unit according to claim 4, characterized in that, The pull-down module includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is connected to the pull-down node, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the pull-up node. The gate of the sixth transistor is connected to the pull-down node, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the signal output terminal.

6. The shift register unit according to claim 4, characterized in that, The pull-down control module includes an eighth transistor and a ninth transistor. The gate of the eighth transistor is connected to the second voltage signal terminal, the first terminal is connected to the second voltage signal terminal, and the second terminal is connected to the gate of the ninth transistor. The first terminal of the ninth transistor is connected to the second voltage signal terminal, and the second terminal is connected to the pull-down node.

7. The shift register unit according to claim 6, characterized in that, The pull-up module includes a tenth transistor and an eleventh transistor. The gate of the tenth transistor is connected to the pull-up node, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the pull-down node. The gate of the eleventh transistor is connected to the pull-up node, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the gate of the ninth transistor.

8. The shift register unit according to claim 4, characterized in that, The second reset module includes a twelfth transistor and a thirteenth transistor. The gate of the twelfth transistor is connected to the second reset signal terminal, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the pull-up node. The gate of the thirteenth transistor is connected to the second reset signal terminal, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the signal output terminal.

9. The shift register unit according to claim 1, characterized in that, The drop-down node includes a first drop-down node and a second drop-down node, and the signal output terminal includes a cascaded signal output terminal and a scan signal output terminal.

10. The shift register unit according to claim 9, characterized in that, The first module includes a first transistor, a second transistor, and a fourteenth transistor; the gate of the first transistor is connected to the first input signal, the first terminal is connected to the first control signal, and the second terminal is connected to the pull-up node; the gate of the second transistor is connected to the first input signal, the first terminal is connected to the second control signal, and the second terminal is connected to the first pull-down node; the gate of the fourteenth transistor is connected to the first input signal, the first terminal is connected to the second control signal, and the second terminal is connected to the second pull-down node. The second module includes a third transistor, a fourth transistor, and a fifteenth transistor. The gate of the third transistor is connected to the second input signal, the first terminal is connected to the second control signal, and the second terminal is connected to the pull-up node. The gate of the fourth transistor is connected to the second input signal, the first terminal is connected to the first control signal, and the second terminal is connected to the first pull-down node. The gate of the fifteenth transistor is connected to the second input signal, the first terminal is connected to the first control signal, and the second terminal is connected to the second pull-down node.

11. The shift register unit according to claim 9, characterized in that, The output module includes a seventh transistor, a seventeenth transistor, and a first capacitor; the gate of the seventh transistor is connected to the pull-up node, the first terminal is connected to the first clock signal terminal, and the second terminal is connected to the scan signal output terminal. The gate of the seventeenth transistor is connected to the pull-up node, the first terminal is connected to the first clock signal terminal, and the second terminal is connected to the cascaded signal output terminal.

12. The shift register unit according to claim 9, characterized in that, It also includes a pull-down module, a pull-down control module, a pull-up module, and a second reset module; the pull-down module includes a first pull-down module and a second pull-down module; the pull-down control module includes a first pull-down control module and a second pull-down control module; the pull-up module includes a first pull-up module and a second pull-up module.

13. The shift register unit according to claim 12, characterized in that, The first pull-down module includes a fifth transistor, a sixteenth transistor, and a sixth transistor; the gate of the fifth transistor is connected to the first pull-down node, the first terminal is connected to the third voltage signal terminal, and the second terminal is connected to the pull-up node; The gate of the sixteenth transistor is connected to the first pull-down node, the first terminal is connected to the third voltage signal terminal, and the second terminal is connected to the cascaded signal output terminal; the gate of the sixth transistor is connected to the first pull-down node, the first terminal is connected to the first voltage signal terminal, and the second terminal is connected to the scan signal output terminal.

14. The shift register unit according to claim 12, characterized in that, The first pull-down control module includes an eighth transistor and a ninth transistor; the gate of the eighth transistor is connected to the second voltage signal terminal 1, the first terminal is connected to the second voltage signal terminal 1, and the second terminal is connected to the gate of the ninth transistor; the first terminal of the ninth transistor is connected to the second voltage signal terminal 1, and the second terminal is connected to the first pull-down node.

15. The shift register unit according to claim 14, characterized in that, The first pull-up module includes a tenth transistor and an eleventh transistor; the gate of the tenth transistor is connected to the pull-up node, the first terminal is connected to the third voltage signal terminal, and the second terminal is connected to the first pull-down node; the gate of the eleventh transistor is connected to the pull-up node, the first terminal is connected to the third voltage signal terminal, and the second terminal is connected to the gate of the ninth transistor.

16. The shift register unit according to claim 12, characterized in that, The second reset module includes a twelfth transistor, the gate of which is connected to a second reset signal terminal, the first terminal of which is connected to a third voltage signal terminal, and the second terminal of which is connected to the pull-up node.

17. A gate driving circuit, characterized in that, include: Multiple cascaded shift register units, wherein the shift register unit is a shift register unit as described in any one of claims 1-16.

18. A display panel, characterized in that, Includes the gate drive circuit as described in claim 17.

19. The display panel according to claim 18, characterized in that, The display panel has two operating modes: a forward scanning mode and a reverse scanning mode. In the forward scanning mode, the first control signal is active and the second control signal is inactive. In the reverse scanning mode, the first control signal is inactive and the second control signal is active.

20. A display device, characterized in that, Includes the display panel as described in claim 19.

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