Display device and driving method thereof

Abstract

The application discloses a display device and a driving method thereof, and relates to the technical field of display, the display device comprising a display panel and a wireless charging assembly, the display panel comprising a plurality of display units, a display driving circuit, a wireless charging driving circuit, a plurality of scanning lines and a plurality of data lines; the display driving circuit provides the display units with scanning signals and data signals; the wireless charging driving circuit provides the wireless charging assembly with charging signals comprising periodic pulse signals; the scanning lines transmit the scanning signals, and the data lines transmit the data signals; the display time of one frame of picture comprises a plurality of row driving stages, and each row driving stage comprises a writing period; in the writing period, the scanning signals are at an enabling level, and the plurality of display units write the data signals; the time length of each row driving stage is an integer multiple of a quarter period of the charging signals. By using the above technical scheme, the display abnormal phenomenon of water ripples can be solved during wireless charging, and the display effect is effectively improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display device and its driving method. Background Technology

[0002] More and more display devices are using wireless charging technology. Wireless charging, also known as inductive charging or non-contact inductive charging, uses near-field induction, or inductive coupling, to transfer energy from a power supply device (such as a charger) to a device with a display function (such as a mobile phone, computer, or other electronic device). The device can then use the received energy to charge its battery and power its own operation.

[0003] However, in some cases, the wireless charging structure within the electronic device can interfere with the display during its operation, causing undesirable display distortion. For example, when the wireless charging structure is working, the wireless charging signal may parasitically couple with the data line, causing abnormal fluctuations in the data signal transmitted on the data line, resulting in a water ripple-like display abnormality on the screen.

[0004] Therefore, how to solve the problem of display abnormalities such as water ripples caused by interference with display devices during wireless charging has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a display device and its driving method to solve the problem that display devices are prone to display abnormalities and poor display effects when wirelessly charging.

[0006] According to one aspect of this application, a display device is provided, comprising: a display panel and a wireless charging component, wherein the display panel includes a driving circuit and a plurality of display units; The driving circuit includes a display driving circuit and a wireless charging driving circuit; The display driving circuit is electrically connected to the display unit and is configured to provide display driving signals to the display unit. The wireless charging driver circuit is electrically connected to the wireless charging component and is configured to provide a charging signal to the wireless charging component; wherein the charging signal includes a periodic pulse signal. The display panel includes multiple scan lines and multiple data lines; the scan lines are electrically connected to multiple display units arranged in rows along a first direction, and the data lines are electrically connected to multiple display units arranged in columns along a second direction, wherein the first direction and the second direction intersect. The display drive signals include scan signals and data signals. The scan lines are configured to transmit scan signals, and the data lines are configured to transmit data signals. The display time of one frame includes multiple line driving stages, and the line driving stage includes a writing period. During the writing period, the scan signal is at the enable level, and multiple display units arranged in rows along the first direction write data signals. The duration of the line drive phase is an integer multiple of a quarter cycle of the charging signal.

[0007] According to another aspect of this application, a driving method for a display device is provided, the driving method being used to drive the display device to operate; The driving method includes: the duration of the row driving phase is an integer multiple of a quarter cycle of the charging signal.

[0008] The technical solution of this application sets the duration of the row driving phase to an integer multiple of a quarter cycle of the charging signal. This ensures that the sum of the durations of four adjacent row driving phases is an integer multiple of the charging signal cycle. Thus, every four row driving phases, the writing period can overlap with the same phase in the charging signal cycle. The charging signal can periodically couple and influence the data signal written to the display unit. The coupling influence period is four rows of display units. This allows the same coupling influence to be presented every four rows of display units. The periodically set adjacent four rows of display units can present different abnormal displays of brightness or darkness. The abnormal display period is four rows of display units. In one abnormal display period, when one or more rows of display units are too bright or too dark, the brightness deviation of other rows of display units in the same abnormal display period can be used to perform brightness equalization or brightness cancellation. This helps to improve the display abnormality problem caused by the coupling of the charging signal with the data signal, and avoids multiple consecutive rows of display units being too bright or too dark, resulting in a water ripple effect that affects the display effect of the display device.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 2 This is a timing diagram illustrating the operation of a display device according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a display unit provided in an embodiment of this application; Figure 4 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 5 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 6 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 7 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 8 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 9 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 10 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 11 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 12 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 13 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 14 This is a schematic diagram of another display device provided in an embodiment of this application; Figure 15 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 16 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 17 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 18 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 19 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 20 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 21 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 22 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 23 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 24 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 25 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 26 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 27 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 28 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 29 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 30 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 31 This is a timing diagram illustrating the operation of another display device provided in this application embodiment; Figure 32 This is a flowchart of a driving method for a display device provided in an embodiment of the present invention. Detailed Implementation

[0012] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0013] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0014] As described in the background section, during wireless charging, the wireless charging signal couples with the data signal in the display device, causing a ripple effect on the screen. Related technologies typically enhance the driving capability of the data cable to weaken the interference from the wireless charging signal. While this reduces the coupling effect of the wireless charging signal on the data signal, it increases power consumption, failing to meet low-power requirements. To meet low-power requirements and reduce the voltage of the data signal, related technologies also employ methods such as adding a shielding structure to the display panel to minimize interference signals during wireless charging. However, this method increases the size of the display device, hindering module thinning, and the shielding effect is not ideal; the interference signals generated during wireless charging still affect the display to some extent, failing to address the problem of display abnormalities and poor display quality during wireless charging.

[0015] To address the aforementioned technical problems, this application provides a display device, comprising: a display panel and a wireless charging component. The display panel includes a driving circuit and multiple display units; the driving circuit includes a display driving circuit and a wireless charging driving circuit; the display driving circuit is electrically connected to the display units and configured to provide a display driving signal to the display units; the wireless charging driving circuit is electrically connected to the wireless charging component and configured to provide a charging signal to the wireless charging component; wherein the charging signal includes a periodic pulse signal; the display panel includes multiple scan lines and multiple data lines; the scan lines are electrically connected to multiple display units arranged in rows along a first direction, and the data lines are electrically connected to multiple display units arranged in columns along a second direction, the first direction and the second direction intersecting; the display driving signal includes a scan signal and a data signal, the scan lines are configured to transmit scan signals, and the data lines are configured to transmit data signals; the display time of one frame includes multiple row driving stages, each row driving stage including a write period, during which the scan signal is at an enable level, and the multiple display units arranged in rows along the first direction write data signals; wherein the duration of the row driving stage is an integer multiple of one-quarter of the charging signal cycle.

[0016] By adopting the above technical solution, by setting the duration of the row driving phase to an integer multiple of a quarter cycle of the charging signal, the sum of the durations of four adjacent row driving phases can be an integer multiple of the charging signal cycle. In this way, every four row driving phases, the writing period can overlap with the same phase in the charging signal cycle. The charging signal can periodically couple and affect the data signal written to the display unit. The coupling effect period is four rows of display units. This allows the same coupling effect to be presented every four rows of display units. The periodically set adjacent four rows of display units can present different abnormal displays of brightness or darkness. The abnormal display period is four rows of display units. In a four-row display unit abnormal display period, when one or more rows of display units are too bright or too dark, the brightness deviation of other rows of display units in the same abnormal display period can be used to perform brightness equalization or brightness cancellation. This helps to improve the display abnormality problem caused by the coupling of the charging signal with the data signal, and avoids multiple rows of display units being too bright or too dark, resulting in a water ripple phenomenon that affects the display effect of the display device.

[0017] The above is the core idea of ​​this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0018] It should be noted that the implementation methods provided in this application can be combined with each other without contradiction.

[0019] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 2 This is a timing diagram illustrating the operation of a display device according to an embodiment of this application. (Refer to...) Figure 1 and Figure 2 The display device 001 includes a display panel 010 and a wireless charging component 020. The display panel 010 includes a driving circuit 100 and a plurality of display units 200. The driving circuit 100 includes a display driving circuit 110 and a wireless charging driving circuit 120. The display driving circuit 110 is electrically connected to the display units 200 and is configured to provide a display driving signal to the display units 200. The wireless charging driving circuit 120 is electrically connected to the wireless charging component 020 and is configured to provide a charging signal wsc to the wireless charging component 020. The charging signal wsc includes a periodic pulse signal.

[0020] The display panel 010 also includes multiple scan lines SL and multiple data lines DL; the scan lines SL are electrically connected to multiple display units 200 arranged in rows along the first direction X, and the data lines DL are electrically connected to multiple display units 200 arranged in columns along the second direction Y, wherein the first direction X and the second direction Y intersect; the display driving signal includes a scan signal scan and a data signal data, the scan lines SL are configured to transmit the scan signal scan, and the data lines DL are configured to transmit the data signal data.

[0021] The display time DF of one frame includes multiple line driving phases H, and the line driving phase H includes a writing period t1. During the writing period t1, the scan signal scan is enabled, and multiple display units 200 arranged along the first direction X row write data signal data. The duration of the line driving phase H is an integer multiple of one-quarter cycle of the charging signal wsc.

[0022] The display panel 010 is a structure in the display device 001 used to display images. In some embodiments, the display panel 010 includes a substrate ( Figure 1 and Figure 2 (not shown in the image) and thin-film transistors located on one side of the substrate ( Figure 1 and Figure 2 (not shown in the image), signal traces (e.g., scan line SL, data line DL), light-emitting elements ( Figure 1 and Figure 2 The display panel 010 includes, but is not limited to, liquid crystal display panels, organic light-emitting diode display panels, micro light-emitting diode display panels, and other display panels, etc., to realize the display function.

[0023] The wireless charging component 020 can be used to provide charging and battery life functions for the display panel 010. In some embodiments, the wireless charging component 020 includes an inductor coil structure or other structures that can realize wireless charging functions. The embodiments of this application do not specifically limit this. In some embodiments, the wireless charging component 020 can receive electrical energy using the inductive coupling effect and transmit the electrical energy to the display panel 010 so that the display panel 010 can use the electrical energy received by the wireless charging component 020 to perform display.

[0024] The display panel 010 includes a driving circuit 100 and a plurality of display units 200. In some embodiments, the driving circuit 100 can receive signals provided by a driving chip and / or a flexible circuit board. Figure 1 and Figure 2 (Not shown in the diagram), and converts the signals provided by the driver chip and / or flexible circuit board into drive signals and provides them to the display unit 200 or the wireless charging component 020. The driver circuit 100 includes a display driver circuit 110. In some embodiments, the display driver circuit 110 includes a gate driver circuit 111 and a source driver circuit 112. The gate driver circuit 111 includes a plurality of cascaded shift register units SRU. The gate driver circuit 111 can provide a plurality of sequentially shifted scan signals scan to the multi-row display unit 200. The source driver circuit 112 can provide a plurality of data signals data to the multi-column display unit. The display unit 200 includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit ( Figure 1 and Figure 2 (Not shown in the image) Pixel circuits include, but are not limited to, pixel circuits such as 2T1C, 7T1C, and 8T1C. When the scan signal it receives is at the enable level, the pixel circuit can write the data signal data transmitted on the data line DL it is electrically connected to, and provide the corresponding driving current to the light-emitting element according to the data signal data, thereby controlling the light-emitting element to display the corresponding brightness so that the display panel 010 can display the image.

[0025] In some implementations... Figure 3 This is a schematic diagram of the structure of a display unit provided in an embodiment of this application, with reference to... Figure 3The pixel circuit PC of the display unit 200 includes at least a driving transistor M1 and a writing transistor M2. The gate of the writing transistor M2 is electrically connected to the scan line SL and receives the scan signal scan. When the scan signal scan is at the enable level, the writing transistor M2 is turned on. The first terminal of the writing transistor M2 is electrically connected to the data line DL and receives the data signal data. The second terminal of the writing transistor M2 is electrically connected to the gate of the driving transistor M1. The first terminal of the driving transistor M1 receives the first power supply signal pvdd. A storage capacitor C can also be provided between the first power supply signal pvdd and the gate of the driving transistor M1. The second terminal of the driving transistor M1 is connected to one end of the light-emitting element OLED, and the other end of the light-emitting element OLED receives the second power supply signal pvee. The driving transistor M1 and the writing transistor M2 can be either N-type transistors or P-type transistors. This application embodiment does not limit the types of transistors. For ease of understanding and explanation, unless otherwise specified, this application embodiment uses P-type transistors as an example, in which case the enable level is low.

[0026] It should be noted that, Figure 1 The example shown only illustrates a non-display area NA where the gate driving circuit 111 is located along the first direction X on one side of the display area AA, and a non-display area NA where the source driving circuit 112 is located along the second direction Y on one side of the display area AA. In other embodiments, the gate driving circuit 111 and the source driving circuit 112 may also be located in other non-display areas NA, or the gate driving circuit 111 and the source driving circuit 112 may also be located in the display area AA. The embodiments of this application do not limit the position of the gate driving circuit 111 and the source driving circuit 112.

[0027] The driving circuit 100 also includes a wireless charging driving circuit 120. In some embodiments, the charging signal of the wireless charging driving circuit 120 can be provided by a driving chip or a flexible circuit board. In some embodiments, the wireless charging driving circuit 120 can be located within any non-display area NA. This application does not specifically limit the location of the wireless charging driving circuit 120, as long as it is electrically connected to the wireless charging component 020. The wireless charging signal provided by the driving chip or flexible circuit board can be transmitted to the wireless charging component 020 through the wireless charging driving circuit 120, controlling the wireless charging component 020 to provide charging functionality to the display device 001. When the display device 001 is wirelessly charging, the wireless charging driving circuit 120 transmits the charging signal wsc to the wireless charging component 020. The periodic pulse signal of the charging signal wsc will couple with the data signal data transmitted to the data line DL, causing abnormal fluctuations in the data signal written by the display unit 200, affecting the brightness of the display unit 200.

[0028] The display time DF of one frame is the complete display cycle of one frame, that is, the total time occupied by displaying one frame of image, which is also the time for the display panel 010 to refresh one frame. In some embodiments, the display driving circuit 110 includes an oscillation unit for generating an oscillation clock signal ( Figure 1 and Figure 2 (Not shown in the image) The display driving circuit 110 can generate a horizontal synchronization signal by counting the oscillating clock signal. The horizontal synchronization signal includes multiple horizontal trigger pulses ( Figure 1 and Figure 2 (Not shown in the image) The period of the row trigger pulse is the driving time of a row display unit 200, and the time interval between the start times of two adjacent row trigger pulses is the row driving phase H. The gate driving circuit 111 can provide multiple scan signals scan, which are shifted sequentially, to multiple scan lines SL by receiving the start signal STV and clock signals CK and XCK generated based on the row synchronization signal. In the row driving phase H, the gate driving circuit 111 outputs an enable level of a scan signal scan, which can control the write transistor M2 in the row display unit 200 to be turned on. The source driving circuit 112 can generate multiple data signals data based on the image data and the row synchronization signal. In the row driving phase H, the source driving circuit 112 can output the data signal data of the row display unit 200.

[0029] In some implementations, the time DF of a frame includes n line driving stages H, where n is the number of rows of the display unit 200. During the time DF of a frame, the m-th line driving stage H includes the m-th write period t1. Along the direction of the cascaded shift register units SRU, the gate driving circuit 111 provides the enable level of the scan signal scan to the m-th scan line SL to control the write transistor M2 in the m-th row display unit 200 to be turned on, allowing the m-th row display unit 200 to write the data signal transmitted on the data line DL. During the m-th line driving stage H, the source driving circuit 112 provides the data signal data of the m-th row display unit 200 to multiple data lines DL, enabling the data signal data of the m-th row display unit 200 transmitted on multiple data lines DL to be written to the m-th row display unit 200.

[0030] In some embodiments, the display device 001 includes a wireless charging phase TW, during which the wireless charging drive circuit 120 provides a charging signal wsc to the wireless charging component 020, the charging signal wsc including a periodic pulse signal; the wireless charging phase TW may overlap with multiple line drive phases H of a frame time DF, and / or the wireless charging phase TW may overlap with multiple write periods t1 of a frame time DF.

[0031] In some implementations, the periodic pulse signal of the charging signal wsc includes a rising phase ta, a peak phase tb, a falling phase tc, and a trough phase td within one period tsc of the charging signal wsc.

[0032] The rising phase ta lies between the trough phase td and the peak phase tb, and it occurs after the trough phase td and before the peak phase tb. During the rising phase ta, the potential of the charging signal wsc increases, which in turn increases the potential of the data signal data on the data line DL. In one embodiment, during the rising phase ta, the absolute value of the rate of change of the charging signal wsc's potential is relatively large, resulting in a stronger coupling effect on the data signal data.

[0033] The peak phase tb is located between the rising phase ta and the falling phase tc, following the rising phase ta and preceding the falling phase tc. During the peak phase tb, the potential of the charging signal wsc first increases and then decreases, which in turn couples to the data signal data on the data line DL, causing the potential to first increase and then decrease. In one embodiment, the highest potential of the charging signal wsc is located at the center of the peak phase tb. In another embodiment, during the peak phase tb, the absolute value of the rate of change of the charging signal wsc's potential is relatively small, resulting in a weaker coupling effect on the data signal data.

[0034] The falling phase tc lies between the peak phase tb and the trough phase td, and it occurs after the peak phase tb and before the trough phase td. During the falling phase tc, the potential of the charging signal wsc decreases, which in turn reduces the potential of the data signal data on the data line DL. In one embodiment, during the falling phase tc, the absolute value of the rate of change of the charging signal wsc's potential is relatively large, resulting in a stronger coupling effect on the data signal data.

[0035] The trough phase td lies between the falling phase tc and the rising phase ta, and it occurs after the falling phase tc and before the rising phase ta. During the trough phase td, the potential of the charging signal wsc first decreases and then increases, which in turn couples to the potential of the data signal data on the data line DL, causing the potential to first decrease and then increase. In one embodiment, the lowest point of the charging signal wsc's potential is located at the center of the trough phase td. In another embodiment, during the trough phase td, the absolute value of the rate of change of the charging signal wsc's potential is relatively small, resulting in a weaker coupling effect on the data signal data.

[0036] In some implementations, the durations of the rising phase ta, peak phase tb, falling phase tc, and trough phase td are all one-quarter of the cycle of the charging signal wsc; that is, the durations of the rising phase ta, peak phase tb, falling phase tc, and trough phase td are all twice the duration of one-quarter of the cycle of the charging signal wsc. In other implementations, the durations of the rising phase ta and falling phase tc can be greater than the durations of the peak phase tb and trough phase td; that is, the durations of the rising phase ta and falling phase tc can be greater than one-quarter of the cycle of the charging signal wsc, and the durations of the peak phase tb and trough phase td can be less than one-quarter of the cycle of the charging signal wsc.

[0037] The duration of the line drive phase H is an integer multiple of a quarter-cycle of the charging signal wsc. The line drive phase H may overlap with at least one of the rising phase ta, peak phase tb, falling phase tc, and trough phase td. When the duration of the line drive phase H is twice the quarter-cycle of the charging signal wsc, the duration of the line drive phase H may be a quarter-cycle of the charging signal wsc. In one embodiment, the line drive phase H may overlap with only one of the rising phase ta, peak phase tb, falling phase tc, and trough phase td.

[0038] For example, taking the duration of the row driving phase H as being one-quarter of the cycle of the charging signal wsc as an example, refer to... Figure 2 , Figure 2 The diagram illustrates the changes in the eight scan signals scan(1) to scan(8) on the first eight scan lines SL during the first eight line drive stages H of a frame in time DF, along the direction of the cascaded shift register units SRU, and the changes in the data signals data of the first eight lines of display units 200 transmitted on the data line DL along the direction of the cascaded shift register units SRU. Figure 2 In the timing diagram, the horizontal dashed line represents the set value of the data signal data on the data line DL. The set value enables the display unit 200 to display the set brightness. In different row driving stages H, the set value of the data signal data on the data line DL can be the same or different. The solid line of the data signal data on the data line DL represents the change of the data signal data on the data line DL relative to the set value. A solid line above the dashed line indicates that the data signal data on the data line DL is coupled high. A solid line above the dashed line indicates that the data signal data on the data line DL is basically equal to the set value. A solid line below the dashed line indicates that the data signal data on the data line DL is coupled low. The same applies to other timing diagrams.

[0039] refer to Figure 2In the time DF of one frame, the first line drive phase H can overlap with the rising phase ta of the charging signal wsc, and the data signal data of the first line display unit 200 on the data line DL is amplified by the charging signal wsc. Figure 2 In the timing diagram, the dashed arrow points upwards, and the solid line of the data signal (data) is located above the horizontal dashed line; the second row driving stage H can overlap with the peak stage tb of the charging signal wsc, and the data signal (data) of the second row display unit 200 on the data line DL is coupled by the charging signal wsc, first increasing and then decreasing. Figure 2 In the timing diagram, the dashed arrows first go upward and then downward, and the solid line of the data signal (data) is located on the horizontal dashed line; the third row drive phase H can overlap with the falling phase tc of the charging signal wsc, and the data signal (data) of the third row display unit 200 on the data line DL is reduced by coupling with the charging signal wsc. Figure 2 The dashed arrow in the timing diagram points downwards, and the solid line of the data signal (data) is located below the horizontal dashed line; the fourth row drive stage H can overlap with the trough stage td of the charging signal wsc, and the data signal (data) of the fourth row display unit 200 on the data line DL is coupled by the charging signal wsc, first decreasing and then increasing. Figure 2 In the timing diagram, the dashed arrows first point downwards and then upwards, while the solid data signal (data) is located on the horizontal dashed line.

[0040] refer to Figure 2 and Figure 3 When the driving transistor M1 is a P-type transistor, the data signal data is usually less than zero. During the time DF of one frame, along the cascaded direction of the shift register units SRU, the data signal data written by the first row display unit 200 in the first row driving stage H increases, which will cause the absolute value of the gate-source voltage |Vgs| of the driving transistor M1 to decrease, the driving current supplied to the light-emitting element OLED to decrease, the brightness of the first row display unit 200 to decrease, and the first row display unit 200 to be darker. Figure 2 The first row of display units 200 is filled with downward arrows in the display area AA; the data signal data written by H in the second row driving stage of the second row display unit 200 can remain stable and basically unchanged, and the brightness of the second row display unit 200 also remains basically unchanged, neither too bright nor too dark. Figure 2 The second row of display units 200 is filled with horizontal lines in the display area AA. The data signal data written by the third row of display units 300 during the third row driving stage decreases, which increases the absolute value of the gate-source voltage |Vgs| of the driving transistor M1, increasing the driving current supplied to the OLED light-emitting element, thus increasing the brightness of the third row of display units 200, making the third row of display units 200 brighter. Figure 2The third row of display units 200, filled with upward arrows in the display area AA; the data signal data written by H in the fourth row of display units 200 during the fourth row driving stage can remain stable and basically unchanged, and the brightness of the fourth row of display units 200 also remains basically unchanged, neither too bright nor too dark. Figure 2 The fourth row of display units 200 in the display area AA is filled with horizontal lines.

[0041] Similarly, along the direction of the cascaded shift register units SRU, the fifth row display unit 200 is slightly darker. Figure 2 The fifth row of display units 200 in the display area AA is filled with downward arrows, and the sixth row of display units 200 is neither too bright nor too dark. Figure 2 The sixth row of display units 200 in the display area AA is filled with horizontal lines, and the seventh row of display units 200 is slightly brighter. Figure 2 The seventh row of display units 200 in the display area AA is filled with an upward arrow, and the eighth row of display units 200 is neither too bright nor too dark. Figure 2 The eighth row of display unit 200 in the display area AA is filled with horizontal lines.

[0042] As can be seen from the above, when the duration of the horizontal driving phase H is twice the quarter-cycle of the charging signal wsc, the four adjacent horizontal driving phases H can overlap with the four phases (e.g., rising phase ta, peak phase tb, falling phase tc, and trough phase td) of one cycle tsc of the charging signal wsc. This allows the charging signal wsc to periodically couple the data signal data on the data line DL, with the coupling period being the four adjacent horizontal driving phases H. Consequently, the data signal data written by the display unit 200 can also exhibit periodic changes, with the change period being the four adjacent horizontal display units 200. Thus, the brightness change of the display unit 200 also exhibits periodic changes, with the change period being the four adjacent horizontal display units 200. When the charging signal wsc coupled with the data signal data causes the display unit 200 to display abnormally (too bright or too dark), the display unit 200 with abnormal display can cancel the brightness and darkness of other display units 200 with abnormal display nearby (such as other row display units 200). This can improve the display abnormality problem caused by the charging signal wsc coupled with the data signal data. It can avoid the regular coupling of the charging signal wsc to the data signal data, which would cause the charging signal wsc to increase or decrease the data signal data in multiple consecutive row driving stages, resulting in multiple consecutive rows of display units 200 being too bright or too dark, and a regular water ripple phenomenon, affecting the display effect.

[0043] It is understood that in other embodiments, the driving transistor M1 can also be an N-type transistor. In this case, the data signal data is usually greater than zero. When the data signal data written by the display unit 200 during the row driving stage H increases, the absolute value of the gate-source voltage |Vgs| of the driving transistor M1 increases, the driving current supplied to the light-emitting element OLED increases, and the brightness of the first row display unit 200 increases. When the data signal data written by the display unit 200 during the row driving stage H decreases, the absolute value of the gate-source voltage |Vgs| of the driving transistor M1 decreases, the driving current supplied to the light-emitting element OLED decreases, and the brightness of the first row display unit 200 decreases. When the driving transistor M1 is an N-type transistor, the brightness change trend of the display unit 200 is opposite to that when the driving transistor M1 is a P-type transistor. However, the brightness change of the four adjacent rows of display units 200 can still exhibit a periodic change trend. The display unit 200 with display abnormalities can cancel out the brightness of other display units 200 with display abnormalities nearby (e.g., other rows of display units 200), effectively improving the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data. For ease of understanding and explanation, unless otherwise specified, the embodiments of this application will be explained using a P-type transistor as the driving transistor M1 in the following text.

[0044] It is also understandable that when the duration of the line drive phase H is twice the quarter-cycle of the charging signal wsc, the line drive phase H may overlap with only one of the rising phase ta, peak phase tb, falling phase tc, and trough phase td, or may overlap with one of the rising phase ta, peak phase tb, falling phase tc, and trough phase td for most of the time. The duration of the write period t1 can be less than or equal to one-quarter of the cycle of the charging signal wsc. That is, the duration of the write period t1 can be less than or equal to the duration of any one of the rising phase ta, peak phase tb, falling phase tc, or trough phase td. The write period t1 can overlap with the same one of the rising phase ta, peak phase tb, falling phase tc, or trough phase td in the row driving phase H. This ensures that in the row driving phase H, regardless of whether the data signal data on the data line DL is floating, the duration of the write period t1, or which sub-phase of the row driving phase H the write period t1 is located in, the trend of the change of the data signal data written by the display unit 200 in the write period t1 is fixed.

[0045] like Figure 2As shown, in the row driving stage H, regardless of whether the data signal data on the data line DL is floating, the duration of the writing period t1, or which sub-stage of the row driving stage H the writing period t1 is located in, the data signal data written by the first row display unit 200 is always too large, the data signal data written by the second row display unit 200 is always basically unchanged (neither too large nor too small), the data signal data written by the third row display unit 200 is always too small, and the data signal data written by the fourth row display unit 200 is always basically unchanged (neither too large nor too small). Among them, the absolute value of the potential change rate of the charging signal wsc during the peak phase tb and trough phase td is usually smaller than the absolute value of the potential change rate during the rising phase ta and falling phase tc. The second and fourth line drive phases H overlap with the peak phase tb and trough phase td. During the second and fourth line drive phases H, the coupling effect of the charging signal wsc on the data line DL is weak. Therefore, even during the second and fourth line drive phases H, when the display unit 200 writes the data signal data during the writing period t1, the data signal data on the data line DL is not coupled and canceled out (first increasing). (If the data signal data written by the second and fourth line display units 200 during the writing period t1 is slightly larger or smaller than expected, the trend of the data signal data written by the second and fourth line display units 200 during the writing period t1 may be basically unchanged compared to the trend of the data signal data written by the first and third line display units 200 during the writing period t1. That is, the coupling effect of the data signal data written by the second and fourth line display units 200 during the writing period t1 is weak and can be ignored.)

[0046] It is also understood that when the duration of the row driving phase H is greater than one-quarter of the charging signal wsc, that is, when the duration of the row driving phase H is an integer multiple of one greater than one-quarter of the charging signal wsc, the row driving phase H can overlap with multiple of the rising phase ta, peak phase tb, falling phase tc, and trough phase td. The duration of the write period t1 can still be less than or equal to one-quarter of the charging signal wsc. In this case, the write period t1 can overlap with only one of the rising phase ta, peak phase tb, falling phase tc, and trough phase td. Alternatively, the duration of the write period t1 can also be greater than one-quarter of the charging signal wsc. In this case, the write period t1 can also overlap with multiple of the rising phase ta, peak phase tb, falling phase tc, and trough phase td. In one embodiment, the duration of the write period t1 can be an integer multiple of one-quarter of the charging signal wsc; in another embodiment, the duration of the write period t1 is less than the duration of the row driving phase H.

[0047] The overlap between the row drive phase H and multiple overlaps in the rising phase ta, peak phase tb, falling phase tc, and trough phase td, and / or the overlap between the write period t1 and multiple overlaps in the rising phase ta, peak phase tb, falling phase tc, and trough phase td, means that in the row drive phase H, the position of the write period t1 in the row drive phase, whether the data signal data on the data line DL is floating, and the duration of the write period t1 may all affect the trend of the data signal data written by the display unit 200 in the write period t1.

[0048] In an optional embodiment, during the row driving phase H, the driver chip ( Figure 1 (not shown in the image) and / or the source drive circuit 112 can continuously charge the data signal data to the data line DL. During the writing period t1, when the display unit 200 writes the data signal data on the data line DL, the data signal data on the data line DL is an active signal. In this case, the display unit 200 writes the data signal data in a "direct charging" manner, and the drive chip ( Figure 1 (Not shown in the diagram) and / or the source drive circuit 112 can directly provide the data signal data to the display unit 200. If the display unit 200 writes the data signal data in the "direct charging" mode, during the writing period t1, when the display unit 200 writes the data signal data on the data line DL, the data signal data on the data line DL is not floating.

[0049] For example, taking a row-driven phase H whose duration is three times a quarter cycle of the charging signal wsc, and a write period t1 whose duration is less than or equal to a quarter cycle of the charging signal wsc, and where the write period t1 overlaps only with one of the rising phase ta, the peak phase tb, the falling phase tc, or the trough phase td. Figure 4 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 4 The diagram also shows the trend of the eight scan signals scan(1) to scan(8) on the first eight scan lines SL in the time DF of a frame, along the direction of the cascaded shift register units SRU, and the change trend of the data signal data of the first eight lines of display units 200 transmitted on the data line DL along the direction of the cascaded shift register units SRU. (See reference...) Figure 4 In the m-th line driving stage H of a frame's time DF, the driving chip ( Figure 1 (not shown in the diagram) and / or the source drive circuit 112 can continuously charge the data signal data of the m-th row display unit 200 to the data line DL. In different sub-stages of the row drive stage H, the change of the data signal data on the data line DL is only related to the charging signal wsc of the current sub-stage. Figure 4 The position of the solid line representing the data signal corresponds to the dashed arrow of the current sub-stage.

[0050] In an optional implementation, the row driving phase H may include three sub-phases, the duration of which may be equal to a quarter cycle of the charging signal wsc, and the write phase t1 may overlap with the first sub-phase. (See reference) Figure 3 and Figure 4 In the time DF of one frame, the first line drive phase H can overlap with the rising phase ta, peak phase tb, and falling phase tc of the charging signal wsc, and the write time period t1 overlaps with the rising phase ta of the charging signal wsc; along the direction of the cascaded shift register unit SRU, when the first line display unit 200 writes the data signal data, the data signal data of the first line display unit 200 on the data line DL is amplified by the charging signal wsc ( Figure 4 In the timing diagram, the dashed arrow points upwards, and the solid line of the data signal (data) is located above the horizontal dashed line. Therefore, the data signal (data) written by the first row display unit 200 increases. When the driving transistor M1 is a P-type transistor, the increase in the data signal (data) written by the first row display unit 200 will reduce the brightness of the first row display unit 200, making the first row display unit 200 appear dimmer. Figure 4 The first row of display units 200 in the display area AA is filled with a downward arrow.

[0051] The second row drive phase H can overlap with the trough phase td, rise phase ta, and peak phase tb of the charging signal wsc, and the write period t1 overlaps with the trough phase td of the charging signal wsc; along the direction of the cascaded shift register unit SRU, when the second row display unit 200 writes the data signal data, the data signal data of the second row display unit 200 on the data line DL is basically equal to the set value ( Figure 4 The dashed arrow in the timing diagram points to the right, and the solid line of the data signal (data) is located on the horizontal dashed line. Therefore, the data signal (data) written to the second row display unit 200 is basically equal to the set value, and the brightness of the second row display unit 200 also remains basically unchanged. The second row display unit 200 is neither too bright nor too dark. Figure 4 The second row of display units 200 in the display area AA is filled with horizontal lines.

[0052] The third row drive phase H can overlap with the falling phase tc, trough phase td, and rising phase ta of the charging signal wsc; the write period t1 overlaps with the falling phase tc of the charging signal wsc; along the direction of the cascaded shift register unit SRU, when the third row display unit 200 writes the data signal data, the data signal data of the third row display unit 200 on the data line DL is reduced by the coupling of the charging signal wsc. Figure 4 In the timing diagram, the dashed arrow points downwards, and the solid line of the data signal (data) is located below the horizontal dashed line. Therefore, the data signal (data) written by the third row display unit 200 decreases. When the driving transistor M1 is a P-type transistor, the decrease in the data signal (data) written by the third row display unit 200 will cause the brightness of the first row display unit 200 to increase, making the first row display unit 200 brighter. Figure 4 The third row of display units 200 in the display area AA is filled with an upward arrow.

[0053] The fourth row driving phase H can overlap with the peak phase tb, the falling phase tc, and the trough phase td of the charging signal wsc. The writing period t1 overlaps with the peak phase tb of the charging signal wsc. Along the direction of the cascaded shift register unit SRU, when the fourth row display unit 200 writes the data signal data, the data signal data of the fourth row display unit 200 on the data line DL is basically equal to the set value. Figure 4 The dashed arrow in the timing diagram points to the right, and the solid line of the data signal (data) is located on the horizontal dashed line. Therefore, the data signal (data) written to the fourth row display unit 200 is basically equal to the set value, and the brightness of the fourth row display unit 200 remains basically unchanged. The fourth row display unit 200 is neither too bright nor too dark. Figure 4 The fourth row of display units 200 in the display area AA is filled with horizontal lines.

[0054] Similarly, along the direction of the cascaded shift register units SRU, the fifth row display unit 200 is slightly darker. Figure 4 The fifth row of display units 200 in the display area AA is filled with downward arrows, and the sixth row of display units 200 is neither too bright nor too dark. Figure 4 The sixth row of display units 200 in the display area AA is filled with horizontal lines, and the seventh row of display units 200 is slightly brighter. Figure 4 The seventh row of display units 200 in the display area AA is filled with an upward arrow, and the eighth row of display units 200 is neither too bright nor too dark. Figure 4 The eighth row of display unit 200 in the display area AA is filled with horizontal lines.

[0055] In other alternative implementations, Figure 5 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 6 This is a timing diagram of another display device in operation provided in the embodiments of this application. The row driving stage H may include three sub-stages, and the write time period t1 may overlap with the second or third sub-stage. Figure 5 , Figure 6 and Figure 4 The difference between the two solutions is that Figure 4The write time period t1 overlaps with the first sub-stage of the row-driven stage H. Figure 5 and Figure 6 The write period t1 does not overlap with the first sub-stage of the row-driven stage H. Figure 5 and Figure 6 When each row display unit 200 writes the data signal data, the change of the data signal data on the data line DL is as follows: Figure 4 The differences shown lead to the coupling effect of the data signal data written by each row display unit 200 during the writing period t1. Figure 4 The results are different. Figure 5 and Figure 6 Display abnormalities of each row display unit 200 and Figure 4 The difference shown is ( Figure 5 , Figure 6 The direction of the fill arrow in the display unit 200 is the same as the direction of the arrow. Figure 4 (The fill arrows in display unit 200 have different directions), but Figure 5 and Figure 6 The display abnormality of the fifth row display unit 200 can still be the same as that of the first row display unit 200, the display abnormality of the sixth row display unit 200 can still be the same as that of the second row display unit 200, the display abnormality of the seventh row display unit 200 can still be the same as that of the third row display unit 200, and the display abnormality of the eighth row display unit 200 can still be the same as that of the fourth row display unit 200.

[0056] Therefore, it can be seen that in the row driving stage H, the position of the writing time period t1 in the row driving stage will affect the change trend of the data signal data written by the display unit 200 in the writing time period t1. However, the data signal data written by the display unit 200 can also have periodic changes, and the brightness change of the display unit 200 also has periodic changes. The change period is four adjacent rows of display units 200, which can still effectively improve the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data.

[0057] In another alternative embodiment, during the row driving phase H, the driver chip ( Figure 1 (not shown in the image) and / or the source drive circuit 112 may also charge the data line DL with the data signal data only during a portion of the row drive phase H. During the write phase t1, when the display unit 200 writes the data signal data on the data line DL, the drive chip ( Figure 1 (Not shown in the image) and / or the source drive circuit 112 no longer charges the data signal data to the data line DL. The data signal data on the data line DL is a passive signal. In this case, the display unit 200 writes the data signal data in the form of "line charging". The driver chip ( Figure 1 (Not shown in the diagram) and / or the source drive circuit 112 can indirectly provide the data signal data to the display unit 200 via the data line DL. If the display unit 200 writes the data signal data in the manner of "line charging", during the writing period t1, when the display unit 200 writes the data signal data on the data line DL, the data signal data on the data line DL is floating.

[0058] For example, taking a row-driven phase H whose duration is three times a quarter cycle of the charging signal wsc, and a write period t1 whose duration is less than or equal to a quarter cycle of the charging signal wsc, and where the write period t1 overlaps only with one of the rising phase ta, the peak phase tb, the falling phase tc, or the trough phase td. Figure 7 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 7 The diagram also shows the trend of the eight scan signals scan(1) to scan(8) on the first eight scan lines SL in the time DF of a frame, along the direction of the cascaded shift register units SRU, and the change trend of the data signal data of the first eight lines of display units 200 transmitted on the data line DL along the direction of the cascaded shift register units SRU. (See reference...) Figure 7 In the m-th line driving stage H of a frame's time DF, the driving chip ( Figure 1 (not shown in the diagram) and / or the source drive circuit 112 may charge the data signal data of the m-th row display unit 200 to the data line DL before the write period t1 (e.g., at least part of the first sub-stage in the row drive stage H), and in the second and third sub-stages, the drive chip ( Figure 1 (Not shown in the image) and / or the source drive circuit 112 stops charging the data signal data of the m-th row display unit 200 to the data line DL. The data signal data on the data line DL is floated. In the second and third sub-stages of the row drive phase H, the change of the data signal data on the data line DL is related to the charging signal wsc of the current sub-stage and the sub-stage before the current sub-stage. Figure 7 The position of the solid line for the data signal may not correspond to the dashed arrow of the current sub-stage.

[0059] Continue to refer to Figure 7 The line drive stage H can include three sub-stages. In the first sub-stage, the driver chip ( Figure 1 (Not shown in the image) and / or the source drive circuit 112 can charge the data line DL with the data signal data. In the time DF of one frame, during the first line drive phase H, the first sub-phase overlaps with the rising phase ta, and the data signal data on the data line DL is increased by coupling with the charging signal wsc. Figure 7In the timing diagram, the dashed arrow points upwards, and the solid data signal (data) is located above the horizontal dashed line; the second sub-stage overlaps with the peak stage (tb), and the data signal (data) on the data line (DL) remains basically stable. Figure 7 (The dashed arrow in the timing diagram points to the right), but the data signal data on the data line DL is floating. The potential of the data signal data on the data line DL is affected by the change in the first sub-stage. The data signal data on the data line DL is still in a state of being coupled and increased by the charging signal wsc. Figure 7 In the timing diagram, the solid line of the data signal (data) is located above the horizontal dashed line; the third sub-stage overlaps with the descent stage (tc), and the data signal (data) on the data line (DL) is reduced by the charging signal (wsc). Figure 7 (The dashed arrow in the timing diagram points downwards) The potential of the data signal data on the data line DL is affected by the changes in the first and second sub-stages. After the coupling of the three sub-stages, the data signal data on the data line DL first increases, remains stable, and then decreases, eventually recovering to approximately equal to the set value. Figure 7 In the timing diagram, the solid line of the data signal "data" is located on a horizontal dashed line. The display unit 200 shows the trend of the data signal "data" written during writing period t1, and the relationship between the potential of the data signal "data" on the data line DL during writing period t1 and the set value. Figure 7 The relationship between the position of the solid line (data) and the horizontal dashed line in the timing diagram is related to this.

[0060] In an optional implementation, the row-driving phase H may include three sub-phases, the duration of which may be equal to one-quarter of the cycle of the charging signal wsc, and the write period t1 may overlap with the second sub-phase. (See reference) Figure 3 and Figure 7 Along the direction of the cascaded shift register units SRU, the first row of display units 200 is slightly darker. Figure 7 The first row of display units 200 in the display area AA is filled with downward arrows, and the second row of display units 200 is darker. Figure 7 The second row of display units 200 in the display area AA is filled with downward arrows, and the third row of display units 200 is brighter. Figure 7 The third row of display units 200 in the display area AA is filled with an upward arrow, and the fourth row of display units 200 is slightly brighter. Figure 7 The fourth row of display unit 200 in the display area AA is filled with an upward arrow.

[0061] Figure 7 and Figure 5 The difference between the two solutions is that Figure 5 The data signal is written to the display unit 200 via "direct charging". Figure 7The data signal is written to the display unit 200 via "line charging". Figure 7 When the display unit 200 writes the data signal data, the change of the data signal data on the data line DL is as follows: Figure 5 The difference shown leads to Figure 7 The coupling effect of the data signal data written by the display unit 200 during the writing period t1 and Figure 5 The results are different. Figure 7 and Figure 5 The display abnormalities of the middle display unit 200 are different, but the display abnormality of the fifth row display unit 200 can still be the same as that of the first row display unit 200, the sixth row display unit 200 can still be the same as that of the second row display unit 200, the seventh row display unit 200 can still be the same as that of the third row display unit 200, and the eighth row display unit 200 can still be the same as that of the fourth row display unit 200.

[0062] Therefore, it can be seen that in the row driving stage H, the way the display unit 200 writes the data signal data, that is, whether the data signal data on the data line DL is floating, will affect the change trend of the data signal data written by the display unit 200 in the writing period t1. However, the data signal data written by the display unit 200 can also have periodic changes, and the brightness change of the display unit 200 also has periodic changes. The change period is four adjacent rows of display units 200, which can still effectively improve the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data.

[0063] In yet another alternative embodiment, Figure 8 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 8 The duration of the row drive phase H and the duration of the write period t1 are both greater than a quarter of the cycle of the charging signal wsc. The write period t1 can overlap with multiple phases of the rising phase ta, the peak phase tb, the falling phase tc, and the trough phase td.

[0064] For example, taking the duration of the row drive phase H as three times a quarter cycle of the charging signal wsc, refer to... Figure 8 The row drive phase H may include three sub-phases. The duration of each sub-phase may be equal to one-quarter of the cycle of the charging signal wsc. The write period t1 may overlap with multiple sub-phases of the row drive phase H. The final change trend of the data signal data written by the display unit 200 in the write period t1 is related to the data signal data on the data line DL and the set value in the last sub-phase that usually overlaps with the write period t1. Figure 8The relationship between the solid line and the horizontal dashed line of the data signal (data) in the timing diagram is related. Therefore, when the write period t1 overlaps with multiple sub-stages of the row driving stage H, the different durations of the write period t1 will result in different last sub-stages overlapping with the write period t1, affecting the final change trend of the data signal data written by the display unit 200 in the write period t1. Figure 8 The example shown only illustrates the case where the display unit 200 writes the data signal "data" in the manner of "line charging" ( Figure 8 (The position of the solid line of the data signal may not correspond to the dashed arrow of the current sub-stage). However, when the display unit 200 writes the data signal data in the "direct charge" manner, the same applies. The different durations of the writing period t1 will result in different last sub-stages overlapping with the writing period t1, affecting the final change trend of the data signal data written by the display unit 200 in the writing period t1.

[0065] In an optional implementation, the row driving phase H may include three sub-phases, the duration of which may be equal to one-quarter of the cycle of the charging signal wsc, and the write period t1 may overlap with all three sub-phases. (See reference) Figure 3 and Figure 8 Along the direction of the cascaded shift register units SRU, the first row of display units 200 is neither too bright nor too dark. Figure 8 The first row of display units 200 in the display area AA is filled with horizontal lines, and the second row of display units 200 is darker. Figure 8 The second row of display units 200 in the display area AA is filled with downward arrows, and the third row of display units 200 is neither too bright nor too dark. Figure 8 The third row of display units 200 in the display area AA is filled with horizontal lines, and the fourth row of display units 200 is slightly brighter. Figure 8 The fourth row of display unit 200 in the display area AA is filled with an upward arrow.

[0066] Figure 8 and Figure 7 The difference is that, Figure 8 The duration of time period t1 is written in the middle. Figure 7 The duration of the write period t1 is different, resulting in Figure 8 The position of write time period t1 in row-driven phase H and Figure 7 The position of H in the row-driven phase differs depending on the write time period t1. Figure 8 The last sub-stage overlapping with time period t1 is written in the middle. Figure 7 The last sub-stage overlapping with the write time period t1 is also different, causing... Figure 8 The coupling effect of the data signal data written by the display unit 200 during the writing period t1 and Figure 7The results are different. Figure 8 and Figure 7 The display abnormalities of the middle display unit 200 are different, but the display abnormality of the fifth row display unit 200 can still be the same as that of the first row display unit 200, the sixth row display unit 200 can still be the same as that of the second row display unit 200, the seventh row display unit 200 can still be the same as that of the third row display unit 200, and the eighth row display unit 200 can still be the same as that of the fourth row display unit 200.

[0067] Therefore, it can be seen that in the row driving stage H, the duration of the writing period t1 may also affect the change trend of the data signal data written by the display unit 200 in the writing period t1. However, the data signal data written by the display unit 200 can also have periodic changes, and the brightness change of the display unit 200 also has periodic changes. The change period is four adjacent rows of display units 200, which can still effectively improve the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data. In addition, in special cases, such as when the display unit 200 includes a 7T1C pixel circuit, during the threshold compensation stage, after the P-channel driving transistor enters the critical conduction state, if the data signal data in the next sub-stage is coupled and increased, the increased data signal data may not be written to the display unit 200. As a result, during the last sub-stage overlapping with the writing period t1, the change in the data signal data on the data line DL cannot be written to the display unit 200. This may cause the brightness change of the display unit 200 to fail to change periodically. That is, among the four adjacent rows of display units 200, the display unit 200 with abnormal display may not be able to achieve brightness and darkness cancellation with other rows of display units 200. However, it can still avoid the regular coupling of the charging signal wsc to the data signal data, which would cause the charging signal wsc to increase or decrease the data signal data in multiple consecutive row driving stages, resulting in multiple consecutive rows of display units 200 being too bright or too dark, with a regular water ripple phenomenon, affecting the display effect, but also helping to improve the display effect.

[0068] As can be seen from the above, when the duration of the horizontal driving phase H is three times a quarter cycle of the charging signal wsc, the horizontal driving phase H can overlap with three of the four phases (e.g., rising phase ta, peak phase tb, falling phase tc, and trough phase td) in one cycle tsc of the charging signal wsc. The four adjacent horizontal driving phases H can overlap with three cycles tsc of the charging signal wsc. That is, if the duration of the horizontal driving phase H is several times a quarter cycle of the charging signal wsc, the four adjacent horizontal driving phases H can overlap with several cycles tsc of the charging signal wsc. Thus, regardless of how many times the duration of the horizontal driving phase H is a quarter cycle of the charging signal wsc, the charging signal wsc can periodically couple the data signal data on the data line DL, causing the data signal data written by the display unit 200 to also exhibit periodic changes. Consequently, the brightness change of the display unit 200 also exhibits periodic changes, effectively improving the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data.

[0069] Furthermore, even though the position of the write period t1 in the horizontal driving phase, whether the data signal data on the data line DL is floating, and the duration of the write period t1 may affect the trend of the change of the data signal data written by the display unit 200 in the write period t1, the data signal data written by the display unit 200 can still change periodically, so that the brightness change of the display unit 200 can be periodically changed. The display units 200 with the same change period can achieve brightness and darkness cancellation, which can effectively improve the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data. Therefore, the position of the write period t1 in the horizontal driving phase, whether the data signal data on the data line DL is floating, and the duration of the write period t1 will not affect the improvement of the water ripple phenomenon.

[0070] It is understood that the above embodiments are all exemplified by the example that the data line DL transmits only the data signal data of the m-th row display unit 200 in the m-th row driving stage H. In other embodiments, when the write time period t1 is located at an earlier position in the row driving stage H, after the m-th row display unit 200 writes the data signal data in the write time period t1 of the m-th row driving stage H, the data line DL can transmit the data signal data of the (m+1)-th row display unit 200 in a part of the m-th row driving stage H; or, when the write time period t1 is located at a later position in the row driving stage H, before the m-th row display unit 200 writes the data signal data in the write time period t1 of the m-th row driving stage H, the data line DL can transmit the data signal data of the (m-1)-th row display unit 200 in a part of the m-th row driving stage H.

[0071] In some implementations, during the display time DF of a frame, the timing relationship between the start and end times of the write period t1 and the start and end times of the line driving phase H is fixed; and / or, the timing relationship between the start and end times of the write period t1 and the start and end times of the data line DL being charged with data signal data is fixed. Regardless of whether the data line DL transmits the data signal data of the (m+1)th or (m-1)th line display unit 200 during a portion of the m-th line driving phase H, the data signal data written by the display unit 200 can exhibit periodic changes, and the brightness changes of the display unit 200 can also exhibit periodic changes. The change period is the same as that of four adjacent lines of display units 200, which can effectively improve the display abnormality problem caused by the coupling of the charging signal wsc with the data signal data. Therefore, whether the data line DL transmits multiple line display unit 200 data signals data during the line driving phase H will not affect the improvement of the water ripple phenomenon. For ease of understanding and explanation, unless otherwise specified, in the following embodiments, the data signal data of the m-th row display unit 200 transmitted only by the data line DL in the m-th row driving stage H will be used as an example for explanation.

[0072] In this embodiment, by setting the duration of the row driving phase to an integer multiple of a quarter cycle of the charging signal, the sum of the durations of four adjacent row driving phases can be an integer multiple of the charging signal cycle. Thus, every four row driving phases, the writing period can overlap with the same phase in the charging signal cycle. The charging signal can periodically couple and influence the data signal written to the display unit. The coupling influence period is four rows of display units. This allows the same coupling influence to be presented every four rows of display units. The periodically set adjacent four rows of display units can present different abnormal displays of brightness or darkness. The abnormal display period is four rows of display units. In a four-row display unit abnormal display period, when one or more rows of display units are too bright or too dark, the brightness deviation of other rows of display units in the same abnormal display period can be used to perform brightness equalization or brightness cancellation. This helps to improve the display abnormality problem caused by the charging signal coupling with the data signal, and avoids multiple consecutive rows of display units being too bright or too dark, resulting in a water ripple phenomenon that affects the display effect of the display device.

[0073] Optional, Figure 9 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 9The duration of the row driving phase H is an integer multiple of half the period of the charging signal wsc. By setting the duration of the row driving phase H to an integer multiple of half the period of the charging signal wsc, the sum of the durations of two adjacent row driving phases can be an integer multiple of the period of the charging signal. Thus, every two row driving phases H, the writing period t1 can overlap with the same phase (one or more of the rising phase ta, peak phase tb, falling phase tc, and trough phase td) in the charging signal period tsc. The charging signal wsc can periodically couple and affect the data signal written by the display unit 200. The coupling and effect period is two rows of display units 200. In two rows of display units 200 in an abnormal display period, if a display unit 200 is too bright or too dark, the brightness deviation of the other row of display units 200 in the same abnormal display period can be used for brightness equalization or brightness cancellation. This helps to reduce the coupling and effect period of the charging signal wsc on the display unit 200 and further optimize the display effect.

[0074] In an optional embodiment, the duration of the line drive phase H is an odd multiple of half a period of the charging signal wsc.

[0075] For example, taking the duration of the row driving phase H as being twice the half-cycle of the charging signal wsc, and continuing to refer to... Figure 9 In the display time DF of a frame, during two adjacent line driving stages H, the change trend of the charging signal WSC in the i-th line driving stage H is opposite to that in the (i+1)-th line driving stage H. This makes the change trend of the data signal data written by the display unit 200 during the writing period t1 of the i-th line driving stage opposite to that of the data signal data written by the display unit 200 during the writing period t1 of the i-th line driving stage. This makes the display abnormalities of the two adjacent line display units 200 opposite. When one line display unit 200 is brighter, the other line display unit 200 can be darker, and the degree of deviation is similar. This helps the brightness and darkness deviations of the two adjacent line display units 200 to cancel each other out, and the human eye can hardly see the abnormal brightness deviation.

[0076] It is understandable that when the duration of the line driving phase H is three or five times the half-cycle of the charging signal wsc, in the display time DF of one frame, the change trend of the charging signal WSC in the i-th line driving phase H is opposite to that in the (i+1)-th line driving phase H. This also makes the change trend of the data signal data written by the display unit 200 during the writing period t1 of the i-th line driving phase opposite to that of the data signal data written by the display unit 200 during the writing period t1 of the i-th line driving phase. This is beneficial for the brightness and darkness deviations of adjacent line display units 200 to cancel each other out, and the human eye can hardly see the abnormal brightness deviation.

[0077] In an alternative implementation, Figure 10 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 10 The charging signal wsc includes a rising phase ta, a peak phase tb, a falling phase tc, and a trough phase td. In the display time DF of a frame, the writing period t1 of the i-th row driving phase H overlaps with the rising phase ta of the charging signal wsc, and the writing period t1 of the (i+1)-th row driving phase H overlaps with the falling phase tc of the charging signal wsc. i is a positive integer.

[0078] For example, taking the duration of the row driving phase H as being twice the half-cycle of the charging signal wsc, and continuing to refer to... Figure 10 The duration of the line drive phase H includes two sub-phases. The first sub-phase overlaps with the peak phase tb or the trough phase td, and the second sub-phase overlaps with the falling phase tc or the rising phase ta. Thus, in the first sub-phase, the data signal data on the data line DL remains stable and basically unchanged. In the second sub-phase, the data signal data on the data line DL may only be related to the charging signal wsc of the second sub-phase. Figure 10 The position of the solid line of the data signal corresponds to the dashed arrow of the current sub-stage. When the write period t1 overlaps with the second sub-stage of the row drive stage H, the write period t1 of the odd-numbered row drive stage H can overlap with the falling phase tc of the charging signal wsc, and the write period t1 of the even-numbered row drive stage H can overlap with the rising phase ta of the charging signal wsc. When the driving transistor is a P-type transistor, the brightness of the odd-numbered row display unit 200 is made brighter. Figure 10 The odd-numbered rows of display units 200 in the display area AA are filled with upward arrows, and the even-numbered display units 200 are dimmer. Figure 10The even-numbered rows of display units 200 in the display area AA are filled with downward arrows. In this way, the brightness and darkness deviations of adjacent odd-numbered rows of display units 200 and even-numbered rows of display units 200 can cancel each other out, and the abnormal brightness deviation is almost invisible to the human eye.

[0079] In another alternative implementation, Figure 11 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 11 The charging signal wsc includes a rising phase ta, a peak phase tb, a falling phase tc, and a trough phase td. In the display time DF of a frame, the writing period t1 of the i-th row driving phase H overlaps with the peak phase tb of the charging signal wsc, and the writing period t1 of the (i+1)-th row driving phase H overlaps with the trough phase td of the charging signal wsc. i is a positive integer.

[0080] For example, taking the duration of the row driving phase H as being twice the half-cycle of the charging signal wsc, and continuing to refer to... Figure 11 The duration of the line drive phase H includes two sub-phases. The first sub-phase overlaps with the peak phase tb or the trough phase td, and the second sub-phase overlaps with the falling phase tc or the rising phase ta. Thus, in the first sub-phase, the data signal data on the data line DL remains stable and basically unchanged. In the second sub-phase, the data signal data on the data line DL may only be related to the charging signal wsc of the second sub-phase. Figure 11 The position of the solid line of the data signal corresponds to the dashed arrow of the current sub-stage. When the write time period t1 overlaps with the first sub-stage of the row drive stage H, the write time period t1 of the odd-numbered row drive stage H can overlap with the peak stage tb of the charging signal wsc, and the write time period t1 of the even-numbered row drive stage H can overlap with the trough stage td of the charging signal wsc. This ensures that the brightness of both the odd-numbered and even-numbered display units 200 is close to the set brightness, neither too bright nor too dark. Figure 11 The display area AA is filled with horizontal lines (odd-numbered row display units 200 and even-numbered row display units 200), making the abnormal brightness deviation almost imperceptible to the human eye. Furthermore, even if there is a slight brightness deviation between the odd-numbered and even-numbered row display units 200, their opposite brightness deviations will cancel each other out, making the abnormal brightness deviation almost invisible to the human eye.

[0081] It is understandable that when the duration of the line drive phase H is twice the half-cycle of the charging signal wsc, the relationship between the two sub-phases of the line drive phase H and the periodic pulse signal of the charging signal wsc is not limited to... Figure 10 and Figure 11The relationship shown can also be, for example, the first sub-stage overlapping with the rising stage ta or the falling stage tc, and the second sub-stage overlapping with the peak stage tb or the trough stage td. Figure 10 and Figure 11 (Not shown in the image) The writing period t1 can overlap with the first or second sub-stage of the row driving stage H, which can also cause the brightness and darkness deviations of adjacent odd-numbered row display units 200 and even-numbered row display units 200 to cancel each other out. The human eye can hardly see the abnormal brightness deviation. Similarly, when the duration of the row driving stage H is half the period of the charging signal wsc, and other odd multiples, the change stages of the charging signal wsc that overlap in the writing period t1 of two adjacent row driving stages H correspond to each other (the change stages are opposite in trend, for example, the change trends of the charging signal wsc are opposite in the rising stage ta and the falling stage tc, and the change trends of the charging signal wsc are opposite in the peak stage tb and the trough stage td). This can cause the brightness and darkness deviations of adjacent odd-numbered row display units 200 and even-numbered row display units 200 to cancel each other out, and the human eye can hardly see the abnormal brightness deviation.

[0082] In another alternative embodiment, Figure 12 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 12 The duration of the row drive phase H is an even multiple of half the period of the charging signal wsc, that is, the duration of the row drive phase H is an integer multiple of the period tsc of the charging signal wsc.

[0083] For example, taking the duration of the row driving phase H as twice the half-cycle of the charging signal wsc, that is, the duration of the row driving phase H as once the cycle tsc of the charging signal wsc, and continuing to refer to... Figure 12 The writing period t1 can overlap with the same stage in the charging signal cycle. In this way, the final change trend of the data signal data written by the multi-line display unit 200 in the writing period t1 is the same. Although it is impossible to make the brightness and darkness deviation of adjacent line display units 200 cancel each other out, it can make the brightness and darkness deviation of adjacent line display units 200 the same, achieve brightness balance, and also help improve the display effect, avoid the local continuous multi-line display units 200 being too bright or too dark, and the water ripple phenomenon.

[0084] In an alternative implementation, continue to refer to Figure 12The charging signal wsc includes a rising phase ta, a peak phase tb, a falling phase tc, and a trough phase td. When the driving transistor is a P-type transistor, in the display time DF of one frame, the writing period of the i-th line driving phase H and the writing period t1 of the (i+1)-th line driving phase H both overlap with the falling phase tc of the charging signal wsc. Alternatively, when the driving transistor is an N-type transistor, in the display time DF of one frame, the writing period of the i-th line driving phase H and the writing period t1 of the (i+1)-th line driving phase H both overlap with the rising phase ta of the charging signal wsc. i is a positive integer.

[0085] For example, taking a P-type transistor as the driving transistor, the duration of the horizontal driving phase H is twice the half-cycle of the charging signal wsc, that is, the duration of the horizontal driving phase H is once the cycle tsc of the charging signal wsc. Continuing with this example... Figure 12 The duration of the row-driven phase H includes four sub-phases, which can overlap with the falling phase tc, the trough phase td, the rising phase ta, and the peak phase tb, respectively. The write period t1 can overlap with the first sub-phase, that is, the write period t1 can overlap with the falling phase tc. Thus, the data signal 'data' written by the display unit 200 during the write period t1 is relatively small, which makes each row of the display unit 200 appear brighter. Figure 12 The display area AA (with upward arrows filling the display units 200) is used to improve the display effect and avoid the phenomenon of multiple consecutive rows of display units 200 being too bright or too dark, resulting in a water ripple effect. On the other hand, when all rows of display units 200 are too bright due to the coupling effect of the charging signal wsc, the absolute value of the data signal data can be appropriately reduced, which is beneficial to low power consumption.

[0086] In another alternative implementation, Figure 13 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 13 The charging signal wsc includes a rising phase ta, a peak phase tb, a falling phase tc, and a trough phase td; in the display time DF of a frame, the writing time period of the i-th row driving phase H and the writing time period t1 of the (i+1)-th row driving phase H both overlap with the peak phase tb of the charging signal wsc; or, the writing time period of the i-th row driving phase H and the writing time period t1 of the (i+1)-th row driving phase H both overlap with the trough phase td of the charging signal wsc; i is a positive integer.

[0087] For example, taking the duration of the row driving phase H as twice the half-cycle of the charging signal wsc, that is, the duration of the row driving phase H as once the cycle tsc of the charging signal wsc, and continuing to refer to... Figure 13The duration of the row drive phase H includes four sub-phases, which can overlap with the peak phase tb, the falling phase tc, the trough phase td, and the rising phase ta, respectively. The write period t1 can overlap with the first sub-phase, that is, the write period t1 can overlap with the peak phase tb. Thus, the data signal data written by the display unit 200 during the write period t1 can remain stable and essentially unchanged, ensuring that each row of the display unit 200 remains essentially stable, neither too bright nor too dark. Figure 13 The horizontal lines filling the display area AA (display unit 200) help improve the display effect and reduce the water ripple phenomenon. In addition, even under the coupling influence of the charging signal wsc, if each row of display units 200 has a certain degree of brightness deviation, the brightness deviation of each row of display units 200 can be kept consistent, either all brighter or all darker, which helps to avoid local brightness or local darkness, and also helps to improve the display effect.

[0088] It is understandable that when the duration of the line drive phase H is twice the half-cycle of the charging signal wsc, the relationship between the four sub-phases of the line drive phase H and the periodic pulse signal of the charging signal wsc is not limited to... Figure 12 and Figure 13 The relationships shown, for example, the four sub-stages of the row-driven stage H can also overlap with the trough stage td, the rising stage ta, the peak stage tb, and the falling stage tc, or the rising stage ta, the peak stage tb, the falling stage tc, and the trough stage td, respectively. Figure 12 and Figure 13 (Not shown in the image) The write period t1 can overlap with the second, third, or fourth sub-stage, which can also avoid local overexposure or underexposure, thus improving the display effect and reducing the water ripple effect. The same applies when the duration of the row drive stage H is half the period of the charging signal wsc or other even multiples. In the display time DF of one frame, the change phase of the charging signal wsc that overlaps in the write periods t1 of two adjacent row drive stages H is the same, which can avoid local overexposure or underexposure, thus improving the display effect and reducing the water ripple effect.

[0089] Optional, Figure 14 This is a schematic diagram of another display device provided in an embodiment of this application. Figure 15 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 14 and Figure 15The display panel 010 also includes multiple demux circuits and multiple ML gate lines. Each demux circuit includes multiple MD1 and MD2 gate switches. Within the same demux circuit, the inputs of the multiple MD1 and MD2 gate switches are electrically connected, their outputs are electrically connected to different data lines DL, and their control terminals are electrically connected to different ML gate lines. The display drive signal also includes a strobe signal sob, and the ML gate line is configured to transmit the sob signal. The horizontal drive phase H includes multiple strobe periods tm. During tm, the sob signal is at an enabled level, one of the demux gate switches (MD1 or MD2) is turned on, and the data line DL is filled with the data signal data. During the gating period tm, the gating signal sob includes a first starting voltage edge J1 that transitions from a disabled level to an enabled level; during the row drive phase H, the duration between the first starting voltage edges J1 of adjacent gating periods tm is a first duration Δt01, which is an integer multiple of a quarter cycle of the charging signal wsc.

[0090] In some implementations, the row driving phase H includes multiple gating time periods tm, and the number of gating time periods tm in the same row driving phase H is equal to the number of gating switches in the gating circuit demux; in the same row driving phase H, the multiple gating switches in the gating circuit demux are turned on in a time-division manner.

[0091] For example, the display panel 010 includes a first gate line ML1 and a second gate line ML2. The gate circuit demux includes a first gate switch MD1 and a second gate switch MD2. The first gate line ML1 can be electrically connected to the control terminal of the first gate switch MD1, and the second gate line ML2 can be electrically connected to the control terminal of the second gate switch MD2. The first gate line ML1 can transmit a first gate signal sob1, and the second gate line ML2 can transmit a second gate signal sob2. The first gate switch MD1 and the second gate switch MD2 can be electrically connected to the first data line DL1 and the second data line DL2, respectively, to provide a first data signal data1 and a second data signal data2 to the first data line DL1 and the second data line DL2 in a time-division multiplexing manner when the circuit is turned on. In some embodiments, the first data line DL1 can be electrically connected to the odd-numbered column display unit 200, and the second data line DL2 can be electrically connected to the even-numbered column display unit 200.

[0092] In one embodiment, both the first gating switch MD1 and the second gating switch MD2 include P-type transistors. The enable levels of both the first gating signal sob1 and the second gating signal sob2 are low, and the periods during which the first gating signal sob1 and the second gating signal sob2 are enabled do not overlap. When the first gating signal sob1 is low, the first gating switch MD1 is turned on, and the gating circuit demux can provide the first data signal data1 to the first data line DL1. When the first gating signal sob1 is high, the first data signal data1 on the first data line DL1 is floating. When the second gating signal sob2 is low, the second gating switch MD2 is turned on, and the gating circuit demux can provide the second data signal data2 to the second data line DL2. When the second gating signal sob2 is high, the second data signal data2 on the second data line DL2 is floating. In other embodiments, the gating switches may also include N-type transistors, in which case the enable level of the gating signal sob is high. For ease of understanding and explanation, unless otherwise specified, the following text will use the example of a gating switch including a P-type transistor and a gating signal sob having a low enable level.

[0093] For example, taking the first duration Δt01 as one-quarter of the cycle of the charging signal wsc as an example, and continuing to refer to... Figure 14 and Figure 15 The duration of the horizontal drive phase H can be twice a quarter cycle of the charging signal wsc. The horizontal drive phase H can include two sub-phases, each with a duration equal to a quarter cycle of the charging signal wsc. In the first sub-phase, the first gating switch MD1 is turned on, and the gating circuit demux provides the first data signal data1 to the first data line DL1. The change in the first data signal data1 is only related to the charging signal wsc in the current first sub-phase. Figure 15 The position of the solid line representing the first data signal data1 in the first sub-stage of the BOC drive phase H corresponds to the dashed arrow in the current sub-stage; the second data signal data2 on the second data line DL2 is floating, and the change of the second data signal data2 is related to the charging signal wsc of the current first sub-stage and the second sub-stage of the previous BOC drive phase H. In the second sub-stage, the second gating switch MD2 is turned on, and the gating circuit demux provides the second data signal data2 to the second data line DL2. The change of the second data signal data2 is only related to the charging signal wsc of the current first sub-stage. Figure 15The position of the solid line of the second data signal data2 in the second sub-stage of the BOC drive phase H corresponds to the dashed arrow of the current sub-stage; the first data signal data1 on the first data line DL1 is floating, and the change of the first data signal data1 is related to the charging signal wsc of the current second sub-stage and the first sub-stage before it. Figure 15 Does the position of the solid line of the first data signal data1 in the second sub-stage of the Bank of China's driving phase H correspond to the dashed arrow of the current sub-stage?

[0094] In the time DF of one frame, during the odd-numbered line drive phase H, the first sub-phase can overlap with the falling phase tc of the charging signal wsc. The second data signal data2 on the first data line DL1 and the second data line DL2 is coupled and reduced. The first data signal data1 is not floating and is not affected by the changes in the second sub-phase of the previous line drive phase H. The first data signal data1 is less than its set value. The second data signal data2 is floating and is affected by the changes in the second sub-phase of the previous line drive phase H. The second data signal data2 can also be less than its set value. Each sub-stage can overlap with the trough stage td of the charging signal wsc. The first data signal data1 on the first data line DL1 and the second data signal data2 on the second data line DL2 remain basically stable. The first data signal data1 is floating. The first data signal data1 is affected by the changes in the first sub-stage. The first data signal data1 is still in a state of being reduced by the coupling of the charging signal wsc. The first data signal data1 is less than its set value. The second data signal data2 is not floating. The second data signal data21 is not affected by the changes in the first sub-stage. The second data signal data2 is basically equal to its set value.

[0095] In the time DF of one frame, during the even-numbered line drive phase H, the first sub-phase can overlap with the rising phase ta of the charging signal wsc. The second data signal data2 on the first data line DL1 and the second data line DL2 is coupled and increased. The first data signal data1 is not floating and is not affected by the changes in the second sub-phase of the previous line drive phase H. The first data signal data1 is greater than its set value. The second data signal data2 is floating and is affected by the changes in the second sub-phase of the previous line drive phase H. The second data signal data2 can also be greater than its set value. Each sub-stage can overlap with the peak stage tb of the charging signal wsc. The first data signal data1 on the first data line DL1 and the second data signal data2 on the second data line DL2 remain basically stable. The first data signal data1 is floating. The first data signal data1 is affected by the changes in the first sub-stage. The first data signal data1 is still in a state of being increased by coupling with the charging signal wsc. The first data signal data1 is greater than its set value. The second data signal data2 is not floating. The second data signal data21 is not affected by the changes in the first sub-stage. The second data signal data2 is basically equal to its set value.

[0096] The write period t1 of the row driving stage H can be located in the second sub-stage of the row driving stage H. In one embodiment, the write period t1 can overlap with the period when the second gating switch MD2 is turned on. During the write period t1 of the odd-numbered row driving stage H in the time DF of one frame, the display units 200 located in the odd-numbered columns of the odd-numbered row display units 200 can write a first data signal data1 that is less than a set value, and the display units 200 located in the even-numbered columns of the odd-numbered row display units 200 can write a second data signal data2 that is basically equal to the set value. That is, the display units 200 located in the odd-numbered columns of the odd-numbered row display units 200 are brighter, and the display units 200 located in the even-numbered columns of the odd-numbered row display units 200 are neither brighter nor darker. During the writing period t1 of the even-numbered row driving stage H of the time DF in one frame, the display unit 200 located in the odd-numbered column of the even-numbered row display unit 200 can write a first data signal data1 greater than the set value, and the display unit 200 located in the even-numbered column of the even-numbered row display unit 200 can write a second data signal data2 that is basically equal to the set value. That is, the display unit 200 located in the odd-numbered column of the even-numbered row display unit 200 is darker, and the display unit 200 located in the even-numbered column of the even-numbered row display unit 200 is neither brighter nor darker.

[0097] Thus, in the same row of display units 200, the data signals written by multiple display units 200 arranged along the first direction X row can also change periodically, and the brightness of the display units 200 can also change periodically. Multiple display units 200 in the same row (e.g., adjacent odd-numbered column display units 200 and even-numbered column display units 200 in the same row) can perform brightness deviation equalization or brightness deviation cancellation, which is also beneficial to improve the display abnormality problem caused by the coupling of charging signal and data signal, so as to avoid multiple consecutive columns of display units being too bright or too dark, resulting in a water ripple phenomenon and affecting the display effect of the display device. At the same time, combined with the above description, adjacent odd-numbered row display units 200 and even-numbered row display units 200 in the same column can perform brightness deviation equalization or brightness deviation cancellation, which can avoid the same brightness deviation of display units 200 in the same row or column, which is beneficial to further optimize and improve the display abnormality problem caused by the coupling of charging signal and data signal, so as to avoid multiple consecutive rows or columns of display units being too bright or too dark, resulting in a bright and dark stripe phenomenon and affecting the display effect of the display device.

[0098] In an optional embodiment, Figure 16 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 16 The first duration Δt01 is twice a quarter cycle of the charging signal wsc.

[0099] For example, refer to Figure 16 The row drive phase H includes two gating periods tm; the duration of the row drive phase H is three times a quarter cycle of the charging signal wsc. The row drive phase H can include three sub-phases, the duration of which is equal to a quarter cycle of the charging signal wsc. In the first sub-phase, the first gating signal sob1 on the first gating line ML1 is enabled, the first gating switch MD1 is turned on, and the gating circuit demux charges the first data signal data1 to the first data line DL1. In the third sub-phase, the second gating signal sob2 on the second gating line ML2 is enabled, the second gating switch MD2 is turned on, and the gating circuit demux charges the second data signal data2 to the second data line DL2. The write period t1 overlaps with the third sub-phase, that is, the write period t1 can overlap with the period when the second gating switch MD2 is turned on.

[0100] In the time DF of one frame, in the odd-numbered row driving stage H, the first sub-stage can overlap with the falling stage tc or rising stage ta of the charging signal wsc, and the third sub-stage can overlap with the rising stage ta or the falling stage tc; in the even-numbered row driving stage H, the first sub-stage can overlap with the peak stage tb or the trough stage td of the charging signal wsc, and the third sub-stage can overlap with the trough stage td or the peak stage tb. During the writing period t1 of the odd-numbered row driving stage H of one frame, the display units 200 located in the odd-numbered columns of the odd-numbered row display units 200 can write a first data signal data1 that is basically equal to the set value, and the display units 200 located in the even-numbered columns of the odd-numbered row display units 200 can write a second data signal data2 that is greater than the set value. That is, the display units 200 located in the odd-numbered columns of the odd-numbered row display units 200 are neither too bright nor too dark, and the display units 200 located in the even-numbered columns of the odd-numbered row display units 200 are too dark. During the writing period t1 of the even-numbered row driving stage H of the time DF in one frame, the display unit 200 located in the odd-numbered column of the even-numbered row display unit 200 can write a first data signal data1 that is less than the set value, and the display unit 200 located in the even-numbered column of the even-numbered row display unit 200 can write a second data signal data2 that is basically equal to the set value. That is, the display unit 200 located in the odd-numbered column of the even-numbered row display unit 200 is brighter, and the display unit 200 located in the even-numbered column of the even-numbered row display unit 200 is neither brighter nor darker.

[0101] Thus, the data signals written by multiple display units 200 arranged along the first direction X row in the same row display unit 200 and the data signals written by multiple display units 200 arranged along the second direction Y row in the same column display unit 200 can both exhibit periodic changes. This is beneficial for achieving brightness deviation balance or cancellation in the first direction X row direction and the second direction Y column direction. Furthermore, when the row driving phase H includes two gating periods tm, and the duration of the row driving phase H is three times a quarter cycle of the charging signal wsc, it also ensures that the brighter and darker display units 200 are neither located in the same row nor in the same column. This further improves the display effect and avoids the brighter and darker display units 200 being located adjacent to each other in the same row or column, which would cause the center distance of the brighter and darker display units 200 to be too close, increasing the contrast in the same row or column and hindering the improvement of the display effect.

[0102] In another optional embodiment, the duration of the line driving phase H is 2n+1 times half the period of the charging signal wsc; where n is a positive integer.

[0103] For example, continuing with the first duration Δt01 being twice a quarter cycle of the charging signal wsc, and taking the row drive phase H as an example, which includes two gating periods tm, Figure 17 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 17 The duration of the line drive phase H is six times the quarter-cycle of the charging signal wsc, which is three times the half-cycle of the charging signal wsc. (Reference) Figure 17 The row drive phase H can include six sub-phases. The duration of each sub-phase is equal to one-quarter of the cycle of the charging signal wsc. In the first sub-phase, the first gating signal sob1 on the first gating line ML1 is enabled, the first gating switch MD1 is turned on, and the gating circuit demux charges the first data signal data1 to the first data line DL1. In the third sub-phase, the second gating signal sob2 on the second gating line ML2 is enabled, the second gating switch MD2 is turned on, and the gating circuit demux charges the second data signal data2 to the second data line DL2. The write period t1 overlaps with the third sub-phase, that is, the write period t1 can overlap with the period when the second gating switch MD2 is turned on.

[0104] In the time DF of a frame, in the odd-numbered row driving stage H, the first sub-stage can overlap with the peak stage tb of the charging signal wsc, and the third sub-stage can overlap with the trough stage td; in the even-numbered row driving stage H, the first sub-stage can overlap with the trough stage td of the charging signal wsc, and the third sub-stage can overlap with the peak stage tb. The display units 200 in odd-numbered rows and columns are brighter, while those in even-numbered columns are neither brighter nor darker; similarly, the display units 200 in odd-numbered rows and columns are darker, while those in even-numbered rows and columns are neither brighter nor darker. This also helps to achieve brightness deviation balance or cancellation in the first direction (X-row) and the second direction (Y-column).

[0105] It should be noted that the above implementation only illustrates the case where the write time period t1 overlaps with the last strobe time period tm in the row-driven stage H. In other implementations, the write time period t1 may not overlap with the last strobe time period tm in the row-driven stage H. In other implementations, Figure 18 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 18 Time series and Figure 17 The difference in timing is that, Figure 18 The write period t1 overlaps with the fourth sub-stage, but the write period t1 does not overlap with the period when the second gating switch MD2 is turned on. (Reference) Figure 18The display units 200 in odd-numbered rows and odd-numbered columns of the odd-numbered display units 200 are neither too bright nor too dark, while the display units 200 in even-numbered columns of the odd-numbered display units 200 are slightly darker; the display units 200 in odd-numbered columns of the even-numbered display units 200 are neither too bright nor too dark, while the display units 200 in even-numbered columns of the even-numbered display units 200 are slightly brighter. This also helps to achieve a balance or cancellation of brightness deviations in the first direction (X-row) and the second direction (Y-column).

[0106] It should also be noted that the above implementation only exemplifies that the row-driven stage H includes two gating periods tm. In other implementations, the row-driven stage H may also include three or four gating periods tm, which are greater than two. Figure 19 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, and... Figure 18 Compared to the other options, Figure 19 The scheme includes a third gating line ML3 in the display panel, and a third gating switch MD3 in the gating circuit demux. The third gating line ML3 can be electrically connected to the control terminal of the third gating switch MD3, and can transmit a third gating signal sob3. The third gating switch MD3 can be electrically connected to a third data line DL3 to provide a third data signal data3 to the third data line DL3 when it is turned on. In some embodiments, the first data line DL1 can be electrically connected to the 3×q+1 column display unit 200, the second data line DL2 can be electrically connected to the 3×q+2 column display unit 200, and the third data line DL3 can be electrically connected to the 3×q+3 column display unit 200, where q is a non-negative integer. (Reference) Figure 19 In odd-numbered row display units 200, the display units 200 located in the 3×q+1 and 3×q+3 columns are slightly darker, while the display unit 200 located in the 3×q+2 column is neither too bright nor too dark. In even-numbered row display units 200, the display units 200 located in the 3×q+1 and 3×q+3 columns are slightly brighter, while the display unit 200 located in the 3×q+2 column is neither too bright nor too dark. This also helps to achieve brightness deviation balance or brightness deviation cancellation in the first direction (X-row) and the second direction (Y-column).

[0107] Figure 20 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, and... Figure 19 Compared to the other options, Figure 20The scheme includes a fourth gate line ML4 in the display panel, and a fourth gate switch MD4 in the demux circuit. The fourth gate line ML4 can be electrically connected to the control terminal of the fourth gate switch MD4, and can transmit a fourth gate signal sob4. The fourth gate switch MD4 can be electrically connected to a fourth data line DL4 to provide a fourth data signal data4 to the fourth data line DL4 when it is turned on. The first data line DL1 can be electrically connected to the 4×q+1 column display unit 200, the second data line DL2 can be electrically connected to the 4×q+2 column display unit 200, the third data line DL3 can be electrically connected to the 4×q+3 column display unit 200, and the fourth data line DL4 can be electrically connected to the 4×q+4 column display unit 200, where q is a non-negative integer. (Reference) Figure 20 In odd-numbered row display units 200, the display units 200 located in the 4×q+1 and 4×q+3 columns are slightly darker, while the display units 200 located in the 4×q+2 and 4×q+4 columns are neither too bright nor too dark. In even-numbered row display units 200, the display units 200 located in the 4×q+1 and 4×q+3 columns are slightly brighter, while the display units 200 located in the 4×q+2 and 4×q+4 columns are neither too bright nor too dark. This also helps to achieve brightness deviation balance or brightness deviation cancellation in the first direction (X-row) and the second direction (Y-column).

[0108] Based on the above embodiments, the strobe signal sob includes the j-th strobe signal sob and the (j+1)-th strobe signal sob; during the display time DF of a frame, in the i-th line driving stage H, the j-th strobe signal sob jumps to the enable level before the (j+1)-th strobe signal sob, and in the (i+1)-th line driving stage H, the j-th strobe signal sob jumps to the enable level before the (j+1)-th strobe signal sob; i and j are both positive integers.

[0109] For example, refer to Figures 15 to 20Multiple gating signals sob are transmitted on multiple gating lines ML. The line driving phase H includes multiple gating time periods tm. In the line driving phase H, the multiple gating signals sob transmitted on multiple gating lines ML change to the enable level in the same order. During the display time DF of one frame, the first gating signal sob that changes to the enable level in the i-th line driving phase H and the first gating signal sob that changes to the enable level in the (i+1)-th line driving phase H are gating signals sob transmitted on the same gating line ML. The second gating signal sob that changes to the enable level in the i-th line driving phase H and the second gating signal sob that changes to the enable level in the (i+1)-th line driving phase H are gating signals sob transmitted on the same gating line ML. This continues until the last gating signal sob that changes to the enable level in the i-th line driving phase H and the last gating signal sob that changes to the enable level in the (i+1)-th line driving phase H are gating signals sob transmitted on the same gating line ML. Thus, in the row driving stage H, the display unit 200 connected to the first data line DL1 and the display unit 200 connected to the second data line DL2 can be sequentially charged with data signals data. This is beneficial to make the data signals data written by the multiple display units 200 arranged along the first direction X row have periodic changes, and / or the data signals data written by the multiple display units 200 arranged along the second direction Y row have periodic changes, so as to achieve brightness deviation balance or brightness deviation cancellation in the first direction X row direction and the second direction Y column direction.

[0110] Based on the above embodiments, the strobe signal sob can also include the j-th strobe signal sob and the (j+1)-th strobe signal sob; during the display time DF of a frame, in the i-th line driving stage H, the j-th strobe signal sob jumps to the enable level before the (j+1)-th strobe signal sob, and in the (i+1)-th line driving stage H, the (j+1)-th strobe signal sob jumps to the enable level before the j-th strobe signal sob; i and j are both positive integers.

[0111] For example, Figure 21 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 22 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 21 and Figure 22Multiple gating signals sob are transmitted on multiple gating lines ML. The row driving phase H includes multiple gating time periods tm. In adjacent row driving phases H, the multiple gating signals sob transmitted on multiple gating lines ML change to the enable level in reverse order. During the display time DF of one frame, the first gating signal sob that transitions to the enable level in the i-th line driving stage H and the last gating signal sob that transitions to the enable level in the (i+1)-th line driving stage H are gating signals sob transmitted on the same gating line ML. The second gating signal sob that transitions to the enable level in the i-th line driving stage H and the second-to-last gating signal sob that transitions to the enable level in the (i+1)-th line driving stage H are gating signals sob transmitted on the same gating line ML. This continues until the last gating signal sob that transitions to the enable level in the i-th line driving stage H and the first gating signal sob that transitions to the enable level in the (i+1)-th line driving stage H are gating signals sob transmitted on the same gating line ML.

[0112] Figure 21 The order in which the strobe signals sob in the odd-numbered line drive stage H of a frame display time transition to the enable level is related to the display time of a single frame. Figure 18 In the display time of a frame, the order in which the strobe signals sob in the odd-numbered line driving stage H of DF change to the enable level is the same. Figure 21 and Figure 18 The difference between the two solutions is that Figure 21 The display time of a frame in DF, the order in which the strobe signals sob in the even-numbered line drive stage H transition to the enable level, and the sequence of transitions are related to... Figure 18 In the display time of a frame, the order in which the strobe signals sob in the even-numbered line drive stage H of DF change to the enable level is reversed. Figure 21 Brightness deviation of odd-numbered row display units 200 and Figure 18 The brightness deviation of the odd-numbered row display units 200 is the same; Figure 21 The brightness deviation of the display units 200 located in the odd-numbered columns of the even-numbered rows of display units 200 and Figure 18 The brightness deviation of the display units 200 located in even-numbered columns among the even-numbered row display units 200. Figure 21 The brightness deviation of the display units 200 located in even-numbered columns of the even-numbered row display units 200 and Figure 18 The brightness deviation of the display units 200 located in odd-numbered columns within the even-numbered rows of display units 200 is the same; that is, compared to... Figure 18 Brightness deviation of the display unit 200 Figure 21 The brightness deviations of the display units 200 located in the odd and even columns of the even-numbered rows of the display units 200 are arranged symmetrically.

[0113] Figure 22 The order in which the strobe signals sob in the odd-numbered line drive stage H of a frame display time transition to the enable level is related to the display time of a single frame. Figure 20 In the display time of a frame, the order in which the strobe signals sob in the odd-numbered line driving stage H of DF change to the enable level is the same. Figure 22 and Figure 20 The difference between the two solutions is that Figure 22 The display time of a frame in DF, the order in which the strobe signals sob in the even-numbered line drive stage H transition to the enable level, and the sequence of transitions are related to... Figure 20 In the display time of a frame, the order in which the strobe signals sob in the even-numbered line drive stage H of DF transition to the enable level is reversed. Similarly, compared to Figure 20 Brightness deviation of the display unit 200 Figure 22 The brightness deviations of the display units 200 located in the 4×q+1, 4×q+2, 4×q+3 and 4×q+4 columns of the even-numbered row display units 200 are arranged symmetrically.

[0114] By adjusting the order in which the strobe signals sob transition to the enable level in a portion of the row driving stage H, the order in which the strobe signals sob transition to the enable level in two adjacent row driving stages H can be different. This can change the distribution of brightness deviation in a portion of the row display unit 200, thereby flexibly adjusting the brightness deviation in the display unit 200 and further improving the display effect.

[0115] In other alternative embodiments, Figure 23 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 23 The first duration Δt01 is three times a quarter cycle of the charging signal wsc.

[0116] For example, refer to Figure 23The row drive phase H includes three gating periods tm. The duration of the row drive phase H is ten times the quarter-cycle of the charging signal wsc, or five times the half-cycle of the charging signal wsc. The row drive phase H can include ten sub-phases, each with a duration equal to a quarter-cycle of the charging signal wsc. In the first sub-phase, the first gating signal sob1 on the first gating line ML1 is enabled, the first gating switch MD1 is turned on, and the gating circuit demux charges the first data signal data1 to the first data line DL1. In the fourth sub-phase, the second gating signal sob2 on the second gating line ML2 is enabled, the second gating switch MD2 is turned on, and the gating circuit demux charges the second data signal data2 to the second data line DL2. In the seventh sub-phase, the third gating signal sob3 on the third gating line ML3 is enabled, the third gating switch MD3 is turned on, and the gating circuit demux charges the third data signal data3 to the third data line DL3. The write period t1 overlaps with the ninth sub-phase.

[0117] Continue to refer to Figure 23 In the first driving phase H, the first sub-phase can overlap with the rising phase ta or the falling phase tc, the fourth sub-phase can overlap with the trough phase td or the peak phase tb, the seventh sub-phase can overlap with the falling phase tc or the rising phase ta, and the ninth sub-phase can overlap with the rising phase ta or the falling phase tc. That is, the write period t1 can overlap with the rising phase ta or the falling phase tc. In odd-numbered row display units 200, the display units 200 located in the 3×q+1 and 3×q+2 columns are slightly darker, while the display unit 200 located in the 3×q+3 column is neither too bright nor too dark. In even-numbered row display units 200, the display units 200 located in the 3×q+1 and 3×q+2 columns are slightly brighter, while the display unit 200 located in the 3×q+3 column is neither too bright nor too dark. The data signals written to the multiple display units 200 arranged along the first X-row and the multiple display units 200 arranged along the second Y-row can also exhibit periodic changes, which is also beneficial for achieving brightness deviation balance or brightness deviation cancellation in the first X-row and second Y-row directions.

[0118] Based on the above embodiments, continue to refer to Figure 23 The duration of the row driving phase H is 2n+1 times half the period of the charging signal wsc; n is a positive integer, which is beneficial for achieving brightness deviation balance or brightness deviation cancellation in the first direction X row direction and the second direction Y column direction.

[0119] Optional, Figure 24This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 25 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 24 , Figure 25 The diagram also shows a portion of the structure within the display panel 010, for reference. Figure 24 and Figure 25 The display unit 200 includes a first color display unit 201, a second color display unit 202, and a third color display unit 203; multiple first color display units 201 are arranged in columns along the second direction Y to form a first color display column LC1, multiple second color display units LC2 are arranged in columns along the second direction Y to form a second color display column LC2, and multiple third color display units LC2 are arranged in columns along the second direction Y to form a third color display column LC3; the first color display column LC1, the second color display column LC2, and the third color display column LC3 constitute a display column group LCG, which is arranged along the first direction X; in the display column group LCG, the first color display column LC1, the second color display column LC2, the third color display column LC3, and the second color display column LC2 are arranged sequentially along the first direction X; the second color display unit 202 is configured to display green.

[0120] The gating period tm includes a first gating period tm1 and a second gating period tm2. During the row driving phase H, the first gating period tm1 is located before or after the second gating period tm2. During the first gating period tm1, the data line DL electrically connected to the first color display column LC1 or the third color display column LC3 is charged with the data signal data. During the second gating period tm2, the data line DL electrically connected to the second color display column LC2 is charged with the data signal data.

[0121] In an optional embodiment, the write period t1 and the second gating period tm2 do not overlap; during the write period t1, the scan signal scan includes a second starting voltage edge J2 that transitions from an enabled level to an enabled level; during the row drive phase H, the duration between the first starting voltage edge J1 of the second gating period tm2 and the second starting voltage edge J2 of the write period t1 is a second duration Δt02; the second duration Δt02 is greater than or equal to twice a quarter-cycle of the charging signal wsc, and less than or equal to three times a quarter-cycle of the charging signal wsc; wherein the gating period tm overlaps with the rising phase ta or falling phase tc of the charging signal wsc, that is, the gating period tm does not overlap with the peak time tb of the charging signal wsc, nor does the gating period tm overlap with the trough time td of the charging signal wsc.

[0122] For example, refer to Figure 24 and Figure 25The display panel includes a first gating line ML1 and a second gating line ML2, and the gating circuit demux includes a first gating switch MD1 and a second gating switch MD2. During the first gating period tm1, the first gating signal sob1 transmitted by the first gating line ML1 is at an enabled level, and the gating circuit demux can charge the first data signal data1 to the first data line DL1 electrically connected to the first color display column LC1, or to the first data line DL1 electrically connected to the third color display column LC3. During the second gating period tm2, the second gating signal sob2 transmitted by the second gating line ML2 is at an enabled level, and the gating circuit demux can charge the second data signal data2 to the second data line DL2 electrically connected to the second color display column LC2. In one embodiment, the first color display unit 201 is configured to display red, and the third color display unit 202 is configured to display blue; in another embodiment, the first color display unit 201 is configured to display blue, and the third color display unit 202 is configured to display red. In some implementations, the duration of the row drive phase H can be three times half the period of the charging signal wsc. In the row drive phase H, the first gating period tm1 and the second gating period tm2 can overlap with the successively adjacent rising phase ta and falling phase tc, respectively. Alternatively, the first gating period tm1 and the second gating period tm2 can also overlap with the successively adjacent falling phase tc and rising phase ta, respectively.

[0123] In an optional implementation, within the same row driving phase H, the first gating period tm1 precedes the second gating period tm2.

[0124] For example, refer to Figure 24 In the same row driving phase H, the write period t1 and the last gating period tm do not overlap. When the second duration Δt02 is twice a quarter period of the charging signal wsc, in the same row driving phase H, the write period t1 and the first gating period tm1 overlap with the same phase (rising phase ta or falling phase tc) of the charging signal wsc; when the second duration Δt02 is three times a quarter period of the charging signal wsc, in the same row driving phase H, the period between the first gating period tm1 and the second gating period tm2 can overlap with the same phase (peak phase tb or trough phase td) of the write period t1 and the charging signal wsc.

[0125] Thus, during the write phase t1 of each row driving phase H, the absolute value of the difference between the first data signal data1 on the first data line DL1, which is electrically connected to the first color display column LC1 or the third color display column LC3, and the set value is relatively large, while the absolute value of the difference between the second data signal data2 on the second data line DL2, which is electrically connected to the second color display column LC2, and the set value is relatively small. This allows the display unit 200 with a larger brightness deviation to be located in the first color display column LC1 and / or the third color display column LC3, while the display unit 200 with a smaller brightness deviation (neither too bright nor too dark) is located in the second color display column LC2. This is beneficial for improving display uniformity and avoids a large deviation in the data signal data received by the second display unit 202 with higher luminous efficiency, which would lead to a large brightness deviation in the second display unit 202 in the second color display column LC2 and affect display uniformity.

[0126] In another alternative implementation, in the same row driving phase H, the first gating period tm1 is located after the second gating period tm2.

[0127] For example, refer to Figure 25 When the second duration Δt02 is twice the quarter-cycle of the charging signal wsc, in the same row driving stage H, the write period t1 can overlap with the last gating period tm, that is, the write period t1 can overlap with the first gating period tm1; when the second duration Δt02 is three times the quarter-cycle of the charging signal wsc, the write period t1 can be located after the last gating period tm, that is, the write period t1 can be located after the first gating period tm1, and the write period t1 can not overlap with the first gating period tm1. Similarly, in the write stage t1 of each row driving stage H, the absolute value of the difference between the first data signal data1 on the first data line DL1, which is electrically connected to the first color display column LC1 or the third color display column LC3, and the set value is relatively large, while the absolute value of the difference between the second data signal data2 on the second data line DL2, which is electrically connected to the second color display column LC2, and the set value is relatively small. This allows the display unit 200 with a larger brightness deviation to be located in the first color display column LC1 and / or the third color display column LC3, while the display unit 200 with a smaller brightness deviation (neither too bright nor too dark) is located in the second color display column LC2. This is beneficial for improving display uniformity and avoids a large deviation in the data signal data received by the second display unit 202 with higher luminous efficiency, which would lead to a large brightness deviation in the second display unit 202 in the second color display column LC2 and affect display uniformity.

[0128] In another alternative embodiment, Figure 26 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 26 The diagram also shows a portion of the structure within the display panel 010, for reference. Figure 26 The write period t1 can also overlap with the second gating period tm2; the first gating period tm1 is located before the second gating period tm2, and the duration of the row drive phase H is twice the quarter-cycle of the charging signal wsc, that is, half the cycle of the charging signal wsc; the first gating period tm1 overlaps with the rising phase ta or falling phase tc of the charging signal wsc, that is, the first gating period tm1 does not overlap with the peak time tb of the charging signal wsc, nor does it overlap with the trough time td of the charging signal wsc. In this way, the display unit 200 with a large brightness deviation can be located in the first color display column LC1 and / or the third color display column LC3, and the display unit 200 with a small brightness deviation (neither too bright nor too dark) can be located in the second color display column LC2, which is beneficial to improving display uniformity.

[0129] In yet another alternative embodiment, Figure 27 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 27 The diagram also shows a portion of the structure within the display panel 010, for reference. Figure 27 The gating period tm also includes a third gating period tm3 and a fourth gating period tm4. During the row driving phase H, the first gating period tm1, the second gating period tm2, the third gating period tm3, and the fourth gating period tm4 are performed sequentially. In the first gating period tm1, the data line DL electrically connected to the first color display column LC1 is charged with the data signal data. In the second gating period tm2, the data line DL electrically connected to the second color display column LC2 is charged with the data signal data. In the third gating period tm3, the data line DL electrically connected to the third color display column LC3 is charged with the data signal data. In the fourth gating period tm4, the data line DL electrically connected to the fourth color display column LC4 is charged with the data signal data.

[0130] In the same row driving phase H, the write period t1 is located after the fourth gating period tm4. In the row driving phase H, the duration between the first starting voltage edge J1 of the fourth gating period tm4 and the second starting voltage edge J2 of the write period t1 is the third duration Δt03. The third duration Δt03 is greater than or equal to twice a quarter period of the charging signal wsc, and less than or equal to three times a quarter period of the charging signal wsc. Among them, the gating period tm overlaps with the rising phase ta or falling phase tc of the charging signal wsc. That is, the gating period tm does not overlap with the peak time tb of the charging signal wsc, nor does the gating period tm overlap with the trough time td of the charging signal wsc.

[0131] For example, refer to Figure 27The display panel also includes a third gating line ML3 and a fourth gating line ML4, and the gating circuit demux also includes a third gating switch MD3 and a fourth gating switch MD4. During the first gating period tm1, the first gating signal sob1 transmitted by the first gating line ML1 is at an enabled level, and the gating circuit demux can charge the first data signal data1 to the first data line DL1 electrically connected to the first color display column LC1; during the second gating period tm2, the second gating signal sob2 transmitted by the second gating line ML2 is at an enabled level, and the gating circuit demux can charge the second data signal data2 to the second data line DL2 electrically connected to the second color display column LC2; during the third gating period tm3, the third gating signal sob3 transmitted by the third gating line ML3 is at an enabled level, and the gating circuit demux can charge the third data signal data3 to the third data line DL3 electrically connected to the third color display column LC3; during the fourth gating period tm4, the fourth gating signal sob3 transmitted by the fourth gating line ML4 is at an enabled level, and the gating circuit demux can charge the fourth data signal data4 to the fourth data line DL4 electrically connected to the second color display column LC2. In one embodiment, the first color display unit 201 is configured to display red, and the third color display unit 202 is configured to display blue; in another embodiment, the first color display unit 201 is configured to display blue, and the third color display unit 202 is configured to display red. In some embodiments, the duration of the row driving phase H can be five times half the cycle of the charging signal wsc. This allows display units 200 with larger brightness deviations to be located in the first color display column LC1 and / or the third color display column LC3, while display units 200 with smaller brightness deviations (neither too bright nor too dark) are located in the second color display column LC2, which is beneficial for improving display uniformity.

[0132] Optional, Figure 28 This is a timing diagram illustrating the operation of another display device provided in this application embodiment. Figure 28 The diagram also shows a portion of the structure within the display panel 010, for reference. Figure 28The display unit 200 includes a first color display unit 201, a second color display unit 202, and a third color display unit 203; multiple first color display units 201 are arranged in columns along the second direction Y to form a first color display column LC1, multiple second color display units 202 are arranged in columns along the second direction Y to form a second color display column LC2, and multiple third color display units 203 are arranged in columns along the second direction Y to form a third color display column LC; the first color display column LC1, the second color display column LC2, and the third color display column LC3 constitute a display column group LCG, which is arranged along the first direction X; in the display column group LCG, the first color display column LC1, the second color display column LC2, and the third color display column LC3 are arranged sequentially along the first direction X; the second color display unit 202 is configured to display green.

[0133] The gating period tm includes a first gating period tm1, a second gating period tm2, and a third gating period tm3. During the row driving phase H, the second gating period tm2 is located between the first gating period tm1 and the third gating period tm3. During the first gating period tm1, the data line DL electrically connected to the first color display column LC1 is charged with the data signal data. During the second gating period tm2, the data line DL electrically connected to the second color display column LC2 is charged with the data signal data. During the third gating period tm3, the data line DL electrically connected to the third color display column LC3 is charged with the data signal data. The gating period tm overlaps with the rising phase ta or falling phase tc of the charging signal wsc. That is, the gating period tm does not overlap with the peak time tb of the charging signal wsc, nor does it overlap with the trough time td of the charging signal wsc.

[0134] For example, refer to Figure 28The display panel includes a first gating line ML1, a second gating line ML2, and a third gating line ML3. The gating circuit demux includes a first gating switch MD1, a second gating switch MD2, and a third gating switch MD3. During the first gating period tm1, the first gating signal sob1 transmitted by the first gating line ML1 is at an enabled level, and the gating circuit demux can charge the first data signal data1 to the first data line DL1 electrically connected to the first color display column LC1. During the second gating period tm2, the second gating signal sob2 transmitted by the second gating line ML2 is at an enabled level, and the gating circuit demux can charge the second data signal data2 to the second data line DL2 electrically connected to the second color display column LC2. During the third gating period tm3, when the third gating signal sob3 transmitted by the third gating line ML3 is at an enabled level, the gating circuit demux can charge the third data signal data3 to the third data line DL3 electrically connected to the third color display column LC3. In one embodiment, the first color display unit 201 is configured to display red and the third color display unit 202 is configured to display blue; in another embodiment, the first color display unit 201 is configured to display blue and the third color display unit 202 is configured to display red.

[0135] The duration of the row drive phase H can be three times half the period of the charging signal wsc. In the row drive phase H, the first gating period tm1, the second gating period tm2, and the third gating period tm3 can overlap with the sequentially adjacent rising phase ta, falling phase tc, and rising phase ta, respectively. Alternatively, the first gating period tm1, the second gating period tm2, and the third gating period tm3 can also overlap with the sequentially adjacent falling phase tc, rising phase ta, and falling phase tc, respectively. The write period t1 can overlap with or not overlap with the last gating period tm. The transition timing of the gating signal wob in two adjacent row drive phases H of the display time DF of the same frame can be the same or different. In this way, the display unit 200 with a larger brightness deviation can be located in the first color display column LC1 and / or the third color display column LC3, while the display unit 200 with a smaller brightness deviation (neither too bright nor too dark) can be located in the second color display column LC2. This is beneficial to improve display uniformity and avoids a large deviation in the data signal data received by the second display unit 202 with higher luminous efficiency, which would result in a large brightness deviation of the second display unit 202 in the second color display column LC2 and affect display uniformity.

[0136] Optional, Figure 29 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 1 and Figure 29The display panel includes a low-frequency display mode, which includes multiple display cycles TF. The display cycle TF includes a first display frame DF1 and a second display frame DF2. The first display frame DF1 is located before the second display frame DF2. In the first display frame DF1, the scan signal scan includes an enable level. In the second display frame DF2, the scan signal scan is at a disable level. In the second display frame DF2, the wireless charging drive circuit 120 provides a charging signal wsc to the wireless charging component 020.

[0137] For example, the display period TF includes a first display frame DF1 and at least one second display frame DF2. In the first display frame DF1, the scan signals scan on multiple scan lines SL all include an enable level. Display units 200 located in different rows write data lines data on data lines DL in a time-division manner, enabling display units 200 to refresh the stored data signals data to display a new image based on the data signals data. In the second display frame DF2, the scan signals scan are disabled, and display units 200 do not write data lines data on data lines DL. The data signals data stored in display units 200 are still the data signals data written in the first display frame DF1 in the same display period TF, and the displayed image remains unchanged, still being the image of the first display frame DF1 in the same display period TF. In the second display frame DF2, the wireless charging drive circuit 120 provides a charging signal wsc to the wireless charging component 020. The charging signal wsc can couple and affect the potential of the data line data on the data line DL. However, the display unit 200 does not write data to the data line data on the data line DL, and the parasitic capacitance between the display unit 200 and the wireless charging component 020 is small. Therefore, the coupling effect of the charging signal wsc on the display unit 200 is negligible. By setting the display panel to include a low-frequency display mode, and including the second display frame DF2, and configuring the wireless charging drive circuit 120 to provide a periodic pulse signal of the charging signal wsc to the wireless charging component 020 in the second display frame DF2, it is beneficial to improve wireless charging efficiency and reduce the impact of wireless charging on the display function.

[0138] In an alternative embodiment, reference continues. Figure 29 In the first display frame DF1, the wireless charging drive circuit 120 stops providing the charging signal wsc to the wireless charging component 020.

[0139] For example, refer to Figure 29The display device 001 includes a wireless charging phase TW. During the wireless charging phase TW, the wireless charging drive circuit 120 provides a charging signal wsc to the wireless charging component 020. The charging signal wsc includes a periodic pulse signal. The wireless charging phase TW may overlap only with the second display frame DF2 and does not overlap with the first display frame DF1. In this way, the charging signal wsc can be avoided from coupling with the data signal data on the data line DL in the first display frame DF1, which would cause the data signal data written by the display unit 200 to deviate significantly from the set value and affect the display effect.

[0140] In another alternative embodiment, Figure 30 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 30 In the first display frame DF1, the wireless charging drive circuit 120 provides a charging signal wsc to the wireless charging component 020. Combined with the content described above, the display units in the display area can exhibit periodic brightness deviations. The display units in the same abnormal display cycle can perform brightness equalization or brightness cancellation, which can also reduce the impact of the charging signal wsc on the display effect.

[0141] Based on the above embodiments, Figure 31 This is a timing diagram illustrating the operation of another display device provided in this application embodiment, with reference to... Figure 31 In the first display frame DF1, the peak voltage of the charging signal wsc is the first peak value; in the second display frame DF2, the peak voltage of the charging signal wsc is the second peak value; the first peak value is less than the second peak value.

[0142] For example, refer to Figure 31 In the first display frame DF1, the jump amplitude and / or maximum voltage change rate of the charging signal wsc are less than those in the second display frame DF1. This helps to reduce the coupling effect of the charging signal wsc on the data signal data in the first display frame DF1, and further reduces the impact of the charging signal wsc on the display effect.

[0143] In some implementations, the switching frequency of the first display frame DF1 of the charging signal wsc is less than the switching frequency of the second display frame DF2 of the charging signal wsc. On the one hand, this helps to reduce the coupling effect of the charging signal wsc on the data signal data in the first display frame DF1. On the other hand, it also helps to improve the charging rate.

[0144] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a display device, used to drive the display device provided in any embodiment of the present invention. Figure 32This is a flowchart of a driving method for a display device provided in an embodiment of the present invention, see reference. Figure 32 The driving methods include: S1001, the duration of the line drive phase is an integer multiple of one-quarter of the charging signal cycle.

[0145] The driving method for the display device provided in this embodiment of the invention can couple the data signal data on the data line DL during the horizontal driving stage H. By setting the duration of the horizontal driving stage to an integer multiple of a quarter cycle of the charging signal wsc, the data signal data on the data line DL can be periodically coupled, so that the brightness change of the display unit 200 also has a periodic change. The display units in the same abnormal display cycle can perform brightness equalization or brightness cancellation, which can improve the display abnormality problem caused by the coupling of the charging signal wsc to the data signal data. It can avoid the regular coupling of the charging signal wsc to the data signal data, which would cause the charging signal wsc to increase or decrease the data signal data in multiple consecutive horizontal driving stages H, resulting in multiple consecutive rows of display units 200 being too bright or too dark, with a regular water ripple phenomenon, affecting the display effect.

[0146] During the initialization phase, the second write module can be turned on by the second scan signal, and the first reference signal at the first reference voltage terminal can be transmitted to the first node through the second write module to initialize the potential of the first node and control the driving transistor to be in the on state. During the threshold compensation phase, the second write module and the compensation module can be turned on by the second scan signal and the third scan signal to compensate the threshold voltage of the driving transistor into the driving transistor. During the writing phase, the first write module can be turned on by the first scan signal, and the data signal at the data voltage terminal can be transmitted to the first node through the first write module. Under the action of the first capacitor and the second capacitor, the third node is partially coupled. The first capacitor can also store the gate-source voltage of the driving transistor. During the light emission phase, the first light emission control module and the second light emission control module can be turned on by the first light emission control signal and the second light emission control signal. The driving current of the pixel circuit can be provided to the light emission element, so that the light emission element emits light. When this pixel circuit is applied to a display panel, it can improve the problems of image retention and low-frequency flicker of the display panel.

[0147] The display device driving method provided in the embodiments of the present invention drives the display device provided in any embodiment of the present invention, and has the corresponding technical features and beneficial effects of the display device. For the contents not described in detail in the embodiments of the display device driving method, please refer to the description of the display device above, and will not be repeated here. Similarly, the display device of the embodiments of the present invention also has functional modules and beneficial effects that can execute the display device driving method provided in the embodiments of the present invention. For the contents not described in detail in the embodiments of the display device, please refer to the description of the display device driving method above, and will not be repeated here.

[0148] The display device provided in this application embodiment can be any electronic product with display function and wireless charging function, including but not limited to the following categories: mobile phone, laptop computer, tablet computer, digital camera, smart bracelet, smart glasses, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0149] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A display device, characterized in that, include: A display panel and a wireless charging assembly, wherein the display panel includes a driving circuit and multiple display units; The driving circuit includes a display driving circuit and a wireless charging driving circuit. The display driving circuit is electrically connected to the display unit, and the display driving circuit is configured to provide a display driving signal to the display unit; The wireless charging drive circuit is electrically connected to the wireless charging component, and the wireless charging drive circuit is configured to provide a charging signal to the wireless charging component; wherein the charging signal includes a periodic pulse signal. The display panel includes multiple scan lines and multiple data lines; the scan lines are electrically connected to multiple display units arranged in rows along a first direction, and the data lines are electrically connected to multiple display units arranged in columns along a second direction, wherein the first direction and the second direction intersect. The display driving signal includes a scan signal and a data signal, the scan line is configured to transmit the scan signal, and the data line is configured to transmit the data signal; The display time of one frame includes multiple line driving stages, and the line driving stage includes a writing period. During the writing period, the scan signal is at the enable level, and the multiple display units arranged in rows along the first direction write the data signal. The duration of the line driving phase is an integer multiple of a quarter cycle of the charging signal.

2. The display device according to claim 1, characterized in that, The duration of the line driving phase is an integer multiple of half a cycle of the charging signal.

3. The display device according to claim 2, characterized in that, The duration of the line driving phase is an odd multiple of half a cycle of the charging signal.

4. The display device according to claim 3, characterized in that, The charging signal includes a rising phase, a peak phase, a falling phase, and a trough phase; In the display time of one frame, the write period of the i-th row driving stage overlaps with the rising phase of the charging signal, and the write period of the (i+1)-th row driving stage overlaps with the falling phase of the charging signal; or, the write period of the i-th row driving stage overlaps with the peak phase of the charging signal, and the write period of the (i+1)-th row driving stage overlaps with the trough phase of the charging signal; i is a positive integer.

5. The display device according to claim 1, characterized in that, The display panel further includes multiple gating circuits and multiple gating lines; the gating circuit includes multiple gating switches; in the same gating circuit, the input terminals of multiple gating switches are electrically connected, the output terminals of multiple gating switches are electrically connected to different data lines respectively, and the control terminals of multiple gating switches are electrically connected to different gating lines respectively. The display drive signal also includes a strobe signal, and the strobe line is configured to transmit the strobe signal; The row driving phase includes multiple gating periods. During the gating period, the gating signal is at an enable level, one of the gating switches in the gating circuit is turned on, and the data line is filled with the data signal. During the gating period, the gating signal includes a first starting voltage edge that transitions from a disabled level to an enabled level; In the row driving phase, the duration between the first starting voltage edges of adjacent gating periods is a first duration, which is an integer multiple of a quarter cycle of the charging signal.

6. The display device according to claim 5, characterized in that, The first duration is twice a quarter cycle of the charging signal.

7. The display device according to claim 5, characterized in that, The duration of the line driving phase is 2n+1 times half the period of the charging signal; n is a positive integer.

8. The display device according to claim 6, characterized in that, The row-driven phase includes two gating periods; The duration of the line drive phase is three times the quarter-cycle of the charging signal.

9. The display device according to claim 5, characterized in that, The gating signal includes the j-th gating signal and the (j+1)-th gating signal; During the display time of one frame, in the i-th row driving phase, the j-th strobe signal jumps to the enable level before the (j+1)-th strobe signal, and in the (i+1)-th row driving phase, the (j+1)-th strobe signal jumps to the enable level before the j-th strobe signal. Both i and j are positive integers.

10. The display device according to claim 5, characterized in that, The gating signal includes the j-th gating signal and the (j+1)-th gating signal; During the display time of one frame, in the i-th row driving phase, the j-th strobe signal jumps to the enable level before the (j+1)-th strobe signal, and in the (i+1)-th row driving phase, the j-th strobe signal jumps to the enable level before the (j+1)-th strobe signal. Both i and j are positive integers.

11. The display device according to claim 5, characterized in that, The first duration is three times a quarter cycle of the charging signal.

12. The display device according to claim 8, characterized in that, The display unit includes a first color display unit, a second color display unit, and a third color display unit; A plurality of first color display units are arranged in a column along a second direction to form a first color display column, a plurality of second color display units are arranged in a column along a second direction to form a second color display column, and a plurality of third color display units are arranged in a column along a second direction to form a third color display column; The first color display column, the second color display column, and the third color display column constitute a display column group, which is arranged along a first direction; in the display column group, the first color display column, the second color display column, the third color display column, and the second color display column are arranged sequentially along the first direction; The gating period includes a first gating period and a second gating period. In the row driving phase, the first gating period is located before or after the second gating period. During the first gating period, the data line electrically connected to the first color display column or the third color display column is charged with the data signal. During the second gating period, the data line electrically connected to the second color display column is charged with the data signal. The writing period does not overlap with the second strobe period; During the write period, the scan signal includes a second start voltage edge that transitions from a disabled level to an enabled level; In the row driving phase, the duration between the first start voltage edge of the second gating period and the second start voltage edge of the write period is the second duration; the second duration is greater than or equal to twice a quarter cycle of the charging signal, and less than or equal to three times a quarter cycle of the charging signal. The gating period overlaps with the rising or falling phase of the charging signal; the second color display unit is configured to display green.

13. The display device according to claim 1, characterized in that, The display panel includes a low-frequency display mode, which includes multiple display cycles. Each display cycle includes a first display frame and a second display frame, with the first display frame preceding the second display frame. In the first display frame, the scan signal includes an enable level; in the second display frame, the scan signal is at a disable level. In the second display frame, the wireless charging drive circuit provides the charging signal to the wireless charging component.

14. The display device according to claim 13, characterized in that, In the first display frame, the wireless charging drive circuit stops providing the charging signal to the wireless charging component.

15. The display device according to claim 13, characterized in that, In the first display frame, the wireless charging drive circuit provides the charging signal to the wireless charging component; In the first display frame, the peak voltage of the charging signal is a first peak value; in the second display frame, the peak voltage of the charging signal is a second peak value; the first peak value is less than the second peak value.

16. A driving method for a display device, characterized in that, The driving method is used to drive the display device according to any one of claims 1-15 to operate; The driving method includes: the duration of the row driving phase is an integer multiple of a quarter cycle of the charging signal.

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