A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area at least partially; the display panel comprises an array substrate, the array substrate comprises pixel driving circuits located in the display area and a plurality of gate driving circuits located in the non-display area; the pixel driving circuit comprises a threshold compensation module, a driving module and a first initialization module, the threshold compensation module writes a threshold voltage for compensating the driving module, and the first initialization module initializes a light emitting element corresponding to the pixel driving circuit; the plurality of gate driving circuits comprises a first gate driving circuit and a second gate driving circuit, the first gate driving circuit drives the threshold compensation module, and the second gate driving circuit drives the first initialization module; the first gate driving circuit and the second gate driving circuit are located in the non-display area close to the display area; and a light shielding layer is located on one side of the array substrate and in the display area and part of the non-display area. The application improves the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] As display panels continue to iterate and be updated, the bezels of these panels are gradually becoming narrower. Narrowing the bezels affects the drive signals of the gate drive circuit and significantly impacts the display effect. Summary of the Invention

[0003] The present invention provides a display panel and a display device to improve the display effect of the display panel.

[0004] According to one aspect of the present invention, a display panel is provided, comprising a display area and a non-display area at least partially surrounding the display area; the display panel includes:

[0005] An array substrate includes a pixel driving circuit located in the display area and a plurality of gate driving circuits located in the non-display area; the pixel driving circuit includes a threshold compensation module, a driving module and a first initialization module, the threshold compensation module is used to write a threshold voltage to compensate the driving module, and the first initialization module is used to initialize the light-emitting element corresponding to the pixel driving circuit;

[0006] The plurality of gate driving circuits include a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is used to drive the threshold compensation module, and the second gate driving circuit is used to drive the first initialization module. The first gate driving circuit and the second gate driving circuit are respectively located in the non-display areas on both sides of the display area, and both are located in the non-display areas close to the display area.

[0007] A light-shielding layer is located on one side of the array substrate and is located in the display area and part of the non-display area.

[0008] Optionally, the pixel driving circuit further includes a data writing module, which is used to write data voltage to the driving module;

[0009] The plurality of gate driving circuits further includes a third gate driving circuit, which is used to drive the data writing module.

[0010] The third gate driving circuit is located in the non-display area on one side of the display area, and is located at a position away from the display area from the first gate driving circuit, or at a position away from the display area from the second gate driving circuit.

[0011] Optionally, the plurality of gate driving circuits further includes a fourth gate driving circuit, which is used to drive the data writing module; the third gate driving circuit has the same structure as the fourth gate driving circuit.

[0012] The third gate driving circuit and the fourth gate driving circuit are respectively located in the non-display areas on both sides of the display area;

[0013] Preferably, the fourth gate driving circuit is located in the non-display area on one side of the display area, and is located at a position away from the display area from the first gate driving circuit, or at a position away from the display area from the second gate driving circuit.

[0014] Optionally, the pixel driving circuit further includes a light emission control module, which is used to control the light emission element to emit light;

[0015] The plurality of gate driving circuits further includes at least one fifth gate driving circuit, the fifth gate driving circuit being used to drive the light emission control module;

[0016] The fifth gate driving circuit is located in the non-display area on one or both sides of the display area, and is located at a position away from the display area from the first gate driving circuit, and / or at a position away from the display area from the second gate driving circuit.

[0017] Optionally, the pixel driving circuit further includes a second initialization module, which is used to initialize the driving module;

[0018] The plurality of gate driving circuits further includes at least one sixth gate driving circuit, the sixth gate driving circuit being used to drive the second initialization module;

[0019] The sixth gate driving circuit is located in the non-display area on one or both sides of the display area, and is located at a position away from the display area from the first gate driving circuit, and / or at a position away from the display area from the second gate driving circuit;

[0020] Preferably, three sets of gate driving circuits are provided in each of the non-display areas on both sides of the display area.

[0021] Optionally, the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0022] Alternatively, the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0023] Alternatively, the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0024] Alternatively, the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0025] Alternatively, the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0026] Alternatively, the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0027] Alternatively, the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0028] Alternatively, the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0029] Alternatively, the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0030] Alternatively, the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0031] Alternatively, the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0032] Alternatively, the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0033] Alternatively, the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0034] Alternatively, the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0035] Alternatively, the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0036] Alternatively, the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

[0037] Optionally, the light-shielding layer covers each of the gate drive circuits.

[0038] Optionally, the distance between the edge of the light-shielding layer and the edge of the display area is greater than a first preset distance.

[0039] Optionally, the pixel driving circuit further includes a storage module and a third initialization module;

[0040] The first end of the light-emitting control module is connected to the first power supply, the second end of the light-emitting control module is connected to the first end of the driving module, the second end of the driving module is connected to the third end of the light-emitting control module, and the fourth end of the light-emitting control module is connected to the first electrode of the light-emitting element.

[0041] The first end of the storage module is connected to the first power supply, and the second end of the storage module is connected to the control end of the drive module;

[0042] The data writing module is connected to the second end of the light emission control module;

[0043] The first end of the threshold compensation module is connected to the second end of the storage module, and the second end of the threshold compensation module is connected to the third end of the light emission control module.

[0044] The second initialization module is connected to the second end of the threshold compensation module;

[0045] The first initialization module is connected to the first electrode of the light-emitting element; the third initialization module is connected to the second end of the driving module.

[0046] According to another aspect of the present invention, a display device is provided, comprising: a display panel provided in any embodiment of the present invention.

[0047] The technical solution provided by this invention optimizes the positions of the first gate driving circuit and the second gate driving circuit, resulting in a more stable driving effect for the threshold compensation module and the first initialization module. This allows the threshold compensation module to better write the threshold voltage of the compensation driving module, and the first initialization module to better initialize the light-emitting elements corresponding to the pixel driving circuit. Through the new arrangement of the gate driving circuits, this invention ensures that the light-shielding layer still blocks the critical gate driving circuits even when the bezel of the display panel is narrow, resulting in a better display effect and preventing horizontal lines and other phenomena caused by illumination.

[0048] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of a first gate driving circuit according to an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of a second gate driving circuit according to an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of another display panel structure provided according to an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of another pixel driving circuit provided according to an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram of the structure of another display panel provided according to an embodiment of the present invention;

[0057] Figure 8 This is a schematic diagram of another pixel driving circuit provided according to an embodiment of the present invention;

[0058] Figure 9 This is a schematic diagram of another pixel driving circuit provided according to an embodiment of the present invention;

[0059] Figure 10 This is a schematic diagram of the structure of a display device according to an embodiment of the present invention. Detailed Implementation

[0060] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0062] This invention provides a display panel. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. (In conjunction with...) Figure 1 and Figure 2 The display panel includes a display area 1 and a non-display area 2 that at least partially surrounds the display area 1. The display panel includes: an array substrate, which includes a pixel driving circuit 10 located in the display area 1 and a plurality of gate driving circuits located in the non-display area 2; the pixel driving circuit 10 includes a threshold compensation module 101, a driving module 102, and a first initialization module 103, wherein the threshold compensation module 101 is used to write a threshold voltage to compensate the driving module 102, and the first initialization module 103 is used to initialize the light-emitting element 104 corresponding to the pixel driving circuit 10; the plurality of gate driving circuits include a first gate driving circuit 21 and a second gate driving circuit 22, wherein the first gate driving circuit 21 is used to drive the threshold compensation module 101, and the second gate driving circuit 22 is used to drive the first initialization module 103; the first gate driving circuit 21 and the second gate driving circuit 22 are respectively located in the non-display areas 2 on both sides of the display area 1, and are both located in the non-display areas 2 close to the display area 1; and a light-shielding layer 3, located on one side of the array substrate, and located in the display area 1 and part of the non-display area 2.

[0063] The light-shielding layer 3 can be used to shield the entire display area 1 and also to shield the gate driving circuit in the non-display area 2. Considering the cutting precision of the display panel and the attachment precision of the light-shielding layer 3, the light-shielding layer 3 cannot completely cover the display area 1 and the non-display area 2, and a certain distance needs to be maintained at the edge of the non-display area 2. As the bezel of the display panel continues to decrease, the area of ​​the non-display area 2 also gradually decreases, and therefore, the area of ​​the light-shielding layer 3 also continuously decreases. At this time, the light-shielding layer 3 may cause light to leak into the gate driving circuit due to its excessively small area, thereby affecting the stability of the driving signal output by the gate driving circuit.

[0064] The non-display area 2 includes multiple gate driving circuits. The first gate driving circuit 21 drives the threshold compensation module 101, allowing it to input the threshold voltage of the compensation driving module 102. This threshold voltage improves the stability of the pixel circuit and enhances display performance. The second gate driving circuit 22 drives the first initialization module 103, enabling it to initialize the light-emitting element 104 corresponding to the pixel driving circuit 10. Before each frame begins display, initializing the light-emitting element 104 removes any residual charge. If residual charge remains on the light-emitting element 104 after the previous frame ends, it will affect the display effect of the next frame, causing uneven brightness and color deviation. Therefore, the ability of the first gate driving circuit 21 and the second gate driving circuit 22 to output stable driving signals is crucial to the display effect of the display panel.

[0065] To minimize the impact of light on the first gate driving circuit 21 and the second gate driving circuit 22, they can be positioned on either side of the display area 1 and close to it. Their positions can be interchanged. In this case, the first gate driving circuit 21 and the second gate driving circuit 22 are located at the furthest distance from the edge of the light-shielding layer 3, thus providing more comprehensive shielding and minimizing their impact from light, enabling continuous and stable operation.

[0066] The technical solution provided by this invention optimizes the positions of the first gate driving circuit and the second gate driving circuit, resulting in a more stable driving effect for the threshold compensation module and the first initialization module. This allows the threshold compensation module to better write the threshold voltage of the compensation driving module, and the first initialization module to better initialize the light-emitting elements corresponding to the pixel driving circuit. Through the new arrangement of the gate driving circuits, this invention ensures that the light-shielding layer still blocks the critical gate driving circuits even when the bezel of the display panel is narrow, resulting in a better display effect and preventing horizontal lines and other phenomena caused by illumination.

[0067] Figure 3 A schematic diagram of a first gate drive circuit is shown as an example. (Reference) Figure 3Optionally, the first gate drive circuit includes: an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0068] Specifically, the control terminals of the eleventh transistor T11 and the thirteenth transistor T13 are connected to the first clock signal SCK1. The first terminal of the eleventh transistor T11 is connected to the control terminal of the twelfth transistor T12. The second terminal of the eleventh transistor T11 is connected to the start pulse signal SIN. The first terminal of the twelfth transistor T12 is connected to the control terminal of the eleventh transistor T11. The second terminal of the twelfth transistor T12 is connected to the first terminal of the thirteenth transistor T13. The second terminal of the thirteenth transistor T13 is connected to the negative low voltage. The first terminal of the fourteenth transistor T14 is connected to the negative high voltage NVGH. The control terminal of the fourteenth transistor T14 is connected to the second terminal of the twelfth transistor T12. The second terminal of the fourteenth transistor T14 is connected to the first terminal of the fifteenth transistor T15. The second terminal and control terminal of the fifteenth transistor T15 are connected to the second clock signal SCK2. The first terminal of the sixteenth transistor T16 is connected to the negative high voltage NVGH. The second terminal of the sixteenth transistor T16 is connected to the first terminal of the seventeenth transistor T17. The control terminal of the sixteenth transistor T16 is connected to the first terminal of the eleventh transistor T11. The second terminal of the seventeenth transistor T17 is connected to the first capacitor C1 and the eighteenth transistor. The first terminal of transistor T18 and the control terminal of the seventeenth transistor T17 are connected to the second clock signal SCK2. The control terminal of the eighteenth transistor T18 is connected to the second terminal of the first capacitor C1. The second terminal of the eighteenth transistor T18 is connected to the second clock signal SCK2. The first terminal of the third capacitor C3 and the nineteenth transistor T19 are connected to the negative high voltage NVGH. The second terminal of the third capacitor C3 is connected to the control terminal of the nineteenth transistor T19. The second terminal of the nineteenth transistor T19 is connected to the first terminal of the twentieth transistor T20. The control terminal of the twentieth transistor T20 is connected to the second capacitor C2. The second terminal of the twentieth transistor T20 is connected to the negative low voltage NVGL. The first terminal of the twenty-first transistor T21 is connected to the second terminal of the twelfth transistor T12. The second terminal of the twenty-first transistor T21 is connected to the control terminal of the eighteenth transistor T18. The control terminal of the twenty-first transistor T21 is connected to the negative low voltage NVGL. The first terminal of the twenty-second transistor T22 is connected to the control terminal of the sixteenth transistor T16, and the second terminal of the twenty-second transistor T22 is connected to the first terminal of the second capacitor C2. The control terminal of the twenty-second transistor T22 is connected to the negative low voltage NVGL. The first terminal of the twenty-third transistor T23 is connected to the negative high voltage NVGH, and the control terminal of the twenty-third transistor T23 is connected to the reset signal RESET. The second terminal of the twenty-third transistor T23 is connected to the first terminal of the twenty-second transistor T22. The first terminal of the twentieth transistor T20 serves as the output terminal of the first gate drive circuit.

[0069] Specifically, the first gate driving circuit can be used to output high and low level signals. When the first gate driving circuit is switching from outputting a high level signal to a low level signal, it may not be able to jump directly from high level to low level. Instead, it may pause at a certain potential between high and low levels and then continue to decrease to low level.

[0070] For example, when the first clock signal SCK1 jumps from high to low, the eleventh transistor T11 turns on, and the start pulse signal SIN is written to the control terminal of the twentieth transistor T20 through the eleventh transistor T11 and the twenty-second transistor T22. For instance, if the start pulse signal SIN and the negative low voltage NVGL are both -7V, and the threshold voltage of each transistor is -2V, the voltage input to the control terminal of the twentieth transistor T20 is the start pulse signal SIN minus two threshold voltages, which is -3V. Because the voltage at the second terminal of the twentieth transistor T20 is -7V, and the voltage at the control terminal of the twentieth transistor T20 is greater than the voltage at the first terminal, the first terminal of the twentieth transistor T20 can output a voltage of -1V. Therefore, the voltage between the first terminal and the control terminal of the twentieth transistor T20 reaches the threshold voltage, and the twentieth transistor T20 no longer adjusts its opening degree. The twentieth transistor T20 maintains this conduction level and outputs a voltage of -1V.

[0071] When the second clock signal SCK2 transitions from high to low, the fifteenth transistor T15 turns on, pulling the voltage of the second capacitor C2 low. The second capacitor C2 can couple its own voltage to the control terminal of the twentieth transistor T20. For example, this voltage can be -19V. At this time, the voltage at the control terminal of the twentieth transistor T20 changes from -3V to -19V. Because the voltage at the control terminal of the twentieth transistor T20 is low, the twentieth transistor T20 is fully turned on, and the low negative voltage NVGL can be directly output through the first terminal of the twentieth transistor T20.

[0072] Therefore, during the transition from a high-level signal to a low-level signal, the first gate driving circuit briefly pauses at -1V before transitioning to -7V again. This transition time is short and constant, having minimal impact on the threshold compensation module. However, if the first gate driving circuit is exposed to light, especially if the transistors within it experience uneven illumination, the threshold voltages of each transistor will change. This alters the transition process between high and low levels, potentially changing the voltage value from -1V to other values ​​or altering the dwell time at that voltage. This, in turn, affects the driving signal output by the first gate driving circuit and consequently, the light emission of the display panel. Therefore, the first gate driving circuit should be kept away from light as much as possible.

[0073] Figure 4A schematic diagram of a second gate drive circuit is shown as an example. (Reference) Figure 4 Optionally, the second gate driving circuit has the same structure as the first gate driving circuit. The first terminals of the fourteenth transistor T14, the twenty-third transistor T23, the sixteenth transistor T16, and the nineteenth transistor T19 in the second gate driving circuit are connected to the positive high voltage PVGH. The second terminal of the eleventh transistor T11 is connected to the enable pulse signal EIN. The control terminals of the eleventh transistor T11 and the thirteenth transistor T13 are connected to the first enable clock signal ECK1. The control and second terminals of the fifteenth transistor T15, the seventeenth transistor T17, and the eighteenth transistor T18 are connected to the second enable clock signal ECK2. The second terminal of the thirteenth transistor T13, the control terminals of the twenty-first transistor T21 and the twenty-second transistor T22, and the second terminal of the twentieth transistor T20 are connected to the positive low voltage PVGL.

[0074] For example, when the first clock signal SCK1 jumps from high to low, the eleventh transistor T11 and the twenty-second transistor T22 are turned on, and the start pulse signal SIN is written to the control terminal of the twentieth transistor T20 through the eleventh transistor T11 and the twenty-second transistor T22. For instance, if both the start pulse signal SIN and the positive low voltage PVGL are -7V, the output voltage of the second gate drive circuit is the same as that of the first gate drive circuit, both outputting a voltage of -1V.

[0075] When the second clock signal SCK2 transitions from high to low, the fifteenth transistor T15 turns on, pulling the voltage of the second capacitor C2 low. The second capacitor C2 can couple its own voltage to the control terminal of the twentieth transistor T20. For example, this voltage can be -19V. At this time, the voltage at the control terminal of the twentieth transistor T20 changes from -3V to -19V. Because the voltage at the control terminal of the twentieth transistor T20 is low, the twentieth transistor T20 is fully turned on, and the low positive voltage PVGL can be directly output through the first terminal of the twentieth transistor T20.

[0076] Therefore, the drive signal output by the second gate drive circuit also experiences signal transitions. If the second gate drive circuit is exposed to light, especially if the transistors within it are exposed to uneven light, the threshold voltages of each transistor will change. This alters the transition process between high and low level signals in the second gate drive circuit. The voltage value of this intermediate transition may change from -1V to other values, or the dwell time at that voltage value may vary, thus affecting the drive signal output by the second gate drive circuit and consequently the light emission of the display panel. Therefore, the second gate drive circuit should also be protected from light as much as possible.

[0077] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. (In conjunction with...) Figure 5 and Figure 6 Based on the above embodiments, optionally, the pixel driving circuit 10 further includes a data writing module 105, which is used to write data voltage to the driving module 102. The plurality of gate driving circuits also include a third gate driving circuit 23, which is used to drive the data writing module 105. The third gate driving circuit 23 is located in the non-display area 2 on one side of the display area 1, and is located either at a position away from the display area 1 by the first gate driving circuit 21, or at a position away from the display area 1 by the second gate driving circuit 22.

[0078] in, Figure 5 An example is shown where the third gate driving circuit 23 is located away from the first gate driving circuit 21. The third gate driving circuit 23 may also be located away from the second gate driving circuit 22.

[0079] During data writing, the third gate driving circuit 23 drives the data writing module 105, enabling the data writing module 105 to transmit data voltage. This voltage then passes through the driving module 102 and the threshold compensation module 101 before being input to the control terminal of the driving module 102. Therefore, the conduction state of the threshold compensation module 101 is crucial during data writing, determining the accuracy and stability of the data voltage writing to the driving module 102.

[0080] For example, the data voltage may include image data information, which can be used to ensure that the display panel displays the correct image and displays it at a stable frame rate, avoiding problems such as flickering or image distortion.

[0081] In this embodiment of the invention, by placing the first gate driving circuit on the side closer to the display area, the first gate driving circuit can minimize the influence of light, enabling it to stably drive the threshold compensation module. This allows the threshold compensation module to write data to the control terminal of the data voltage transmitted by the module, which is then stably input to the drive module, thereby improving the display effect of the display panel.

[0082] Continue to combine Figure 5 and Figure 6Based on the above embodiments, optionally, the plurality of gate driving circuits further include a fourth gate driving circuit 24, which is used to drive the data writing module 105; the third gate driving circuit 23 has the same structure as the fourth gate driving circuit 24; the third gate driving circuit 23 and the fourth gate driving circuit 24 are respectively located in the non-display areas 2 on both sides of the display area 1.

[0083] The third gate driving circuit 23 and the fourth gate driving circuit 24 are located on both sides of the display area 1, and their positions can be interchanged.

[0084] When the gate driving circuit used to drive the data writing module 105 adopts a dual-side driving method, the gate driving circuit can simultaneously input driving signals from both sides of the display area 1 to the pixel driving circuit in the display area 1. This setting method can reduce the delay and attenuation of driving signal transmission, improve the refresh rate and response speed of the display panel. Especially for large-size display panels, dual-side driving can better ensure the uniformity and stability of the image, reduce edge distortion and other problems, and improve display quality.

[0085] Continue to refer to Figure 5 Based on the above embodiments, optionally, the fourth gate driving circuit is located in the non-display area on one side of the display area, and is located at a position away from the display area from the first gate driving circuit, or at a position away from the display area from the second gate driving circuit.

[0086] in, Figure 5 The example shows the fourth gate driving circuit 24 located away from the display area 1 from the second gate driving circuit 22. In other embodiments, the fourth gate driving circuit 24 may also be located away from the display area 1 from the first gate driving circuit 21.

[0087] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. (Combined with...) Figure 7 and Figure 8 Based on the above embodiments, optionally, the pixel driving circuit further includes a light-emitting control module 106, which controls the light-emitting element 104 to emit light. The plurality of gate driving circuits also include at least one fifth gate driving circuit 25, which drives the light-emitting control module. The fifth gate driving circuit 25 is located in the non-display areas 2 on one or both sides of the display area 1, and is located at a position away from the display area 1 from the first gate driving circuit 21, and / or at a position away from the display area 1 from the second gate driving circuit 22.

[0088] in, Figure 7An exemplary illustration shows the fifth gate driving circuit 25 located at a position away from the display area 1, corresponding to the third gate driving circuit 23. The fifth gate driving circuit 25 can also be interchanged with the third gate driving circuit 23, and can also be positioned at a position away from the display area 1, corresponding to the second gate driving circuit 22. Optionally, the fifth gate driving circuit 25 and the second gate driving circuit 22 can have the same circuit structure.

[0089] For example, at least two fifth gate driving circuits 25 may be provided and disposed in the non-display areas 2 on both sides of the display area 1, so that the fifth gate driving circuits 25 can control the light emission control module 106 by means of bilateral driving.

[0090] Specifically, the light-emitting control module 106 is turned on by the drive signal of the fifth gate drive circuit 25. The light-emitting control module 106 is used to turn on the power supply circuit of the light-emitting element 104, so that the light-emitting element 104 emits light. When the light-emitting element 104 emits light, the drive module 102 adjusts the opening degree according to the data voltage transmitted by the data writing module 105, thereby adjusting the input current of the light-emitting element 104, so that the light-emitting element 104 emits light of different brightness.

[0091] Continue to combine Figure 7 and Figure 8 Based on the above embodiments, optionally, the pixel driving circuit further includes a second initialization module 107, which is used to initialize the driving module 102. The plurality of gate driving circuits also include at least one sixth gate driving circuit 26, which is used to drive the second initialization module 107. The sixth gate driving circuit 26 is located in the non-display areas 2 on one or both sides of the display area 1, and is located at a position away from the display area 1 from the first gate driving circuit 21, and / or at a position away from the display area 1 from the second gate driving circuit 22.

[0092] in, Figure 7 An exemplary illustration shows the sixth gate driving circuit 26 located at a position away from the display area 1, corresponding to the fourth gate driving circuit 24. The sixth gate driving circuit 26 can also be interchanged with the fourth gate driving circuit 24, and can also be positioned at a position away from the display area 1, corresponding to the first gate driving circuit 21. Optionally, the sixth gate driving circuit 26 and the first gate driving circuit 21 can have the same circuit structure.

[0093] For example, at least two sixth gate driving circuits 26 may be provided and disposed in the non-display areas 2 on both sides of the display area 1, so that the sixth gate driving circuits 26 can control the second initialization module 107 by means of bilateral driving.

[0094] Specifically, after one light-emitting cycle, the light-emitting element 104 may accumulate some charge in the driving module 102. This accumulated charge can affect the subsequent operating state of the driving module 102, such as changing its threshold voltage and interfering with normal current control. By setting the sixth gate driving circuit 26, the second initialization module 107 can be used to reset the driving module 102, enabling the driving module 102 to clear these accumulated charges at the beginning of each display cycle, returning the driving module 102 to its initial state and ensuring that it can accurately respond to input signals. This ensures that each pixel driving circuit starts working under the same conditions in each display cycle, thereby improving the brightness uniformity of the displayed image and making the display effect clearer and more comfortable.

[0095] Based on the above embodiments, optionally, three sets of gate driving circuits are provided in the non-display areas on both sides of the display area.

[0096] By setting three sets of gate driving circuits in each non-display area on each side, and including one fifth and one sixth gate driving circuit, the gate driving circuits at different locations can precisely control each module in the pixel driving circuit. Through the coordinated operation of multiple sets of gate driving circuits on both sides, the on and off times of the light-emitting elements can be adjusted more accurately, reducing display differences caused by varying signal transmission distances. This results in more uniform brightness, contrast, and other parameters of the entire display screen, effectively avoiding problems such as uneven brightness and color deviation.

[0097] By setting three sets of gate drive circuits in the non-display areas on both sides of the display area, the wiring can be distributed to both sides, shortening the length of each wiring, reducing wiring complexity, reducing signal interference, and improving the quality of signal transmission.

[0098] Based on the above embodiments, optionally, the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the third and sixth gate driving circuits are sequentially positioned away from the display area from the first gate driving circuit; the fifth and fourth gate driving circuits are sequentially positioned away from the display area from the second gate driving circuit. Alternatively, the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area from the first gate driving circuit; the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area from the second gate driving circuit.Alternatively, the fourth and sixth gate driving circuits are sequentially positioned away from the display area from the first gate driving circuit; the third and fifth gate driving circuits are sequentially positioned away from the display area from the second gate driving circuit.

[0099] Table 1

[0100]

[0101]

[0102] Table 1 is a layout table of a gate driving circuit according to the present invention. Referring to Table 1, optionally, in the display panel provided by the embodiments of the present invention, the first gate driving circuit and the second gate driving circuit are positioned close to the display area, and the positions of other gate driving circuits can be adjusted adaptively according to the actual display panel. With this arrangement, the first gate driving circuit and the second gate driving circuit can be positioned at the furthest point from the edge of the light-shielding layer, allowing the light-shielding layer to better shield the first and second gate driving circuits, thereby maximizing the protection of the first and second gate driving circuits from the influence of light. This results in a more stable driving effect for the threshold compensation module by the first gate driving circuit and for the first initialization module by the second gate driving circuit. Furthermore, this allows the threshold compensation module to better write the threshold voltage of the compensation driving module, and the first initialization module to better initialize the light-emitting elements corresponding to the pixel driving circuit.

[0103] Continue to refer to Figure 7 Optionally, based on the above embodiments, the light-shielding layer 3 covers each gate driving circuit.

[0104] In this system, to reduce the impact of light on the gate driving circuits when exposed to illumination, a light-shielding layer 3 can be placed over each gate driving circuit. This ensures the stable operation of each gate driving circuit to the greatest extent possible. However, because the edge of the light-shielding layer needs to be at a certain distance from the edge of the non-display area, the gate driving circuits located at the edge of the light-shielding layer may not be as affected by illumination. By placing the first gate driving circuit 21 and the second gate driving circuit 22 on both sides of the display area 1 and close to it, the two gate driving circuits that have the greatest impact on the light emission of the light-emitting element can be minimized from being exposed to light. This allows the first gate driving circuit 21 and the second gate driving circuit 22 to operate continuously and stably, thereby improving the display effect of the display panel.

[0105] Based on the above embodiments, optionally, the distance between the edge of the light-shielding layer and the edge of the display area is greater than a first preset distance.

[0106] The first preset distance is the minimum distance between the edge of the light-shielding layer and the edge of the display area. For example, the first preset distance can be 300 micrometers, or 0.3 millimeters. Therefore, this embodiment of the invention is applicable to display panels with narrow bezels. When the distance between the edge of the light-shielding layer and the edge of the display area is greater than the first preset distance, the invention ensures a good display effect for the display panel.

[0107] Figure 9 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. (Reference) Figure 9 Based on the above embodiments, optionally, the pixel driving circuit further includes a storage module 108 and a third initialization module 109. The first terminal of the light-emitting control module 106 is connected to the first power supply ELVDD, the second terminal of the light-emitting control module 106 is connected to the first terminal of the driving module 102, the second terminal of the driving module 102 is connected to the third terminal of the light-emitting control module 106, and the fourth terminal of the light-emitting control module 106 is connected to the first electrode of the light-emitting element 104. The first terminal of the storage module 108 is connected to the first power supply ELVDD, and the second terminal of the storage module 108 is connected to the control terminal of the driving module 102. The data writing module 105 is connected to the second terminal of the light-emitting control module 106. The first terminal of the threshold compensation module 101 is connected to the second terminal of the storage module 108, and the second terminal of the threshold compensation module 101 is connected to the third terminal of the light-emitting control module 106. The second initialization module 107 is connected to the second terminal of the threshold compensation module 101. The first initialization module 103 is connected to the first electrode of the light-emitting element 104, the light-emitting element 10 is also connected to the second power supply ELVSS, and the third initialization module 109 is connected to the second end of the driving module 102.

[0108] The threshold compensation module 101 includes a first transistor T1, the control terminal of which is connected to a first gate driving circuit. The driving module 102 includes a second transistor T2. The data writing module 105 includes a fifth transistor T5, the control terminal of which is connected to a third or fourth gate driving circuit. The storage module 108 includes a storage capacitor Cst. When the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, the data voltage Vdata can be input to the control terminal of the second transistor T2 through the fifth transistor T5, the second transistor T2, and the first transistor T1. The data voltage Vdata is then stored by the storage capacitor Cst.

[0109] The first initialization module 103 includes a third transistor T3, and the third initialization module 109 includes an eighth transistor T8 and a ninth transistor T9. The control terminals of the third transistor T3, the eighth transistor T8, and the ninth transistor T9 are connected to the second gate drive circuit. When the third transistor T3 is turned on, the second reset signal Vref2 is input to the anode of the light-emitting element 104 through the third transistor T3. When the eighth transistor T8 and the ninth transistor T9 are turned on, the third reset signal Vref3 is input to the second terminal of the second transistor T2 through the eighth transistor T8 and the ninth transistor T9.

[0110] The light-emitting control module 106 includes a fourth transistor T4 and a sixth transistor T6, the control terminals of which are connected to a fifth gate drive circuit. When the fourth transistor T4, the second transistor T2, and the sixth transistor T6 are turned on, the light-emitting element 104 emits light.

[0111] The second initialization module 107 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is connected to the sixth gate drive circuit. When the first transistor T1 and the seventh transistor T7 are turned on, the first reset signal Vref1 is input to the control terminal of the second transistor T2 through the first transistor T1 and the seventh transistor T7.

[0112] This invention also provides a display device. Figure 10 This is a schematic diagram of a display device provided in an embodiment of the present invention. (Reference) Figure 10 The display device includes a display panel 100 provided in any embodiment of the present invention, which has similar beneficial effects to the display panel and will not be described in detail here.

[0113] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0114] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area at least partially surrounding the display area; the display panel includes: An array substrate includes a pixel driving circuit located in the display area and a plurality of gate driving circuits located in the non-display area; the pixel driving circuit includes a threshold compensation module, a driving module and a first initialization module, the threshold compensation module is used to write a threshold voltage to compensate the driving module, and the first initialization module is used to initialize the light-emitting element corresponding to the pixel driving circuit; The plurality of gate driving circuits include a first gate driving circuit and a second gate driving circuit. The first gate driving circuit is used to drive the threshold compensation module, and the second gate driving circuit is used to drive the first initialization module. The first gate driving circuit and the second gate driving circuit are respectively located in the non-display areas on both sides of the display area, and both are located in the non-display areas close to the display area. A light-shielding layer is located on one side of the array substrate and is located in the display area and part of the non-display area.

2. The display panel according to claim 1, characterized in that, The pixel driving circuit further includes a data writing module, which is used to write data voltage into the driving module. The plurality of gate driving circuits further includes a third gate driving circuit, which is used to drive the data writing module. The third gate driving circuit is located in the non-display area on one side of the display area, and is located at a position away from the display area from the first gate driving circuit, or at a position away from the display area from the second gate driving circuit.

3. The display panel according to claim 2, characterized in that, The plurality of gate driving circuits further includes a fourth gate driving circuit, which is used to drive the data writing module; the third gate driving circuit has the same structure as the fourth gate driving circuit. The third gate driving circuit and the fourth gate driving circuit are respectively located in the non-display areas on both sides of the display area; Preferably, the fourth gate driving circuit is located in the non-display area on one side of the display area, and is located at a position away from the display area from the first gate driving circuit, or at a position away from the display area from the second gate driving circuit.

4. The display panel according to claim 3, characterized in that, The pixel driving circuit also includes a light emission control module, which is used to control the light emission element to emit light. The plurality of gate driving circuits further includes at least one fifth gate driving circuit, the fifth gate driving circuit being used to drive the light emission control module; The fifth gate driving circuit is located in the non-display area on one or both sides of the display area, and is located at a position away from the display area from the first gate driving circuit, and / or at a position away from the display area from the second gate driving circuit.

5. The display panel according to claim 4, characterized in that, The pixel driving circuit further includes a second initialization module, which is used to initialize the driving module. The plurality of gate driving circuits further includes at least one sixth gate driving circuit, the sixth gate driving circuit being used to drive the second initialization module; The sixth gate driving circuit is located in the non-display area on one or both sides of the display area, and is located at a position away from the display area from the first gate driving circuit, and / or at a position away from the display area from the second gate driving circuit; Preferably, three sets of gate driving circuits are provided in each of the non-display areas on both sides of the display area.

6. The display panel according to claim 5, characterized in that, The third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fourth gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fifth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the sixth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the fourth gate driving circuit and the sixth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the third gate driving circuit and the fifth gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit. Alternatively, the sixth gate driving circuit and the fourth gate driving circuit are sequentially disposed at a position away from the display area of ​​the first gate driving circuit; the fifth gate driving circuit and the third gate driving circuit are sequentially disposed at a position away from the display area of ​​the second gate driving circuit.

7. The display panel according to claim 1, characterized in that, The light-shielding layer covers each of the gate drive circuits.

8. The display panel according to claim 1, characterized in that, The distance between the edge of the light-shielding layer and the edge of the display area is greater than a first preset distance.

9. The display panel according to claim 6, characterized in that, The pixel driving circuit also includes a storage module and a third initialization module; The first end of the light-emitting control module is connected to the first power supply, the second end of the light-emitting control module is connected to the first end of the driving module, the second end of the driving module is connected to the third end of the light-emitting control module, and the fourth end of the light-emitting control module is connected to the first electrode of the light-emitting element. The first end of the storage module is connected to the first power supply, and the second end of the storage module is connected to the control end of the drive module; The data writing module is connected to the second end of the light emission control module; The first end of the threshold compensation module is connected to the second end of the storage module, and the second end of the threshold compensation module is connected to the third end of the light emission control module. The second initialization module is connected to the second end of the threshold compensation module; The first initialization module is connected to the first electrode of the light-emitting element; the third initialization module is connected to the second end of the driving module.

10. A display device, characterized in that, include: The display panel according to any one of claims 1-9.

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