Display panel and pixel driving circuit

Abstract

The present disclosure provides a display panel and a pixel driving circuit, and belongs to the technical field of display driving. The display panel comprises a gate driver, a pixel driving unit connected with the gate driver, a first light emitting element and a second light emitting element connected with the pixel driving unit. The pixel driving unit comprises a first light emitting control circuit, a second light emitting control circuit, an anode reset circuit and an isolation circuit. One end of the isolation circuit is connected with a driving current, and the other end is connected with the anode reset circuit, the first light emitting control circuit and the second light emitting control circuit at a first node. The first light emitting control circuit is connected between the first node and the first light emitting element. The second light emitting control circuit is connected between the first node and the second light emitting element. In this way, by multiplexing the first light emitting control circuit and the second light emitting control circuit in the reset stage, the first light emitting element and the second light emitting element share one anode reset circuit, and there is no need to set anode reset circuits respectively.

Description

Technical Field

[0001] This disclosure relates to the field of display driving technology, and in particular to a display panel and pixel driving circuit. Background Technology

[0002] With the popularization of mobile smart terminals, users' demand for privacy protection of display panels is increasing. Privacy protection for display panels can be achieved by controlling the light emission state of different light-emitting elements in the display area to switch the display mode. That is, the pixel driving unit is used to drive the privacy light-emitting element and the non-privacy light-emitting element respectively.

[0003] Currently, the method of implementing privacy mode through pixel driving unit requires setting up anode reset circuits for each of the two types of light-emitting elements, namely privacy light-emitting elements and non-privacy light-emitting elements, during the reset phase of each frame image display.

[0004] Therefore, simplifying the circuit structure of the pixel driving unit that supports privacy protection is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a display panel to at least partially solve the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of the present disclosure, a display panel is provided, including a gate driver, a pixel driving unit connected to the gate driver, a first light-emitting element and a second light-emitting element connected to the pixel driving unit; The pixel driving unit includes a first light-emitting control circuit, a second light-emitting control circuit, an anode reset circuit, and an isolation circuit. One end of the isolation circuit is used to connect to the driving current provided by the first voltage source, and the other end is connected to the anode reset circuit, the first light-emitting control circuit and the second light-emitting control circuit at the first node respectively. The first light-emitting control circuit is connected between the first node and the first light-emitting element; the second light-emitting control circuit is connected between the first node and the second light-emitting element.

[0007] Optionally, the display cycle of the pixel driving unit includes an anode reset phase; During the anode reset phase, the isolation circuit is used to control the disconnection between the first voltage source and the first node, the anode reset circuit is used to transmit the anode reset voltage to the first node, and the first light-emitting control circuit and the second light-emitting control circuit are used to selectively transmit the anode reset voltage of the first node to at least one of the first light-emitting element and the second light-emitting element to perform anode reset on at least one of the first light-emitting element and the second light-emitting element.

[0008] Optionally, the gate driver includes a first driving unit and a second driving unit; The first light-emitting control circuit includes a first transistor; the second light-emitting control circuit includes a second transistor. The first transistor includes a first electrode connected to the first node, a second electrode connected to the anode of the first light-emitting element, and a control electrode connected to the first driving unit to receive the first light-emitting control signal; The second transistor includes a first electrode connected to the first node, a second electrode connected to the anode of the second light-emitting element, and a control electrode connected to the second driving unit to receive a second light-emitting control signal.

[0009] Optionally, the gate driver includes a third driving unit; the pixel driving unit further includes a driving transistor connected between the first voltage source and the isolation circuit; The anode reset circuit includes a third transistor; the isolation circuit includes a fourth transistor; The third transistor includes a first electrode connected to the anode reset voltage, a second electrode connected to the first node, and a control electrode connected to the third driving unit to receive a driving signal; The fourth transistor includes a first electrode connected to the second node of the driving transistor, a second electrode connected to the first node, and a control electrode connected to the third driving unit to receive a driving signal; The third transistor and the fourth transistor are of different types.

[0010] Optionally, when the pixel driving unit operates in the first light emission mode, during the anode reset phase, the third driving unit outputs the driving signal to drive the third transistor to turn on and the fourth transistor to turn off, the first driving unit outputs the first light emission control signal to drive the first transistor to turn on, and the second driving unit outputs the second light emission control signal to drive the second transistor to turn off, so as to reset the anode of the first light emission element; When the pixel driving unit operates in the second light emission mode, during the anode reset phase, the third driving unit outputs the driving signal to drive the third transistor to turn on and the fourth transistor to turn off, the first driving unit outputs the first light emission control signal to drive the first transistor to turn off, and the second driving unit outputs the second light emission control signal to drive the second transistor to turn on, so as to reset the anode of the second light emission element. When the pixel driving unit operates in the third light emission mode, during the anode reset phase, the third driving unit outputs the driving signal to drive the third transistor to turn on and the fourth transistor to turn off, the first driving unit outputs the first light emission control signal to drive the first transistor to turn on, and the second driving unit outputs the second light emission control signal to drive the second transistor to turn on, so as to simultaneously reset the anode of the first light emission element and the anode of the second light emission element.

[0011] Optionally, the pixel driving unit further includes a third light-emitting control circuit and a fourth light-emitting control circuit disposed between the first voltage source and the driving transistor; The third light-emitting control circuit includes a fifth transistor, which includes a first electrode connected to the first voltage source, a second electrode connected to the driving transistor at a third node, and a control electrode connected to the first driving unit to receive the first light-emitting control signal. The fourth light-emitting control circuit includes a sixth transistor, which includes a first electrode connected to the first voltage source, a second electrode connected to the third node, and a control electrode connected to the second driving unit to receive the second light-emitting control signal.

[0012] Optionally, the display cycle of the pixel driving unit further includes a light-emitting phase; When the pixel driving unit operates in the first light-emitting mode, the first driving unit outputs a first light-emitting control signal to drive the first transistor and the fifth transistor to turn on, the second driving unit outputs a second light-emitting control signal to drive the second transistor and the sixth transistor to turn off, and the driving transistor turns on according to the written data voltage, so that the first light-emitting element emits light; When the pixel driving unit operates in the second light-emitting mode, the first driving unit outputs a first light-emitting control signal to drive the first transistor and the fifth transistor to disconnect, the second driving unit outputs a second light-emitting control signal to drive the second transistor and the sixth transistor to turn on, and the driving transistor turns on according to the written data voltage, so that the second light-emitting element emits light; When the pixel driving unit operates in the third light emission mode, the first driving unit outputs a first light emission control signal to drive the first transistor and the fifth transistor to turn on, the second driving unit outputs a second light emission control signal to drive the second transistor and the sixth transistor to turn on, and the driving transistor turns on according to the written data voltage, so that the first light emission element and the second light emission element emit light respectively.

[0013] Optionally, the pixel driving unit further includes a data reset circuit connected to the third node; The data reset circuit includes a seventh transistor, which includes a first electrode that receives the data reset voltage, a second electrode that is connected to the third node, and a control electrode that is connected to the third driving unit to receive the driving signal. During the anode reset phase, the third driving unit outputs the driving signal to turn on the seventh transistor, thereby outputting the data reset voltage to the third node to reset the third node.

[0014] Optionally, it further includes a data writing sub-circuit for writing a data voltage to the control electrode of the driving transistor; the data writing sub-circuit includes a writing circuit, a reset circuit, and a connection circuit; the gate driver further includes a fourth driving unit, a fifth driving unit, and a sixth driving unit; The write circuit includes an eighth transistor, which includes a first electrode that receives a data voltage, a second electrode that is connected to the third node, and a control electrode that is connected to the fourth driving unit to receive a write control signal. The reset circuit includes a ninth transistor, which includes a first electrode that is connected to the reset voltage, a second electrode that is connected to the control electrode of the driving transistor at a fourth node, and a control electrode that is connected to the fifth driving unit to receive the reset driving signal. The connection circuit includes a tenth transistor, which includes a first electrode connected to the second node, a second electrode connected to the fourth node, and a control electrode connected to the sixth driving unit to access a communication control signal.

[0015] According to a second aspect of this disclosure, a pixel driving circuit is provided, including a first light-emitting control circuit, a second light-emitting control circuit, an isolation circuit, and an anode reset circuit. One end of the isolation circuit is used to connect to the driving current provided by the first voltage source, and the other end is connected to the anode reset circuit, the first light-emitting control circuit and the second light-emitting control circuit at the first node respectively. The first light-emitting control circuit is connected between the first node and the first light-emitting element; the second light-emitting control circuit is connected between the first node and the second light-emitting element.

[0016] In summary, in this disclosure, firstly, the first node can be reset by the anode reset circuit, pulling it low to a low level. Simultaneously, the first light-emitting control circuit can control the conduction between the first node and the first light-emitting element, releasing the residual charge on the anode of the first light-emitting element to the first node, thus resetting the first light-emitting element. Secondly, the second light-emitting control circuit can control the conduction between the first node and the second light-emitting element, releasing the residual charge on the anode of the second light-emitting element to the first node, thus resetting the second light-emitting element. This allows for individual resets of the first and second light-emitting elements, as well as simultaneous resets of the first and second light-emitting elements. During this process, the isolation circuit isolates the driving current, preventing it from being transmitted to the first node and avoiding accidental emission of the first and second light-emitting elements during the reset process. Thus, by reusing the first and second light-emitting control circuits during the reset phase, the first and second light-emitting elements share a single anode reset circuit, eliminating the need for separate anode reset circuits and reducing the components required for the pixel driving unit reset process.

[0017] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this disclosure. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0019] To gain a more complete understanding of this disclosure and its beneficial effects, the following description will be made in conjunction with the accompanying drawings, wherein the same reference numerals denote the same parts in the following description.

[0020] Figure 1 This is a circuit connection diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the current flow direction in the first anode reset stage provided in the exemplary embodiments of this disclosure; Figure 3 This is a timing diagram of a first pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 4This is a schematic diagram of the current flow direction in the second anode reset stage provided in the exemplary embodiments of this disclosure; Figure 5 This is a timing diagram of a second pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the current flow direction in the third anode reset stage provided in the exemplary embodiments of this disclosure; Figure 7 This is a timing diagram of a third pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 8 This is a schematic diagram of the current flow direction for node reset provided in an exemplary embodiment of this disclosure; Figure 9 This is a schematic diagram of the current flow direction in the first light-emitting stage provided in an exemplary embodiment of this disclosure; Figure 10 This is a schematic diagram of the current flow direction in the second light-emitting stage provided in an exemplary embodiment of this disclosure; Figure 11 This is a schematic diagram of the current flow direction in the third light-emitting stage provided in an exemplary embodiment of this disclosure; Figure 12 This is a schematic diagram of a display device provided in an exemplary embodiment of this disclosure.

[0021] Explanation of reference numerals in the attached diagram: Tr, driving transistor; 1, first light-emitting control circuit; 2, second light-emitting control circuit; 3, anode reset circuit; 4, isolation circuit; 5, third light-emitting control circuit; 6, fourth light-emitting control circuit; 7, data reset circuit; 8, write circuit; 9, reset circuit; 10, connection circuit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; D1, first light-emitting element; D2, second light-emitting element; A, first node; B, second node; C, third node; Q, fourth node; EM1, first light-emitting control signal; EM2, second light-emitting control signal; Pscan, driving signal; Pscan2, write control signal; Nscan1, connection control signal; Nscan2, reset driving signal. Detailed Implementation

[0022] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0023] First, the background of this disclosure will be further explained. During the operation of a display panel, if the residual charge at the anode node of the light-emitting element cannot be fully released, it will directly cause adverse phenomena such as brightness shift, grayscale abnormalities, image ghosting, and inter-pixel crosstalk in the next frame. In an architecture with both privacy protection and normal display modes, the pixel unit contains two independent light-emitting paths, corresponding to two types of light-emitting elements. Currently, it is necessary to configure independent anode reset circuits for the two types of light-emitting elements to meet the reset requirements of different modes. In addition to significantly increasing the redundancy of the circuit structure and manufacturing costs, the additional reset transistor will introduce more leakage current paths, accelerate the potential decay of the anode node, and cause the display brightness to decrease significantly with the increase of the light emission time. Furthermore, setting a separate reset transistor for each light-emitting element also requires the addition of a corresponding gate driving circuit, which is not conducive to the realization of narrow bezels. Based on this, the embodiments of this disclosure are proposed.

[0024] According to a first aspect of this disclosure, a display panel is provided, including a gate driver, a pixel driving unit connected to the gate driver, and a first light-emitting element D1 and a second light-emitting element D2 connected to the pixel driving unit. The pixel driving unit includes a first light-emitting control circuit 1, a second light-emitting control circuit 2, an anode reset circuit 3, and an isolation circuit 4. One end of the isolation circuit 4 is connected to a driving current provided by a first voltage source, and the other end is connected to the anode reset circuit 3, the first light-emitting control circuit 1, and the second light-emitting control circuit 2 at a first node A. The first light-emitting control circuit 1 is connected between the first node A and the first light-emitting element D1. The second light-emitting control circuit 2 is connected between the first node A and the second light-emitting element D2.

[0025] The first light-emitting element D1 and the second light-emitting element D2 have different light-emitting angles. The light-emitting angle of the first light-emitting element D1 can be greater or smaller than that of the second light-emitting element D2, depending on the actual situation, and no specific limitation is made here. Taking the light-emitting angle of the first light-emitting element D1 being smaller than that of the second light-emitting element D2 as an example, the light-emitting angle of the first light-emitting element D1 corresponds to the main viewing angle light path within a small angle range directly in front of the display area; the light-emitting angle of the second light-emitting element D2 corresponds to the privacy viewing angle light path within a large angle range on the left and right sides of the display area, and its light diverges to both sides at large angles. By controlling the on / off state of the first light-emitting element D1 and the second light-emitting element D2, the privacy function and non-privacy mode can be switched.

[0026] In the above embodiments, firstly, the anode reset circuit 3 can reset the first node A, pulling it down to a low level. Simultaneously, the first light-emitting control circuit 1 can control the conduction between the first node A and the first light-emitting element D1, releasing the residual charge on the anode of the first light-emitting element D1 to the first node A, thus resetting the first light-emitting element D1. Alternatively, the second light-emitting control circuit 2 can control the conduction between the first node A and the second light-emitting element D2, releasing the residual charge on the anode of the second light-emitting element D2 to the first node A, thus resetting the second light-emitting element D2. This allows for individual resets of the first light-emitting element D1 and the second light-emitting element D2, as well as simultaneous resets of the first and second light-emitting elements D1 and D2. During this process, the isolation circuit 4 isolates the driving current, preventing it from being transmitted to the first node A and avoiding accidental light emission from the first and second light-emitting elements D1 and D2 during the reset process. Thus, by reusing the first light-emitting control circuit 1 and the second light-emitting control circuit 2 during the reset phase, the first light-emitting element D1 and the second light-emitting element D2 can share a single anode reset circuit 3, eliminating the need to set up separate anode reset circuits 3 and reducing the components required during the pixel driving unit reset process.

[0027] In some embodiments, the display cycle of the pixel driving unit includes an anode reset phase. (Refer to...) Figure 3 The display cycle of the pixel driving unit may include an initial phase t1, a reset phase t2, a data writing phase t3, an anode reset phase t4, and an emission phase t5.

[0028] In the anode reset stage, the isolation circuit 4 is used to control the disconnection between the first voltage source and the first node A, the anode reset circuit 3 is used to transmit the anode reset voltage to the first node A, and the first light-emitting control circuit 1 and the second light-emitting control circuit 2 are used to selectively transmit the anode reset voltage of the first node A to at least one of the first light-emitting element D1 and the second light-emitting element D2, so as to perform anode reset on at least one of the first light-emitting element D1 and the second light-emitting element D2.

[0029] As an example, parasitic capacitance exists between the anode and cathode of the first light-emitting element D1 and the second light-emitting element D2. After the previous frame of image is displayed, a charge corresponding to the brightness of the previous frame remains on the parasitic capacitance, causing the initial anode potential to deviate from the preset value when the next frame is displayed, resulting in brightness deviation and inter-frame ghosting. Therefore, an anode reset stage for anode reset needs to be set in each frame display cycle to eliminate the influence of residual charge.

[0030] In the anode reset phase, isolation circuit 4 first disconnects the connection between the first voltage source and the first node A, completely isolating the first node A from the driving current path and preventing the high potential of the first voltage source from interfering with the anode reset process. Subsequently, anode reset circuit 3 is turned on, transmitting a low-level anode reset voltage to the first node A, pulling the potential of the first node A to the anode reset voltage. At this time, by controlling the switching states of the first light-emitting control circuit 1 and the second light-emitting control circuit 2, the anode reset voltage of the first node A can be selectively transmitted to the anode of the first light-emitting element D1 and / or the second light-emitting element D2, enabling independent or simultaneous reset of the first light-emitting element D1 and the second light-emitting element D2. Thus, by using only one anode reset third transistor T3 combined with two light-emitting control first transistors T1 and T2, multiple reset modes for the first light-emitting element D1 and the second light-emitting element D2 can be achieved. Compared to separately setting reset transistors at the anodes of the first light-emitting element D1 and the second light-emitting element D2, this reduces the number of transistors and driving unit groups, contributing to a narrow bezel on the display panel.

[0031] In some embodiments, the gate driver includes a first driving unit and a second driving unit. A first light-emitting control circuit 1 includes a first transistor T1. A second light-emitting control circuit 2 includes a second transistor T2. The first transistor T1 includes a first electrode connected to a first node A, a second electrode connected to the anode of the first light-emitting element D1, and a control electrode connected to the first driving unit to receive a first light-emitting control signal EM1. The second transistor T2 includes a first electrode connected to the first node A, a second electrode connected to the anode of the second light-emitting element D2, and a control electrode connected to the second driving unit to receive a second light-emitting control signal EM2.

[0032] The first driving unit and the second driving unit are two independent signal output channels in the gate driver, used to output the first light-emitting control signal EM1 and the second light-emitting control signal EM2, respectively. The first light-emitting control signal EM1 is used to control the switching state of the first transistor T1, thereby controlling the on / off state between the first light-emitting element D1 and the first node A; the second light-emitting control signal EM2 is used to control the switching state of the second transistor T2, thereby controlling the on / off state between the second light-emitting element D2 and the first node A. The signals output by the first driving unit and the second driving unit are independent of each other, thus enabling independent control of the two first light-emitting elements D1 and the second light-emitting element D2.

[0033] As an example, the first transistor T1 and the second transistor T2 can both be P-type transistors. When the first driving unit outputs a low-level first light-emitting control signal EM1, the first transistor T1 is turned on; when the second driving unit outputs a low-level second light-emitting control signal EM2, the second transistor T2 is turned on.

[0034] In the above embodiments, firstly, by using independent first and second driving units to control the first transistor T1 and the second transistor T2 respectively, independent on / off control of the first light-emitting element D1 and the second light-emitting element D2 can be achieved to meet the different light-emitting requirements of the first light-emitting element D1 and the second light-emitting element D2 in different operating modes. Secondly, the first transistor T1 and the second transistor T2 also serve as switches for anode reset, achieving multiplexing and eliminating the need for additional reset transistors, which helps to reduce the number of transistors in the pixel driving unit.

[0035] In some embodiments, the gate driver includes a third driving unit. The pixel driving unit further includes a driving transistor Tr connected between the first voltage source and the isolation circuit 4. The anode reset circuit 3 includes a third transistor T3. The isolation circuit 4 includes a fourth transistor T4. The third transistor T3 includes a first electrode connected to the anode reset voltage, a second electrode connected to the first node A, and a control electrode connected to the third driving unit to receive the driving signal Pscan. The fourth transistor T4 includes a first electrode connected to the driving transistor Tr at the second node B, a second electrode connected to the first node A, and a control electrode connected to the third driving unit to receive the driving signal Pscan. The third transistor T3 and the fourth transistor T4 are of different types.

[0036] As an example, the driving transistor Tr is used to adjust the current output from the first voltage source to the driving current according to the voltage value stored in its control electrode, so as to control the brightness of the first light-emitting element D1 and the second light-emitting element D2. The driving transistor Tr can be a P-type transistor. The first electrode of the driving transistor Tr is used to receive the driving current from the first voltage source; the second electrode is connected to the second node B and is used to transmit the driving current to the isolation circuit 4.

[0037] As an example, the third transistor T3 can be any N-type transistor, such as an IGZO TFT (Indium Gallium Zinc Oxide Thin-Film Transistor). The fourth transistor T4 can be any type of P-type transistor, such as an LTPS TFT (Low Temperature Poly-Silicon Thin-Film Transistor). Alternatively, the third transistor T3 can be a P-type transistor and the fourth transistor T4 can be an N-type transistor; no specific limitation is made here. By using different types of transistors for the third transistor T3 and the fourth transistor T4, complementary conduction of the two transistors can be achieved. Taking the third transistor T3 as an N-type transistor and the fourth transistor T4 as a P-type transistor as an example, when the drive signal Pscan is high, the third transistor T3 is turned on, while the gate-source voltage of the fourth transistor T4 is less than its threshold voltage, so the fourth transistor T4 is turned off. When the drive signal Pscan is low, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. By complementary conduction of the third transistor T3 and the fourth transistor T4, the third transistor T3 is turned on and the fourth transistor T4 is turned off when the first light-emitting element D1 and the second light-emitting element D2 are reset. When the first light-emitting element D1 and the second light-emitting element D2 are driven to emit light, the third transistor T3 is turned off and the fourth transistor T4 is turned on, so that the emission and reset of the first light-emitting element D1 and the second light-emitting element D2 will not interfere with each other.

[0038] As an example, the third drive unit is used to output the drive signal Pscan, which simultaneously controls the switching states of the third transistor T3 and the fourth transistor T4. By connecting the control electrodes of both the third transistor T3 and the fourth transistor T4 to the third drive unit, synchronous complementary switching control of the third transistor T3 and the fourth transistor T4 can be achieved without adding additional control signals, thus reducing the number of drive units required in the gate driver.

[0039] Reference Figure 2 In some embodiments, when the pixel driving unit operates in the first light emission mode, during the anode reset phase, the third driving unit outputs a driving signal Pscan to drive the third transistor T3 to turn on and the fourth transistor T4 to turn off, the first driving unit outputs a first light emission control signal EM1 to drive the first transistor T1 to turn on, and the second driving unit outputs a second light emission control signal EM2 to drive the second transistor T2 to turn off, so as to reset the anode of the first light emission element D1.

[0040] As an example, when the first light-emitting element D1 is a privacy-protecting light-emitting element, the first light-emitting mode is a privacy-protecting display mode. In the first light-emitting mode, only the first light-emitting element D1 emits light for display, while the second light-emitting element D2 is off. Combined with... Figure 3 During the anode reset phase, the third driving unit outputs a high-level driving signal Pscan, turning on the third transistor T3 and turning off the fourth transistor T4. After the third transistor T3 turns on, the anode reset voltage is transmitted to the first node A through the third transistor T3, pulling the potential of the first node A to the anode reset voltage Vi_Ano. At this time, the first driving unit outputs a low-level first light-emitting control signal EM1, turning on the first transistor T1. The anode reset voltage of the first node A is transmitted to the anode of the first light-emitting element D1 through the first transistor T1, releasing the residual charge on the parasitic capacitance of the anode of the first light-emitting element D1 to the anode reset voltage, completing the anode reset of the first light-emitting element D1. The second driving unit outputs a high-level second light-emitting control signal EM2, turning off the second transistor T2, thus not resetting the second light-emitting element D2.

[0041] Reference Figure 4 When the pixel driving unit operates in the second light emission mode, during the anode reset phase, the third driving unit outputs a driving signal Pscan to drive the third transistor T3 to turn on and the fourth transistor T4 to turn off. The first driving unit outputs a first light emission control signal EM1 to drive the first transistor T1 to turn off, and the second driving unit outputs a second light emission control signal EM2 to drive the second transistor T2 to turn on, so as to reset the anode of the second light emission element D2.

[0042] As an example, continuing with the first light-emitting element D1 as the privacy-protecting light-emitting element, the second light-emitting mode is the normal light-emitting mode, where the light emission of the display area can be observed from both front and side viewing angles. In the second light-emitting mode, only the second light-emitting element D2 emits light, while the first light-emitting element D1 is off. Combined with... Figure 5 During the anode reset phase, the third driving unit outputs a high-level driving signal Pscan, turning on the third transistor T3 and turning off the fourth transistor T4. At this time, the second driving unit outputs a low-level second light-emitting control signal EM2, turning on the second transistor T2. The anode reset voltage of the first node A is transmitted to the anode of the second light-emitting element D2 through the second transistor T2, completing the anode reset of the second light-emitting element D2. The first driving unit outputs a high-level first light-emitting control signal EM1, turning off the first transistor T1.

[0043] Reference Figure 6When the pixel driving unit operates in the third light emission mode, during the anode reset phase, the third driving unit outputs a driving signal Pscan to drive the third transistor T3 to turn on and the fourth transistor T4 to turn off. The first driving unit outputs a first light emission control signal EM1 to drive the first transistor T1 to turn on, and the second driving unit outputs a second light emission control signal EM2 to drive the second transistor T2 to turn on, so as to simultaneously reset the anode of the first light emission element D1 and the anode of the second light emission element D2.

[0044] As an example, the third emission mode can be a shared display mode with a full viewing angle. In the third emission mode, the first emission element D1 and the second emission element D2 emit light simultaneously, and the image displayed in the display area emits light uniformly across the entire viewing angle. Figure 7 During the anode reset phase, the third driving unit outputs a high-level driving signal Pscan, turning on the third transistor T3 and turning off the fourth transistor T4. At this time, the first driving unit and the second driving unit simultaneously output low-level first light-emitting control signal EM1 and second light-emitting control signal EM2, turning on the first transistor T1 and the second transistor T2 simultaneously. The anode reset voltage of the first node A is transmitted to the anodes of the first light-emitting element D1 and the second light-emitting element D2 through the first transistor T1 and the second transistor T2, respectively, completing the simultaneous anode reset of the first light-emitting element D1 and the second light-emitting element D2.

[0045] In the above embodiments, by selectively resetting the anode, only the light-emitting elements that need to participate in the display can be reset according to the requirements of different display modes. Light-emitting elements that do not participate in the display do not need to be reset, which can reduce unnecessary charge charging and discharging processes. Furthermore, the light-emitting elements that do not participate in the display can be controlled to always be in the off state, and the anode potential remains stable, which can reduce the aging rate of the light-emitting elements.

[0046] Reference Figure 1 In some embodiments, the pixel driving unit further includes a third light-emitting control circuit 5 and a fourth light-emitting control circuit 6 disposed between the first voltage source and the driving transistor Tr. The third light-emitting control circuit 5 includes a fifth transistor T5, which includes a first electrode connected to the first voltage source, a second electrode connected to the driving transistor Tr at a third node C, and a control electrode connected to the first driving unit to receive a first light-emitting control signal EM1. The fourth light-emitting control circuit 6 includes a sixth transistor T6, which includes a first electrode connected to the first voltage source, a second electrode connected to the third node C, and a control electrode connected to the second driving unit to receive a second light-emitting control signal EM2. The third light-emitting control circuit 5 and the fourth light-emitting control circuit 6 are used to control the current flow between the first voltage source and the driving transistor Tr.

[0047] As an example, the fifth transistor T5 and the first transistor T1 can be of the same type, allowing them to be synchronously controlled by the same first light-emitting control signal EM1 output from the same first driving unit. Similarly, the sixth transistor T6 and the second transistor T2 can be of the same type, and are synchronously controlled by the same second light-emitting control signal EM2 output from the same second driving unit, enabling synchronous switching on and off of the power supply side switch and the light-emitting side switch.

[0048] As an example, when the first driving unit outputs a low-level first light-emitting control signal EM1, the fifth transistor T5 and the first transistor T1 are synchronously turned on. The driving current provided by the first voltage source can flow into the first light-emitting element D1 through the fifth transistor T5, the third node C, the driving transistor Tr, the second node B, the fourth transistor T4, the first node A, and the first transistor T1 in sequence, forming a complete current path. When the second driving unit outputs a low-level second light-emitting control signal EM2, the sixth transistor T6 and the second transistor T2 are synchronously turned on. The driving current can flow into the second light-emitting element D2 through the fifth transistor T5, the third node C, the driving transistor Tr, the second node B, the fourth transistor T4, the first node A, and the second transistor T2 in sequence, forming a complete current path.

[0049] In this way, there is no need to set up additional driving units for the fifth transistor T5 and the sixth transistor T6. The first light emission control signal EM1 output by the first driving unit and the second light emission control signal EM2 output by the second driving unit can be reused respectively. Thus, without increasing the number of driving unit groups, the current path on the power supply side and the light emission side can be cut off at the same time, eliminating the dark-state light leakage caused by leakage current.

[0050] Reference Figure 1 In some embodiments, the pixel driving unit further includes a data reset circuit 7 connected to the third node C. The data reset circuit 7 includes a seventh transistor T7, which includes a first electrode connected to a data reset voltage, a second electrode connected to the third node C, and a control electrode connected to the third driving unit to receive the driving signal Pscan.

[0051] Reference Figure 6In the anode reset phase, the third driving unit outputs a driving signal Pscan to turn on the seventh transistor T7, causing a data reset voltage to be output to the third node C to reset the third node C. This reset is then passed to the driving transistor Tr to reset the second node B, eliminating residual charge on the second node B and the third node C and preventing residual charge from affecting the brightness. The seventh transistor T7 can be the same type as the third transistor T3. Connecting the control electrode of the seventh transistor T7 to the control electrodes of the third transistor T3 and the fourth transistor T4 to the same third driving unit allows for simultaneous data reset of the third node C and anode reset of the light-emitting element during the anode reset phase, simplifying the timing control of the display cycle. Thus, within the same anode reset phase, the reset of the second node B, the third node C, and the anode reset can be completed simultaneously without occupying additional timing parameters.

[0052] Reference Figure 8 After the anode reset phase, the third drive unit can continue to output a high-level drive signal Pscan, keeping the seventh transistor T7 and the third transistor T3 on. The data reset voltage Vi_T is transmitted to the third node C through the seventh transistor T7, pulling the potential of the third node C to a low data reset voltage, and then resetting the second node B via the drive transistor Tr. Simultaneously, the third transistor T3 is turned on to reset the first node A using the anode reset voltage. This allows for secondary resets of the first node A, the second node B, and the third node C, optimizing the reset effect.

[0053] In some embodiments, the display cycle of the pixel driving unit further includes a light-emitting phase.

[0054] Reference Figure 9 When the pixel driving unit operates in the first light emission mode, the first driving unit outputs the first light emission control signal EM1 to drive the first transistor T1 and the fifth transistor T5 to turn on, the second driving unit outputs the second light emission control signal EM2 to drive the second transistor T2 and the sixth transistor T6 to turn off, and the driving transistor Tr turns on according to the written data voltage, so that the first light emission element D1 emits light.

[0055] Combination Figure 3As an example, during the light-emitting phase of the first light-emitting mode, the first driving unit outputs a low-level first light-emitting control signal EM1, causing the fifth transistor T5 and the first transistor T1 to conduct simultaneously; the second driving unit outputs a high-level second light-emitting control signal EM2, causing the sixth transistor T6 and the second transistor T2 to be turned off simultaneously. At this time, the driving current provided by the first voltage source VDD flows sequentially through the fifth transistor T5, the third node C, the driving transistor Tr, the second node B, the fourth transistor T4, the first node A, and the first transistor T1, into the anode of the first light-emitting element D1, and then flows out from the cathode of the first light-emitting element D1 to the second voltage source VSS, forming a complete current loop, causing the first light-emitting element D1 to emit light.

[0056] Reference Figure 10 When the pixel driving unit operates in the second light emission mode, the first driving unit outputs the first light emission control signal EM1 to drive the first transistor T1 and the fifth transistor T5 to turn off, the second driving unit outputs the second light emission control signal EM2 to drive the second transistor T2 and the sixth transistor T6 to turn on, and the driving transistor Tr turns on according to the written data voltage, so that the second light emission element D2 emits light.

[0057] Combination Figure 5 As an example, during the light-emitting phase of the second light-emitting mode, the second driving unit outputs a low-level second light-emitting control signal EM2, causing the sixth transistor T6 and the second transistor T2 to conduct simultaneously; the first driving unit outputs a high-level first light-emitting control signal EM1, causing the fifth transistor T5 and the first transistor T1 to turn off simultaneously. At this time, the driving current flows sequentially through the sixth transistor T6, the third node C, the driving transistor Tr, the second node B, the fourth transistor T4, the first node A, and the second transistor T2, into the anode of the second light-emitting element D2, causing the second light-emitting element D2 to emit light.

[0058] Reference Figure 11 When the pixel driving unit operates in the third light emission mode, the first driving unit outputs the first light emission control signal EM1 to drive the first transistor T1 and the fifth transistor T5 to turn on, the second driving unit outputs the second light emission control signal EM2 to drive the second transistor T2 and the sixth transistor T6 to turn on, and the driving transistor Tr turns on according to the written data voltage, so that the first light emission element D1 and the second light emission element D2 emit light respectively.

[0059] Combination Figure 7As an example, during the light-emitting phase of the third light-emitting mode, the first and second driving units simultaneously output low-level control signals, causing the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the second transistor T2 to conduct simultaneously. At this time, the driving current provided by the first voltage source VDD passes sequentially through the third node C, the driving transistor Tr, the fourth transistor T4, and the first node A, and splits into two paths at the first node A. One driving current flows through the first transistor T1 into the first light-emitting element D1; the other driving current flows through the second transistor T2 into the second light-emitting element D2, causing the first light-emitting element D1 and the second light-emitting element D2 to emit light simultaneously for shared display. Throughout the light-emitting phase, the third driving unit outputs a low-level driving signal Pscan, causing the third transistor T3 to turn off and the fourth transistor T4 to turn on. The turning off of the third transistor T3 prevents the anode reset voltage from leaking to the first node A, affecting the stability of the light-emitting current; simultaneously, the turning on of the fourth transistor T4 allows the driving current to be transmitted from the second node B to the first node A, providing a current path for the first light-emitting element D1 and the second light-emitting element D2.

[0060] Reference Figure 1 In some embodiments, the pixel driving unit further includes a data writing sub-circuit for writing data voltage to the control electrode of the driving transistor.

[0061] As an example of a data writing sub-circuit, the data writing sub-circuit includes a writing circuit 8, a reset circuit 9, and a connection circuit 10. The gate driver also includes a fourth driving unit, a fifth driving unit, and a sixth driving unit. The writing circuit 8 includes an eighth transistor T8, which includes a first electrode connected to a data voltage, a second electrode connected to a third node C, and a control electrode connected to the fourth driving unit to access the write control signal Pscan2. The reset circuit 9 includes a ninth transistor T9, which includes a first electrode connected to a reset voltage, a second electrode connected to the control electrode of the driving transistor Tr at the fourth node Q, and a control electrode connected to the fifth driving unit to access the reset driving signal Nscan2. The connection circuit 10 includes a tenth transistor T10, which includes a first electrode connected to a second node B, a second electrode connected to the fourth node Q, and a control electrode connected to the sixth driving unit to access the connection control signal Nscan1.

[0062] As another example of the data writing sub-circuit, the data writing sub-circuit may also include a write transistor connected to the fourth node Q. The write transistor includes a first electrode that receives the data voltage, a second electrode that is connected to the fourth node Q, and a control electrode that receives the write control signal Pscan2, so as to directly transmit the data voltage to the fourth node through the write transistor.

[0063] It should be noted that the data writing sub-circuit can also adopt other architectures that can write data voltage to the fourth node Q, without specific limitations here.

[0064] As an example, the write circuit 8 is used to write the data voltage output by the external data driving circuit to the control electrode of the driving transistor Tr. When the fourth driving unit outputs a low-level write control signal Pscan2, the eighth transistor T8 is turned on, and the data voltage is transmitted sequentially through the eighth transistor T8, the third node C, the driving transistor Tr, and the tenth transistor T10 to the control electrode of the driving transistor Tr. The reset circuit 9 is used to reset the potential of the control electrode of the driving transistor Tr at the initial stage of the display cycle, eliminating the charge remaining in the fourth node Q after the previous frame is displayed, and ensuring the accurate writing of the data voltage for the next frame. When the fifth driving unit outputs a high-level reset drive signal Nscan2, the ninth transistor T9 is turned on, pulling the potential of the fourth node Q to the reset voltage. The connection circuit 10 is used to connect the second electrode of the driving transistor Tr to the control electrode, realizing threshold voltage compensation of the driving transistor Tr. When the sixth driving unit outputs a high-level connection control signal Nscan1, the tenth transistor T10 is turned on, connecting the second node B and the fourth node Q.

[0065] Reference Figure 3 , 5 7. This disclosure exemplarily describes the operation process of a display panel, wherein the display cycle of the pixel driving unit sequentially includes an initial stage t1, a reset stage t2, a data writing stage t3, an anode reset stage t4, and a light emission stage t5.

[0066] In the initial stage t1, the fifth driving unit outputs a reset driving signal Nscan2 to drive the ninth transistor T9 to turn on, transmitting the reset voltage to the fourth node Q to perform an initial reset on the control electrode of the driving transistor Tr.

[0067] During the reset phase t2, the fifth drive unit outputs a reset drive signal Nscan2 to drive the ninth transistor T9 to turn on, and the sixth drive unit outputs a connection control signal Nscan1 to drive the tenth transistor T10 to turn on. At this time, the drive transistor Tr remains on after the initial reset, so that the reset voltage resets the second node B through the ninth transistor T9 and the tenth transistor T10, and resets the third node C through the drive transistor Tr.

[0068] During the data writing phase t3, the fourth driving unit outputs a low-level write control signal Pscan2, turning on the eighth transistor T8. The data voltage is then transmitted to the third node C through the eighth transistor T8. Simultaneously, the sixth driving unit continues to output a high-level connection control signal Nscan1, keeping the tenth transistor T10 on and connecting the second node B and the fourth node Q. At this time, the data voltage at the third node C is transmitted to the fourth node Q through the driving transistor Tr and the tenth transistor T10. The control electrode potential of the driving transistor Tr is charged to the sum of the data voltage and the threshold voltage, completing the data voltage writing and threshold voltage compensation.

[0069] In the first, second, and third light-emitting modes, the workflows of the initial stage t1, reset stage t2, and data writing stage t3 are the same, but the workflows of the anode reset stage t4 and the light-emitting stage t5 are different. The following is a description of each light-emitting mode.

[0070] Reference Figure 3 For the first light-emitting mode, during the anode reset stage t4, the third driving unit outputs a driving signal Pscan, driving the third transistor T3 to turn on, the fourth transistor T4 to turn off, and the seventh transistor T7 to turn on. After the seventh transistor T7 turns on, the data reset voltage is transmitted to the third node C through the seventh transistor T7, completing the reset of the third node C. The fourth transistor T4 turns off to isolate the interference of the driving current on the anode reset. After the third transistor T3 turns on, the anode reset voltage is transmitted to the first node A through the third transistor T3. At this time, the first driving unit drives the first transistor T1 to turn on, and the second driving unit drives the second transistor T2 to turn off. The anode reset voltage of the first node A is transmitted to the anode of the first light-emitting element D1 through the turned-on first transistor T1, resetting only the anode of the first light-emitting element D1.

[0071] For the first light-emitting mode, during the light-emitting stage t5, the third driving unit outputs the corresponding driving signal Pscan to drive the fourth transistor T4 to conduct, thereby connecting the driving current transmission path between the second node B and the first node A. The driving transistor Tr maintains its conducting state according to the data voltage written during the data writing stage t3; the first driving unit drives the first transistor T1 and the fifth transistor T5 to conduct synchronously; the driving current output from the first voltage source flows into the first light-emitting element D1 through the fifth transistor T5, the third node C, the driving transistor Tr, the second node B, the fourth transistor T4, the first node A, and the first transistor T1, thereby achieving the effect of driving only the first light-emitting element D1 to emit light.

[0072] Reference Figure 5 Regarding the second emission mode, the difference from the first emission mode is as follows: During the anode reset phase t4, the first driving unit outputs the first light-emitting control signal EM1 to turn off the first transistor T1, and the second driving unit outputs the second light-emitting control signal EM2 to turn on the second transistor T2. The anode reset voltage of the first node A is transmitted to the anode of the second light-emitting element D2 through the turned-on second transistor T2, resetting only the anode of the second light-emitting element D2. During the light-emitting phase t5, the second driving unit outputs the second light-emitting control signal EM2, driving the second transistor T2 and the sixth transistor T6 to turn on synchronously. The driving current flows into the second light-emitting element D2 through the sixth transistor T6, the driving transistor Tr, the fourth transistor T4, and the second transistor T2, achieving the effect of driving only the second light-emitting element D2 to emit light.

[0073] Reference Figure 7 Regarding the third emission mode, the difference from the first emission mode is as follows: During the anode reset phase t4, the first driving unit drives the first transistor T1 to conduct, and the second driving unit drives the second transistor T2 to conduct synchronously. The anode reset voltage of the first node A is transmitted to the anodes of the first light-emitting element D1 and the second light-emitting element D2 through the first transistor T1 and the second transistor T2 respectively for synchronous anode potential reset. During the light-emitting phase t5, the first driving unit drives the first transistor T1 and the fifth transistor T5 to conduct synchronously; the second driving unit drives the second transistor T2 and the sixth transistor T6 to conduct synchronously. The driving current at the first node A is divided into two paths: one path flows into the first light-emitting element D1 through the first transistor T1, and the other path flows into the second light-emitting element D2 through the second transistor T2, realizing synchronous light emission of the first light-emitting element D1 and the second light-emitting element D2.

[0074] In some embodiments, the pixel driving unit further includes a storage capacitor Cst and a boost capacitor Cboost. The first plate of the storage capacitor Cst is connected to the fourth node Q, and the second plate of the storage capacitor Cst is connected to the first voltage source. The first plate of the boost capacitor Cboost is connected to the fourth node Q, and the second plate of the boost capacitor Cboost is connected to the control electrode of the eighth transistor T8.

[0075] Reference Figure 12 , Figure 12 This is a schematic diagram of the architecture of the display device used in the display panel in the embodiments of this disclosure. The display device also includes a timing controller 300 and a source driver 400.

[0076] The display device includes a display area AA, which may include multiple scan lines G1 to Gn, multiple data lines intersecting the scan lines G1 to Gn, and multiple pixel driving units 100 respectively disposed in multiple areas defined by the intersections of the scan lines G1 to Gn and the data lines. Each pixel driving unit 100 is a dual-emitting-element pixel driving unit, including a first emitting-element D1 and a second emitting-element D2.

[0077] The timing controller 300 receives externally input image data and control signals, and performs preprocessing such as format conversion and data sorting on the image data to obtain data signals. Simultaneously, the timing controller 300 generates six independent gate control signals and clock signals, as well as source control signals. The six independent gate control signals are: a first light emission control signal EM1, a second light emission control signal EM2, a drive signal Pscan, a write control signal Pscan2, a connection control signal Nscan1, and a reset drive signal Nscan2. Then, the data signals and source control signals are sent to the source driver 400, and the aforementioned gate control signals and clock signals are sent to the gate driver 200.

[0078] The gate driver 200 integrates a first driving unit, a second driving unit, a third driving unit, a fourth driving unit, a fifth driving unit, and a sixth driving unit. Each driving unit receives corresponding control signals and clock signals from the timing controller 300, generates a gate driving signal for line-by-line scanning, and transmits it sequentially to the pixel driving unit 100 of the corresponding row through scan lines G1 to Gn, independently controlling the on / off timing of each transistor in the pixel driving unit 100. After receiving the data signal and control signal from the timing controller 300, the source driver 400 stores the data signal in an internal register and outputs it synchronously according to the scan signal of the gate driver 200. The data voltage is written into the pixel driving unit 100 of the corresponding column through the data line, ultimately realizing the display of the image.

[0079] According to a second aspect of this disclosure, a pixel driving circuit is provided, including a first light-emitting control circuit 1, a second light-emitting control circuit 2, an isolation circuit 4, and an anode reset circuit 3. One end of the isolation circuit 4 is connected to a driving current provided by a first voltage source, and the other end is connected to the anode reset circuit 3, the first light-emitting control circuit 1, and the second light-emitting control circuit 2 at a first node A. The first light-emitting control circuit 1 is connected between the first node A and a first light-emitting element D1. The second light-emitting control circuit 2 is connected between the first node A and a second light-emitting element D2. This pixel driving circuit possesses all the beneficial effects of the aforementioned display panel, which will not be elaborated further in this disclosure.

[0080] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0082] The embodiments, implementation methods and related technical features disclosed herein can be combined and substituted for each other without conflict.

[0083] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A display panel, characterized in that, It includes a gate driver, a pixel driving unit connected to the gate driver, and a first light-emitting element and a second light-emitting element connected to the pixel driving unit; The pixel driving unit includes a first light-emitting control circuit, a second light-emitting control circuit, an anode reset circuit, and an isolation circuit. One end of the isolation circuit is used to connect to the driving current provided by the first voltage source, and the other end is connected to the anode reset circuit, the first light-emitting control circuit and the second light-emitting control circuit at the first node respectively. The first light-emitting control circuit is connected between the first node and the first light-emitting element; the second light-emitting control circuit is connected between the first node and the second light-emitting element.

2. The display panel according to claim 1, characterized in that, The display cycle of the pixel driving unit includes an anode reset phase; During the anode reset phase, the isolation circuit is used to control the disconnection between the first voltage source and the first node, the anode reset circuit is used to transmit the anode reset voltage to the first node, and the first light-emitting control circuit and the second light-emitting control circuit are used to selectively transmit the anode reset voltage of the first node to at least one of the first light-emitting element and the second light-emitting element to perform anode reset on at least one of the first light-emitting element and the second light-emitting element.

3. The display panel according to claim 2, characterized in that, The gate driver includes a first driving unit and a second driving unit; The first light-emitting control circuit includes a first transistor; the second light-emitting control circuit includes a second transistor. The first transistor includes a first electrode connected to the first node, a second electrode connected to the anode of the first light-emitting element, and a control electrode connected to the first driving unit to receive the first light-emitting control signal; The second transistor includes a first electrode connected to the first node, a second electrode connected to the anode of the second light-emitting element, and a control electrode connected to the second driving unit to receive a second light-emitting control signal.

4. The display panel according to claim 3, characterized in that, The gate driver includes a third driving unit; the pixel driving unit further includes a driving transistor connected between the first voltage source and the isolation circuit; The anode reset circuit includes a third transistor; the isolation circuit includes a fourth transistor; The third transistor includes a first electrode connected to the anode reset voltage, a second electrode connected to the first node, and a control electrode connected to the third driving unit to receive a driving signal; The fourth transistor includes a first electrode connected to the second node of the driving transistor, a second electrode connected to the first node, and a control electrode connected to the third driving unit to receive a driving signal; The third transistor and the fourth transistor are of different types.

5. The display panel according to claim 4, characterized in that: When the pixel driving unit is operating in the first light emission mode, during the anode reset phase, the third driving unit outputs the driving signal to drive the third transistor to turn on and the fourth transistor to turn off, the first driving unit outputs the first light emission control signal to drive the first transistor to turn on, and the second driving unit outputs the second light emission control signal to drive the second transistor to turn off, so as to reset the anode of the first light emission element. When the pixel driving unit operates in the second light emission mode, during the anode reset phase, the third driving unit outputs the driving signal to drive the third transistor to turn on and the fourth transistor to turn off, the first driving unit outputs the first light emission control signal to drive the first transistor to turn off, and the second driving unit outputs the second light emission control signal to drive the second transistor to turn on, so as to reset the anode of the second light emission element. When the pixel driving unit operates in the third light emission mode, during the anode reset phase, the third driving unit outputs the driving signal to drive the third transistor to turn on and the fourth transistor to turn off, the first driving unit outputs the first light emission control signal to drive the first transistor to turn on, and the second driving unit outputs the second light emission control signal to drive the second transistor to turn on, so as to simultaneously reset the anode of the first light emission element and the anode of the second light emission element.

6. The display panel according to claim 4, characterized in that, The pixel driving unit further includes a third light-emitting control circuit and a fourth light-emitting control circuit disposed between the first voltage source and the driving transistor; The third light-emitting control circuit includes a fifth transistor, which includes a first electrode connected to the first voltage source, a second electrode connected to the driving transistor at a third node, and a control electrode connected to the first driving unit to receive the first light-emitting control signal. The fourth light-emitting control circuit includes a sixth transistor, which includes a first electrode connected to the first voltage source, a second electrode connected to the third node, and a control electrode connected to the second driving unit to receive the second light-emitting control signal.

7. The display panel according to claim 6, characterized in that, The display cycle of the pixel driving unit also includes a light-emitting phase; When the pixel driving unit operates in the first light-emitting mode, the first driving unit outputs a first light-emitting control signal to drive the first transistor and the fifth transistor to turn on, the second driving unit outputs a second light-emitting control signal to drive the second transistor and the sixth transistor to turn off, and the driving transistor turns on according to the written data voltage, so that the first light-emitting element emits light; When the pixel driving unit operates in the second light-emitting mode, the first driving unit outputs a first light-emitting control signal to drive the first transistor and the fifth transistor to disconnect, the second driving unit outputs a second light-emitting control signal to drive the second transistor and the sixth transistor to turn on, and the driving transistor turns on according to the written data voltage, so that the second light-emitting element emits light; When the pixel driving unit operates in the third light emission mode, the first driving unit outputs a first light emission control signal to drive the first transistor and the fifth transistor to turn on, the second driving unit outputs a second light emission control signal to drive the second transistor and the sixth transistor to turn on, and the driving transistor turns on according to the written data voltage, so that the first light emission element and the second light emission element emit light respectively.

8. The display panel according to claim 6, characterized in that, The pixel driving unit also includes a data reset circuit connected to the third node; The data reset circuit includes a seventh transistor, which includes a first electrode that receives the data reset voltage, a second electrode that is connected to the third node, and a control electrode that is connected to the third driving unit to receive the driving signal. During the anode reset phase, the third driving unit outputs the driving signal to turn on the seventh transistor, thereby outputting the data reset voltage to the third node to reset the third node.

9. The display panel according to claim 6, characterized in that, It also includes a data writing sub-circuit for writing a data voltage to the control electrode of the driving transistor; the data writing sub-circuit includes a writing circuit, a reset circuit, and a connection circuit; the gate driver also includes a fourth driving unit, a fifth driving unit, and a sixth driving unit; The write circuit includes an eighth transistor, which includes a first electrode that receives a data voltage, a second electrode that is connected to the third node, and a control electrode that is connected to the fourth driving unit to receive a write control signal. The reset circuit includes a ninth transistor, which includes a first electrode that receives a reset voltage, a second electrode that is connected to the control electrode of the driving transistor at a fourth node, and a control electrode that is connected to the fifth driving unit to receive the reset driving signal. The connection circuit includes a tenth transistor, which includes a first electrode connected to the second node, a second electrode connected to the fourth node, and a control electrode connected to the sixth driving unit to access a communication control signal.

10. A pixel driving circuit, characterized in that, It includes a first light-emitting control circuit, a second light-emitting control circuit, an isolation circuit, and an anode reset circuit; One end of the isolation circuit is used to connect to the driving current provided by the first voltage source, and the other end is connected to the anode reset circuit, the first light-emitting control circuit and the second light-emitting control circuit at the first node respectively. The first light-emitting control circuit is connected between the first node and the first light-emitting element; the second light-emitting control circuit is connected between the first node and the second light-emitting element.

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