A circuit for generating a serial RGB data stream and a method of designing the same

Abstract

The application provides a circuit for generating serial RGB data stream and a design method thereof, adopts a new circuit and a design method thereof, and generates serial RGB data stream capable of driving a full-color LED screen. Meanwhile, the circuit has strong expansion and supports multi-screen cascade, and one CPU can drive multiple display screens. The application adopts a bus connection mode to input the CPU end RGB signal into a latch and a buffer, time-division multiplexes, carries out latch processing on parallel RGB data, and outputs serial RGB data for driving a full-color LED screen of a HUB75E interface.

Description

Technical Field

[0001] This invention belongs to the field of LED display driving technology, and specifically relates to a circuit for generating a serial RGB data stream and its design method. Background Technology

[0002] In existing technologies, LED display technology uses a matrix of LED beads as the basic light source. Content is displayed by controlling the brightness, color, and intensity of each LED bead in the display module. Due to their inorganic material properties, LEDs offer relatively good stability and have lower requirements for the application environment, making them suitable for both indoor and outdoor all-weather use. Furthermore, LEDs' infinite scalability allows them to cover display products ranging from small to ultra-large sizes. In addition, as self-emissive displays, they feature high brightness, wide viewing angles, and high definition, meeting the needs of various environments. Currently, LED displays, with their advantages of high brightness, rich colors, and wide viewing angles, are widely used in outdoor advertising, stage backdrops, and sports venues. From the initial monochrome indication to the latest full-color ultra-high-definition displays, LED display and driving technology has consistently evolved towards the goal of "brighter, denser, and smarter."

[0003] LED driving technology has evolved from constant voltage driving to constant current control, and the scanning mechanism of the driving signal has gradually transformed from static scanning to dynamic scanning, with interfaces becoming increasingly standardized. Among these, HUB12, HUB08, and HUB75E are three common interface types, each with its specific driving principle and application scenarios. The HUB12 interface uses 1 / 4 scan technology, allowing for high-density pixel control with a lower pin count, and is specifically designed for outdoor three-color displays. The HUB08 interface uses 1 / 16 scan, updating more display data in the same amount of time, and is commonly used in indoor three-color displays. Unlike HUB12 and HUB08, HUB75E uses 1 / 32 scan technology, supporting higher resolution and color depth, meeting the needs of fine image processing, and is mainly used in indoor full-color displays, making it ideal for commercial advertising and exhibitions.

[0004] However, the shortcomings of existing technologies are:

[0005] While using high-end interfaces can enable LED full-color screens to achieve higher resolution and color depth, the large number of pins required on these interfaces necessitates more precise control of the drive signals over high-density pixels. Current technologies often employ direct GPIO control or FPGA hardware generation. The former results in excessive CPU resource consumption and limited refresh rates, preventing the LED display from achieving the expected resolution. The latter, based on FPGAs, can directly generate the timing signals required for the HUB75E interface using hardware description languages. While this technology supports high-resolution and high-refresh-rate screens, its development costs are extremely high, requiring developers with advanced hardware design capabilities, thus hindering current technology from meeting the demands of the application market.

[0006] In addition, the technical terms in this field include:

[0007] LED Display Screen: LED is the abbreviation for light emitting diode, or simply LED. It uses the electroluminescence principle of a semiconductor PN junction to produce red, green, and blue colors. In recent years, LEDs have greatly improved in terms of emission wavelength range and performance, and have begun to be used in flat panel display products, namely LED displays.

[0008] RGB: RGB format is a color encoding method based on the combination of the three primary colors: red, green, and blue. It is a widely used color standard in the industry, generating various colors by adjusting the intensity values ​​of these three colors (ranging from 0 to 255). The core principle of the RGB format is additive mixing, that is, generating other colors by superimposing red, green, and blue light. When the intensity of all three is 255, white is generated; when the intensity of all three is 0, black is generated.

[0009] GPIO: GPIO stands for General Purpose Input / Output. GPIO is a crucial hardware resource in embedded systems, widely used in microcontrollers, development boards, and other electronic devices. It implements digital signal input and output through software control, offering high flexibility and versatility.

[0010] FPGA: FPGA stands for Field Programmable Gate Array. It is a programmable logic device that users can program using a hardware description language to implement specific digital logic functions. It initially emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), solving the shortcomings of custom circuits while overcoming the limitation of the limited gate count of traditional programmable devices.

[0011] CPU: CPU stands for Central Processing Unit, the core hardware component of a computer system. It is responsible for executing program code, processing data, and controlling the operation of other hardware devices. The CPU receives instructions from memory or input devices, executes arithmetic and logical operations according to the instructions, and finally outputs the results. It is also responsible for performing various operations on data, including arithmetic operations, logical operations, and data transfer. At the same time, it coordinates and controls the operation of other hardware devices in the computer system to ensure the efficient operation of the system.

[0012] D-type flip-flop: A D-type flip-flop is a digital electronic circuit with memory function. It samples the input signal at each rising edge of the clock and holds its state until the next rising edge of the clock arrives. The main function of a D-type flip-flop is to delay the state change of the output signal, ensuring reliable data transmission and processing.

[0013] Latch: A latch is a level-sensitive memory unit whose state changes depending on the level of the input signal. When the enable signal is valid, the output changes in real time with the input data; when the enable signal is invalid, the output remains locked.

[0014] Buffers: These typically refer to buffer registers, which are divided into input buffers and output buffers. The former temporarily stores data sent by peripherals for CPU processing, while the latter temporarily stores data sent by the CPU to peripherals. They coordinate data transfer between the high-speed CPU and low-speed peripherals (such as printers and hard drives) to ensure synchronization. Summary of the Invention

[0015] To address the aforementioned problems, the purpose of this application is to provide a novel circuit and its design method for generating a serial RGB data stream capable of driving a full-color LED screen. Furthermore, the circuit of this invention offers strong scalability, supporting multi-screen cascading, allowing a single CPU to drive multiple displays.

[0016] This invention uses a bus connection to input the CPU-side RGB signal to the latch and buffer, performs time-division multiplexing, latches the parallel RGB data, and outputs serial RGB data to drive the HUB75E interface LED full-color screen.

[0017] Specifically, the present invention provides a circuit for generating a serial RGB data stream, the circuit comprising:

[0018] A latch module is used to time-division latch 24-bit parallel RGB data and convert it into a serial RGB data stream. The latch module includes an edge-triggered SN74HC574 and a level-triggered SN74HC573.

[0019] The SN74HC574 is an 8-bit edge-triggered D flip-flop with tri-state output function, used to latch the data at the input on the rising edge of the clock signal.

[0020] The SN74HC573 is an 8-bit level-triggered transparent latch used to latch RGB data, and its latching triggering mode is level-triggered.

[0021] The buffer module, including the SN74HC245, is used to enhance the driving capability of line control signals and provide level matching and signal isolation;

[0022] The SN74HC245 is an 8-bit bidirectional buffer used to provide drive capability for row control signals and has the functions of level matching and signal isolation.

[0023] The control signal generation module is used to generate the row control signals, clock signals, latch signals, and enable signals required by the HUB75E interface.

[0024] The interface module is used to map serial RGB data streams and control signals to the corresponding pins of the HUB75E interface.

[0025] The latch module splits the 24-bit RGB data into four groups, three of which are input to SN74HC574 and SN74HC573 respectively, and the fourth group is input to SN74HC245 to generate a latch enable signal and a clock signal.

[0026] The buffer module expands the output channels via a bus connection to drive six HUB75E interfaces.

[0027] The output enable pin of the SN74HC245 is controlled by the master logic and is activated only during data transmission; the circuit includes multiple SN74HC245 buffers connected in parallel for outputting six different sets of latch signals, enable signals and row control signals.

[0028] The circuit supports cascading drive of six HUB75E interfaces; the circuit expands the output channels through a shared bus structure, improving the overall driving capability, and is suitable for use scenarios where multiple LED displays are cascaded.

[0029] This invention also relates to a circuit design method for generating a serial RGB data stream, the method being applicable to any of the circuits described above, and comprising the following steps:

[0030] S1, Signal splitting: The 24-bit parallel RGB data output by the CPU is split into four groups. The first, second and third groups are input to three SN74HC574 latches and three SN74HC573 latches, respectively, and the fourth group is input to the SN74HC245 buffer.

[0031] S2, Latch Control:

[0032] The SN74HC574 is used to latch data on the rising edge of the clock, and the data output state is controlled by the output enable signal.

[0033] The SN74HC573 is used to transparently transmit data when the latch enable signal is high and latch the data on its falling edge.

[0034] S3, Buffer Enhancement: Input the latched row control signal, latch signal and enable signal to the SN74HC245 buffer to enhance the driving capability and match the level;

[0035] S4, Clock signal generation: The D23 signal is buffered by SN74HC245 to generate multiple independent clock signals required by the HUB75E interface.

[0036] S5, Interface Mapping: Map the serial RGB data stream and control signals to the corresponding pins according to the HUB75E interface definition;

[0037] Here, D0-D23 represent 24-bit parallel RGB data signals, including: the first group is D0-D6, the second group is D7-D14, the third group is D15-D21, and the fourth group is D22 and D23; D22 and D23 are multiplexed and no longer transmit RGB data, but instead generate control signals.

[0038] D22 generates latch enable signals LATO_UP and LATO_DOWN to control the latch timing of SN74HC574 / 573;

[0039] D23 generates six clock signals CLK1-CLK6 to drive the synchronization clock of the HUB75E interface.

[0040] The method further includes:

[0041] In the latching control of step S2:

[0042] The D22 signal is buffered by the SN74HC245 to generate two latch enable signals, among which:

[0043] One signal serves as the synchronous latch enable signal for the SN74HC574, triggering data latching on the rising edge; the other signal serves as the latch enable signal for the SN74HC573, latching data when the high level transitions to the low level.

[0044] In step S3, buffer enhancement:

[0045] A bus-shared architecture is adopted, and a set of control signals are input to six SN74HC245 chips to expand the output channels and enhance the driving capability;

[0046] The output enable pin of the SN74HC245 is controlled by the master logic and is activated only during data transmission to avoid bus conflicts.

[0047] In step S4, clock signal generation:

[0048] The D23 signal is buffered by the SN74HC245 to generate 6 independent clock signals, which are connected to the CLK pins of 6 HUB75E interfaces respectively.

[0049] The method further includes:

[0050] The direction of data transmission is fixed by the direction control pin of SN74HC245 to ensure unidirectional signal transmission and avoid current backflow.

[0051] A time-division multiplexing mechanism is adopted, and a latch module is used to convert parallel RGB data into a serial data stream to meet the timing requirements of the HUB75E interface.

[0052] The method supports cascading drive of six HUB75E interfaces and is suitable for long cable transmission and high-load LED display applications.

[0053] The method further includes:

[0054] Signal isolation is set between the latch and the buffer to prevent GPIO overload and ensure the stability of the row scanning logic; it is suitable for LED full-color screen driving and compatible with multi-screen cascading expansion requirements.

[0055] Therefore, the advantage of this solution is:

[0056] This invention generates a serial RGB data stream capable of driving a full-color LED screen. The advantage of using a serial RGB data stream over GPIO control is that it allows for precise control of the scanning frequency and data transmission, enabling high-speed updates of complex patterns and dynamic images, thus meeting the high resolution and high refresh rate requirements of full-color screens.

[0057] Compared to FPGA-based driving schemes, this invention not only simplifies circuit layout and reduces overall power consumption, but also significantly lowers development costs, fully meeting market application demands. It includes:

[0058] First, this solution uses a limited number of pins, offering strong scalability and supporting multi-screen cascading, thus meeting the needs of some large-size video wall applications. For example, using the 24-bit RGB data of a single CPU, it can drive at least six HUB75E type interfaces.

[0059] Secondly, using serial RGB format data streams can balance performance and resource consumption, enabling precise control of scanning frequency and data transmission, achieving high-speed updates of complex patterns and dynamic images, and meeting the high resolution and high refresh rate requirements of LED full-color screens.

[0060] Finally, the hardware circuit design of this invention is not complicated, the principle is easy to understand, and the circuit diagram is relatively easy to draw, which can shorten the product development time and reduce the cost of R&D and mass production. Attached Figure Description

[0061] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0062] Figure 1 This is a schematic diagram of the circuit design scheme of this application.

[0063] Figure 2 This is a schematic diagram showing that D0-D6 in this application obtain a set of control signals after passing through the U2 latch, and then output six sets of control signals through six buffers.

[0064] Figure 3 This is a schematic diagram showing the 24-bit RGB data of a CPU in this application, which can be expanded to drive at least 6 HUB75E type interfaces.

[0065] Figure 4 This is a flowchart illustrating the method used in this application. Detailed Implementation

[0066] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0067] This application relates to a circuit and its design method for generating a serial RGB data stream. The technical solution will be described below with reference to embodiments.

[0068] First, the core function of the circuit:

[0069] The core function of this circuit design is to time-division latch 24-bit parallel RGB data using a latch, outputting a serial RGB data stream to drive the HUB75E interface. Simultaneously, it generates the row control signal, clock signal, latch signal, enable signal, and other control signals required by the HUB75E, and passes the row control signal through a buffer to enhance the driving capability to meet the long cables and high load requirements of the LED screen.

[0070] Secondly, key chip functions:

[0071] (1) SN74HC574. The SN74HC574 is an 8-bit edge-triggered D-type flip-flop with tri-state output functionality. Its core function is to latch multi-bit RGB data using a clock signal and control the data output state according to the output enable signal. When the clock pin detects a rising edge (signal level transitions from low to high), the data at the input terminal is latched into an internal register, and then the output terminal is controlled to be high, low, or high impedance (off state) through the output enable pin. The input data is captured instantaneously at the rising edge of the clock signal, and subsequent input changes do not affect the output until the next rising edge arrives. The latching process is independent of the state of the enable pin; even if the output is disabled, the data is still stored in the flip-flop.

[0072] (2) SN74HC573. The SN74HC573 is an 8-bit level-triggered transparent latch, also used for latching RGB data. Unlike the SN74HC574, the SN74HC573 uses level-triggered latching. When the latch enable pin is high, the input data is directly transmitted to the output data pin. When the latch enable pin transitions from high to low, the chip latches and holds the instantaneous value of the input data, and the output no longer changes with the input. The output state is controlled by the output enable pin; when the output enable pin is high, the output is in a high-impedance state, and when the output enable pin is low, the output is activated. Through transparent latching and a tri-state output mechanism, the SN74HC573 achieves temporary storage, isolation, and driving of parallel data, realizing the temporary storage of parallel RGB data streams.

[0073] (3) The SN74HC245 is an 8-bit bidirectional buffer that provides drive capability for the row control signal and also functions as a level matcher and signal isolation device. It isolates the main controller's GPIO from high-load circuits, preventing current backflow or overload and ensuring the reliability and stability of the row scanning logic. Its direction switching is clock-independent and directly controlled by the direction control pin level. When the direction control pin is high, the data transmission direction is fixed from end A to end B. Conversely, when the direction control pin is low, data is transmitted from end B to end A. Its output enable control pin is active low and controlled by the main controller logic, enabling only during data transmission.

[0074] When the output enable control pin is low, the bus is activated, and data is transmitted in the configured direction. When the output enable control pin is high, all bus ports enter a high-impedance state, isolating them from external circuits and preventing bus conflicts. One set of RGB data after passing through the latch is used as input to multiple SN74HC245 buffers connected in parallel, thus enabling the output of multiple different latch signals, enable signals, and row control signals.

[0075] Finally, the circuit design principle:

[0076] (1) Signal splitting

[0077] First, the CPU's 24-bit RGB data is split into four groups of multi-bit data: the first group is D0-D6, the second group is D7-D14, the third group is D15-D21, and the fourth group is D22 and D23. The first, second, and third groups are connected in parallel and input to three pairs of SN74HC574 and SN74HC573 sensors, respectively. The fourth group consists of two data signals, D22 and D33, which are received by the eight input channels of the SN74HC245, totaling two D22 signals and six D23 signals.

[0078] (2) Latch control

[0079] After the D22 signal is connected to the two input channels of the SN74HC245, there are two corresponding output signals. One of them serves as the synchronous latch enable signal for the three SN74HC574 chips, triggering data latching on the rising edge of the signal. The other serves as the synchronous latch enable signal for the three SN74HC573 chips, triggering the latch signal when the signal transitions from high to low. The six latches output a total of twelve sets of serial RGB data and one set of control signals, including row control, latch, and enable signals. The serial RGB data stream can be directly connected to the HUB75E interface as the data signal to drive the LED full-color screen.

[0080] After D23 is connected to the six input channels of SN74HC245, there are six corresponding output signals. This group of signals are the clock signals of the six HUB75E interfaces, which are directly connected to the corresponding HUB75E interface pins.

[0081] (3) Buffering and driver enhancement

[0082] The D0-D6 data from the CPU passes through an SN74HC574, outputting a set of row control signals, latch signals, and enable signals. These control signals are then connected to the input pins of six SN74HC245 chips via a bus connection. Each SN74HC245 outputs two sets of row control signals, latch signals, and enable signals, for a total of twelve sets. This shared bus architecture not only expands the output channels but also improves the overall driving capability, meets high current requirements, ensures signal integrity during long-distance transmission, and is suitable for cascading multiple LED displays.

[0083] (4) HUB75E interface mapping

[0084] The pin definitions and network mappings of the HUB75E interface are shown in Table 1 below.

[0085] pin Signal Function Corresponding connection 1 RD1 Red data signal latch output signal 2 GD1 Green data signal latch output signal 3 BD1 Blue data signal latch output signal 4 GND power ground power ground 5 RD2 Red data signal latch output signal 6 GD2 Green data signal latch output signal 7 BD2 Blue data signal latch output signal 8 E Line control signal Buffer output signal 9 A Line control signal Buffer output signal 10 B Line control signal Buffer output signal 11 C Line control signal Buffer output signal 12 D Line control signal Buffer output signal 13 CLK clock signal Buffer output signal 14 LE latch signal Buffer output signal 15 OE Enable signal Buffer output signal 16 GND power ground power ground

[0086] Table 1 HUB75E Interface Definitions and Mapping Relationships

[0087] In summary, the circuit for generating a serial RGB data stream in this technical solution is as follows: Figure 1 As shown, the circuit includes:

[0088] A latch module is used to time-division latch 24-bit parallel RGB data and convert it into a serial RGB data stream. The latch module includes an edge-triggered SN74HC574 and a level-triggered SN74HC573.

[0089] The SN74HC574 is an 8-bit edge-triggered D flip-flop with tri-state output function, used to latch the data at the input on the rising edge of the clock signal.

[0090] The SN74HC573 is an 8-bit level-triggered transparent latch used to latch RGB data, and its latching triggering mode is level-triggered.

[0091] The buffer module, including the SN74HC245, is used to enhance the driving capability of line control signals and provide level matching and signal isolation;

[0092] The SN74HC245 is an 8-bit bidirectional buffer used to provide drive capability for row control signals and has the functions of level matching and signal isolation.

[0093] The control signal generation module is used to generate the row control signals, clock signals, latch signals, and enable signals required by the HUB75E interface.

[0094] The interface module is used to map serial RGB data streams and control signals to the corresponding pins of the HUB75E interface.

[0095] like Figure 1 As shown, D0-D21 are divided into three groups and input to the latch via a bus connection. Time-division multiplexing converts parallel RGB data into serial RGB data. D22 and D23 output eight signals after passing through the SN74HC245 buffer. LATO_UP is the latch enable signal of SN74HC574, LATO_DOWN is the latch enable signal of SN74HC573, and CLK1-CLK6 are connected to the clock signal pins of the six HUB75E interfaces.

[0096] The latch module splits the 24-bit RGB data into four groups. Three groups are input to SN74HC574 and SN74HC573 respectively, and the fourth group is input to SN74HC245 to generate latch enable and clock signals. The first group consists of D0-D6, the second group consists of D7-D14, the third group consists of D15-D21, and the fourth group consists of D22 and D23. D22 and D23 are multiplexed and no longer transmit RGB data, but instead generate control signals: such as... Figure 2 As shown, D0-D6 obtain a set of control signals after passing through the U2 latch, and output six sets of control signals after passing through six buffers; D22 generates latch enable signals LATO_UP and LATO_DOWN to control the latch timing of SN74HC574 / 573; D23 generates six clock signals CLK1-CLK6 to drive the synchronization clock of the HUB75E interface.

[0097] The buffer module expands the output channels via a bus connection to drive multiple HUB75E interfaces. For example... Figure 3 As shown, the 24-bit RGB data of one CPU can drive at least 6 HUB75E type interfaces.

[0098] The output enable pin of the SN74HC245 is controlled by the master control logic and is activated only during data transmission; the circuit includes multiple SN74HC245 buffers connected in parallel for outputting multiple sets of different latch signals, enable signals and row control signals.

[0099] The circuit supports cascading drive of at least six HUB75E interfaces. It expands the output channels through a shared bus structure, improving overall driving capability and making it suitable for scenarios involving cascading multiple LED displays. Here, "multiple LED displays" refers to one LED screen connected to one HUB75E interface, so six HUB75E interfaces correspond to a total of six screens. However, cascading is possible; the next level of LED screen connects to the interfaces on the screens connected from the HUB75E interfaces. There is no limit to the number of LED displays that can be cascaded using this method, as the specific number is mainly limited by the software program.

[0100] This invention also relates to a circuit design method for generating a serial RGB data stream, the method being applicable to any of the circuits described above, such as... Figure 4 As shown, it includes the following steps:

[0101] S1, Signal splitting: The 24-bit parallel RGB data output by the CPU is split into four groups. The first, second and third groups are input to three SN74HC574 latches and three SN74HC573 latches, respectively, and the fourth group is input to the SN74HC245 buffer.

[0102] S2, Latch Control:

[0103] The SN74HC574 is used to latch data on the rising edge of the clock, and the data output state is controlled by the output enable signal.

[0104] The SN74HC573 is used to transparently transmit data when the latch enable signal is high and latch the data on its falling edge.

[0105] S3, Buffer Enhancement: Input the latched row control signal, latch signal and enable signal to the SN74HC245 buffer to enhance the driving capability and match the level;

[0106] S4, Clock signal generation: The D23 signal is buffered by SN74HC245 to generate multiple independent clock signals required by the HUB75E interface.

[0107] S5, Interface Mapping: Map the serial RGB data stream and control signals to the corresponding pins according to the HUB75E interface definition;

[0108] Here, D0-D23 represent 24-bit parallel RGB data signals, including: the first group is D0-D6, the second group is D7-D14, the third group is D15-D21, and the fourth group is D22 and D23; D22 and D23 are multiplexed and no longer transmit RGB data, but instead generate control signals.

[0109] D22 generates latch enable signals LATO_UP and LATO_DOWN to control the latch timing of SN74HC574 / 573;

[0110] D23 generates six clock signals CLK1-CLK6 to drive the synchronization clock of the HUB75E interface.

[0111] Further includes:

[0112] In the latching control of step S2:

[0113] The D22 signal is buffered by the SN74HC245 to generate two latch enable signals, among which:

[0114] One signal serves as the synchronous latch enable signal for the SN74HC574, triggering data latching on the rising edge; the other signal serves as the latch enable signal for the SN74HC573, latching data when the high level transitions to the low level.

[0115] In step S3, buffer enhancement:

[0116] A bus-shared architecture is adopted, in which a set of control signals are input to multiple SN74HC245 chips to expand the output channels and enhance the driving capability;

[0117] The output enable pin of the SN74HC245 is controlled by the master logic and is activated only during data transmission to avoid bus conflicts.

[0118] In step S4, clock signal generation:

[0119] The D23 signal is buffered by the SN74HC245 to generate 6 independent clock signals, which are connected to the CLK pins of 6 HUB75E interfaces respectively.

[0120] The method further includes:

[0121] The direction of data transmission is fixed by the direction control pin of SN74HC245 to ensure unidirectional signal transmission and avoid current backflow.

[0122] A time-division multiplexing mechanism is adopted, and a latch module is used to convert parallel RGB data into a serial data stream to meet the timing requirements of the HUB75E interface.

[0123] The method supports cascading drive of 6 HUB75E interfaces and is suitable for long cable transmission and high-load LED display applications.

[0124] The method further includes:

[0125] Signal isolation is set between the latch and the buffer to prevent GPIO overload and ensure the stability of the row scanning logic; it is suitable for LED full-color screen driving and compatible with multi-screen cascading expansion requirements.

[0126] The following is a specific example based on the Beijing Junzheng PD_X2600_LED_V1.0 development board. The circuit design of the PD_X2600_LED_V1.0 development board related to this patent is described as follows: First, the LCDD0-D23 pins of the main control chip X2600 are divided into four groups of multi-bit data: the first group is D0-D6, the second group is D7-D14, the third group is D15-D21, and the fourth group is D22 and D23, which are connected to three SN74HC574 chips, three SN74HC573 chips, and six SN74HC245 chips, respectively.

[0127] The grouped LCD data lines are then connected as follows: D0-D6 drive one SN74HC574 to generate control signals AE, LAT, and OE, which are then connected to six SN74HC245 chips to output six sets of control signals, which are then connected to the corresponding control pins of the six HUB75E interfaces. D0-D6 are also time-multiplexed to one SN74HC573 via a bus connection to generate data R6-R8, G6-G7, and B6-B7. D7-D14 drive a second SN74HC574 to generate data R1-R3, G1-G3, and B1-B2, and simultaneously time-multiplexed to drive a second SN74HC573 to generate data R9-R10, G8-G10, and B9-B10. D15-D21 drive the third SN74HC574 to generate R4-R5, G4-G5, and B3-B5 data, and simultaneously time-division multiplexes it to drive the third SN74HC573 to generate R11-R12, G11-G12, and B11-B12 data. These generated serial RGB data streams (R1-R12, G1-G12, B1-B12) are connected to six HUB75E interfaces, each connected to its corresponding pin. Signal D22, a software-generated clock signal, is connected to two input channels of the SN74HC245, resulting in two corresponding output clock signals, which serve as latch enable signals for the three SN74HC574s and three SN74HC573s. Signal D23, connected to the six input channels of the SN74HC245, outputs six signals; this set of signals serves as the clock signals for the six HUB75E interfaces, directly connected to their corresponding pins. Finally, the HUB75E interface on the development board is connected to the LED display screen via a ribbon cable. Typically, an LED display screen has four sets of row drivers and four sets of column drivers. Each set of row drivers consists of three row driver chips, and each set of column drivers consists of four column driver chips. At this point, the entire hardware circuit fabrication and environment setup are complete. Since the circuit principles and design methods described in this patent do not involve the driver circuitry on the connected LED display screen, the circuitry on the LED display screen will not be described in detail.

[0128] The test process for the display effect is as follows: By filling R1-R12 with 0xff, G1-G12 with 0x00, and B1-B12 with 0x00 through the software configuration program, the LED display screen will light up red; filling R1-R12 with 0x00, G1-G12 with 0xff, and B1-B12 with 0x00 will light up green; filling R1-R12 with 0x00, G1-G12 with 0x00, and B1-B12 with 0xff will light up blue. The test results are in line with expectations.

[0129] In summary, the present invention can achieve:

[0130] The CPU's RGB data is input to the latch and cache via a bus connection. Time-division multiplexing enables multiple devices to share the same set of signal sources, thereby converting parallel RGB format data into serial RGB data.

[0131] This technical solution can be applied to Ingenic X2600 series chips and other chips with LCDRGB controllers and H.264 decoding capabilities.

[0132] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit for generating a serial RGB data stream, characterized in that, The circuit includes: A latch module is used to time-division latch 24-bit parallel RGB data and convert it into a serial RGB data stream. The latch module includes an edge-triggered SN74HC574 and a level-triggered SN74HC573. The SN74HC574 is an 8-bit edge-triggered D flip-flop with tri-state output function, used to latch the data at the input on the rising edge of the clock signal. The SN74HC573 is an 8-bit level-triggered transparent latch used to latch RGB data, and its latching triggering mode is level-triggered. The buffer module, including the SN74HC245, is used to enhance the driving capability of line control signals and provide level matching and signal isolation; The SN74HC245 is an 8-bit bidirectional buffer used to provide drive capability for row control signals and has the functions of level matching and signal isolation. The control signal generation module is used to generate the row control signals, clock signals, latch signals, and enable signals required by the HUB75E interface. The interface module is used to map serial RGB data streams and control signals to the corresponding pins of the HUB75E interface.

2. The circuit for generating a serial RGB data stream according to claim 1, characterized in that, The latch module splits the 24-bit RGB data into four groups, three of which are input to SN74HC574 and SN74HC573 respectively, and the fourth group is input to SN74HC245 to generate a latch enable signal and a clock signal.

3. The circuit for generating a serial RGB data stream according to claim 1, characterized in that, The buffer module expands the output channels via a bus connection to drive six HUB75E interfaces.

4. The circuit for generating a serial RGB data stream according to claim 1, characterized in that, The output enable pin of the SN74HC245 is controlled by the master logic and is activated only during data transmission; the circuit includes multiple SN74HC245 buffers connected in parallel for outputting six different sets of latch signals, enable signals and row control signals.

5. The circuit for generating a serial RGB data stream according to claim 1, characterized in that, The circuit supports cascading drive of six HUB75E interfaces; the circuit expands the output channels through a shared bus structure, improving the overall driving capability, and is suitable for use scenarios where multiple LED displays are cascaded.

6. A circuit design method for generating a serial RGB data stream, characterized in that, The method is applicable to any of the circuits described in claims 1-5 above, and includes the following steps: S1, Signal splitting: The 24-bit parallel RGB data output by the CPU is split into four groups. The first, second and third groups are input to three SN74HC574 latches and three SN74HC573 latches, respectively, and the fourth group is input to the SN74HC245 buffer. S2, Latch Control: The SN74HC574 is used to latch data on the rising edge of the clock, and the data output state is controlled by the output enable signal. The SN74HC573 is used to transparently transmit data when the latch enable signal is high and latch the data on its falling edge. S3, Buffer Enhancement: Input the latched row control signal, latch signal and enable signal to the SN74HC245 buffer to enhance the driving capability and match the level; S4, Clock signal generation: The D23 signal is buffered by SN74HC245 to generate multiple independent clock signals required by the HUB75E interface. S5, Interface Mapping: Map the serial RGB data stream and control signals to the corresponding pins according to the HUB75E interface definition; Here, D0-D23 represent 24-bit parallel RGB data signals, including: the first group is D0-D6, the second group is D7-D14, the third group is D15-D21, and the fourth group is D22 and D23; D22 and D23 are multiplexed and no longer transmit RGB data, but instead generate control signals. D22 generates latch enable signals LATO_UP and LATO_DOWN to control the latch timing of SN74HC574 / 573; D23 generates six clock signals CLK1-CLK6 to drive the synchronization clock of the HUB75E interface.

7. The circuit design method for generating a serial RGB data stream according to claim 6, characterized in that, Further includes: In the latching control of step S2: The D22 signal is buffered by the SN74HC245 to generate two latch enable signals, among which: One signal serves as the synchronous latch enable signal for the SN74HC574, triggering data latching on the rising edge; the other signal serves as the latch enable signal for the SN74HC573, latching data when the high level transitions to the low level. In step S3, buffer enhancement: A bus-shared architecture is adopted, and a set of control signals are input to six SN74HC245 chips to expand the output channels and enhance the driving capability; The output enable pin of the SN74HC245 is controlled by the master logic and is activated only during data transmission to avoid bus conflicts. In step S4, clock signal generation: The D23 signal is buffered by the SN74HC245 to generate 6 independent clock signals, which are connected to the CLK pins of 6 HUB75E interfaces respectively.

8. The circuit design method for generating a serial RGB data stream according to claim 6, characterized in that, The method further includes: The direction of data transmission is fixed by the direction control pin of SN74HC245 to ensure unidirectional signal transmission and avoid current backflow. A time-division multiplexing mechanism is adopted, and a latch module is used to convert parallel RGB data into a serial data stream to meet the timing requirements of the HUB75E interface.

9. The circuit design method for generating a serial RGB data stream according to claim 6, characterized in that, The method supports cascading drive of six HUB75E interfaces and is suitable for long cable transmission and high-load LED display applications.

10. The circuit design method for generating a serial RGB data stream according to claim 6, characterized in that, The method further includes: Signal isolation is set between the latch and the buffer to prevent GPIO overload and ensure the stability of the row scanning logic; it is suitable for LED full-color screen driving and compatible with multi-screen cascading expansion requirements.

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