Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a pixel including a first transistor including a gate connected to a first node, a first terminal to receive a first power voltage, and a second terminal connected to a second node, a second transistor to transmit a data signal to a third node in response to a write gate signal, a first capacitor connected between the first node and the third node, a third transistor to connect the first node to the second node in response to a compensation gate signal, a fourth transistor including a gate, a first terminal connected to the second node, and a second terminal connected to a fourth node, and a light emitting element including a first terminal connected to the fourth node and a second terminal to receive a second power voltage. An activation voltage level of a signal received by the gate of the fourth transistor is different from an activation voltage level of the write gate signal.

Description

Technical Field

[0001] The embodiments relate to a display device. More specifically, the embodiments relate to a display device including pixels that emit light and an electronic device including a display device for displaying images. Background Technology

[0002] The display device may include a display panel, a gate driver, and a data driver. The display panel may include pixels, the gate driver may provide gate signals to the pixels, and the data driver may provide data voltages to the pixels.

[0003] A pixel may include a light-emitting element and multiple transistors. The light-emitting element emits light with a brightness corresponding to a driving current, and the multiple transistors include a driving transistor that generates the driving current. Based on a gate signal and a data voltage provided to the pixel, the driving transistor can be initialized, its threshold voltage can be compensated, a data voltage can be written to it, the light-emitting element can be initialized, and the light-emitting element can emit light. Summary of the Invention

[0004] The embodiments provide a display device with improved display quality and an electronic device including the display device.

[0005] A display device according to an embodiment includes: a display panel including pixels; a gate driver for providing a write gate signal and a compensation gate signal to each pixel; an emitter driver for providing an emitter signal to each pixel; and a data driver for providing a data signal to each pixel. Each pixel includes: a first transistor including a gate connected to a first node, a first terminal for receiving a first electrical voltage, and a second terminal connected to a second node; a second transistor for transmitting a data signal to a third node in response to the write gate signal; a first capacitor connected between the first node and the third node; a third transistor for connecting the first node to the second node in response to the compensation gate signal; a fourth transistor including a gate, a first terminal connected to the second node, and a second terminal connected to the fourth node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal for receiving a second electrical voltage. The activation voltage level of the signal received by the gate of the fourth transistor is different from the activation voltage level of the write gate signal.

[0006] In an embodiment, the difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor can be less than the difference between the activation voltage level and the deactivation voltage level of the written gate signal.

[0007] In one embodiment, the activation voltage level of the signal received by the gate of the fourth transistor can be higher than the activation voltage level of the write gate signal.

[0008] In an embodiment, the activation voltage level of the signal received by the gate of the fourth transistor during the initialization period when the gate of the first transistor is initialized may be different from the activation voltage level of the signal received by the gate of the fourth transistor during the emission period when the light-emitting element emits light.

[0009] In an embodiment, the difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor during the initialization period can be greater than the difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor during the transmission period.

[0010] In one embodiment, the activation voltage level of the signal received by the gate of the fourth transistor during the initialization period may be lower than the activation voltage level of the signal received by the gate of the fourth transistor during the transmission period.

[0011] In this embodiment, the first transistor is of the same type as the fourth transistor.

[0012] In an embodiment, each pixel may further include a second capacitor connected between the first node and the power line transmitting the first power voltage.

[0013] In an embodiment, each pixel may further include a fifth transistor that transmits a ground voltage to a fourth node in response to a bypass gate signal.

[0014] In an embodiment, the transmission signal may include a first transmission signal and a second transmission signal, the gate of the fourth transistor may receive the first transmission signal, and each pixel in the pixel may further include: a sixth transistor that transmits a first electrical voltage to a first terminal of the first transistor in response to the second transmission signal.

[0015] In one embodiment, the gate of the fourth transistor can receive the transmitted signal.

[0016] In an embodiment, a pixel may include a red pixel, a green pixel, and a blue pixel. The activation voltage level of the red emission signal received by the gate of the fourth transistor of the red pixel, the activation voltage level of the green emission signal received by the gate of the fourth transistor of the green pixel, and the activation voltage level of the blue emission signal received by the gate of the fourth transistor of the blue pixel may be different from each other.

[0017] In an embodiment, the fourth transistor may include: a fourth-first transistor including a gate for receiving a bias voltage, a second terminal and a first terminal connected to a second node; and a fourth-second transistor including a gate for receiving a transmitted signal, a first terminal connected to the second terminal of the fourth-first transistor and a second terminal connected to a fourth node.

[0018] In an embodiment, the transmitted signal may include a first transmitted signal, a second transmitted signal, and a third transmitted signal. Each pixel in the pixel may further include: a seventh-first transistor, including a gate for receiving the first transmitted signal, a first terminal for receiving a first bias voltage, and a second terminal connected to the gate of a fourth transistor; a seventh-second transistor, including a gate for receiving the second transmitted signal, a first terminal for receiving a second bias voltage, and a second terminal connected to the gate of the fourth transistor; and a seventh-third transistor, including a gate for receiving the third transmitted signal, a first terminal for receiving the third bias voltage, and a second terminal connected to the gate of the fourth transistor.

[0019] In an embodiment, each pixel may further include a seventh transistor, including a gate for receiving a transmitted signal, a first terminal connected to a first node, a third node, or a fourth node, and a second terminal connected to the gate of the fourth transistor.

[0020] A display device according to an embodiment includes: a display panel including pixels; a gate driver for providing a write gate signal to each pixel in the pixels; an emitter driver for providing a first emitter signal and a second emitter signal to each pixel in the pixels; and a data driver for providing a data signal to each pixel in the pixels. Each pixel in the pixels includes: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor for transmitting a data signal to the first node in response to the write gate signal; a first capacitor connected between the first node and the second node; a fourth transistor for connecting a fourth node to the fourth node in response to the first emitter signal; a sixth transistor for transmitting a first electrical voltage to the second node in response to the second emitter signal; and a light-emitting element including a first terminal connected to the fourth node and a second terminal receiving the second electrical voltage. The activation voltage level of the first emitter signal is different from the activation voltage level of the write gate signal.

[0021] In an embodiment, the difference between the activation voltage level and the deactivation voltage level of the first transmit signal may be less than the difference between the activation voltage level and the deactivation voltage level of the write gate signal.

[0022] In an embodiment, the activation voltage level of the first transmit signal may be higher than the activation voltage level of the write gate signal.

[0023] In an embodiment, each pixel may further include: a second capacitor connected between the second node and the power line transmitting the first power voltage; and a fifth transistor for transmitting a ground voltage to the fourth node in response to a bypass gate signal.

[0024] An electronic device according to an embodiment includes: a processor for generating input image data; a display device for displaying an image based on the input image data; and a power module connected to the processor and the display device. The display device includes: a display panel including pixels; a gate driver for providing a write gate signal and a compensation gate signal to each pixel; a transmit driver for providing a transmit signal to each pixel; and a data driver for providing a data signal to each pixel. Each pixel includes: a first transistor including a gate connected to a first node, a first terminal for receiving a first power voltage, and a second terminal connected to a second node; a second transistor for transmitting a data signal to a third node in response to the write gate signal; a first capacitor connected between the first node and the third node; a third transistor for connecting the first node to the second node in response to the compensation gate signal; a fourth transistor including a gate, a first terminal connected to the second node, and a second terminal connected to the fourth node; and a light-emitting element including a first terminal connected to the fourth node and a second terminal for receiving a second power voltage. The activation voltage level of the signal received by the gate of the fourth transistor is different from the activation voltage level of the write gate signal.

[0025] In the pixel according to the embodiment, the activation voltage level of the signal received by the gate of the fourth transistor is different from (higher than) the activation voltage level of the write gate signal, so that the short-circuit path current flowing through the first transistor during the initialization period can be reduced. Therefore, the threshold voltage of the first transistor can be accurately compensated, and the black representation capability of the light-emitting element can be improved.

[0026] In the display device and electronic device according to the embodiments, the quality of the image displayed by the display device can be improved. Attached Figure Description

[0027] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel.

[0030] Figure 3 It is shown Figure 2 The timing diagram of the signal.

[0031] Figure 4 It is used to describe Figure 3 The diagram of the initialization period.

[0032] Figure 5 It is used to describe Figure 3 The graph shows the compensation period.

[0033] Figure 6 It is used to describe Figure 3 A graph showing the write periods.

[0034] Figure 7 It is used to describe Figure 3 The diagram shows the bypass period.

[0035] Figure 8 It is used to describe Figure 3 A diagram showing the launch schedule.

[0036] Figure 9 This is a timing diagram showing the transmitted signal according to the prior art.

[0037] Figure 10 This is a timing diagram showing the transmitted signal, the voltage of the first node, and the short-circuit path current during the initialization period.

[0038] Figure 11 This is a block diagram illustrating a display device according to an embodiment.

[0039] Figure 12 It is shown Figure 11 A circuit diagram of an example pixel.

[0040] Figure 13 It is shown Figure 12 The timing diagram of the signal.

[0041] Figure 14 This is a block diagram illustrating a display device according to an embodiment.

[0042] Figure 15 It is shown Figure 14 A circuit diagram of an example pixel.

[0043] Figure 16 It is shown Figure 15 The timing diagram of the signal.

[0044] Figure 17 This is a block diagram illustrating a display device according to an embodiment.

[0045] Figure 18 It is shown Figure 17 A circuit diagram of an example pixel.

[0046] Figure 19 It is shown Figure 18 The timing diagram of the signal.

[0047] Figure 20 It is shown Figure 1 A circuit diagram of an example pixel.

[0048] Figure 21 It is shown Figure 20 The timing diagram of the signal.

[0049] Figure 22 This is a block diagram illustrating a display device according to an embodiment.

[0050] Figure 23 It is shown Figure 22 A circuit diagram of an example pixel.

[0051] Figure 24 It is shown Figure 23 The timing diagram of the signal.

[0052] Figure 25 It is shown Figure 1 A circuit diagram of an example pixel.

[0053] Figure 26 It is shown Figure 25 The timing diagram of the signal.

[0054] Figure 27 This is a block diagram illustrating an electronic device according to an embodiment.

[0055] Figure 28 This is a diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” and / or “including” and variations thereof are used in this specification, the presence of the stated features, areas, integers, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof is not excluded.

[0057] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0058] In the following, the display device and electronic device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0059] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment.

[0060] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a transmitter driver 130, a data driver 140, and a controller 150.

[0061] The display panel 110 may include pixels PX. Each of the pixels PX may emit light based on a write gate signal GW, a compensation gate signal GC, an transmit signal EM, a bypass gate signal EB, and a data signal DS.

[0062] Gate driver 120 can provide a write gate signal GW and a compensation gate signal GC to each of the pixels PX. Gate driver 120 can generate the write gate signal GW and the compensation gate signal GC based on the pixel row. Gate driver 120 can generate the write gate signal GW and the compensation gate signal GC based on a first control signal CNT1. The first control signal CNT1 may include a write gate start signal, a compensation gate start signal, a gate clock signal, etc.

[0063] The transmit driver 130 can provide the transmit signal EM and the bypass gate signal EB to each of the pixels PX. The transmit driver 130 can generate the transmit signal EM and the bypass gate signal EB based on the pixel row. The transmit driver 130 can generate the transmit signal EM and the bypass gate signal EB based on a second control signal CNT2. The second control signal CNT2 may include a transmit start signal, a bypass gate start signal, a transmit clock signal, etc.

[0064] In an embodiment, such as Figure 1As shown, the bypass gate signal EB can be generated by the emitter driver 130. In an embodiment, the bypass gate signal EB can be generated by the gate driver 120.

[0065] Data driver 140 can provide a data signal DS to each of the pixels PX. Data driver 140 can generate the data signal DS based on the output image data IMD2 and the third control signal CNT3. Data driver 140 can convert the digital output image data IMD2 into the analog data signal DS. The third control signal CNT3 may include a load signal, a data clock signal, an output data enable signal, etc.

[0066] The controller 150 can control the gate driver 120, the transmit driver 130, and the data driver 140. The controller 150 can provide a first control signal CNT1 to the gate driver 120, a second control signal CNT2 to the transmit driver 130, and output image data IMD2 and a third control signal CNT3 to the data driver 140. The controller 150 can generate output image data IMD2, the first control signal CNT1, the second control signal CNT2, and the third control signal CNT3 based on the input image data IMD1 and the control signal CNT0. In this embodiment, the input image data IMD1 may include red image data, green image data, and blue image data. The control signal CNT0 may include a vertical synchronization signal, a horizontal synchronization signal, a master clock signal, an input data enable signal, etc.

[0067] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel PX. Figure 3 It is shown Figure 2 Timing diagrams of signals EM, GC, EB, GW and DS.

[0068] Reference Figure 2 and Figure 3 The pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a light-emitting element OLED.

[0069] The first transistor T1 may include a gate connected to a first node N1, a first terminal receiving a first power voltage ELVDD, and a second terminal connected to a second node N2. The first terminal of the first transistor T1 may be directly connected to the power line PL that transmits the first power voltage ELVDD.

[0070] The second transistor T2 can transmit the data signal DS to the third node N3 in response to the write gate signal GW. The second transistor T2 may include a gate for receiving the write gate signal GW, a first terminal for receiving the data signal DS, and a second terminal connected to the third node N3.

[0071] A first capacitor C1 may be connected between a first node N1 and a third node N3. The first capacitor C1 may include a first terminal connected to the first node N1 and a second terminal connected to the third node N3.

[0072] The second capacitor C2 can be connected between the first node N1 and the power line PL. The second capacitor C2 may include a first terminal connected to the first node N1 and a second terminal receiving the first power voltage ELVDD.

[0073] The third transistor T3 can connect the first node N1 to the second node N2 in response to the compensation gate signal GC. The third transistor T3 may include a gate for receiving the compensation gate signal GC, a first terminal connected to the first node N1, and a second terminal connected to the second node N2.

[0074] The fourth transistor T4 may include a gate, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4. The activation voltage level of the signal received by the gate of the fourth transistor T4 may differ from the activation voltage level of the write gate signal GW. The difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor T4 may be less than the difference between the activation voltage level and the deactivation voltage level of the write gate signal GW. In an embodiment, the activation voltage level of the signal received by the gate of the fourth transistor T4 may be higher than the activation voltage level of the write gate signal GW.

[0075] In this embodiment, the fourth transistor T4 can receive the transmitted signal EM. In this case, the fourth transistor T4 can connect the second node N2 to the fourth node N4 in response to the transmitted signal EM. Hereinafter, with reference to... Figures 2 to 8 In the described embodiment, the signal received by the gate of the fourth transistor T4 is the transmit signal EM.

[0076] The fifth transistor T5 can transmit the ground voltage GND to the fourth node N4 in response to the bypass gate signal EB. The fifth transistor T5 may include a gate for receiving the bypass gate signal EB, a first terminal for receiving the ground voltage GND, and a second terminal connected to the fourth node N4.

[0077] The first transistor T1 can be of the same type as the fourth transistor T4. When the first transistor T1 is a p-type transistor, the fourth transistor T4 can also be a p-type transistor, and when the first transistor T1 is an n-type transistor, the fourth transistor T4 can also be an n-type transistor.

[0078] In an embodiment, such as Figure 2 As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be a p-type transistor (e.g., a PMOS transistor). In another embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be an n-type transistor (e.g., an NMOS transistor).

[0079] In an embodiment, such as Figure 2 As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may also include a fourth terminal (e.g., body, block, or substrate) that receives the first power voltage ELVDD.

[0080] The light-emitting element OLED may include a first terminal (e.g., anode) connected to the fourth node N4 and a second terminal (e.g., cathode) receiving a second electrical voltage ELVSS. In embodiments, the light-emitting element OLED may be one of organic light-emitting diodes, inorganic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes.

[0081] The frame period of a pixel PX can include an initialization period P1, a compensation period P2, a write period P3, a bypass period P4, and an emission period P5. During the initialization period P1, the gate of the first transistor T1 is initialized. During the compensation period P2, the threshold voltage of the first transistor T1 is compensated. During the write period P3, the data voltage Vdata is written to the gate of the first transistor T1. During the bypass period P4, the first terminal of the light-emitting element OLED is initialized. During the emission period P5, the light-emitting element OLED emits light.

[0082] The transmit signal EM can have an activation voltage level LVA1 or LVA2 during the initialization period P1, the bypass period P4, and the transmit period P5, and can have a deactivation voltage level LVD during the compensation period P2 and the write period P3.

[0083] The compensation gate signal GC can have an activation voltage level LVA during the initialization period P1 and the compensation period P2, and can have a deactivation voltage level LVD during the write period P3, the bypass period P4 and the transmit period P5.

[0084] The bypass gate signal EB can have an activation voltage level LVA during the initialization period P1, compensation period P2, write period P3 and bypass period P4, and can have a deactivation voltage level LVD during the transmit period P5.

[0085] The write gate signal GW can have an activation voltage level LVA during the initialization period P1, the compensation period P2, and the write period P3, and can have a deactivation voltage level LVD during the bypass period P4 and the transmit period P5.

[0086] In the transmit signal EM, the compensation gate signal GC, the bypass gate signal EB, and the write gate signal GW, the activation voltage level can be a logic low level, while the deactivation voltage level can be a logic high level. Therefore, in the transmit signal EM, the compensation gate signal GC, the bypass gate signal EB, and the write gate signal GW, the activation voltage level can be lower than the deactivation voltage level.

[0087] The activation voltage level LVA of the compensation gate signal GC, the activation voltage level LVA of the bypass gate signal EB, and the activation voltage level LVA of the write gate signal GW can be equal to each other. The deactivation voltage level LVD of the compensation gate signal GC, the deactivation voltage level LVD of the bypass gate signal EB, and the deactivation voltage level LVD of the write gate signal GW can be equal to each other.

[0088] The activation voltage level LVA1 or LVA2 of the transmit signal EM can be different from the activation voltage level LVA of the compensation gate signal GC, the activation voltage level LVA of the bypass gate signal EB, and the activation voltage level LVA of the write gate signal GW. The difference between the activation voltage level LVA1 or LVA2 of the transmit signal EM and the deactivation voltage level LVD can be less than the difference between the activation voltage level LVA and the deactivation voltage level LVD of the compensation gate signal GC, the difference between the activation voltage level LVA and the deactivation voltage level LVD of the bypass gate signal EB, and the difference between the activation voltage level LVA and the deactivation voltage level LVD of the write gate signal GW.

[0089] In this embodiment, the activation voltage level LVA1 or LVA2 of the transmit signal EM can be higher than the activation voltage level LVA of the compensation gate signal GC, the bypass gate signal EB, and the write gate signal GW. For example, the activation voltage levels LVA of the compensation gate signal GC, the bypass gate signal EB, and the write gate signal GW can be approximately -4.7V. The activation voltage level LVA1 or LVA2 of the transmit signal EM can be higher than -4.7V.

[0090] The deactivation voltage level LVD of the transmit signal EM can be equal to the deactivation voltage level LVD of the compensation gate signal GC, the deactivation voltage level LVD of the bypass gate signal EB, and the deactivation voltage level LVD of the write gate signal GW.

[0091] The first activation voltage level LVA1 of the transmit signal EM in the initialization period P1 can be different from the second activation voltage level LVA2 of the transmit signal EM in the bypass period P4 and the transmit period P5. The difference between the first activation voltage level LVA1 and the deactivation voltage level LVD of the transmit signal EM in the initialization period P1 can be greater than the difference between the second activation voltage level LVA2 and the deactivation voltage level LVD of the transmit signal EM in the bypass period P4 and the transmit period P5.

[0092] In this embodiment, the first activation voltage level LVA1 of the transmit signal EM in the initialization period P1 may be lower than the second activation voltage level LVA2 of the transmit signal EM in the bypass period P4 and the transmit period P5. For example, the first activation voltage level LVA1 of the transmit signal EM in the initialization period P1 may be about 0.5V, while the second activation voltage level LVA2 of the transmit signal EM in the bypass period P4 and the transmit period P5 may be about 1.5V to about 1.6V.

[0093] The data signal DS can have a reference voltage Vref during the initialization period P1, the compensation period P2, the bypass period P4, and the transmission period P5, and can have a data voltage Vdata during the write period P3.

[0094] Figure 4 It is used to describe Figure 3 The diagram of the initialization period P1.

[0095] Reference Figure 3 and Figure 4During the initialization period P1, the reference voltage Vref can be applied to the third node N3 via the second transistor T2, which is turned on in response to the activation voltage level LVA of the write gate signal GW. During the initialization period P1, the third transistor T3, which is turned on in response to the activation voltage level LVA of the compensation gate signal GC, the fourth transistor T4, which is turned on in response to the first activation voltage level LVA1 of the transmit signal EM, and the fifth transistor T5, which is turned on in response to the activation voltage level LVA of the bypass gate signal EB, form the first current path CP1 from the first node N1 to the transmission ground voltage GND, and the voltage level of the first node N1 can be reduced. However, since the first activation voltage level LVA1 of the transmit signal EM is relatively high (because the first activation voltage level LVA1 of the transmit signal EM is higher than the activation voltage level LVA of the write gate signal GW, the activation voltage level LVA of the compensation gate signal GC, and the activation voltage level LVA of the bypass gate signal EB), the current flowing through the turned-on fourth transistor T4 can be relatively small, and the current flowing through the first current path CP1 can be relatively small. Therefore, during the initialization period P1, the voltage level of the first node N1 can be higher than the voltage level of the ground voltage GND.

[0096] During the initialization period P1, as the voltage level of the first node N1 decreases, the voltage difference VSG between the first terminal and the gate of the first transistor T1 can become greater than the threshold voltage VTH of the first transistor T1 (see...). Figure 5 And the first transistor T1 can be turned on. Therefore, during the initialization period P1, a second current path CP2 can be formed from the power line PL to the transmission ground voltage GND through the turned-on first transistor T1, the fourth transistor T4 which is turned on in response to the first activation voltage level LVA1 of the transmit signal EM, and the fifth transistor T5 which is turned on in response to the activation voltage level LVA of the bypass gate signal EB, and the short-circuit path current ISP can flow through the second current path CP2. However, since the voltage difference VSG between the first terminal and the gate of the first transistor T1 is relatively small (because the voltage level of the first node N1 is higher than the voltage level of the ground voltage GND), the current flowing through the turned-on first transistor T1 can be relatively small, and the short-circuit path current ISP flowing through the second current path CP2 can be relatively small.

[0097] Figure 5 It is used to describe Figure 3 The graph shows the compensation period P2.

[0098] Reference Figure 3 and Figure 5During compensation period P2, the reference voltage Vref can be applied to the third node N3 via the second transistor T2, which is turned on in response to the activation voltage level LVA of the write gate signal GW. During compensation period P2, a current path from the power line PL to the first node N1 can be formed by the turned-on first transistor T1 and the third transistor T3, which is turned on in response to the activation voltage level LVA of the compensation gate signal GC, and the voltage level of the first node N1 can increase until the first transistor T1 is turned off (until the voltage difference VSG between the first terminal and the gate of the first transistor T1 becomes equal to the threshold voltage VTH of the first transistor T1). Therefore, during compensation period P2, the voltage of the first node N1 can be equal to the value ELVDD-VTH obtained by subtracting the threshold voltage VTH of the first transistor T1 from the first power voltage ELVDD. During compensation period P2, the ground voltage GND can be applied to the fourth node N4 via the fifth transistor T5, which is turned on in response to the activation voltage level LVA of the bypass gate signal EB. The threshold voltage VTH of the first transistor T1 can be compensated during compensation period P2 using a diode connection scheme.

[0099] Figure 6 It is used to describe Figure 3 The graph shows the write time period P3.

[0100] Reference Figure 3 and Figure 6 During the write phase P3, the data voltage Vdata can be applied to the third node N3 through the second transistor T2, which is turned on in response to the activation voltage level LVA of the write gate signal GW. Therefore, the voltage of the third node N3 can change from the reference voltage Vref to the data voltage Vdata. During the write phase P3, due to the coupling effect of the first capacitor C1, the voltage VN1 of the first node N1 can be calculated using mathematical formula 1.

[0101] [Mathematical Formula 1]

[0102] The gate voltage of the first transistor T1 can be equal to the voltage VN1 of the first node N1 calculated by mathematical formula 1, therefore the first transistor T1 can be turned on during the write period P3. During the write period P3, the ground voltage GND can be applied to the fourth node N4 by the fifth transistor T5, which is turned on in response to the activation voltage level LVA of the bypass gate signal EB.

[0103] Figure 7 It is used to describe Figure 3 The bypass period P4 diagram.

[0104] Reference Figure 3 and Figure 7During the bypass period P4, a current path from the power line PL to the transmission ground voltage GND can be formed by the first transistor T1, the fourth transistor T4 which is turned on in response to the second activation voltage level LVA2 of the emission signal EM, and the fifth transistor T5 which is turned on in response to the activation voltage level LVA of the bypass gate signal EB. Current can flow through this current path. Since the second activation voltage level LVA2 of the emission signal EM in the bypass period P4 is higher than the first activation voltage level LVA1 of the emission signal EM in the initialization period P1, the current flowing through the current path in the bypass period P4 can be less than the short-circuit path current ISP flowing through the second current path CP2 in the initialization period P1. During the bypass period P4, the charge stored in the fourth node N4 due to the parasitic capacitance of the OLED can be discharged to the transmission ground voltage GND, thus improving the black level representation capability of the OLED.

[0105] Figure 8 It is used to describe Figure 3 The image shows the launch time P5.

[0106] Reference Figure 3 and Figure 8 During the emission period P5, a current path is formed from the power line PL to the line transmitting the second power voltage ELVSS through the first transistor T1, the fourth transistor T4 which is turned on in response to the second activation voltage level LVA2 of the emission signal EM, and the light-emitting element OLED. The driving current IOLED can flow through this current path. Since the second activation voltage level LVA2 of the emission signal EM in emission period P5 is higher than the first activation voltage level LVA1 of the emission signal EM in initialization period P1, the driving current IOLED flowing through the current path in emission period P5 can be less than the short-circuit path current ISP flowing through the second current path CP2 in initialization period P1. During emission period P5, the light-emitting element OLED can emit light with a brightness corresponding to the driving current IOLED. The driving current IOLED can be calculated using mathematical formula 2 during emission period P5.

[0107] [Mathematical Formula 2]

[0108] In mathematical formula 2, K is a proportionality constant. According to mathematical formula 2, the driving current IOLED can be determined by the data voltage Vdata, and is independent of the threshold voltage VTH of the first transistor T1, and during the emission period P5, the light-emitting element OLED can emit light with a brightness corresponding to the data voltage Vdata.

[0109] Figure 9This is a timing diagram showing the transmitted signal EM according to the prior art. Figure 10 This is a timing diagram showing the transmitted signal EM, the voltage of the first node N1, and the short-circuit path current ISP during the initialization period P1.

[0110] Reference Figure 3 , Figure 4 , Figure 9 and Figure 10 In the prior art, the activation voltage level LVA of the transmit signal EM can be equal to the activation voltage level LVA of the compensation gate signal GC, the activation voltage level LVA of the bypass gate signal EB, and the activation voltage level LVA of the write gate signal GW. During the initialization period P1 in the prior art, a first current path CP1 from the first node N1 to the transmission ground voltage GND can be formed by a third transistor T3 that is turned on in response to the activation voltage level LVA of the compensation gate signal GC, a fourth transistor T4 that is turned on in response to the activation voltage level LVA of the transmit signal EM, and a fifth transistor T5 that is turned on in response to the activation voltage level LVA of the bypass gate signal EB, and the voltage level of the first node N1 can be reduced. In the prior art, because the activation voltage level LVA of the transmit signal EM is relatively low (since the activation voltage level LVA of the transmit signal EM is equal to the activation voltage level LVA of the write gate signal GW, the activation voltage level LVA of the compensation gate signal GC, and the activation voltage level LVA of the bypass gate signal EB), the current flowing through the conducting fourth transistor T4 can be relatively large, and the current flowing through the first current path CP1 can also be relatively large. Therefore, during the initialization period P1 in the prior art, the voltage level of the first node N1 can be equal to the voltage level of the ground voltage GND.

[0111] In the initialization period P1 of the prior art, as the voltage level of the first node N1 becomes equal to the voltage level of the ground voltage GND, the voltage difference VSG between the first terminal and the gate of the first transistor T1 can become greater than the threshold voltage VTH of the first transistor T1, and the first transistor T1 can be turned on. Therefore, in the initialization period P1 of the prior art, a second current path CP2 from the power line PL to the line transmitting the ground voltage GND can be formed by the turned-on first transistor T1, the fourth transistor T4 which is turned on in response to the activation voltage level LVA of the transmit signal EM, and the fifth transistor T5 which is turned on in response to the activation voltage level LVA of the bypass gate signal EB, and the short-circuit path current ISP can flow through the second current path CP2. In the prior art, since the voltage difference VSG between the first terminal and the gate of the first transistor T1 is relatively large (since the voltage level of the first node N1 is equal to the voltage level of the ground voltage GND), the current flowing through the turned-on first transistor T1 can be relatively large, and the short-circuit path current ISP flowing through the second current path CP2 can be relatively large. When the short-circuit path current ISP is large, ripple may occur in the first power voltage ELVDD. When ripple occurs in the first power voltage ELVDD during the compensation period P2, it may take a relatively long time to recover the first power voltage ELVDD, which may increase the length of the compensation period P2, potentially hindering high-speed driving of the display device. Furthermore, when the short-circuit path current ISP is large, the voltage of the fourth node N4 may increase, potentially reducing the black level of the OLED element and degrading the contrast of the display device.

[0112] In embodiments of this disclosure, since the activation voltage level LVA1 or LVA2 of the transmit signal EM is higher than the activation voltage level LVA of the compensation gate signal GC, the activation voltage level LVA of the bypass gate signal EB, and the activation voltage level LVA of the write gate signal GW, the voltage level of the first node N1 can be higher than the voltage level of the ground voltage GND during the initialization period P1. Therefore, since the short-circuit path current ISP is relatively small, this can be advantageous for high-speed driving of the display device 100 and can improve the contrast of the display device 100.

[0113] Figure 11 This is a block diagram illustrating a display device 101 according to an embodiment.

[0114] Reference Figure 11 The display device 101 may include a display panel 110, a gate driver 120, a transmit driver 131, a data driver 140, and a controller 150. References will be omitted. Figure 11 The described display device 101 and reference Figure 1The description includes components that are substantially the same as or similar to those of the components of the display device 100.

[0115] The display panel 110 may include pixels PX. Each pixel PX may emit light based on a write gate signal GW, a compensation gate signal GC, a first transmit signal EM1, a second transmit signal EM2, a bypass gate signal EB, and a data signal DS. (See reference...) Figures 11 to 13 The first transmitted signal EM1 described can be compared with the reference. Figures 1 to 3 The transmitted signal EM described is the same.

[0116] The transmit driver 131 can provide a first transmit signal EM1, a second transmit signal EM2, and a bypass gate signal EB to each of the pixels PX. The transmit driver 131 can generate the first transmit signal EM1, the second transmit signal EM2, and the bypass gate signal EB based on the pixel row. The transmit driver 131 can also generate the first transmit signal EM1, the second transmit signal EM2, and the bypass gate signal EB based on a second control signal CNT2. The second control signal CNT2 may include a first transmit start signal, a second transmit start signal, a bypass gate start signal, a transmit clock signal, etc.

[0117] Figure 12 It is shown Figure 11 A circuit diagram of an example pixel PX. Figure 13 It is shown Figure 12 Timing diagrams for signals EM2, EM1, GC, EB, GW, and DS.

[0118] Reference Figure 12 and Figure 13 Pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a light-emitting element OLED. References will be omitted. Figure 12 and Figure 13 The described pixel PX and reference Figure 2 and Figure 3 The description of the components of the pixel PX is essentially the same as or similar to the components of the pixel PX.

[0119] The first transistor T1 may include a gate connected to the first node N1, a first terminal receiving a first power voltage ELVDD, and a second terminal connected to the second node N2. The first terminal of the first transistor T1 may be connected to the power line PL via a sixth transistor T6.

[0120] The fourth transistor T4 can connect the second node N2 to the fourth node N4 in response to the first transmit signal EM1. The fourth transistor T4 may include a gate for receiving the first transmit signal EM1, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4.

[0121] The sixth transistor T6 can transmit the first power voltage ELVDD to the first terminal of the first transistor T1 in response to the second transmit signal EM2. The sixth transistor T6 may include a gate for receiving the second transmit signal EM2, a first terminal for receiving the first power voltage ELVDD, and a second terminal connected to the first terminal of the first transistor T1.

[0122] In an embodiment, such as Figure 12 As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a p-type transistor (e.g., a PMOS transistor). In an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be an n-type transistor (e.g., an NMOS transistor).

[0123] The second transmit signal EM2 can have an activation voltage level LVA during the compensation period P2, bypass period P4, and transmit period P5, and a deactivation voltage level LVD during the initialization period P1 and write period P3. The activation voltage level LVA of the second transmit signal EM2 can be logic low, while the deactivation voltage level LVD can be logic high. Therefore, the activation voltage level LVA of the second transmit signal EM2 can be lower than its deactivation voltage level LVD. The activation voltage level LVA of the second transmit signal EM2 can be equal to the activation voltage level LVA of the compensation gate signal GC, the bypass gate signal EB, and the write gate signal GW. The deactivation voltage level LVD of the second transmit signal EM2 can be equal to the deactivation voltage level LVD of the first transmit signal EM1, the compensation gate signal GC, the bypass gate signal EB, and the write gate signal GW.

[0124] Figure 14 This is a block diagram illustrating a display device 102 according to an embodiment.

[0125] Reference Figure 14 The display device 102 may include a display panel 110, a gate driver 122, a transmit driver 131, a data driver 140, and a controller 150. References will be omitted. Figure 14 The described display device 102 and reference Figure 1 The described display device 100 and / or reference Figure 11 The description includes components that are substantially the same as or similar to those of the display device 101.

[0126] The display panel 110 may include pixels PX. Each of the pixels PX may emit light based on a write gate signal GW, a first transmit signal EM1, a second transmit signal EM2, a bypass gate signal EB, and a data signal DS.

[0127] Gate driver 122 can provide a write gate signal GW to each of the pixels PX. Gate driver 122 can generate the write gate signal GW based on the pixel row. Gate driver 122 can generate the write gate signal GW based on a first control signal CNT1. The first control signal CNT1 may include a write gate start signal, a gate clock signal, etc.

[0128] Figure 15 It is shown Figure 14 A circuit diagram of an example pixel PX. Figure 16 It is shown Figure 15 Timing diagrams for signals EM2, EM1, EB, GW, and DS.

[0129] Reference Figure 15 and Figure 16 Pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a light-emitting element OLED. References will be omitted. Figure 15 and Figure 16 The described pixel PX and reference Figure 2 and Figure 3 The described pixel PX and / or reference Figure 12 and Figure 13 The description of the components of the pixel PX is essentially the same as or similar to the components of the pixel PX.

[0130] The first transistor T1 may include a gate connected to the first node N1, a first terminal connected to the second node N2, and a second terminal connected to the third node N3.

[0131] The second transistor T2 can transmit the data signal DS to the first node N1 in response to the write gate signal GW. The second transistor T2 may include a gate for receiving the write gate signal GW, a first terminal for receiving the data signal DS, and a second terminal connected to the first node N1.

[0132] A first capacitor C1 may be connected between a first node N1 and a second node N2. The first capacitor C1 may include a first terminal connected to the first node N1 and a second terminal connected to the second node N2.

[0133] The second capacitor C2 can be connected between the second node N2 and the power line PL. The second capacitor C2 may include a first terminal connected to the second node N2 and a second terminal receiving the first power voltage ELVDD.

[0134] The fourth transistor T4 can connect the third node N3 to the fourth node N4 in response to the first transmit signal EM1. The fourth transistor T4 may include a gate for receiving the first transmit signal EM1, a first terminal connected to the third node N3, and a second terminal connected to the fourth node N4.

[0135] The sixth transistor T6 can transmit the first power voltage ELVDD to the second node N2 in response to the second transmit signal EM2. The sixth transistor T6 may include a gate for receiving the second transmit signal EM2, a first terminal for receiving the first power voltage ELVDD, and a second terminal connected to the second node N2.

[0136] In an embodiment, such as Figure 15 As shown, each of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a p-type transistor (e.g., a PMOS transistor). In an embodiment, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be an n-type transistor (e.g., an NMOS transistor).

[0137] The second transmit signal EM2 can have an activation voltage level LVA during the initialization period P1, compensation period P2, bypass period P4 and transmit period P5, and can have a deactivation voltage level LVD during the write period P3.

[0138] The first transmit signal EM1 can have a deactivation voltage level LVD during the initialization period P1, and can have an activation voltage level LVA1 or LVA2 during the compensation period P2, the write period P3, the bypass period P4, and the transmit period P5.

[0139] The first activation voltage level LVA1 of the first transmit signal EM1 in the compensation period P2 and the write period P3 can be different from the second activation voltage level LVA2 of the first transmit signal EM1 in the bypass period P4 and the transmit period P5. The difference between the first activation voltage level LVA1 and the deactivation voltage level LVD of the first transmit signal EM1 in the compensation period P2 and the write period P3 can be greater than the difference between the second activation voltage level LVA2 and the deactivation voltage level LVD of the first transmit signal EM1 in the bypass period P4 and the transmit period P5.

[0140] In an embodiment, the first activation voltage level LVA1 of the first transmit signal EM1 in the compensation period P2 and the write period P3 can be lower than the second activation voltage level LVA2 of the first transmit signal EM1 in the bypass period P4 and the transmit period P5.

[0141] During the initialization period P1, the reference voltage Vref can be applied to the first node N1 by the second transistor T2, which is turned on in response to the activation voltage level LVA of the write gate signal GW.

[0142] During compensation period P2, the reference voltage Vref can be applied to the first node N1 via the second transistor T2, which is turned on in response to the activation voltage level LVA of the write gate signal GW. During compensation period P2, a current path from the power line PL to the transmission ground voltage GND can be formed by the sixth transistor T6 (turned on in response to the activation voltage level LVA of the second transmit signal EM2), the first transistor T1 (turned on), the fourth transistor T4 (turned on in response to the first activation voltage level LVA1 of the first transmit signal EM1), and the fifth transistor T5 (turned on in response to the activation voltage level LVA of the bypass gate signal EB). The voltage level of the second node N2 can increase until the first transistor T1 is turned off (until the voltage difference VSG between the first terminal and the gate of the first transistor T1 becomes equal to the threshold voltage VTH of the first transistor T1). Therefore, during compensation period P2, the threshold voltage VTH of the first transistor T1 can be stored in the first capacitor C1. The threshold voltage VTH of the first transistor T1 can be compensated during compensation period P2 using a source follower scheme.

[0143] During the write phase P3, the data voltage Vdata can be applied to the first node N1 by the second transistor T2, which is turned on in response to the activation voltage level LVA of the write gate signal GW.

[0144] During the bypass period P4, a current path from the power line PL to the transmission ground voltage GND can be formed by the sixth transistor T6, which is turned on in response to the activation voltage level LVA of the second transmission signal EM2, the first transistor T1, the fourth transistor T4, which is turned on in response to the second activation voltage level LVA2 of the first transmission signal EM1, and the fifth transistor T5, which is turned on in response to the activation voltage level LVA of the bypass gate signal EB, and current can flow through the current path.

[0145] During the emission period P5, a current path is formed from the power line PL to the line transmitting the second power voltage ELVSS by the sixth transistor T6, which is turned on in response to the activation voltage level LVA of the second emission signal EM2, the first transistor T1, the fourth transistor T4, which is turned on in response to the second activation voltage level LVA2 of the first emission signal EM1, and the light-emitting element OLED, and a driving current can flow through the current path. During the emission period P5, the light-emitting element OLED can emit light with a brightness corresponding to the driving current. The driving current can be determined by the data voltage Vdata, and is independent of the threshold voltage VTH of the first transistor T1, and during the emission period P5, the light-emitting element OLED can emit light with a brightness corresponding to the data voltage Vdata.

[0146] Figure 17 This is a block diagram illustrating a display device 103 according to an embodiment.

[0147] Reference Figure 17 The display device 103 may include a display panel 113, a gate driver 120, a transmit driver 133, a data driver 143, and a controller 150. References will be omitted. Figure 17 The described display device 103 and reference Figure 1 The description includes components that are substantially the same as or similar to those of the components of the display device 100.

[0148] Display panel 113 may include red pixels PX_R, green pixels PX_G, and blue pixels PX_B. Each of the red pixels PX_R may emit light based on a write gate signal GW, a compensation gate signal GC, a red emit signal EM_R, a bypass gate signal EB, and a red data signal DS_R. Each of the green pixels PX_G may emit light based on a write gate signal GW, a compensation gate signal GC, a green emit signal EM_G, a bypass gate signal EB, and a green data signal DS_G. Each of the blue pixels PX_B may emit light based on a write gate signal GW, a compensation gate signal GC, a blue emit signal EM_B, a bypass gate signal EB, and a blue data signal DS_B.

[0149] The transmit driver 133 can provide a red transmit signal EM_R and a bypass gate signal EB to each of the red pixels PX_R, a green transmit signal EM_R and a bypass gate signal EB to each of the green pixels PX_G, and a blue transmit signal EM_B and a bypass gate signal EB to each of the blue pixels PX_B. The transmit driver 133 can generate the red transmit signal EM_R, the green transmit signal EM_G, the blue transmit signal EM_B, and the bypass gate signal EB based on a second control signal CNT2. The second control signal CNT2 may include a red transmit start signal, a green transmit start signal, a blue transmit start signal, a bypass gate start signal, a transmit clock signal, etc.

[0150] The data driver 143 can provide a red data signal DS_R to each of the red pixels PX_R, a green data signal DS_G to each of the green pixels PX_G, and a blue data signal DS_B to each of the blue pixels PX_B. The data driver 143 can generate the red data signal DS_R, the green data signal DS_G, and the blue data signal DS_B based on the output image data IMD2 and the third control signal CNT3.

[0151] Figure 18 It is shown Figure 17 Circuit diagrams for examples of pixels PX_R, PX_G, and PX_B. Figure 19 It is shown Figure 18 Timing diagrams for signals EM_R, EM_G, and EM_B.

[0152] Reference Figure 18 and Figure 19 Each of the red pixel PX_R, green pixel PX_G, and blue pixel PX_B may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a light-emitting element OLED. (References omitted) Figure 18 and Figure 19 The description of each of the red pixel PX_R, green pixel PX_G, and blue pixel PX_B with reference Figure 2 and Figure 3 The description of the components of the pixel PX is essentially the same as or similar to the components of the pixel PX.

[0153] The second transistor T2 of the red pixel PX_R can transmit the red data signal DS_R to the third node N3 in response to the write gate signal GW. The second transistor T2 of the red pixel PX_R may include a gate for receiving the write gate signal GW, a first terminal for receiving the red data signal DS_R, and a second terminal connected to the third node N3.

[0154] The second transistor T2 of the green pixel PX_G can transmit the green data signal DS_G to the third node N3 in response to the write gate signal GW. The second transistor T2 of the green pixel PX_G may include a gate for receiving the write gate signal GW, a first terminal for receiving the green data signal DS_G, and a second terminal connected to the third node N3.

[0155] The second transistor T2 of the blue pixel PX_B can transmit the blue data signal DS_B to the third node N3 in response to the write gate signal GW. The second transistor T2 of the blue pixel PX_B may include a gate for receiving the write gate signal GW, a first terminal for receiving the blue data signal DS_B, and a second terminal connected to the third node N3.

[0156] The fourth transistor T4 of the red pixel PX_R can connect the second node N2 to the fourth node N4 in response to the red emission signal EM_R. The fourth transistor T4 of the red pixel PX_R may include a gate for receiving the red emission signal EM_R, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4.

[0157] The fourth transistor T4 of the green pixel PX_G can connect the second node N2 to the fourth node N4 in response to the green emission signal EM_G. The fourth transistor T4 of the green pixel PX_G may include a gate for receiving the green emission signal EM_G, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4.

[0158] The fourth transistor T4 of the blue pixel PX_B can connect the second node N2 to the fourth node N4 in response to the blue emission signal EM_B. The fourth transistor T4 of the blue pixel PX_B may include a gate for receiving the blue emission signal EM_B, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4.

[0159] The red transmit signal EM_R can have an activation voltage level LVA1_R or LVA2_R during the initialization period P1, bypass period P4, and transmit period P5, and a deactivation voltage level LVD during the compensation period P2 and write period P3. The green transmit signal EM_G can have an activation voltage level LVA1_G or LVA2_G during the initialization period P1, bypass period P4, and transmit period P5, and a deactivation voltage level LVD during the compensation period P2 and write period P3. The blue transmit signal EM_B can have an activation voltage level LVA1_B or LVA2_B during the initialization period P1, bypass period P4, and transmit period P5, and a deactivation voltage level LVD during the compensation period P2 and write period P3.

[0160] The activation voltage levels LVA1_R or LVA2_R of the red emission signal EM_R, LVA1_G or LVA2_G of the green emission signal EM_G, and LVA1_B or LVA2_B of the blue emission signal EM_B can be different from each other. Since the efficiency and threshold voltage characteristics of the OLED light-emitting element differ in the red pixel PX_R, green pixel PX_G, and blue pixel PX_B, red emission signals EM_R, green emission signals EM_G, and blue emission signals EM_B with different activation voltage levels can be provided to the red pixel PX_R, green pixel PX_G, and blue pixel PX_B, respectively. For example, during the emission period P5, red emission signals EM_R, green emission signals EM_G, and blue emission signals EM_B with different second activation voltage levels LVA2_R, LVA2_G, and LVA2_B can be provided to red pixel PX_R, green pixel PX_G, and blue pixel PX_B, respectively, so that the brightness uniformity and lifetime balance among red pixel PX_R, green pixel PX_G, and blue pixel PX_B can be optimized.

[0161] Figure 20 It is shown Figure 1 A circuit diagram of an example pixel PX. Figure 21 It is shown Figure 20 Timing diagrams of the EM and VEM signals.

[0162] Reference Figure 20 and Figure 21 Pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a light-emitting element OLED. References will be omitted. Figure 20 and Figure 21 The described pixel PX and reference Figure 2 and Figure 3 The description of the components of the pixel PX is essentially the same as or similar to the components of the pixel PX.

[0163] The fourth transistor T4 may include a fourth-first transistor T4-1 and a fourth-second transistor T4-2. The fourth-first transistor T4-1 may include a gate for receiving a bias voltage VEM, a first terminal connected to a second terminal of the second node N2, and a second terminal connected to the fourth node N4. The fourth-second transistor T4-2 may include a gate for receiving a transmit signal EM, a first terminal connected to the second terminal of the fourth-first transistor T4-1, and a second terminal connected to the fourth node N4.

[0164] The transmit signal EM can have an activation voltage level LVA during the initialization period P1, the bypass period P4, and the transmit period P5, and can have a deactivation voltage level LVD during the compensation period P2 and the write period P3. The activation voltage level LVA of the transmit signal EM can be equal to the activation voltage level of the compensation gate signal GC, the activation voltage level of the bypass gate signal EB, and the activation voltage level of the write gate signal GW.

[0165] The bias voltage VEM can have a first activation voltage level LVA1 during the initialization period P1, compensation period P2, write period P3, bypass period P4, and transmit period P5. In an embodiment, the bias voltage VEM can be a constant voltage.

[0166] The first activation voltage level LVA1 of the bias voltage VEM can be a logic low level. The first activation voltage level LVA1 of the bias voltage VEM can be different from the activation voltage level LVA of the transmit signal EM. In an embodiment, the first activation voltage level LVA1 of the bias voltage VEM can be higher than the activation voltage level LVA of the transmit signal EM.

[0167] In reference Figure 20 and Figure 21 In the described embodiment, the fourth transistor T4 can be formed as a stacked cascode structure including a fourth-first transistor T4-1 and a fourth-second transistor T4-2. A bias voltage VEM, as a constant voltage, can be applied to the gate of the fourth-first transistor T4-1, enabling the fourth-first transistor T4-1 to perform the cascode function. An emission signal EM, as a switching signal, can be applied to the gate of the fourth-second transistor T4-2, enabling the fourth-second transistor T4-2 to control the emission time of the light-emitting element OLED.

[0168] Figure 22 This is a block diagram illustrating a display device 104 according to an embodiment.

[0169] Reference Figure 22 The display device 104 may include a display panel 110, a gate driver 120, a transmit driver 134, a data driver 140, and a controller 150. References will be omitted. Figure 22 The described display device 104 and reference Figure 1 The description includes components that are substantially the same as or similar to those of the components of the display device 100.

[0170] The display panel 110 may include pixels PX. Each of the pixels PX may emit light based on a write gate signal GW, a compensation gate signal GC, a first transmit signal EM1, a second transmit signal EM2, a third transmit signal EM3, a bypass gate signal EB, and a data signal DS.

[0171] The transmit driver 134 can provide a first transmit signal EM1, a second transmit signal EM2, a third transmit signal EM3, and a bypass gate signal EB to each of the pixels PX. The transmit driver 134 can generate the first transmit signal EM1, the second transmit signal EM2, the third transmit signal EM3, and the bypass gate signal EB based on the pixel row. The transmit driver 134 can also generate the first transmit signal EM1, the second transmit signal EM2, the third transmit signal EM3, and the bypass gate signal EB based on a second control signal CNT2. The second control signal CNT2 may include a first transmit start signal, a second transmit start signal, a third transmit start signal, a bypass gate start signal, a transmit clock signal, etc.

[0172] Figure 23 It is shown Figure 22 A circuit diagram of an example pixel PX. Figure 24 It is shown Figure 23 Timing diagrams for signals EM1, EM2, EM3, VEM1, VEM2, and VEM3.

[0173] Reference Figure 23 and Figure 24 Pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a seventh-first transistor T7-1, a seventh-second transistor T7-2, a seventh-third transistor T7-3, and a light-emitting element OLED. References will be omitted. Figure 23 and Figure 24 The described pixel PX and reference Figure 2 and Figure 3 The description of the components of the pixel PX is essentially the same as or similar to the components of the pixel PX.

[0174] The fourth transistor T4 may include a gate, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4.

[0175] The seventh-first transistor T7-1 can transmit a first bias voltage VEM1 to the gate of the fourth transistor T4 in response to the first transmit signal EM1. The seventh-first transistor T7-1 may include a gate for receiving the first transmit signal EM1, a first terminal for receiving the first bias voltage VEM1, and a second terminal connected to the gate of the fourth transistor T4.

[0176] The seventh-second transistor T7-2 can transmit a second bias voltage VEM2 to the gate of the fourth transistor T4 in response to the second transmit signal EM2. The seventh-second transistor T7-2 may include a gate for receiving the second transmit signal EM2, a first terminal for receiving the second bias voltage VEM2, and a second terminal connected to the gate of the fourth transistor T4.

[0177] The seventh-third transistor T7-3 can transmit a third bias voltage VEM3 to the gate of the fourth transistor T4 in response to the third transmit signal EM3. The seventh-third transistor T7-3 may include a gate for receiving the third transmit signal EM3, a first terminal for receiving the third bias voltage VEM3, and a second terminal connected to the gate of the fourth transistor T4.

[0178] The first transmit signal EM1 can have an activation voltage level LVA during the initialization period P1, and a deactivation voltage level LVD during the compensation period P2, write period P3, bypass period P4, and transmit period P5. The second transmit signal EM2 can have a deactivation voltage level LVD during the initialization period P1, compensation period P2, and write period P3, and an activation voltage level LVA during the bypass period P4 and transmit period P5. The third transmit signal EM3 can have a deactivation voltage level LVD during the initialization period P1, bypass period P4, and transmit period P5, and an activation voltage level LVA during the compensation period P2 and write period P3.

[0179] The activation voltage level LVA of each of the first transmit signal EM1, the second transmit signal EM2, and the third transmit signal EM3 can be equal to the activation voltage level of the compensation gate signal GC, the activation voltage level of the bypass gate signal GB, and the activation voltage level of the write gate signal GW. The deactivation voltage level LVD of each of the first transmit signal EM1, the second transmit signal EM2, and the third transmit signal EM3 can be equal to the deactivation voltage level of the compensation gate signal GC, the deactivation voltage level of the bypass gate signal GB, and the deactivation voltage level of the write gate signal GW.

[0180] The first bias voltage VEM1 may have a first activation voltage level LVA1 during the initialization period P1, compensation period P2, write period P3, bypass period P4, and transmit period P5; the second bias voltage VEM2 may have a second activation voltage level LVA2 during the initialization period P1, compensation period P2, write period P3, bypass period P4, and transmit period P5; and the third bias voltage VEM3 may have a deactivation voltage level LVD during the initialization period P1, compensation period P2, write period P3, bypass period P4, and transmit period P5. In an embodiment, each of the first bias voltage VEM1, the second bias voltage VEM2, and the third bias voltage VEM3 may be a constant voltage.

[0181] Each of the first activation voltage level LVA1 of the first bias voltage VEM1 and the second activation voltage level LVA2 of the second bias voltage VEM2 can be a logic low level, while the deactivation voltage level LVD of the third bias voltage VEM3 can be a logic high level. The first activation voltage level LVA1 of the first bias voltage VEM1 and the second activation voltage level LVA2 of the second bias voltage VEM2 can be different from the activation voltage level LVA of each of the first transmit signal EM1, the second transmit signal EM2, and the third transmit signal EM3. In an embodiment, the first activation voltage level LVA1 of the first bias voltage VEM1 and the second activation voltage level LVA2 of the second bias voltage VEM2 can be higher than the activation voltage level LVA of each of the first transmit signal EM1, the second transmit signal EM2, and the third transmit signal EM3.

[0182] The first activation voltage level LVA1 of the first bias voltage VEM1 and the second activation voltage level LVA2 of the second bias voltage VEM2 can be different from each other. Figure 24 An embodiment is shown in which the first activation voltage level LVA1 of the first bias voltage VEM1 is lower than the second activation voltage level LVA2 of the second bias voltage VEM2; however, this disclosure is not limited thereto. In another embodiment, the first activation voltage level LVA1 of the first bias voltage VEM1 may be higher than the second activation voltage level LVA2 of the second bias voltage VEM2.

[0183] In reference Figures 22 to 24 In the described embodiment, the lines transmitting the first bias voltage VEM1, the second bias voltage VEM2, and the third bias voltage VEM3 can be connected to the gate of the fourth transistor T4 via the seventh-first transistor T7-1, the seventh-second transistor T7-2, and the seventh-third transistor T7-3. Therefore, voltage drops in the bias voltages VEM1, VEM2, or VEM3 can be prevented, and voltage uniformity between pixels PX can be improved.

[0184] Figure 25 It is shown Figure 1 A circuit diagram of an example pixel PX. Figure 26 It is shown Figure 25 The timing diagram of the signal EM.

[0185] Reference Figure 25 and Figure 26 Pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, and a light-emitting element OLED. (References omitted) Figure 25 and Figure 26 The described pixel PX and reference Figure 2 and Figure 3 The description of the components of the pixel PX is essentially the same as or similar to the components of the pixel PX.

[0186] The fourth transistor T4 may include a gate, a first terminal connected to the second node N2, and a second terminal connected to the fourth node N4.

[0187] The seventh transistor T7 can connect the first node N1, the third node N3, or the fourth node N4 to the gate of the fourth transistor T4 in response to the transmitted signal EM. The seventh transistor T7 may include a gate for receiving the transmitted signal EM, a first terminal connected to the first node N1, the third node N3, or the fourth node N4, and a second terminal connected to the gate of the fourth transistor T4.

[0188] The transmit signal EM can have an activation voltage level LVA during the initialization period P1, the bypass period P4, and the transmit period P5, and can have a deactivation voltage level LVD during the compensation period P2 and the write period P3. The activation voltage level LVA of the transmit signal EM can be equal to the activation voltage level of the compensation gate signal GC, the activation voltage level of the bypass gate signal GB, and the activation voltage level of the write gate signal GW.

[0189] The first node N1, the third node N3, or the fourth node N4 can have an activation voltage level during the initialization period P1, the bypass period P4, and the transmission period P5.

[0190] The activation voltage level of the first node N1, the third node N3, or the fourth node N4 can be a logic low level. The activation voltage level of the first node N1, the third node N3, or the fourth node N4 can be different from the activation voltage level LVA of the transmitted signal EM. In an embodiment, the activation voltage level of the first node N1, the third node N3, or the fourth node N4 can be higher than the activation voltage level LVA of the transmitted signal EM.

[0191] In reference Figure 25 and Figure 26In the described embodiment, the voltage of the first node N1, the third node N3, or the fourth node N4 in the pixel PX can be applied to the gate of the fourth transistor T4 without providing voltage from outside the pixel PX.

[0192] Figure 27 This is a block diagram illustrating an electronic device 10 according to an embodiment.

[0193] Reference Figure 27 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0194] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor, and a controller.

[0195] Memory 13 can store data necessary for the operation of processor 12 or display module 11. When processor 12 executes an application stored in memory 13, Figure 1 , Figure 11 , Figure 14 , Figure 17 and Figure 22 Input image data IMD1 and Figure 1 , Figure 11 , Figure 14 , Figure 17 and Figure 22 The control signal CNT0 can be transmitted to the display module 11, and the display module 11 can output image information based on the input image data IMD1 and the control signal CNT0.

[0196] The power module 14 may include a power module such as a power adapter, a battery device, etc., and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0197] According to the above embodiments, at least one of the components of the electronic device 10 may be included in Figure 1 Display device 100 Figure 11 Display device 101, Figure 14 Display device 102, Figure 17 The display device 103 or Figure 22The display device 104 is included. Furthermore, some of the various modules functionally included in a single module may be included in display devices 100, 101, 102, 103, or 104, while other modules may be separately arranged from display devices 100, 101, 102, 103, or 104. For example, display devices 100, 101, 102, 103, or 104 may include display module 11, and processor 12, memory 13, and power module 14 may be arranged within electronic device 10 in the form of other devices besides display devices 100, 101, 102, 103, or 104.

[0198] Figure 28 This is a diagram illustrating an electronic device according to an embodiment.

[0199] Reference Figure 28 The electronic devices that utilize the display device according to the embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, and vehicle electronic devices 10_3 including display modules such as car dashboards, central instrument panels, central information displays (CID) arranged on the dashboard, and interior mirror displays.

[0200] The display device according to the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, smartwatches, PMPs, PDAs, MP3 players, etc.

[0201] Although the display device, pixel, and electronic device according to embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the claims.

Claims

1. A display device, the display device comprising: Display panel, including pixels; A gate driver provides write gate signals and compensation gate signals to each pixel in the pixel; A transmitter driver that provides a transmitter signal to each of the pixels; as well as The data driver provides data signals to each of the pixels. Each pixel in the pixel includes: The first transistor includes a gate connected to a first node, a first terminal receiving a first electrical voltage, and a second terminal connected to a second node; The second transistor transmits the data signal to the third node in response to the write gate signal; A first capacitor is connected between the first node and the third node; A third transistor connects the first node to the second node in response to the compensation gate signal; The fourth transistor includes a gate, a first terminal connected to the second node, and a second terminal connected to the fourth node; and The light-emitting element includes a first terminal connected to the fourth node and a second terminal receiving a second electrical voltage. The activation voltage level of the signal received by the gate of the fourth transistor is different from the activation voltage level of the write gate signal.

2. The display device according to claim 1, wherein, The difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor is less than the difference between the activation voltage level and the deactivation voltage level of the write gate signal.

3. The display device according to claim 1, wherein, The activation voltage level of the signal received by the gate of the fourth transistor is higher than the activation voltage level of the write gate signal.

4. The display device according to claim 1, wherein, The activation voltage level of the signal received by the gate of the fourth transistor during the initialization period when the gate of the first transistor is initialized is different from the activation voltage level of the signal received by the gate of the fourth transistor during the emission period when the light-emitting element emits light.

5. The display device according to claim 4, wherein, The difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor during the initialization period is greater than the difference between the activation voltage level and the deactivation voltage level of the signal received by the gate of the fourth transistor during the transmission period.

6. The display device according to claim 4, wherein, The activation voltage level of the signal received by the gate of the fourth transistor during the initialization period is lower than the activation voltage level of the signal received by the gate of the fourth transistor during the transmission period.

7. The display device according to claim 1, wherein, The first transistor is of the same type as the fourth transistor.

8. The display device according to claim 1, wherein, Each pixel in the pixel also includes: A second capacitor is connected between the first node and the power line that transmits the first power voltage.

9. The display device according to claim 1, wherein, Each pixel in the pixel also includes: The fifth transistor transmits the ground voltage to the fourth node in response to the bypass gate signal.

10. The display device according to claim 1, wherein, The transmitted signal includes a first transmitted signal and a second transmitted signal. Wherein, the gate of the fourth transistor receives the first transmitted signal, and Each pixel in the pixel further includes: The sixth transistor transmits the first electrical voltage to the first terminal of the first transistor in response to the second transmit signal.

11. The display device according to claim 1, wherein, The gate of the fourth transistor receives the transmitted signal.

12. The display device according to claim 11, wherein, The pixels include red pixels, green pixels, and blue pixels, and The activation voltage levels of the red emission signal received by the gate of the fourth transistor of the red pixel, the activation voltage levels of the green emission signal received by the gate of the fourth transistor of the green pixel, and the activation voltage levels of the blue emission signal received by the gate of the fourth transistor of the blue pixel are different from each other.

13. The display device according to claim 1, wherein, The fourth transistor includes: The fourth-first transistor includes a gate for receiving a bias voltage, a first terminal connected to the second node, and a second terminal; and The fourth-second transistor includes a gate for receiving the transmitted signal, a first terminal connected to the second terminal of the fourth-first transistor, and a second terminal connected to the fourth node.

14. The display device according to claim 1, wherein, The transmitted signals include a first transmitted signal, a second transmitted signal, and a third transmitted signal. Each pixel in the pixel further includes: The seventh-first transistor includes a gate for receiving the first transmitted signal, a first terminal for receiving a first bias voltage, and a second terminal connected to the gate of the fourth transistor; The seventh-second transistor includes a gate for receiving the second transmitted signal, a first terminal for receiving a second bias voltage, and a second terminal connected to the gate of the fourth transistor; and The seventh-third transistor includes a gate for receiving the third transmitted signal, a first terminal for receiving a third bias voltage, and a second terminal connected to the gate of the fourth transistor.

15. The display device according to claim 1, wherein, Each pixel in the pixel also includes: The seventh transistor includes a gate for receiving the transmitted signal, a first terminal connected to the first node, the third node, or the fourth node, and a second terminal connected to the gate of the fourth transistor.

16. A display device, the display device comprising: Display panel, including pixels; The gate driver provides a write gate signal to each pixel in the pixel; A transmitter driver provides a first and a second transmitter signal to each of the pixels; as well as The data driver provides data signals to each of the pixels. Each pixel in the pixel includes: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor transmits the data signal to the first node in response to the write gate signal; A first capacitor is connected between the first node and the second node; A fourth transistor connects the third node to the fourth node in response to the first transmit signal; The sixth transistor, in response to the second transmit signal, transmits the first power voltage to the second node; and The light-emitting element includes a first terminal connected to the fourth node and a second terminal receiving a second electrical voltage. The activation voltage level of the first transmit signal is different from the activation voltage level of the write gate signal.

17. The display device according to claim 16, wherein, The difference between the activation voltage level and the deactivation voltage level of the first transmit signal is less than the difference between the activation voltage level and the deactivation voltage level of the write gate signal.

18. The display device according to claim 16, wherein, The activation voltage level of the first transmit signal is higher than the activation voltage level of the write gate signal.

19. The display device according to claim 16, wherein, Each pixel in the pixel also includes: A second capacitor is connected between the second node and the power line transmitting the first power voltage; and The fifth transistor transmits the ground voltage to the fourth node in response to the bypass gate signal.

20. An electronic device, the electronic device comprising: The processor generates the input image data; The display device displays an image based on the input image; as well as The power module is connected to the processor and the display device. The display device includes: Display panel, including pixels; A gate driver provides write gate signals and compensation gate signals to each pixel in the pixel; A transmit driver that provides a transmit signal to each of the pixels; and The data driver provides data signals to each of the pixels. Each pixel in the pixel includes: The first transistor includes a gate connected to a first node, a first terminal receiving a first electrical voltage, and a second terminal connected to a second node; The second transistor transmits the data signal to the third node in response to the write gate signal; A first capacitor is connected between the first node and the third node; A third transistor connects the first node to the second node in response to the compensation gate signal; The fourth transistor includes a gate, a first terminal connected to the second node, and a second terminal connected to the fourth node; and The light-emitting element includes a first terminal connected to the fourth node and a second terminal receiving a second electrical voltage. The activation voltage level of the signal received by the gate of the fourth transistor is different from the activation voltage level of the write gate signal.

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