Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes a display area including a plurality of pixel areas and a plurality of circuit areas; a sub-pixel configured to receive a data voltage based on a first scan signal supplied through a first gate line to allow a light emitting device to emit light; and a plurality of first scan blocks distributed and disposed in the display area and each including a first scan circuit disposed in a plurality of first circuit areas and configured to generate the first scan signal to supply the first scan signal to the first gate line, wherein the display area includes a notch area of which a portion is recessed, the plurality of first gate lines includes a plurality of first side gate lines and a plurality of first upper gate lines, and the plurality of first upper gate lines includes a plurality of open circuit portions of which a portion is open.

Description

Technical Field

[0001] This disclosure relates to display panels and display devices. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Recently, various flat panel display devices, such as electroluminescent display devices including organic light-emitting diode (OLED) display devices, quantum dot light-emitting diode (QLED) display devices, and micro-LED display devices, are being used.

[0003] Recently, among these various display devices, automotive display devices installed in vehicles are receiving considerable development. Due to space constraints, the display panels used in automotive display devices may have various shapes, such as those with a horizontal length much greater than a vertical length.

[0004] In addition, considering dashboards such as speedometers and fuel gauges in vehicles, the display panel of an automotive display device may include a recessed portion of the display panel.

[0005] The descriptions provided in this Background section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0006] To overcome the aforementioned limitations of the related technologies, this disclosure provides a display panel and display device that can enhance the quality of the image displayed thereon, even when a notched area is provided therein.

[0007] Additional advantages, aspects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon reviewing the following, or may be learned from practice of this disclosure. Various aspects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims, and in the accompanying drawings.

[0008] To achieve these and other aspects and in accordance with the purposes of this disclosure, as specifically implemented and broadly described herein, a display panel includes: a display area comprising a plurality of pixel areas arranged spaced apart from each other in a first direction and a plurality of circuit areas arranged between the plurality of pixel areas; subpixels disposed in each of the plurality of pixel areas and configured to receive a data voltage based on a first scan signal supplied via a first gate line extending in the first direction to allow a light-emitting device to emit light; and a plurality of first scan blocks distributed and disposed in the display area and each including a first scan circuit disposed in the plurality of circuit areas. The multiple first circuit regions are configured to generate a first scan signal to supply the first scan signal to the first gate lines. The display region includes a notch region in which a portion of the display region is recessed in a second direction intersecting the first direction. The multiple first gate lines include multiple first side gate lines and multiple first upper gate lines. The multiple first side gate lines are disposed corresponding to the notch region and each includes an end adjacent to the notch region. The multiple first upper gate lines are disposed above the notch region in the second direction, and the multiple first upper gate lines include multiple open-circuit portions in which a portion of the first upper gate line is disconnected and open-circuited.

[0009] In another aspect of this disclosure, a display device includes: a display area comprising a plurality of pixel areas arranged spaced apart from each other in a first direction and a plurality of circuit areas arranged between the plurality of pixel areas; a subpixel disposed in each of the plurality of pixel areas and configured to receive a data voltage based on a first scan signal supplied via a first gate line extending in the first direction to allow a light-emitting device to emit light; and a plurality of first scan blocks distributed and disposed in the display area and each including a first scan circuit, the first scan circuits being disposed in the plurality of first circuit areas and configured to generate a first scan signal to... A first scan signal is supplied to a first gate line, wherein the display area includes a notch area, in which a portion of the display area is recessed in a second direction intersecting the first direction, and a plurality of first gate lines include a plurality of first side gate lines and a plurality of first upper gate lines, the plurality of first side gate lines being disposed corresponding to the notch area and each including an end adjacent to the notch area, the plurality of first upper gate lines being disposed above the notch area in the second direction, the plurality of first upper gate lines including a plurality of open portions, in which a portion of the first upper gate line is disconnected and open-circuited, and the open ends of the first upper gate lines are spaced apart from each other in the first direction.

[0010] In another aspect of this disclosure, a display panel is provided, comprising: a display area including a plurality of pixel areas and a plurality of circuit areas, the plurality of pixel areas being arranged spaced apart from each other in a first direction and having a plurality of sub-pixels disposed in the plurality of pixel areas, and the plurality of circuit areas being arranged between the plurality of pixel areas; and a gating driver distributed and disposed in the plurality of circuit areas and configured to generate a first scan signal to supply the first scan signal to the sub-pixels respectively via a plurality of first gating lines, wherein the display area includes a notch area, in which a portion of the display area is recessed in a second direction intersecting the first direction, the plurality of first gating lines including a plurality of first side gating lines and a plurality of first upper gating lines, the plurality of first side gating lines being disposed corresponding to the notch area, the plurality of first upper gating lines being disposed above the notch area in the second direction, and the plurality of first upper gating lines including a plurality of open portions, in which a portion of the first upper gating line is disconnected and open-circuited.

[0011] When the display panel includes a notched area, embodiments of this disclosure may include an open-circuit portion in which a portion of the first upper select line is disconnected and open-circuited, thereby improving the brightness deviation between the side and top of the notched area in the display area and thus enhancing the quality of the display screen.

[0012] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0013] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the various principles of the disclosure. In the drawings: Figure 1 This is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure; Figure 2 yes Figure 1 An example of an enlarged view of section K1 in the image; Figure 3 yes Figure 2 An example of the equivalent circuit of the sub-pixels included in the pixel region; Figure 4 This is an example of a cross-sectional view used to describe the cross-sectional structure of a sub-pixel; Figure 5 It is used to describe Figure 2 A diagram showing an example configuration of shift registers included in the strobe driver; Figure 6 An example arrangement of a first scan block, a second scan block, and a third scan block included in a display panel is schematically illustrated. Figure 7 yes Figure 6 An example of an enlarged view of section K2 in the image; Figure 8 yes Figure 6 An enlarged view of section K3 in order to describe in more detail the open portion included in the first and second blocks of the first scan block and each of the first strobe lines; Figure 9 This is a diagram illustrating an example configuration for each of the first and second scan circuits; Figure 10 It is used to describe Figure 9 A diagram showing an example of the first and second scanning circuits applied to multiple first and second circuit regions; Figure 11 It is used to describe Figure 7 A diagram illustrating an example of an EM circuit; Figure 12 It is used to describe the Figure 11 A diagram illustrating an example of an EM circuit applied to multiple third circuit regions; Figure 13 yes Figure 8 An example of an enlarged view of section K4 in the image; Figure 14 This is an example along Figure 13 A cross-sectional view of the section intercepted by line CS-CS'; and Figure 15A and Figure 15B It is a diagram used to describe the effect based on the open circuit portion.

[0014] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and illustrations of these elements may be exaggerated. Detailed Implementation

[0015] In the following description, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification, when adding reference numerals to elements in each drawing, care should be taken to use the same reference numerals already used to denote the same elements in other drawings for those elements whenever possible. In the following description, detailed descriptions will be omitted where it is determined that a detailed description of a related known function or configuration would unnecessarily obscure the essential points of the present disclosure. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that need to occur in a specific order. The names of the corresponding elements used in the following description may be chosen solely for ease of writing and therefore may differ from the names used in actual products.

[0016] The advantages and features of this disclosure, and methods of implementing them, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary embodiments are provided so that this disclosure may be thorough and complete, and fully convey the concept of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the appended claims.

[0017] Furthermore, numerous specific details are set forth in the following detailed description of this disclosure in order to provide a sufficiently thorough understanding of this disclosure. However, it will be understood that this disclosure can be practiced without these specific details. In other instances, known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of this disclosure.

[0018] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. Similar reference numerals refer to similar elements throughout. The same elements are designated by the same reference numerals throughout this specification. As used herein, the terms “comprising,” “having,” “including,” etc., indicate that additional components may be added, unless more restrictive terms such as “only” are used. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Any implementation described herein as an “example” is not necessarily to be construed as more preferred or advantageous than other implementations.

[0019] When describing positional relationships, for example, when using terms such as "above," "over," "below," "above," "below," "below," "near," "adjacent," "next to," "beside," or "adjoining" to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being "above," "over," "below," "above," "below," "below," "near," "adjacent," "beside," or "adjoining" another structure, this description should be interpreted to include situations where these structures are in contact with each other and situations where a third structure is positioned or inserted between them. Furthermore, the terms "left side," "right side," "top," "bottom," "downward," "upward," "upper part," "lower part," etc., refer to any frame of reference.

[0020] When describing temporal relationships, such as when time sequence is described as “after,” “next,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “only,” “directly,” or “immediately” are used.

[0021] The term “at least one” should be understood to include any and all combinations of one or more of the relevant listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0022] It will be understood that although the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and do not limit the nature, order, sequence, or number of elements. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0023] Similar reference numerals denote similar elements. Furthermore, for ease of description, the thickness, ratios, and dimensions of each element described herein are illustrated as partially enlarged or reduced. For ease of description, the scale of each element shown in the accompanying drawings of this disclosure may differ from the actual scale, and is not limited to the scales shown in the drawings.

[0024] In this disclosure, when any element (or region, layer, part, etc.) is described as “on,” “connected,” or “linked,” this may indicate that the arbitrary element can be directly connected to / linked to another element, or that a third element may be placed therein.

[0025] The term "and / or" can include all combinations of one or more combinations that can be defined by the relevant elements.

[0026] Terms such as "first" and "second" may be used to describe various elements, but the elements should not be limited by these terms. These terms may be used only for the purpose of distinguishing one element from another. For example, without departing from the spirit and scope of the inventive concept, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless otherwise indicated, singular terms may include plural forms.

[0027] The terms “below,” “under,” “above,” and “over” can be used to describe the relationship between elements shown in the accompanying drawings. These terms can be relative concepts and can be described relative to the directions shown in the drawings. For example, one or more other elements may be positioned between two elements unless “exactly” or “directly” is used. The spatially relative terms “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one device or element and other devices or elements as shown. Thus, for example, “below” and “lower” relative to the first element can be opposite to “above” and “upper.”

[0028] It should be understood that spatial relative terms are terms that include not only the orientations shown in the figures but also the different orientations of the elements during use or operation. For example, if the device in the figures is flipped, an element described as being "below" or "below" other elements can be placed "above" other elements. Thus, the exemplary term "below" can include both "below" and "above" orientations. Similarly, the exemplary terms "above" or "upper" can include both "above" and "below" orientations.

[0029] It should be understood that "including", "comprise", "includes", or "contains" specifies a property, area, fixed quantity, step, process, element and / or component, but does not exclude other properties, areas, fixed quantities, steps, processes, elements and / or components.

[0030] Features of the various embodiments of this disclosure may be partially or wholly linked or combined with each other, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent manner.

[0031] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and shall not be interpreted as having an overly idealized or overly formal meaning, unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0032] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, all components of each display panel or each display device according to all embodiments of the present disclosure are operatively connected and configured. For ease of description, the scale of each element shown in the drawings differs from the actual scale; therefore, the description is not limited to the scales shown in the figures.

[0033] Figure 1 This is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure, and Figure 2 yes Figure 1 An enlarged view of part K1 in the image.

[0034] like Figure 1 As shown, a display device according to an embodiment of the present disclosure may include a display panel 100, a timing controller 120, a gating driver 130, a data driver 140, a power supply circuit 180, and a sub-pixel PXL.

[0035] like Figure 1 As shown, the display panel 100 may include a display area AA and an adjacent non-display area NA. The non-display area NA may be disposed along the edge of the display panel 100 and may be disposed outside the display area AA in the display panel 100.

[0036] The display area AA can display an image based on an image signal, and the non-display area NA can form a border area of ​​the display panel 100 where no image is displayed. The display area AA may include multiple pixel areas AP and multiple circuit areas AG.

[0037] like Figure 1 As shown, the gating driver 130 and sub-pixel PXL can be set in the display area AA. Figure 1 For ease of understanding, this example uses one gating driver 130 and one sub-pixel PXL, but it is not limited to this. Each pixel region AP can have one or more sub-pixels PXL, and the gating driver 130 can be distributed and disposed in each circuit region AG. The distribution of the gating driver 130 can refer to the situation where the components or elements included in the gating driver 130 are divided into two or more groups or blocks and disposed at different locations in the circuit region AG.

[0038] For example, such as Figure 2 As shown, multiple pixel regions AP and multiple circuit regions AG can be arranged alternately in a first direction x (or horizontal direction), and therefore, multiple circuit regions AG can be arranged between multiple pixel regions AP. Each of the multiple pixel regions AP and multiple circuit regions AG can extend in a second direction y (or column direction) intersecting the first direction x.

[0039] Each of the multiple pixel regions AP can have at least one unit pixel. Each unit pixel can be arranged in the multiple pixel regions AP along a first direction x, and can also be arranged in a second direction y, which is the length direction of each pixel region AP, so that they can be arranged in a matrix form, thereby forming a pixel array.

[0040] Each unit pixel may include multiple subpixels PXL. The multiple subpixels PXL included in each unit pixel may include red (R) subpixels, green (G) subpixels and blue (B) subpixels, or may include red (R) subpixels, green (G) subpixels, blue (B) subpixels and white (W) subpixels, but this disclosure is not limited thereto.

[0041] For example, the red (R) subpixel, green (G) subpixel, and blue (B) subpixel included in each unit pixel can achieve various colors by controlling the brightness of each subpixel PXL.

[0042] Therefore, for example, multiple subpixels including red (R) subpixels, green (G) subpixels and blue (B) subpixels can be set in a pixel region AP arranged between two adjacent circuit regions AG.

[0043] exist Figure 2 The example illustrates that each pixel region AP has one sub-pixel PXL, but this is for ease of understanding, and each pixel region AP can have at least one unit pixel in the first direction x. For example, each pixel region AP can have one unit pixel including multiple sub-pixels PXL in the first direction x, and the multiple unit pixels can be arranged in the second direction y.

[0044] In each sub-pixel PXL of pixel region AP, at least one gate line GL1, GL2, and GL3 extending in the first direction x can intersect with a data line DL extending in the second direction y. Each sub-pixel PXL can be provided with a first scan signal SC1(n), a second scan signal SC2(n), or a light emission control signal EM(n) through the gate lines GL1, GL2, and GL3, and can be provided with a data voltage Vdata through the data line DL. Each sub-pixel PXL can be provided with a data voltage Vdata according to the first scan signal SC1(n), and can control the light emission of the light-emitting device included in the sub-pixel PXL according to the light emission control signal EM(n).

[0045] exist Figure 2The illustration uses the case where one data line DL and three gate lines GL1, GL2, and GL3 intersect each other in each sub-pixel PXL as an example. The three gate lines GL1, GL2, and GL3 may include a first gate line GL1, a second gate line GL2, and a third gate line GL3. However, this is merely an example, and the disclosure is not limited thereto, and more or fewer gate lines may be provided in each sub-pixel. For example, in... Figure 2 The second gate line GL2 or the third gate line GL3 can be omitted. In the following text, for ease of description, reference will be made to... Figure 2 Description of embodiments of this disclosure.

[0046] Each of the gate lines GL1, GL2, and GL3 can extend in the first direction x and can be configured to overlap with multiple pixel regions AP and multiple circuit regions AG, and can be jointly connected to the sub-pixel PXL adjacent to it in the first direction x. Each data line DL can extend along each pixel region AP in the second direction y and can be jointly connected to the sub-pixel PXL adjacent to it in the second direction y.

[0047] For example, each data line DL can extend in the second direction y in the pixel region AP and can be electrically connected to the corresponding sub-pixel PXL in the plurality of sub-pixels PXL, and each of the gating lines GL1, GL2 and GL3 can extend in the first direction x, can be electrically connected to each sub-pixel PXL in the pixel region AP, and can be connected to a portion of the desired gating driver 130 in the circuit region AG in which a plurality of gating drivers 130 are distributed and configured.

[0048] The first scan signal SC1(n) can be applied to the first gating line GL1, the second scan signal SC2(n) can be applied to the second gating line GL2, and the light emission control signal EM(n) can be applied to the third gating line GL3.

[0049] The first scan signal SC1(n) allows control to be executed to apply the data voltage Vdata to the sub-pixel PXL, the second scan signal SC2(n) allows control to be executed to initialize the pixel circuit configured for each sub-pixel PXL to the reference voltage Vref, and the light emission control signal EM(n) allows control to be executed to supply the light emission current generated by the driving transistor to the light emission device.

[0050] The data driver 140 can generate an analog data voltage Vdata and supply the analog data voltage Vdata to the sub-pixel PXL connected to it via the data line DL.

[0051] The data driver 140 can convert digital image data input from the timing controller 120 into an analog data voltage Vdata based on a data timing control signal, and can supply the data voltage Vdata to the sub-pixel PXL via the data line DL. Each data voltage Vdata can have a voltage value corresponding to the image grayscale level to be expressed in each sub-pixel PXL.

[0052] For this purpose, the data driver 140 may include a data driver integrated circuit (IC) electrically connected to a non-display area NA of the display panel 100. For example... Figure 1 As shown, the data driver 140 may include a plurality of data driver ICs (D-ICs) arranged along the outer edge of the display panel 100.

[0053] When the sub-pixel PXL is provided with gating drive signals such as scan signals SC1(n) and SC2(n) and a light emission control signal EM(n), the gating driver 130 may include, for example, a first scan circuit, a second scan circuit, and an EM circuit. Here, the first scan circuit, the second scan circuit, and the EM circuit may be distributed and arranged in multiple circuit regions AG. Referring below... Figure 5 The first scanning circuit, the second scanning circuit, and the EM circuit are described in detail.

[0054] The first and second scan circuits and the EM circuit of the gating driver 130 can operate based on signals and voltages output from the timing controller 120, the power supply circuit 180, and the level shifter 160. The first and second scan circuits and the EM circuit can output signals via gating lines GL1, GL2, and GL3 connected to the display panel 100 in response to a gating timing control signal GDC supplied from the timing controller 120. The gating driver 130 may include a shift register for outputting signals. The first and second scan circuits and the EM circuit may be included in the shift register.

[0055] Level shifter 160 can receive a gating timing control signal GDC from timing controller 120 and convert the gating timing control signal GDC into a signal with an on-state voltage level or an off-state voltage level. The level-converted gating timing control signal can be input to the first scan circuit, the second scan circuit, and the EM circuit. Level shifter 160 can be included as part of gating driver 130. For example, in addition to the first scan circuit, the second scan circuit, and the EM circuit, gating driver 130 may further include level shifter 160.

[0056] The first scanning circuit generates a first scanning signal SC1(n) and supplies it to the first gating line GL1. The second scanning circuit generates a second scanning signal SC2(n) and supplies it to the second gating line GL2. The EM circuit generates an illumination control signal EM(n) and supplies it to the third gating line GL3.

[0057] The EM circuit can receive the voltage of the gating timing control signal from the level shifter 160 to generate the light emission control signal EM(n), and can supply the generated light emission control signal EM(n) to each sub-pixel PXL.

[0058] The first and second scanning circuits can receive the voltage of the gating timing control signal from the level shifter 160 to generate the first scanning signal SC1(n) and the second scanning signal SC2(n), and supply the first scanning signal SC1(n) and the second scanning signal SC2(n) to each sub-pixel PXL.

[0059] Each of the first scanning circuit, the second scanning circuit, and the EM circuit can be distributed and arranged in multiple circuit areas AG provided in the display area AA. The following will refer to... Figure 5 The arrangement of the strobe driver 130 is described in detail.

[0060] The power supply circuit 180 can process the input power according to the power timing control signal PDC input from the timing controller 120 to generate a high-level drive voltage VDD and a low-level drive voltage VSS to be supplied to each sub-pixel PXL, or it can generate gating high voltages VGH and VEH and gating low voltages VGL and VEL to be supplied to the transistors included in the first scan circuit, the second scan circuit, and the EM circuit.

[0061] The timing controller 120 can generate timing control signals GDC, DDC and PDC based on the digital image data D-DATA input from the host system 10, and can supply the timing control signals GDC, DDC and PDC to the gating driver 130, the data driver 140 and the power supply circuit 180 respectively.

[0062] The timing controller 120 can divide a frame period into an initialization period, a programming period after the initialization period, and a light emission period after the programming period, so as to supply timing control signals GDC and DDC to the data driver 140 and the strobe driver 130.

[0063] The host system 10 can supply digital image data D-DATA to the timing controller 120, and can be a motherboard such as a television system, set-top box, navigation system, personal computer and home theater system, but the embodiments disclosed herein are not limited thereto.

[0064] Each of the multiple sub-pixels PXL may include a light-emitting device and a driving element, the driving element generating a light-emitting current based on the voltage difference between its gate and source to drive the light-emitting device.

[0065] The light-emitting device may include an anode electrode, a cathode electrode, and an organic compound layer formed between the electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a pixel current flows through the light-emitting device, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) can move to the emissive layer (EML) to form excitons; therefore, the emissive layer (EML) can emit visible light. Alternatively, the organic compound layer may be replaced by an inorganic compound layer.

[0066] The driving element can be implemented using, but is not limited to, low-temperature polycrystalline silicon (LTPS) or oxide thin-film transistors (TFTs) based on an organic substrate (or plastic substrate). The driving element can also be implemented as a complementary metal-oxide-semiconductor (CMOS) transistor based on a silicon wafer. Each sub-pixel PXL may include pixel driving circuitry. This will be referenced below. Figure 3 Describe it.

[0067] Furthermore, the display panel 100 according to the embodiments of this disclosure can be used as an automotive display panel 100, and considering vehicle dashboards such as speedometers and fuel gauges, the display panel 100 may include a recessed notch region NC. Therefore, a portion of the display area AA may also include the notch region NC.

[0068] The notch region NC may have a width in the first horizontal direction x, representing a portion of the lower end of the display region AA, and may be recessed upwards in the second horizontal direction y, but this disclosure is not limited thereto. The notch region NC may be formed on any side of the display panel, including the lower side, upper side, left side, right side, or corner side. Embodiments of this disclosure can be described by way of example when the notch region NC is formed in the lower part of the display panel.

[0069] Because of this notch region NC, when the gate drivers 130 are distributed and arranged in the display area AA, in a plan view, the output characteristics of the scan signals SC1(n) and SC2(n) applied to the side gate lines GL1, GL2, and GL3 arranged on the side of the notch region NC may differ from the output characteristics of the scan signals SC1(n) and SC2(n) applied to the upper gate lines GL1, GL2, and GL3 arranged above the notch region NC. In the following text, a side gate line may refer to a gate line corresponding to the notch region, and an upper gate line may refer to other gate lines among the multiple gate lines of the display panel besides the side gate lines, but this disclosure is not limited thereto.

[0070] Therefore, in a planar view, a brightness difference may occur between the light emitted by the light-emitting device of the sub-pixel PXL located on the side of the notch region NC and the light emitted by the light-emitting device of the sub-pixel PXL located above the notch region NC. For example, in Figure 1 In the notch region NC, there may be a brightness difference between the side sub-pixel PXL connected to the side gate lines GL1, GL2 and GL3 and the upper sub-pixel PXL connected to the upper gate lines GL1, GL2 and GL3.

[0071] However, this disclosure may include multiple open-circuit portions, wherein a portion of the first upper gate line disposed above the notch region in the first gate line GL1 that receives the supply of the data voltage Vdata described above is disconnected and open-circuited, thereby improving or reducing the brightness deviation as described above, thereby further enhancing the quality of the display screen. This will be referred to below. Figure 6 Detailed description.

[0072] Figure 3 yes Figure 2 An example of the equivalent circuit of the sub-pixels included in the pixel region.

[0073] Figure 3 The equivalent circuit of the sub-pixel PXL shown is an example, but this disclosure is not limited thereto and may be replaced by other circuit configurations.

[0074] For example, such as Figure 3 As shown, the sub-pixel PXL circuit may include a driving transistor DT, multiple switching transistors T1 to T5, a capacitor Cst, and a light-emitting device OLED.

[0075] The driving transistor DT may include a first electrode to which a high-level driving voltage VDD is applied, a second electrode connected to a third node n3, and a gate electrode connected to a second node n2. The driving transistor DT can generate a driving current based on the data voltage Vdata applied to the second node n2 and supply the data voltage Vdata to the third node n3.

[0076] The capacitor Cst may include a first electrode connected to a first node n1 and a second electrode connected to a second node n2, and the data voltage Vdata applied to the first node n1 may be stored in the capacitor Cst.

[0077] The first transistor T1 may include a first electrode to which a data voltage Vdata is applied and a second electrode connected to a first node n1, and may apply a first scan signal SC1(n) to its gate electrode. The first transistor T1 may transmit the data voltage Vdata to the first node n1 in response to the first scan signal SC1(n).

[0078] The second transistor T2 may include a first electrode connected to the third node n3, a second electrode connected to the second node n2, and a gate electrode for receiving the second scan signal SC2(n). The second transistor T2 may be diode-connected between the gate electrode and the second electrode of the driving transistor DT.

[0079] The third transistor T3 may include a first electrode that receives a reference voltage Vref lower than the high-level drive voltage VDD, a second electrode connected to the first node n1, and a gate electrode that receives the light emission control signal EM(n).

[0080] The fourth transistor T4 may include a first electrode connected to the third node n3, a second electrode connected to the fourth node n4, and a gate electrode for receiving the light emission control signal EM(n).

[0081] The fifth transistor T5 may include a first electrode to which a reference voltage Vref is applied, a second electrode connected to the fourth node n4, and a gate electrode to which the second scan signal SC2(n) is received.

[0082] An OLED (Optical Display Panel) device may include an anode electrode connected to a fourth node n4 and a cathode electrode to which a low-level driving voltage VSS is applied. Although Figure 3 The pixel circuit shown includes a 5T1C, but this disclosure is not limited thereto, and the pixel circuit of this disclosure may include more or fewer elements than shown. For example, structures such as 2T1C, 3T1C, 4T1C, 3T2C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T2C, etc., are also feasible. Furthermore, it may contain more or fewer transistors and capacitors.

[0083] For example, a pixel circuit can operate as follows.

[0084] During the initialization period, a light emission control signal EM(n) with a conduction voltage and a second scan signal SC2(n) can be applied, so that the first node n1 to the fourth node n4 can be initialized to the reference voltage Vref. During the programming period, a first scan signal SC1(n) with a conduction voltage can be applied, so that the data voltage Vdata can be stored in the capacitor Cst, and the high-level drive voltage EVDD and the threshold voltage of the drive transistor DT can be supplied to the second node n2, so that the threshold voltage can be reflected in the data voltage Vdata and stored.

[0085] Subsequently, during the light-emitting period, a light-emitting control signal EM(n) with a conduction voltage can be applied. Therefore, the driving transistor DT can generate a driving current based on the data voltage Vdata, and the generated driving current can be supplied to the light-emitting device OLED. At this time, since the threshold voltage of the driving transistor DT is reflected in it, the generated driving current can have a compensated current value.

[0086] Such sub-pixels PXL can have, for example Figure 4 The cross-sectional structure shown.

[0087] Figure 4 This is an example of a cross-sectional diagram used to describe the structure of a sub-pixel cross section.

[0088] exist Figure 4 For ease of understanding, an example with only one transistor TR is shown, but it is not limited to this, and Figure 3 The multiple transistors TR shown can all be included in a single pixel.

[0089] like Figure 4 As shown, the cross-sectional structure of the sub-pixel PXL may include a substrate 110, a buffer layer 145, a gate insulating layer 150, an interlayer insulating layer 200, a planarization layer 300, a dam 400, a light-emitting device OLED, a transistor TR, and an encapsulation layer 500.

[0090] Furthermore, despite Figure 4 The image is not shown, but a lens, a black matrix, and a touch electrode array may be additionally disposed on the encapsulation layer 500.

[0091] For example, a lens disposed on the encapsulation layer 500 can be disposed in each sub-pixel PXL, and a light-absorbing black matrix can be disposed between adjacent sub-pixels PXL.

[0092] In addition, lenses and black matrices can also be set up. Figure 2 The circuit region AG shown. Therefore, at least some of the multiple circuit regions AG can be configured to overlap with the lens and the black matrix.

[0093] The touch electrode array can be independent Figure 2 The circuit region AC and pixel region AP are arranged on the lens and black matrix as shown.

[0094] The substrate 110 can be formed using a flexible plastic material to achieve flexibility, and may also include a thin and flexible glass material. The substrate 110 can be disposed in the display area AA and the non-display area NA of the display panel 100.

[0095] A buffer layer 145 may be disposed on the substrate 110 and may comprise an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer layer 145 may comprise a multilayer structure containing the same or different materials. A semiconductor layer ACT configuring the transistor TR may be disposed on the buffer layer 145.

[0096] The semiconductor layer ACT may include a channel region with low conductivity and carrier concentration disposed at the center of the overlap with the gate electrode G, and source-drain regions with high conductivity and carrier concentration may be disposed on both sides of the channel region. The channel region can form a channel in response to a voltage applied to the gate electrode G, and a drive current can flow through the formed channel.

[0097] The semiconductor layer ACT may include semiconductor materials such as low-temperature polycrystalline silicon (LTPS) or oxide semiconductor materials such as indium gallium zinc oxide (IGZO).

[0098] A gate insulating layer 150 may cover a buffer layer 145 and be disposed on the semiconductor layer ACT. The gate insulating layer 150 may comprise an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). A gate electrode G configuring the transistor TR may be disposed on the gate insulating layer 150. The gate electrode G may overlap with the semiconductor layer ACT. The gate electrode G may be supplied with a first scan signal SC1(n) and a second scan signal SC2(n) or a light emission control signal EM(n), or a voltage of a second node n2 may be applied to it. The gate insulating layer 150 may insulate the semiconductor layer ACT from the gate electrode G.

[0099] Interlayer insulating layer 200 may cover the gate electrode G and may be disposed on the gate insulating layer 150. Interlayer insulating layer 200 may comprise an inorganic insulating material such as SiOx, SiNx, or SiOxNy. The source electrode SD1a and drain electrode SD1b of transistor TR, respectively, may be disposed on the interlayer insulating layer 200. Interlayer insulating layer 200 may insulate the source electrode SD1a and drain electrode SD1b from the gate electrode G.

[0100] Each of the source electrode SD1a and the drain electrode SD1b can pass through the interlayer insulating layer 200 and the gate insulating layer 150, and can be electrically connected to the source-drain region of the semiconductor layer ACT.

[0101] The source electrode SD1a and the drain electrode SD1b may comprise the same material, and may comprise, for example, at least one of metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0102] The planarization layer 300 may cover the source electrode SD1a and the drain electrode SD1b and may be disposed on the interlayer insulating layer 200. The planarization layer 300 may remove the step height caused by the transistor TR and may include a flat surface. The planarization layer 300 may include an organic insulating material with high fluidity.

[0103] The planarization layer 300 may include a first planarization layer 310 and a second planarization layer 320 disposed on the first planarization layer 310. The intermediate electrode SD2 may be disposed between the first planarization layer 310 and the second planarization layer 320, and the intermediate electrode SD2 may electrically connect one of the source electrode SD1a and the drain electrode SD1b to the anode electrode E1 of the light-emitting device OLED.

[0104] The intermediate electrode SD2 can pass through the first planarization layer 310, can be electrically connected to one of the source electrode SD1a and the drain electrode SD1b, and can be electrically connected to the anode electrode E1 passing through the second planarization layer 320. The intermediate electrode SD2 may include at least one metal such as Al, Cr, Cu, Ti, Mo and W.

[0105] The anode electrode E1 of the OLED light-emitting device can be disposed on the second planarization layer 320.

[0106] As described above, the transistor TR may include a semiconductor layer ACT, a gate electrode G, a source electrode SD1a, and a drain electrode SD1b.

[0107] The embankment 400 can cover the edge of the anode electrode E1 and can be disposed on the second planarization layer 320. The embankment 400 can define the light-emitting area of ​​each sub-pixel PXL. For example, the light-emitting area of ​​each sub-pixel PXL can be divided by the embankment 400.

[0108] An OLED light-emitting device may include an anode electrode E1, an emissive layer EL, and a cathode electrode E2. The emissive layer EL and the cathode electrode E2 may be disposed in the portion of the anode electrode E1 exposed by the embankment 400.

[0109] The light-emitting layer EL can emit light, and the brightness of the light can be controlled by the voltage difference formed between the anode electrode E1 and the cathode electrode E2. The light-emitting layer EL may include a light-emitting material layer containing organic materials, but this disclosure is not limited thereto.

[0110] An encapsulation layer 500 can be disposed on the light-emitting device OLED and the dam 400 of each sub-pixel PXL. The encapsulation layer 500 can prevent or reduce damage to the light-emitting device OLED caused by external impacts and water. The encapsulation layer 500 can have a multilayer structure. For example, the encapsulation layer 500 can be formed by alternately stacking a first inorganic insulating layer 501 and a second inorganic insulating layer 503 comprising an inorganic insulating material, and an organic insulating layer 502 comprising an organic insulating material. For example, the organic insulating layer 502 can be disposed between the first inorganic insulating layer 501 and the second inorganic insulating layer 503.

[0111] The first inorganic insulating layer 501 can be disposed in the display area AA and the non-display area NA. The first inorganic insulating layer 501 can be disposed on the embankment 400 while covering the cathode electrode E2.

[0112] An organic insulating layer 502 can be disposed on the first inorganic insulating layer 501 in the display area AA and the non-display area NA. The organic insulating layer 502 can eliminate the step height caused by multiple light-emitting devices (OLEDs).

[0113] The second inorganic insulating layer 503 can be disposed on the organic insulating layer 502 in the display area AA and the non-display area NA, thereby sealing the organic insulating layer 502.

[0114] Therefore, the encapsulation layer 500 can effectively prevent or reduce damage to the OLED light-emitting device caused by external impacts and water. The step height caused by the OLED light-emitting device of each pixel can be eliminated by the encapsulation layer 500. For example, the top surface of the encapsulation layer 500 facing the substrate 110 can be a flat plane.

[0115] The aforementioned sub-pixel PXL can be set in each pixel region AP of the display area AA.

[0116] Furthermore, as described above, the shift register included in the gating driver 130 may include the first scan circuit, the second scan circuit, and the EM circuit as described above. This will be described below.

[0117] Figure 5 It is used to describe Figure 2 A diagram showing the configuration of the shift registers included in the strobe driver.

[0118] The shift registers included in the gating driver 130 may include multiple stages STG1 to STGm. These multiple stages STG1 to STGm may have an associated connection to output signals sequentially. The multiple stages STG1 to STGm may include a first scan circuit SCN1 that generates a first scan signal SC1(n), a second scan circuit SCN2 that generates a second scan signal SC2(n), and an EM circuit EMD that generates a light emission control signal EM(n).

[0119] Each of the first scan circuit SCN1, the second scan circuit SCN2, and the EM circuit EMD can be connected to a line to which each of the clock signals GCLKS and ECLKS is applied, as well as a line to which on-state voltages (e.g., VGL and EVL) and off-state voltages (e.g., VGH and EVH) are applied.

[0120] The first scan circuit SCN1 and the second scan circuit SCN2, as well as the EM circuit EMD, set in each stage can be connected in association, and the signal generated in the previous stage can be used as the start signal input for the next stage.

[0121] The first scanning circuit SCN1-1, the second scanning circuit SCN2-1, and the EM circuit EMD-1 set in the first stage STG1 can receive the start signals GVST and EVST. Therefore, the operation of each of the first scanning circuit SCN1, the second scanning circuit SCN2, and the EM circuit EMD can begin.

[0122] Each of the first scanning circuits SCN1-2 to SCN1-m and the second scanning circuits SCN2-2 to SCN2-m, and the EM circuits EMD-2 to EMD-m, respectively, located in the back-end stages STG2 to STGm, can use the output signal of the circuit located in the front-end stage as the start signal.

[0123] As described above, the first scan circuit SCN1 and the second scan circuit SCN2, as well as the EM circuit EMD, located in each stage, can be distributed and arranged in multiple circuit regions AG. This can be referred to below. Figure 6 Describe it.

[0124] Figure 6 The arrangement of the first scan block, the second scan block, and the third scan block included in the display panel is schematically illustrated. Figure 7 yes Figure 6 An enlarged view of section K2 in the image.

[0125] exist Figure 6For ease of understanding, the second gate line GL2 and the third gate line GL3 are omitted in the display area AA, and only the first gate line GL1 is briefly shown. However, the embodiments of this disclosure are not limited to this, and the second gate line GL2 and the third gate line GL3 can be set.

[0126] In the following text, for ease of description, among the multiple first gate lines GL1, second gate lines GL2 and third gate lines GL3, the gate line that is set on the side of the notch region NC and is set on the other side of the notch region NC along the first direction x on the straight line extension line can be called a side gate line, and the gate line that is set on the upper part of the notch region NC in the second direction y and is not set on the notch region NC on the straight line extension line can be called an upper gate line.

[0127] For example, a side selector line can be set on the side of the notch region NC, and the end of the side selector line can contact the side of the notch region NC (or the inclined surface), and an upper selector line can be set above the notch region NC, and the end of the upper selector line can not contact the side of the notch region NC.

[0128] Therefore, each of the above-mentioned multiple first gating lines GL1, second gating lines GL2 and third gating lines GL3 may include a first side gating line, a second side gating line and a third side gating line, as well as a first upper gating line, a second upper gating line and a third upper gating line.

[0129] exist Figure 6 In the multiple first gate lines GL1, the first-1 gate line GL11 to the third-3 gate line GL13 can be the first upper gate line GL1-u, and the first-4 gate line GL14 to the first-6 gate line GL16 can be the first side gate line GL1-s.

[0130] As in Figure 6 In the case where the first side selection line GL1-s is disposed on both sides of the notch region NC, the first side selection line GL1-s disposed on one side of the notch region NC can be electrically isolated from the first side selection line GL1-s disposed on the other side of the notch region NC.

[0131] In the following text, among the multiple circuit regions AG, the multiple circuit regions AG with the first scanning circuit SCN1 can be referred to as multiple first circuit regions AG1, the multiple circuit regions AG with the second scanning circuit SCN2 can be referred to as multiple second circuit regions AG2, and the multiple circuit regions AG with the EM circuit EMD can be referred to as multiple third circuit regions AG3.

[0132] In addition, Figure 7For ease of understanding, multiple first gate lines GL11 to GL1y, second gate lines GL21 to GL2y, and third gate lines GL31 to GL3y are shown on the side of section K2. Each of these gate lines can extend in the first direction x and can overlap with multiple pixel regions AP and multiple first circuit regions AG1, second circuit regions AG2, and third circuit regions AG3. Each of these gate lines can be electrically connected to multiple sub-pixels PXL arranged in the multiple pixel regions AP.

[0133] As described above, the first scanning circuits SCN1-1 to SCN1-8, the second scanning circuits SCN2-1 to SCN2-10, and the EM circuits EMD-1 to EMD-8 can be distributed and arranged in multiple circuit regions AG.

[0134] For example, the first scanning circuits SCN1-1 to SCN1-8 can be distributed and disposed in a first scanning block BSC1, which includes multiple first circuit regions AG1; the second scanning circuits SCN2-1 to SCN2-10 can be distributed and disposed in a second scanning block BSC2, which includes multiple second circuit regions AG2 in addition to the first circuit regions AG1; and the EM circuits EMD-1 to EMD-8 can be distributed and disposed in an EM block BEM, which includes multiple third circuit regions AG3 in addition to the first circuit regions AG1 and the second circuit regions AG2.

[0135] exist Figure 6 In this configuration, the first scan block BSC1, the second scan block BSC2, and the EM block BEM can be positioned over the entire display area AA. Within each of the first scan block BSC1, the second scan block BSC2, and the EM block BEM, multiple pixel regions AP can be alternately arranged between multiple first circuit regions AG1, second circuit regions AG2, and third circuit regions AG3.

[0136] For example, such as Figure 7 As shown, multiple first circuit regions AG1 and multiple pixel regions AP can be alternately arranged in the first scan block BSC1 along the first direction x, multiple second circuit regions AG2 and multiple pixel regions AP can be alternately arranged in the second scan block BSC2 along the first direction x, and multiple third circuit regions AG3 and multiple pixel regions AP can be alternately arranged in the EM block BEM along the first direction x.

[0137] Figure 5 The multiple first scan circuits SCN1-1 to SCN1-m shown can be targeted at Figure 6 Each of the plurality of first scan blocks BSC1 is configured, the plurality of second scan circuits SCN2-1 to SCN2-m can be configured for each of the plurality of second scan blocks BSC2, and the plurality of EM circuits EMD-1 to EMD-m can be configured for each of the plurality of EM blocks BEM.

[0138] For example, Figure 5 All of the multiple first scanning circuits SCN1-1 to SCN1-m shown can be set to Figure 7 In the first scan block BSC1 shown.

[0139] For example, such as Figure 7 As shown, the first-1 scan circuit SCN1-1 to the first-4 scan circuit SCN1-4 can be arranged along the first direction x in the first scan block BSC1. The first-5 scan circuit SCN1-5 to the first-8 scan circuit SCN1-8 can be arranged along the first direction x in the first scan block BSC1, but are not limited thereto, and can be positioned below the first-1 scan circuit SCN1-1 to the first-4 scan circuit SCN1-4 in the second direction y. In this way, Figure 5 The first-1 scan circuit SCN1-1 to the first-m scan circuit SCN1-m can be set in each first scan block BSC1.

[0140] The first-1 scanning circuit SCN1-1 can be electrically connected to the first-1 gating line GL11 of the first row R1, and the first-1 gating line GL11 can be electrically connected to multiple sub-pixels PXL located in the pixel area AP of the first row R1.

[0141] The first-1 scan signal SC1(1) generated by the first-1 scan circuit SCN1-1 can be supplied to multiple sub-pixels PXL in the pixel area AP set in the first row R1.

[0142] The first-2 scanning circuit SCN1-2 can be electrically connected to the first-2 gate line GL12 of the second row R2, and the first-2 gate line GL12 can be electrically connected to multiple sub-pixels PXL located in the pixel area AP of the second row R2.

[0143] The first-2 scan signal SC1(2) generated by the first-2 scan circuit SCN1-2 can be supplied to multiple sub-pixels PXL located in the pixel area AP of the first row R1. The first-1 scan signal SC1(1) generated by the first-1 scan circuit SCN1-1 can be input to the first-2 scan circuit SCN1-2 as a start signal. In addition, the first-2 gate line GL12 can overlap with the first-1 scan circuit SCN1-1, but they are not electrically connected to each other.

[0144] In this way, Figure 5 The first-1 scan circuit SCN1-1 to the first-m scan circuit SCN1-m can be set in each first scan block BSC1.

[0145] Figure 5 All of the multiple second scanning circuits SCN2-1 to SCN2-m shown can be set to Figure 7 In a second scan block BSC2 shown.

[0146] For example, such as Figure 7 As shown, the second-1 scan circuits SCN2-1 to the second-5 scan circuits SCN2-5 can be arranged along the first direction x in the second scan block BSC2. The second-6 scan circuits SCN2-6 to the second-10 scan circuits SCN2-10 can be arranged along the first direction x in the second scan block BSC2, but are not limited thereto, and can be positioned below the second-1 scan circuits SCN2-1 to the second-5 scan circuits SCN2-5 in the second direction y. In this way, Figure 5 The second-1 scanning circuit SCN2-1 to the second-m scanning circuit SCN2-m can be set in each second scanning block BSC2.

[0147] Similar to the first scanning circuit SCN1, Figure 5 The second-1 scan circuit SCN2-1 to the second-m scan circuit SCN2-m shown can be electrically connected to the second gate line GL2 of each of the first row R1 to the m-th row (not shown), and can be electrically connected to the sub-pixels PXL arranged in the pixel region AP of each row to supply the second scan signal SC2(n). In this way, Figure 5 The second-1 scanning circuit SCN2-1 to the second-m scanning circuit SCN2-m can be set in each second scanning block BSC2.

[0148] Figure 5 All of the multiple EM circuits shown, EMD-1 to EMD-m, can be set to... Figure 7 The image shows an EM block BEM.

[0149] For example, such as Figure 7 As shown, the first-1 EM circuits EMD-1 to the first-4 EM circuits EMD-4 can be arranged along the first direction x in the EM block BEM. The first-5 EM circuits EMD-5 to the first-8 EM circuits EMD-8 can be arranged along the first direction x in the EM block BEM, but are not limited thereto, and can be positioned below the first-1 EM circuits EMD-1 to the first-4 EM circuits EMD-4 in the second direction y. In this way, Figure 5The first-1 EM circuit EMD-1 to the first-m EM circuit EMD-m can be set in each EM block BEM.

[0150] Similar to the first and second scanning circuits, Figure 5 The first-1 EM circuit EMD-1 to the first-m EM circuit EMD-m shown can be electrically connected to the third gate line GL3 of the first row R1 to the m-th row (not shown), and can be electrically connected to multiple sub-pixels PXL set in the pixel area AP of each row to supply the light emission control signal EM(n). In this way, Figure 5 The first-1 EM circuit EMD-1 to the first-m EM circuit EMD-m can be set within each EM block BEM.

[0151] As described above, the first scanning circuit SCN1, the second scanning circuit SCN2, and the EM circuits EMD-1 to EMD-8 can be distributed and disposed in the first scanning block BSC1, the second scanning block BSC2, and the EM block BEM arranged in the display area AA, respectively.

[0152] Each first scan block BSC1 can output multiple first scan signals SC1(n) to both sides in the first direction x. Each second scan block BSC2 can output multiple second scan signals SC2(n) to both sides in the first direction x. Each EM block BEM can output multiple light emission control signals EM(n) to both sides in the first direction x.

[0153] The recessed area NC in the display panel 100 may include a top surface NC-S1 extending in the first direction x, and inclined surfaces NC-S2a and NC-S2b at the ends of the top surface NC-S1 in a direction intersecting the first and second directions.

[0154] When Figure 6 When the notch region NC is set as shown, the multiple first upper gate lines GL1-u arranged above the notch region NC may include multiple open-circuit portions COP, some of which are disconnected and open-circuited. The open-circuit ends of the first upper gate lines GL1-u may be spaced apart from the open-circuit portions COP in the first direction x.

[0155] like Figure 6 As shown, the multiple open-circuit portions COP included in the multiple first upper select lines GL1-u can be configured to be adjacent to the portions of the top surface NC-S1 of the notch region NC and the inclined surfaces NC-S2a and NC-S2b of the notch region NC that are connected to each other.

[0156] In detail, such as Figure 6As shown, the first scan block BSC1 distributed and set in the display area AA may include first blocks B1 and B3 and second blocks B2 and B4.

[0157] The first blocks B1 and B3, and the second blocks B2 and B4, may be spaced apart from each other in the first direction x, and may each extend in the second direction y. The top surface NC-S1 may be disposed in the extended portion of the first blocks B1 and B3, and the inclined surfaces NC-S2a and NC-S2b may be disposed in the extended portion of the second blocks B2 and B4.

[0158] As in Figure 6 In this configuration, multiple open-circuit sections (COPs) can be arranged between the first B1 and B3 and the second B2 and B4.

[0159] In embodiments of this disclosure, multiple open-circuit portions COP can be configured to be adjacent to the portions of the notch region NC that contact the top surface NC-S1 and the inclined surfaces NC-S2a and NC-S2b. Therefore, the brightness difference between the side and upper regions of the notch region NC can be reduced, thereby improving image quality.

[0160] exist Figure 6 The present invention will be described using the case where multiple open-circuit portions COP are disposed between the first block B1 and B3 disposed on the top surface NC-S1 and the second block B2 and B4 disposed on the inclined surfaces NC-S2a and NC-S2b as an example, but the embodiments disclosed herein are not limited thereto.

[0161] For example, when the first scan block BSC1 is not set on the inclined surfaces NC-S2a and NC-S2b but is set outside the inclined surfaces NC-S2a and NC-S2b, multiple open-circuit portions COP can be set between the first scan block BSC1 set above the top surface NC-S1 and the first scan block BSC1 set outside the inclined surfaces NC-S2a and NC-S2b, with the inclined surfaces NC-S2a and NC-S2b located therebetween.

[0162] Figure 8 yes Figure 6 An enlarged view of section K3 in order to describe in more detail the first and second blocks of the first scan block and the open portion included in each of the first strobe lines.

[0163] exist Figure 8 For ease of understanding, the diagram illustrates the first block B1 and the second block B2, multiple first gating lines GL11-1y, and multiple open sections COP1 to COPk-1, while the diagrams of the second scan block BSC2, the second gating line GL2, the EM block BEM, the third gating line GL3, multiple pixel regions AP, and multiple circuit regions AG are omitted.

[0164] like Figure 8 As shown, multiple first scanning circuits SCN1 can be disposed in the first block B1 of the first scanning block BSC1, and multiple first scanning circuits SCN1 can be disposed in the second block B2 of the first scanning block BSC1. Since the lengths of the first block B1 and the second block B2 are different in the second direction y, the number of first scanning circuits SCN1 disposed in the first block B1 can be different from the number of first scanning circuits SCN1 disposed in the second block B2.

[0165] Multiple first scan circuits SCN1 disposed in the first block B1 can be connected to multiple first upper gate lines GL1-u to supply the first scan signal SC1(n), and the first upper gate lines GL1-u can include GL11 to GL1k-1.

[0166] Some of the multiple first scan circuits SCN1 disposed in the second block B2 can be connected to multiple first upper gate lines GL1-u to supply the first scan signal SC1(n), and the first upper gate lines GL1-u can include GL11 to GL1k-1. The multiple first scan circuits SCN1 disposed on the side of the notch region NC can be connected to multiple first side gate lines GL1-s to supply the first scan signal SC1(n), and the first side gate lines GL1-s can include GL1k to GL1y.

[0167] Specifically, each of the first block B1 and the second block B2 may include a first-1 scanning circuit SCN1-1 and a first-2 scanning circuit SCN1-2. In each of the first block B1 and the second block B2, the first-1 scanning circuit SCN1-1 and the first-2 scanning circuit SCN1-2 may be adjacent to each other in the first direction x.

[0168] The first-1 scanning circuit SCN1-1 can be connected to the first line GL11 of the first upper gate line GL1-u and can supply the first scanning signal SC1(n), and the first-2 scanning circuit SCN1-2 can be connected to the second line GL12 of the first upper gate line GL1-u and can supply the first scanning signal SC1(n).

[0169] The first open-circuit portion COP1 can be located between the first -1 scan circuit SCN1-1 of the first block B1 and the first -1 scan circuit SCN1-1 of the second block B2 on the first line GL1-u, and the second open-circuit portion COP2 can be located between the first -2 scan circuit SCN1-2 of the first block B1 and the first -2 scan circuit SCN1-2 of the second block B2 on the second line GL1-u.

[0170] The first length L1 from the first-1 scan circuit SCN1-1 of the first block B1 to the first open section COP1 can be equal to the second length L2 from the first-1 scan circuit SCN1-1 of the second block B2 to the first open section COP1.

[0171] For example, in the first line GL11, the number of sub-pixels PXL or pixel regions AP disposed between the first open portion COP1 and the first-1 scan circuit SCN1-1 of the first block B1 can be the same as the number of sub-pixels PXL or pixel regions AP disposed between the first open portion COP1 and the first-1 scan circuit SCN1-1 of the second block B2.

[0172] Furthermore, the third length L3 from the first-2 scan circuit SCN1-2 of the first block B1 to the second open portion COP2 of the first block B1 can be equal to the fourth length L4 from the first-2 scan circuit SCN1-2 of the second block B2 to the second open portion COP2.

[0173] For example, in the second line GL12, the number of sub-pixels PXL or pixel regions AP disposed between the first-2 scan circuit SCN1-2 and the second open portion COP2 of the first block B1 can be the same as the number of sub-pixels PXL or pixel regions AP disposed between the first-2 scan circuit SCN1-2 and the second open portion COP2 of the second block B2.

[0174] The first open-circuit portion COP1 and the second open-circuit portion COP2 may not be located on the same line in the second direction y, and may be spaced apart from each other in the first direction x, or may be staggered. For example, when the first open-circuit portion COP1 and the second open-circuit portion COP2 are located in the circuit region AG, the first open-circuit portion COP1 and the second open-circuit portion COP2 may be located in different circuit regions AG.

[0175] As described above, in this disclosure, the first length L1 and the second length L2 can be equal to each other, and the third length L3 and the fourth length L4 can be equal to each other. Therefore, the output characteristics of the first scan signal SC1(n) output from the first block B1 and the second block B2 in the direction of the first open portion COP1 and the second open portion COP2 can be equal to each other, thereby improving the image quality.

[0176] The following will describe an example of the first scanning circuit, the second scanning circuit, and the EM circuit EMD set in the display area AA.

[0177] Figure 9 It is a diagram used to describe the configuration of each of the first and second scan circuits, and Figure 10 It is used to describe Figure 9 The diagram shows an example of a first and second scanning circuit applied to multiple first and second circuit regions.

[0178] Figure 9 The first scanning circuit SCN1 shown may be an example, and the configuration of the first scanning circuit SCN1 according to embodiments of this disclosure is not limited to... Figure 9 Furthermore, the first scanning circuit SCN1 can be configured in various ways.

[0179] Figure 9 The first-n scan circuit SCN1-n can be the first scan circuit SCN1 of the nth stage. Therefore, Figure 9 The first-n scan circuit SCN1-n shown can be applied to the reference. Figures 5 to 8 The first scan circuit SCN1 of each stage is described.

[0180] The high voltage VGH, low voltage VGL, current clock signal GCLK(n), previous clock signal GCLK(n-2), start signal GVST or the first scan signal SC1(n-1) of the previous stage, and reset signal QRST can be applied to the first-n scan circuit SCN1-n, and the first-n scan circuit SCN1-n can include a scan output terminal SRO. The scan output terminal SRO can be connected to the nth line of the first gating line GL1 to output the first scan signal SC1(n). For example, when the first-n scan circuit SCN1-n is... Figures 5 to 8 When the first-2 scan circuit SCN1-2 is in operation, the scan output terminal SRO can be connected to the first-3 scan circuit SCN1-3, and the first scan signal SC1(n) can be supplied as the strobe start signal GVST of the first-3 scan circuit SCN1-3.

[0181] like Figure 9 As shown, the first-n scan circuit SCN1-n may include multiple transistors and multiple capacitors connected relative to Q nodes Q_T1 and Q_T6 and QB node QB.

[0182] The multiple transistors may include T1 and T3 through T8 transistors, Tbv transistor, T_QRST transistor, T_QBRST transistor, CQ capacitor and CQB capacitor.

[0183] The first-n scanning circuit SCN1-n may include a first part P1 to a fourth part P4.

[0184] The first part P1 may include transistors T4 and T7, as well as capacitor CQB. The previous clock signal GCLK(n-2), the high-gating voltage VGH, and the low-gating voltage VGL can be supplied to the first part P1. The first part P1 can be connected to the scan output terminal SRO.

[0185] The second part P2 may include transistors T1, T3, T5, and T8. The second part P2 may be supplied with a gating start signal GVST or the first scan signal SC1(n-1) of the previous stage, a gating low voltage VGL, and a gating high voltage VGH.

[0186] The third part, P3, may include transistors T6 and Tbv, as well as capacitor CQ. The third part, P3, can be supplied with the current clock signal GCLK(n) and the gating low voltage VGL. The third part, P3, can be connected to the scan output terminal SRO.

[0187] Part P4 may include a T_QRST transistor and a T_QBRST transistor, and Part P4 may be supplied with a reset signal and a gating high voltage VGH.

[0188] Such a first-n scanning circuit SCN1-n can generate a first scanning signal SC1(n) through the first part P1 to the fourth part P4, and supply the first scanning signal SC1(n) to the nth line of the first gate line GL1.

[0189] The first part P1 to the fourth part P4 of the first-n scanning circuit (SCN1-n) can be, for example, as follows: Figure 10 The circuits are distributed and arranged in multiple first circuit regions AG11 to AG14 as shown.

[0190] exist Figure 10 The example illustrates multiple first gate lines GL11 to GL14 extending in the first direction x and overlapping with multiple pixel regions AP and multiple first circuit regions (AG11 to AG14). However, this may be for ease of understanding, and multiple second gate lines GL21 to GL24 and third gate lines GL31 to GL34 may also extend in the first direction x in each of the first rows R1 to the fourth rows R4 and overlap with multiple pixel regions AP and multiple first circuit regions AG11 to AG14. Furthermore, in Figure 10 In the first gate line GL1, the nth line is called GL11.

[0191] For example, in Figure 9 In the first-n scanning circuit SCN1-n shown, the first part P1 can be set to... Figure 10In the first-1 circuit region AG11, the second part P2 can be set in the first-3 circuit region AG13, the third part P3 can be set in the first-4 circuit region AG4, and the fourth part P4 can be set in the first-2 circuit region AG12.

[0192] The preceding clock signal GCLK(n-2), the high-gating voltage VGH, and the low-gating voltage VGL supplied to the first part P1 can be supplied to multiple lines extending in the second direction y in the first-1 circuit region AG11.

[0193] The reset signal QRST and the high-gating voltage VGH supplied to the fourth section P4 can be supplied to multiple lines extending in the second direction y in the first-2 circuit region AG12. Furthermore, depending on the situation, the low-gating voltage VGL can be further supplied to the lines extending in the second direction y.

[0194] The gating start signal GVST or the first scan signal SC1(n-1) of the previous stage, the gating low voltage VGL and the gating high voltage VGH to be supplied to the second part P2 can be supplied to multiple lines extending in the second direction y in the first-3 circuit region AG13.

[0195] The current clock signal GCLK(n) and the gating low voltage VGL supplied to the fourth part P4 can be supplied to multiple lines extending in the second direction y in the first-4 circuit region AG14. Furthermore, depending on the situation, the high-level drive voltage VDD supplied to the sub-pixel PXL of the pixel region AP can be further supplied to lines extending in the second direction y.

[0196] The scan output terminal SRO of the first-n scan circuit SCN1-n can be connected to both the first part P1 and the third part P3, and can also be connected to the nth line GL11 of the first gate line GL1. Therefore, at each point in the first-1 circuit region AG11 and the first-4 circuit region AG14 that intersects with the line GL11 of the first row R1, the scan output terminal SRO of the first-n scan circuit SCN1-n can be connected thereto.

[0197] Furthermore, multiple sub-pixels PXL arranged in the pixel region AP of the first row R1 can be connected to the nth first gating line GL11, and can be supplied with the first scan signal SC1(n) of the first-n scan circuit SCN1-n through the nth first gating line GL11. Furthermore, in Figure 9 In the first-n scan circuit SCN1-n, for example, the Q_T1 node, which is commonly connected to the second part P2, the third part P3, and the fourth part P4, can be implemented as a Q_T1 line. This Q_T1 line overlaps with the sub-pixel PXL arranged in the pixel region AP and extends in the first direction x. Figure 10 As shown, the Q_T1 line can contact the first-2 circuit region AG12, the first-3 circuit region AG13, and the first-4 circuit region AG14.

[0198] In addition, Figure 9 In the first-n scan circuit SCN1-n, for example, the QB node commonly connected to the first part P1, the second part P2, and the fourth part P4 can be implemented as a QB line, which overlaps with the sub-pixel PXL arranged in the pixel region AP and extends in the first direction x. Figure 10 As shown, the QB line can contact the first-1 circuit region AG11, the first-3 circuit region AG13, and the first-4 circuit region AG14.

[0199] As described above, the first-n scan circuit SCN1-n, which includes multiple driving elements such as multiple transistors and capacitors according to the embodiments of the present disclosure, can be distributed and disposed in multiple first circuit regions AG11 to AG14, and lines such as Q_T1 lines and QB lines that connect the multiple driving elements to each other can extend in the first direction x and can overlap with sub-pixels PXL.

[0200] Furthermore, despite Figure 10 Not shown, but multiple second gate lines GL21 to GL24 and third gate lines GL31 to GL34 can extend in the first direction x and can overlap with multiple first circuit regions AG11 to AG14. However, the multiple second gate lines GL21 to GL24 and third gate lines GL31 to GL34 may not be connected to the multiple first circuit regions AG11 to AG14. Nevertheless, the multiple second gate lines GL21 to GL24 and third gate lines GL31 to GL34 can be connected to multiple sub-pixels PXL arranged between the multiple first circuit regions AG11 to AG14.

[0201] In addition, such as Figure 10 As shown, lines GL12 to GL14 in the first gate line GL1 can extend and overlap with the first-n scan circuit SCN1-n, but are not limited thereto. They can be connected to multiple sub-pixels PXL in the pixel area AP arranged in the second row R2 to the fourth row R4 instead of the first-n scan circuit SCN1-n.

[0202] The first scan signals SC1(n+1) to SC1(n+3) generated from the other first scan circuits SCN1 in the first scan block BSC1, excluding the first-n scan circuit SCN1-n, can be supplied to lines GL12 to GL14 of the first gating line GL12.

[0203] The second scanning circuit SCN2 can be distributed and arranged in multiple second circuit regions AG2, and can generate a second scanning signal SC2(n) to supply the second scanning signal SC2(n) to the second gate line GL2.

[0204] The method by which the second scanning circuit SCN2, included in the second scanning block BSC2, is distributed and disposed in multiple second circuit regions AG2 is similar to the method by which the first scanning circuit SCN1 is disposed in each of multiple first circuit regions AG11 to AG14. Therefore, its description is omitted.

[0205] Figure 11 It is used to describe Figure 7 The diagram shows an example of an EM circuit, and Figure 12 It is used to describe Figure 11 The diagram shows an example of an EM circuit applied to multiple third circuit regions.

[0206] Figure 11 The EM circuit EMD shown is just an example, and the configuration of the EM circuit EMD is not limited to... Figure 11 Furthermore, the EM circuit EMD can be configured in various ways.

[0207] Figure 11 The nth EM circuit EMD-n in the diagram can be the nth level EM circuit EMD. Therefore, Figure 11 The nth EM circuit EMD-n shown can be applied to the reference. Figures 5 to 8 The EM circuit EMD of each stage is described. Therefore, the nth EM circuit EMD-n can generate the light emission control signal EM(n) and supply the light emission control signal EM(n) to the nth line GL31 of the third gating line GL3.

[0208] The EM start signal EVST or the previous stage's light control signal EM(n-1), the high-voltage gate VEH, the low-voltage gate VEL, and multiple EM clock signals ECLK1 and ECLK2 can be supplied to the nth EM circuit EMD-n, and the nth EM circuit EMD-n can include the EM output terminal EMO. When the nth EM circuit EMD-n is Figures 5 to 8 When the second EM circuit EMD is shown, the EM output terminal EMO can be connected to the third EM circuit EMD, and the light emission control signal EM(n) output from the EM output terminal EMO can be supplied as the EM start signal EVST of the third EM circuit EMD.

[0209] like Figure 11 As shown, the nth EM circuit EMD-n may include multiple transistors and a capacitor interconnected with respect to the Q nodes Q_T1 and Q and the QB node QB.

[0210] like Figure 11 As shown, the nth EM circuit EMD-n may include the first part P1 to the fourth part P4.

[0211] The first part P1 may include transistors T6 and T11, as well as transistor CQ. The first part P1 can be supplied with a low-voltage gate, VEL, and can be connected to the EM output terminal, EMO.

[0212] The second part P2 may include transistors T1, T4, T10, and Tbv. The EM start signal EVST or the previous stage's light control signal EM(n), the gating low voltage VEL, and the second EM clock signal ECLK2 can be supplied to the second part P2.

[0213] The third part, P3, may include transistors T2, T3, T8, T9, and Tbv, as well as capacitor CQ'. The first EM clock signal ECLK1 and the gating high voltage VEH can be supplied to the third part, P3.

[0214] Section P4 may include transistors T5 and T7, as well as a CQB capacitor. A high-gating voltage VEH can be supplied to section P4, and the EM output terminal EMO can be connected to section P4.

[0215] The nth EM circuit EMD-n can generate the nth emission control signal EM(n) through the first part P1 to the fourth part P4, and supply the nth emission control signal EM(n) to the nth line of the third gating line GL3. Therefore, the nth EM circuit EMD-n can supply the nth emission control signal EM(n) to the multiple sub-pixels PXL located in the multiple pixel regions AP and connected to the nth line GL31 of the third gating line GL3.

[0216] like Figure 12 As shown, the first part P1 to the fourth part P4 of the nth EM circuit EMD-n can be distributed and set in, for example, multiple third circuit regions AG31 to AG34.

[0217] exist Figure 12 In the example, multiple third gate lines GL31 to GL34 extend in the first direction x and overlap with multiple pixel regions AP and multiple third circuit regions AG3, while multiple first gate lines GL11 to GL14 and second gate lines GL21 to GL24 do not extend in the first direction x. This may be for ease of understanding, and the multiple first gate lines GL11 to GL14 and second gate lines GL21 to GL24 can extend in the first direction x in each of the first rows R1 to the fourth rows R4 and overlap with multiple pixel regions AP and multiple first circuit regions AG11 to AG14. Furthermore, in Figure 12 In the diagram, the nth line of the third gate line GL3 is called GL31.

[0218] For example, in Figure 12 In the nth EM circuit EMD-n shown, the first part P1 can be set... Figure 12 In the third-1 circuit region AG31, the second part P2 can be set in the third-2 circuit region AG32, the third part P3 can be set in the third-3 circuit region AG33, and the fourth part P4 can be set in the third-4 circuit region AG34.

[0219] The low-voltage gate VEL supplied to the first part P1 can be supplied to multiple lines extending in the second direction y in the third-1 circuit region AG31. Furthermore, depending on the situation, the high-voltage gate VEH can be further supplied to the lines extending in the second direction y.

[0220] The EM start signal EVST to be supplied to the second part P2 or the previous stage's light control signal EM(n-1), the gate low voltage VEL, and the second EM clock signal ECLK2 can be supplied to multiple lines extending in the second direction y in the third-2 circuit region AG32.

[0221] The first EM clock signal ECLK1 and the high-gating voltage VEH, which are to be supplied to the second part P2, can be supplied to multiple lines extending in the second direction y in the third-3 circuit region AG33. Furthermore, depending on the situation, the low-gating voltage VEL can be further supplied to the lines extending in the second direction y.

[0222] The high-level gate voltage VEH supplied to the fourth section P4 can be supplied to multiple lines extending in the second direction y in the third-4 circuit region AG34. Furthermore, depending on the situation, the high-level drive voltage VDD to be supplied to the sub-pixel PXL of the pixel region AP can be additionally supplied to the lines extending in the second direction y.

[0223] The EM output terminal EMO of the nth EM circuit EMD-n can be connected to both the first part P1 and the fourth part P4, and can also be connected to the nth third gating line GL31. Therefore, at the point where the third-1 circuit region AG31 and the third-4 circuit region AG34 intersect with the nth third gating line GL31 of the nth row Rn, the EM output terminal EMO of the nth EM circuit EMD-n can be connected to it.

[0224] Furthermore, multiple sub-pixels PXL arranged in the pixel area AP of the first row R1 can be connected to the nth third gating line GL31, and can be supplied with the light emission control signal EM(n) of the nth EM circuit EMD-n through the nth third gating line GL31.

[0225] In addition, for example, such as Figure 12 As shown, in Figure 11 In the nth EM circuit EMD-n, the Q_T1 node connected to the second part P2, the third part P3, and the fourth part P4 of the nth EM circuit EMD-n can be implemented as a Q_T1 line extending in the first direction x and overlapping with the sub-pixel PXL arranged in the pixel region AP. For example... Figure 12 As shown, the Q_T1 line can contact the third-2 circuit region AG32, the third-3 circuit region AG33, and the third-4 circuit region AG34.

[0226] In addition, for example, such as Figure 12 As shown, in Figure 11 In the nth EM circuit EMD-n, the Q node that is commonly connected to the first part P1 and the second part P2 can be implemented as a Q line extending in the first direction x and overlapping with the sub-pixel PXL arranged in the pixel region AP. For example... Figure 12 As shown, the Q line can contact the third-1 circuit region AG31 and the third-2 circuit region AG32.

[0227] In addition, for example, such as Figure 12 As shown, in Figure 11 In the nth EM circuit EMD-n, the QB node that is commonly connected to the third part P3 and the fourth part P4 can be implemented as a QB line extending in the first direction x and overlapping with the sub-pixel PXL arranged in the pixel region AP. For example... Figure 12 As shown, the QB line can contact the third-3 circuit region AG3 and the third-4 circuit region AG34.

[0228] As described above, according to embodiments of this disclosure, the nth EM circuit EMD-n, which includes multiple driving elements such as multiple transistors and capacitors, can be distributed and disposed in multiple third circuit regions AG31 to AG34. Lines such as Q_T1 lines and QB lines that connect the multiple driving elements to each other can extend in the first direction x and can overlap with sub-pixels PXL.

[0229] Furthermore, despite Figure 12As not shown, multiple first gate lines GL11 to GL14 and second gate lines GL21 to GL24 may extend to and overlap with the third circuit regions AG31 to AG34. However, the multiple first gate lines GL11 to GL14 and second gate lines GL21 to GL24 may not be electrically connected to the multiple third circuit regions AG31 to AG34. However, the multiple first gate lines GL11 to GL14 and second gate lines GL21 to GL24 may be connected to multiple sub-pixels PXL arranged between the multiple third circuit regions AG31 to AG34.

[0230] In addition, such as Figure 12 As shown, the GL32 to GL34 lines of the third gate line GL3 can extend and overlap with the nth EM circuit EMD-n, but the GL32 to GL34 lines of the third gate line GL3 are not connected to the nth EM scanning circuit, and can be connected to multiple sub-pixels PXL in the pixel area AP arranged in the second row R2 to the fourth row R4.

[0231] The third gate line GL3, lines GL32 to GL34, can receive light emission control signals EM(n+1) to EM(n+3) supplied from the EM circuits EMD (excluding the nth EM circuit EMD-n) in the EM block BEM.

[0232] Figure 13 yes Figure 8 An enlarged view of part K4 in the image, and Figure 14 It is along Figure 13 A cross-sectional view of the section cut by line CS-CS' in the diagram.

[0233] like Figure 13 As shown, the first upper gate line GL1-u may include an open-circuit portion COP at the portion adjacent to the inclined surfaces NC-S2a and NC-S2b of the notch region NC. The ends of the first upper gate line GL1-u that are interrupted by the open-circuit portion COP may be spaced apart from each other in the first direction x.

[0234] The open portion COP of the first uppass line GL1-u can be located in one of the multiple circuit regions AG, excluding the first circuit region AG1. For example, the open portion COP of the first uppass line GL1-u can be configured to overlap with one of the second circuit region AG2 or the third circuit region AG3.

[0235] The pixel region AP containing the sub-pixel PXL can be located on two sides of a circuit region, and the first upper gate line GL1-u, the second upper gate line GL2-u, and the third upper gate line GL3-u can overlap with the sub-pixel PXL.

[0236] However, the second upper gate line GL2-u and the third upper gate line GL3-u may not include an open-circuit portion COP in the region adjacent to the inclined surfaces NC-S2a and NC-S2b of the notch region NC. However, embodiments of this disclosure are not limited to this, and depending on the circumstances, similar to the first upper gate line GL1-u, the second upper gate line GL2-u and the third upper gate line GL3-u may also include an open-circuit portion COP in the portion adjacent to the inclined surfaces NC-S2a and NC-S2b of the notch region NC.

[0237] exist Figure 13 In the example, the width d of the open portion COP is less than the spacing between the lines that transmit the gate low voltage VEL, clock signal CLK, or high-level drive voltage VDD in the second circuit region AG2 or the third circuit region AG3. However, the embodiments of this disclosure are not limited to this, and the width d of the open portion COP can be equal to or greater than the spacing between the lines provided in the circuit region AG.

[0238] like Figure 14 As shown, in the second circuit region AG2 or the third circuit region AG3, the first upper gate line GL1-u can extend along the first direction x on the gate insulating layer 150, the open portion COP can be disposed on the gate insulating layer 150, and the open end of the first upper gate line GL1-u can be covered by the interlayer insulating layer 200.

[0239] Therefore, the two ends of the first upper select line GL1-u, which are separated by the open-circuit portion COP, can be insulated from each other by the interlayer insulation layer 200.

[0240] A line extending along the second direction y from the second circuit region AG2 or the third circuit region AG3 and receiving the pass voltage VEL, clock signal CLK, or high-level drive voltage VDD can be disposed between the interlayer insulation layer 200 and the planarization layer 300.

[0241] Figure 15A and Figure 15B It is a diagram used to describe the effect based on the open circuit portion.

[0242] As described above, when an open-circuit portion COP is provided in the first upper gate line GL1-u, so that it is adjacent to the portion of the notch region NC where the top surface NC-S1 and the inclined surfaces NC-S2a and NC-S2b are connected to each other, the output characteristics of the first scan signal SC1(n) supplied to the first upper gate line GL1-u and the first scan signal SC1(n) supplied to the first side gate line GL1-s can be adjusted to be almost equal to each other. Therefore, the brightness of the side region and the upper region of the notch region NC can be adjusted to be almost equal to each other, thereby further improving the image quality.

[0243] In detail, Figure 15A and Figure 15B In this context, line GL1k-1 can be one of the first upper gate lines GL1-u, and line GL1k can be one of the first side gate lines GL1-s. Point P of the first upper gate line GL1-u and the first side gate line GL1-s can be a point adjacent to the point where the top surface NC-S1 and the inclined surfaces NC-S2a and NC-S2b of the notch region NC meet each other. For example, point P can be a point that is horizontally adjacent to the point where the top surface NC-S1 and the inclined surfaces NC-S2a and NC-S2b of the notch region NC meet each other in the first direction x, and can be spaced apart from that point in the second direction y. (Refer to the above...) Figure 8 The first scan block B1 and the second scan block B2 of the first scan block BSC1 described herein can be located on both sides of point P. Point P can be the midpoint of the first scan circuit SCN1 located in each of the first scan blocks B1 and B2.

[0244] like Figure 15A As shown, when the first upper select line GL1-u is not provided with an open section COP, the first scan signal SC1(k-1) can be supplied from both sides of the first block B1 and the second block B2 to the GL1k-1 line provided above the notch region NC. However, the GL1k line provided on the side of the notch region NC can receive the first scan signal SC1(k) from the second block B2 other than the first block B1.

[0245] Therefore, the output characteristics of the first scan signal SC1(k-1) at point P and the output characteristics of the first scan signal SC1(k) at point P can be different.

[0246] For example, the first scan signal SC1(k-1) supplied to point P can be fed from both the first block B1 and the second block B2 of the first scan block BSC1. Therefore, the rate of decrease and increase of the voltage of the first scan signal SC1(k-1) can be relatively greater than the rate of decrease and increase of the voltage of the first scan signal SC1(k).

[0247] Therefore, the driving current of the sub-pixel PXL located in the side region of the notch region NC can differ from the driving current of the sub-pixel PXL located in the upper region, resulting in brightness deviation. Consequently, image quality may deteriorate.

[0248] However, as Figure 15B As shown, when the first upper select line GL1-u includes the open circuit portion COP at point P, the difference in output characteristics between the first scan signal SC1(k-1) and the first scan signal SC1(k) at point P can be reduced. Therefore, the drive current deviation and brightness deviation can be reduced, thereby further improving the image quality.

[0249] As described above, when the display panel includes a notch area, embodiments of this disclosure may include an open-circuit portion that opens a portion of the first upper select line, thereby improving the brightness deviation between the side and top of the notch area in the display area, thereby enhancing the quality of the display screen.

[0250] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0251] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0252] Cross-reference to related applications

[0253] This application claims priority and benefit to Korean Patent Application No. 10-2025-0057148, filed on April 30, 2025, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display panel, the display panel comprising: The display area includes a plurality of pixel areas arranged spaced apart from each other in a first direction and a plurality of circuit areas arranged between the plurality of pixel areas; Sub-pixels, wherein the sub-pixels are disposed in each of the plurality of pixel regions and are configured to receive a data voltage based on a first scan signal supplied via a first gate line extending in the first direction to allow the light-emitting device to emit light; as well as A plurality of first scan blocks are distributed and disposed in the display area, and each of the plurality of first scan blocks includes a first scan circuit, which is disposed in a plurality of first circuit regions and configured to generate a first scan signal to supply the first scan signal to the first gating line. The display area includes a notch area, in which a portion of the display area is recessed in a second direction intersecting the first direction. The plurality of first selection lines include a plurality of first side selection lines and a plurality of first upper selection lines. The plurality of first side selection lines are correspondingly disposed to the notch region and each includes an end adjacent to the notch region. The plurality of first upper selection lines are disposed above the notch region in the second direction. The plurality of first upper gate lines include a plurality of open sections, in which a portion of the first upper gate line is disconnected and open-circuited.

2. The display panel according to claim 1, wherein, The notch region includes a top surface extending in the first direction and an inclined surface at the end of the top surface that slopes in a direction intersecting the first and second directions. The plurality of open portions included in the plurality of first upper select lines are configured to be adjacent to the portions of the top surface and the inclined surface that are in contact with each other in the first direction.

3. The display panel according to claim 2, wherein, The first scan block includes a first block and a second block spaced apart from each other in the first direction and extending in the second direction. The first block includes an extension disposed above the top surface, and the second block includes an extension disposed above the inclined surface or outside the inclined surface. The plurality of open sections are disposed between the first block and the second block.

4. The display panel according to claim 3, wherein, Each of the first block and the second block includes: A first-1 scan circuit, configured to supply the first scan signal to a first line in the first upper gate line; and The first-2 scanning circuit is configured to be adjacent to the first-1 scanning circuit in the first direction and to supply the first scanning signal to the second line in the first upper strobe line.

5. The display panel according to claim 4, wherein, The plurality of open-circuit sections include a first open-circuit section and a second open-circuit section. The first open-circuit portion is disposed on the first line between the first -1 scan circuit of the first block and the first -1 scan circuit of the second block, and The second open-circuit portion is disposed on the second line between the first-2 scan circuit of the first block and the first-2 scan circuit of the second block.

6. The display panel according to claim 5, wherein, The first length from the output terminal of the first-1 scan circuit of the first block to the first open-circuit portion is equal to the second length from the output terminal of the first-1 scan circuit of the second block to the first open-circuit portion, and The third length from the output terminal of the first-2 scan circuit of the first block to the second open portion is equal to the fourth length from the output terminal of the first-2 scan circuit of the second block to the second open portion.

7. The display panel according to claim 5, wherein, In the first line, the number of pixel regions or sub-pixels disposed between the first open-circuit portion and the output terminal of the first-1 scan circuit of the first block is equal to the number of pixel regions or sub-pixels disposed between the first open-circuit portion and the output terminal of the first-1 scan circuit of the second block, and In the second line, the number of pixel regions or sub-pixels disposed between the second open portion and the output terminal of the first-2 scan circuit of the first block is equal to the number of pixel regions or sub-pixels disposed between the second open portion and the output terminal of the first-2 scan circuit of the second block.

8. The display panel according to claim 5, wherein, The first open portion and the second open portion are spaced apart from each other in the first direction.

9. The display panel according to claim 3, wherein, Some of the first scanning circuits disposed in the second block, located above the inclined surface in the notch region, supply the first scanning signal to the first side gate line.

10. The display panel according to claim 4, wherein, The plurality of first circuit regions and the plurality of pixel regions are arranged alternately in each of the first block and the second block, and Each of the first-1 scanning circuit and the first-2 scanning circuit is distributed and disposed in the plurality of first circuit regions.

11. The display panel according to claim 1, wherein, The sub-pixels include: A semiconductor layer disposed on a buffer layer on a substrate; A gate insulating layer, which covers the buffer layer and is disposed on the semiconductor layer; A gate electrode, wherein the gate electrode is disposed on the gate insulating layer and overlaps with the semiconductor layer; An interlayer insulating layer is disposed on the gate insulating layer and covers the gate electrode; A source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed on the interlayer insulating layer and connected to the semiconductor layer; A planarization layer, wherein the planarization layer is disposed on the interlayer insulating layer and covers the source electrode and the drain electrode; and A first electrode is disposed on the planarization layer, connected to one of the source electrode and the drain electrode, and included in the light-emitting device.

12. The display panel according to claim 11, wherein, The first upper gate line extends along the first direction on the gate insulating layer, and the open portion is disposed on the gate insulating layer.

13. The display panel according to claim 1, wherein, The plurality of open-circuit portions are disposed in one of the plurality of circuit regions other than the plurality of first circuit regions.

14. The display panel according to claim 1, wherein, The sub-pixel is also connected to a second gate line that extends in the first direction and receives a second scan signal that controls the supply of a reference voltage. The sub-pixel further includes a second scan block, which is distributed and disposed among the first scan blocks in the display area, and in multiple second circuit areas other than the multiple first circuit areas, and each includes a second scan circuit. The second scan circuit is configured to generate the second scan signal and supply the second scan signal to the second gate line. The plurality of second selection lines include a plurality of second side selection lines and a plurality of second upper selection lines. The plurality of second side selection lines are correspondingly disposed to the notch region and each includes an end adjacent to the notch region. The plurality of second upper selection lines are disposed above the notch region in the second direction. The open section is not located in the portion of the second upper selector line adjacent to the inclined surface of the notch region.

15. The display panel according to claim 1, wherein, The sub-pixel is also connected to a third gate line, which extends in the first direction and receives a light-emitting control signal that controls whether the light-emitting device is allowed to emit light. The sub-pixel further includes an EM block, which is distributed and disposed between the first and second scan blocks in the display area, and in multiple third circuit regions other than the first and second circuit regions among the multiple circuit regions. Each EM block includes an EM circuit, which is configured to generate the light emission control signal and supply the light emission control signal to the third gate line. The plurality of third gate lines include a plurality of third side gate lines and a plurality of third upper gate lines. The plurality of third side gate lines are correspondingly disposed to the notch region and each includes an end adjacent to the notch region. The plurality of third upper gate lines are disposed above the notch region in the second direction. The open section is not located in the portion of the third upper gate line adjacent to the inclined surface of the notch region.

16. The display panel according to claim 1, wherein, The open ends of the first upper selector line are spaced apart from each other in the first direction.

17. A display panel, the display panel comprising: The display area includes multiple pixel areas and multiple circuit areas. The multiple pixel areas are arranged spaced apart from each other in a first direction and multiple sub-pixels are provided in the multiple pixel areas. The multiple circuit areas are arranged between the multiple pixel areas. as well as A gating driver, distributed and disposed in the plurality of circuit regions and configured to generate a first scan signal to supply the first scan signal to the sub-pixel via a plurality of first gating lines respectively. The display area includes a notch area, in which a portion of the display area is recessed in a second direction intersecting the first direction. The plurality of first selection lines include a plurality of first side selection lines and a plurality of first upper selection lines. The plurality of first side selection lines are arranged corresponding to the notch region, and the plurality of first upper selection lines are arranged above the notch region in the second direction. The plurality of first upper gate lines include a plurality of open sections, in which a portion of the first upper gate line is disconnected and open-circuited.

18. A display device, the display device comprising: The display panel according to any one of claims 1 to 17; as well as A data driver configured to supply data voltage to the sub-pixel.

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