Display panel and pixel driving circuit
Patent Information
- Application Number
- CN202610603491.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-30
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]然而，栅极驱动单元的设置会占用显示面板的边框空间，不利于实现窄边框
[0016]综上所述，在本公开中，首先，隔离电路对驱动电流路径与第一节点进行隔离，防止不同阶段的信号相互干扰。然后，通过将第一发光控制电路和第二发光控制电路分别与栅极驱动器中不同级的第一驱动单元连接，可利用同一栅极驱动单元的不同级的输出信号实现两个第一发光控制电路和第二发光控制电路的独立控制，无需为第一发光控制电路和第二发光控制电路分别设置独立的栅极驱动单元。如此，在发光阶段内通过驱动第一发光控制电路和第二发光控制电路的任意一者导通，在实现两种发光模式的切换的情况下，可减少栅极驱动器的驱动单元组数实现窄边框化。
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Figure CN123016889A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of privacy protection driving technology, and in particular to a display panel and pixel driving circuit. Background Technology
[0002] With the popularization of mobile smart terminals, users' demand for privacy protection of display panels is increasing. To address the privacy protection needs of display panels, the display mode can be switched by controlling the light emission state of different light-emitting elements in the display area. That is, the pixel driving unit is used to drive the privacy light-emitting elements and non-privacy light-emitting elements respectively.
[0003] Currently, the method of implementing privacy mode through pixel driving unit requires setting up light emission control circuits for each type of light emission element and equipping each light emission control circuit with an independent gate driving unit during the display of each frame of image, since there are two types of light emission elements: privacy light emission element and non-privacy light emission element. This is to achieve independent control of the two types of light emission elements.
[0004] However, the setup of the gate driving unit will occupy the bezel space of the display panel, which is not conducive to achieving a narrow bezel. Summary of the Invention
[0005] This disclosure provides a display panel to at least partially solve the above-mentioned technical problems.
[0006] To achieve the above objectives, according to a first aspect of the present disclosure, a display panel is provided, including a gate driver, a pixel driving unit connected to the gate driver, a first light-emitting element and a second light-emitting element connected to the pixel driving unit; The gate driver includes a plurality of cascaded first driving units; The pixel driving unit includes a first light-emitting control circuit, a second light-emitting control circuit, and an isolation circuit; One end of the isolation circuit is used to connect to the driving current provided by the first voltage source, and the second end is connected to the first light-emitting control circuit and the second light-emitting control circuit at the first node. The first light-emitting control circuit is connected to the anode of the first light-emitting element, and the second light-emitting control circuit is connected to the anode of the second light-emitting element; The first light-emitting control circuit and the second light-emitting control circuit are respectively connected to the first driving unit at different levels; during the light-emitting phase of the display cycle of the pixel driving unit, the first driving unit drives either the first light-emitting control circuit or the second light-emitting control circuit to be turned on.
[0007] Optionally, the first light-emitting control circuit includes a first transistor, and the second light-emitting control circuit includes a second transistor; The first transistor includes a first electrode connected to the first node, a second electrode connected to the first light-emitting element, and a control electrode connected to the first driving unit of the Nth stage to access the light-emitting selection signal of the Nth stage; The second transistor includes a first electrode connected to the first node, a second electrode connected to the second light-emitting element, and a control electrode connected to the first driving unit of the Na-th stage to access the light-emitting selection signal of the Na-th stage; wherein, N and a are positive integers; The first transistor and the second transistor are of different types.
[0008] Optionally, a is less than or equal to 150.
[0009] Optionally, when the pixel driving unit is operating in the first light emission mode, during the light emission stage, the first driving unit at the Na level outputs a light emission selection signal at the Na level to drive the second transistor to turn off, and the first driving unit at the N level outputs a light emission selection signal at the N level to drive the first transistor to turn on, so that the first light emission element emits light. When the pixel driving unit operates in the second light emission mode, during the light emission stage, the first driving unit of the Na-th stage outputs the Na-th stage light emission selection signal to drive the second transistor to turn on, and the first driving unit of the N-th stage outputs the N-th stage light emission selection signal to drive the first transistor to turn off, so that the second light emission element emits light.
[0010] Optionally, the pixel driving unit further includes a third light-emitting control circuit and a driving transistor connected between the first voltage source and the isolation circuit; the gate driver includes a second driving unit; The driving transistor includes a first electrode connected to the second node of the third light-emitting control circuit and a second electrode connected to the third node of the isolation circuit; The third light-emitting control circuit includes a third transistor, which includes a first electrode connected to the first voltage source, a second electrode connected to the second node, and a control electrode connected to the second driving unit to receive the light-emitting control signal. During the light-emitting stage, the second driving unit outputs the light-emitting control signal to drive the third transistor to turn on, so that the driving current provided by the first voltage source is transmitted to the driving transistor. The pixel driving unit further includes a first reset circuit connected to the second node; the gate driver includes a third driving unit. The first reset circuit includes a fourth transistor, which includes a first electrode connected to a first reset voltage, a second electrode connected to the second node, and a control electrode connected to the third driving unit to receive a reset control signal. The display cycle of the pixel driving unit also includes a first reset phase before the light emission phase; in the first reset phase, the third driving unit outputs the reset control signal to drive the fourth transistor to turn on, so as to reset the second node through the first reset voltage.
[0011] Optionally, the isolation circuit includes a fifth transistor; the fifth transistor includes a first electrode connected to the driving transistor at the second node, a second electrode connected to the first node, and a control electrode connected to the second driving unit to access the light emission control signal; The pixel driving unit further includes a second reset circuit for resetting the anodes of the first light-emitting element and the second light-emitting element.
[0012] Optionally, the second reset circuit includes a first reset transistor and a second reset transistor; The first reset transistor includes a first electrode that receives a second reset voltage, a second electrode that is connected to the anode of the first light-emitting element, and a control electrode that is connected to the third driving unit to receive the reset control signal; The second reset transistor includes a first electrode that is connected to the second reset voltage, a second electrode that is connected to the anode of the second light-emitting element, and a control electrode that is connected to the third driving unit to receive the reset control signal; In the first reset phase, the third driving unit outputs the reset control signal to drive the first reset transistor and the second reset transistor to conduct, so as to perform anodizing reset on the first light-emitting element and the second light-emitting element respectively by the second reset voltage; During the light-emitting phase, the second driving unit outputs the light-emitting control signal to drive the fifth transistor to conduct, so as to transmit the driving current transmitted by the driving transistor to the first node.
[0013] Optionally, the second reset circuit includes a third reset transistor; The third reset transistor includes a first electrode that receives a second reset voltage, a second electrode that is connected to the first node, and a control electrode that is connected to the third driving unit to receive the reset control signal; In the first reset phase, the third driving unit outputs the reset control signal to drive the third reset transistor to conduct, so as to reset the first node through the second reset voltage; the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive one of the second transistor and the first transistor to conduct, so as to perform an anode reset on one of the first light-emitting element and the second light-emitting element through the second reset voltage of the first node.
[0014] Optionally, the isolation circuit includes a fifth transistor; the gate driver further includes a fourth driving unit; The fifth transistor includes a first electrode connected to the second node of the driving transistor, a second electrode connected to the first node, and a control electrode connected to the fourth driving unit to access an isolation control signal; When the pixel driving unit is operating in the first light emission mode, during the first reset phase, the fourth driving unit outputs the isolation control signal to drive the fifth transistor to turn on, the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage to drive the second transistor to turn off, and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive the first transistor to turn on, so that the first reset voltage of the second node resets the anode of the first light emission element through the driving transistor, the fifth transistor and the first transistor; When the pixel driving unit operates in the second light emission mode, during the first reset phase, the fourth driving unit outputs the isolation control signal to drive the fifth transistor to turn on, the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage to drive the second transistor to turn on, and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive the first transistor to turn off, so that the first reset voltage of the second node resets the anode of the second light emission element through the driving transistor, the fifth transistor, and the second transistor.
[0015] According to a second aspect of this disclosure, a pixel driving circuit is provided, including the display panel described above.
[0016] In summary, in this disclosure, firstly, the isolation circuit isolates the drive current path from the first node to prevent signal interference between different stages. Then, by connecting the first and second light-emitting control circuits to different stages of the first driving unit in the gate driver, the output signals of different stages of the same gate driving unit can be used to achieve independent control of the two first and second light-emitting control circuits, eliminating the need for separate gate driving units for each circuit. Thus, by driving either the first or second light-emitting control circuit to conduct during the light-emitting stage, switching between two light-emitting modes can be achieved, reducing the number of driving unit groups in the gate driver and enabling a narrow bezel design.
[0017] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this disclosure. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.
[0018] To gain a more complete understanding of this disclosure and its beneficial effects, the following description will be made in conjunction with the accompanying drawings, wherein the same reference numerals denote the same parts in the following description.
[0019] Figure 1 This is a circuit connection diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 2 This is a current path diagram of the light emission stage in the first light emission mode provided in the exemplary embodiment of this disclosure; Figure 3 This is a timing diagram of the first light emission mode provided in the exemplary embodiments of this disclosure; Figure 4 This is a current path diagram of the light emission stage in the second light emission mode provided in the exemplary embodiments of this disclosure; Figure 5 This is a timing diagram of the second light emission mode provided in the exemplary embodiments of this disclosure; Figure 6 This is a current path diagram of the reset phase provided in an exemplary embodiment of this disclosure; Figure 7 This is a circuit connection diagram of another pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 8This is a current path diagram of the reset phase in another pixel driving circuit provided in an exemplary embodiment of this disclosure. Figure 9 This is a circuit connection diagram of yet another pixel driving circuit provided in an exemplary embodiment of this disclosure; Figure 10 This is a timing diagram of another pixel driving circuit provided in an exemplary embodiment of this disclosure in a first light emission mode; Figure 11 This is another current path diagram of a pixel driving circuit during the reset phase provided in an exemplary embodiment of this disclosure; Figure 12 This is another current path diagram of a pixel driving circuit in the light-emitting stage provided in an exemplary embodiment of this disclosure; Figure 13 This is an architectural diagram of a display panel provided in an exemplary embodiment of this disclosure.
[0020] Explanation of reference numerals in the attached figures: T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T61, first reset transistor; T62, second reset transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; A, first node; B, second node; C, third node; Q, fourth node; D1, first light-emitting element; D2, second light-emitting element; EM2, light-emitting control signal; Pscan2, reset control signal; EM3, isolation control signal; Pscan, write control signal; Nscan, reset drive signal; Nscan2, connection control signal; 1, first light-emitting control circuit; 2, second light-emitting control circuit; 3, isolation circuit; 4, third light-emitting control circuit; 5, first reset circuit; 6, second reset circuit; 7, write circuit; 8, reset circuit; 9, connection circuit. Detailed Implementation
[0021] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the protection scope of this disclosure.
[0022] Reference Figure 1According to a first aspect of this disclosure, a display panel is provided, including a gate driver, a pixel driving unit connected to the gate driver, and a first light-emitting element D1 and a second light-emitting element D2 connected to the pixel driving unit. The gate driver includes a plurality of cascaded first driving units. The pixel driving unit includes a first light-emitting control circuit 1, a second light-emitting control circuit 2, and an isolation circuit 3. One end of the isolation circuit 3 is used to receive a driving current provided by a first voltage source, and the second end is connected to the first light-emitting control circuit 1 and the second light-emitting control circuit 2 at a first node A. The first light-emitting control circuit 1 is connected to the anode of the first light-emitting element D1, and the second light-emitting control circuit 2 is connected to the anode of the second light-emitting element D2.
[0023] The first light-emitting control circuit 1 and the second light-emitting control circuit 2 are respectively connected to different levels of the first driving unit. During the light-emitting phase of the display cycle of the pixel driving unit, the first driving unit drives either the first light-emitting control circuit 1 or the second light-emitting control circuit 2 to conduct.
[0024] As an example, one of the first light-emitting element D1 and the second light-emitting element D2 is a privacy-protecting element, and the other is a non-privacy-protecting element. Different light-emitting modes can be switched by controlling the on / off state of the first light-emitting element D1 and the second light-emitting element D2. The cathodes of the first light-emitting element D1 and the second light-emitting element D2 are respectively connected to the second voltage source VSS. The first light-emitting control circuit 1 is used to control the current on / off of the first light-emitting element D1, and the second light-emitting control circuit 2 is used to control the current on / off of the second light-emitting element D2.
[0025] The first voltage source VDD provides a constant operating voltage to the pixel driving unit. The driving current flows out from the first voltage source, passes through the isolation circuit 3, and is transmitted to the first node A. The first node A is the distribution node for the driving current. The driving current can flow to the first light-emitting element D1 through the first light-emitting control circuit 1, or to the second light-emitting element D2 through the second light-emitting control circuit 2.
[0026] As an example, by connecting the first light-emitting control circuit 1 and the second light-emitting control circuit 2 to different levels of the first driving unit, the timing difference of the output signals of the different levels of the first driving unit can be used to realize the independent control of the first light-emitting element D1 and the second light-emitting element D2.
[0027] In the above embodiment, firstly, the isolation circuit 3 isolates the driving current path from the first node A to prevent signal interference between different stages. Then, by connecting the first light-emitting control circuit 1 and the second light-emitting control circuit 2 to different stages of the first driving unit in the gate driver, the output signals of different stages of the same gate driving unit can be used to achieve independent control of the two first light-emitting control circuits 1 and 2, without the need to set up separate gate driving units for each. Thus, by driving either the first light-emitting control circuit 1 or the second light-emitting control circuit 2 to conduct during the light-emitting stage, the number of driving unit groups in the gate driver can be reduced to achieve a narrow bezel while switching between two light-emitting modes.
[0028] Reference Figure 1 In some embodiments, the first light-emitting control circuit 1 includes a first transistor T1, and the second light-emitting control circuit 2 includes a second transistor T2. The first transistor T1 includes a first electrode connected to a first node A, a second electrode connected to a first light-emitting element D1, and a control electrode connected to a first driving unit of the Nth stage to access the light-emitting selection signal of the Nth stage. The second transistor T2 includes a first electrode connected to the first node A, a second electrode connected to the second light-emitting element D2, and a control electrode connected to a first driving unit of the Nath stage to access the light-emitting selection signal of the Nath stage. Here, N and a are positive integers. The first transistor T1 and the second transistor T2 are of different types.
[0029] As an example, EM1(N) represents the light-emitting selection signal of the Nth stage; EM1(Na) represents the light-emitting selection signal of the Nath stage. The light-emitting selection signal output by the first driving unit of the Nth stage is used to control the on / off state of the first transistor T1. The light-emitting selection signal output by the first driving unit of the Nath stage is a clock cycles ahead of the light-emitting selection signal of the Nth stage. The value of a can be adjusted according to the clock frequency of the gate driver and the duration of the display cycle, and a can take any value less than or equal to 150.
[0030] As an example, the first transistor T1 can be a PMOS (P-channel Metal-Oxide-Semiconductor) transistor, and the second transistor T2 can be an N-type IGZO (Indium Gallium Zinc Oxide) transistor. The first transistor T1 conducts when the voltage at its control electrode is lower than the voltage at its second electrode, and the second transistor T2 conducts when the voltage at its control electrode is higher than the voltage at its second electrode. Utilizing the difference in the conduction conditions of the first transistor T1 and the second transistor T2, and the timing difference of 'a' clock cycles, the first transistor T1 and the second transistor T2 can be controlled separately using the same set of first gate drive units, thereby reducing the number of sets of gate drive units required.
[0031] As an example, the pixel driving unit's operating modes include a first light-emitting mode and a second light-emitting mode. Taking the first light-emitting element D1 as a non-peeping element and the second light-emitting element D2 as a peeping element as an example, the first light-emitting mode can be a normal display mode, achieving normal display at a wide viewing angle. The second light-emitting mode can be a peeping display mode, where the image can only be seen from the frontal view of the display panel and cannot be seen from the side view, thus achieving a peeping effect.
[0032] Reference Figure 2 and Figure 3 In some embodiments, when the pixel driving unit is operating in the first light emission mode, during the light emission stage, the first driving unit of the Na level outputs the light emission selection signal of the Na level to drive the second transistor T2 to turn off, and the first driving unit of the N level outputs the light emission selection signal of the N level to drive the first transistor T1 to turn on, so that the first light emission element D1 emits light.
[0033] As an example, taking the first transistor T1 as a P-type transistor and the second transistor T2 as an N-type transistor, the light-emitting selection signal of the Na-th stage is output a clock cycle earlier than the light-emitting selection signal of the N-th stage. This creates a timing overlap interval where both the Na-th stage light-emitting selection signal and the N-th stage light-emitting selection signal are at a low level during the light-emitting stage. Combined with the different conduction conditions of the first transistor T1 and the second transistor T2, only the first transistor T1 is turned on while the second transistor T2 is turned off. This allows the driving current to flow only to the first light-emitting element D1, enabling the first light-emitting element D1 to emit light independently.
[0034] Reference Figure 4 and Figure 5In some embodiments, when the pixel driving unit operates in the second light emission mode, during the light emission stage, the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage to drive the second transistor T2 to turn on, and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive the first transistor T1 to turn off, so that the second light emission element D2 emits light.
[0035] As an example, continuing with the case where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the light-emitting selection signal of the Na-th stage is output a clock cycle earlier than the light-emitting selection signal of the N-th stage. This creates a timing overlap interval where both the Na-th stage light-emitting selection signal and the N-th stage light-emitting selection signal are at a high level during the light-emitting phase. Combined with the different conduction conditions of the first transistor T1 and the second transistor T2, only the second transistor T2 is turned on while the first transistor T1 is turned off. This allows the driving current to flow only to the second light-emitting element D2, enabling the second light-emitting element D2 to emit light independently.
[0036] Thus, by utilizing the timing difference between the light-emitting selection signal of the Na-th stage and the light-emitting selection signal of the N-th stage, as well as the different conduction conditions of the first transistor T1 and the second transistor T2, only one set of first driving units is needed to independently turn on the first transistor T1 and the second transistor T2.
[0037] It should also be noted that the switching of the Na-level light emission selection signal and the N-level light emission selection signal from the first light emission mode to the second light emission mode can be performed during the non-light emission phase of the display cycle, such as the t1 to t4 phase, so as not to affect the light emission state of the first light emission element D1 and the second light emission element D2.
[0038] In some embodiments, the pixel driving unit further includes a third light-emitting control circuit 4 and a driving transistor Tr connected between the first voltage source and the isolation circuit 3. The gate driver includes a second driving unit. The driving transistor Tr includes a first electrode connected to the third light-emitting control circuit 4 at the second node B and a second electrode connected to the isolation circuit 3 at the third node C. The third light-emitting control circuit 4 includes a third transistor T3, which includes a first electrode connected to the first voltage source, a second electrode connected to the second node B, and a control electrode connected to the second driving unit to receive the light-emitting control signal EM2. As an example, the driving transistor Tr is used to adjust the driving current provided by the first voltage source according to the data voltage written to its control electrode. The third light-emitting control circuit 4 is used to control the on / off connection between the first voltage source and the second node B to control whether the second node B receives or does not receive the driving current.
[0039] As an example, during the light-emitting phase, the second driving unit outputs a light-emitting control signal EM2 to drive the third transistor T3 to conduct, so that the driving current provided by the first voltage source is transmitted to the driving transistor Tr. Then, the driving transistor Tr adjusts the driving current according to its control electrode data voltage. The driving current flows through the isolation circuit 3, the first light-emitting control circuit 1, and the second light-emitting control circuit 2 to the first light-emitting element D1 and the second light-emitting element D2, causing the first light-emitting element D1 and the second light-emitting element D2 to emit light. In other phases besides the light-emitting phase, the light-emitting control signal EM2 drives the third transistor T3 to turn off, disconnecting the connection between the first voltage source and the driving transistor Tr, preventing the first light-emitting element D1 and the second light-emitting element D2 from emitting light during the non-light-emitting phase.
[0040] In some embodiments, the pixel driving unit further includes a first reset circuit 5 connected to the second node B. The gate driver includes a third driving unit. The first reset circuit 5 includes a fourth transistor T4, which includes a first electrode connected to a first reset voltage, a second electrode connected to the second node B, and a control electrode connected to the third driving unit to receive a reset control signal Pscan2. The display cycle of the pixel driving unit also includes a first reset phase prior to the light-emitting phase. In the first reset phase, the third driving unit outputs a reset control signal Pscan2 to drive the fourth transistor T4 to turn on, thereby resetting the second node B using the first reset voltage.
[0041] As an example, the first reset phase can be completed before the data writing phase of the display cycle, or after the data writing phase and before the light emission phase, to eliminate residual charge from the previous frame display before light emission occurs before data writing. The first reset voltage can be a low-level signal used to release residual charge from the second node B, restoring the second node B to its initial state.
[0042] Reference Figure 2 In a first embodiment of the isolation circuit 3, the isolation circuit 3 includes a fifth transistor T5. The fifth transistor T5 includes a first electrode connected to the driving transistor Tr at the second node B, a second electrode connected to the first node A, and a control electrode connected to the second driving unit to receive the light emission control signal EM2. The pixel driving unit also includes a second reset circuit 6 for resetting the anodes of the first light-emitting element D1 and the second light-emitting element D2.
[0043] In a first embodiment of the second reset circuit 6, the second reset circuit 6 includes a first reset transistor T61 and a second reset transistor T62. The first reset transistor T61 includes a first electrode connected to a second reset voltage, a second electrode connected to the anode of the first light-emitting element D1, and a control electrode connected to a third driving unit to receive the reset control signal Pscan2. The second reset transistor T62 includes a first electrode connected to the second reset voltage, a second electrode connected to the anode of the second light-emitting element D2, and a control electrode connected to the third driving unit to receive the reset control signal Pscan2.
[0044] Reference Figure 6 The first reset transistor T61 is used to reset the anode of the first light-emitting element D1, and the second reset transistor T62 is used to reset the anode of the second light-emitting element D2. During the first reset phase, the third driving unit outputs a reset control signal Pscan2 to drive the first reset transistor T61 and the second reset transistor T62 to conduct, thereby resetting the anodes of the first light-emitting element D1 and the second light-emitting element D2 respectively using a second reset voltage. The first reset transistor T61 and the second reset transistor T62 can share the same third driving unit to reduce the number of required gate driving units.
[0045] As an example, the second reset circuit 6 can also be combined with the first light-emitting control circuit 1 and the second light-emitting control circuit 2 to reset the first node A. In the first reset stage, the first driving unit of the Nth stage outputs the Nth stage light-emitting selection signal to drive the first transistor T1 to conduct, causing the second reset voltage to flow to the first node A through the first transistor T1; or, the first driving unit of the Nath stage outputs the Nath stage light-emitting selection signal to drive the second transistor T2 to conduct, causing the second reset voltage to flow to the first node A through the second transistor T2. Thus, the first node A can be reset using the second reset voltage.
[0046] Reference Figure 6 The control electrodes of both the fifth transistor T5 and the third transistor T3 are connected to the second driving unit, and the fifth transistor T5 and the second transistor T2 are of the same type. During the light-emitting phase, the second driving unit outputs a light-emitting control signal EM2 to drive the third transistor T3 to conduct, transmitting the driving current provided by the first voltage source to the second node B, and driving transistor Tr to conduct according to the data voltage. Then, the second driving unit outputs a light-emitting control signal EM2 to drive the fifth transistor T5 to conduct, transmitting the driving current transmitted by driving transistor Tr to the first node A; then, the first light-emitting control circuit 1 and the second light-emitting control circuit 2 are used to selectively transmit the driving current of the first node A to either the first light-emitting element D1 or the second light-emitting element D2 to form a complete current path.
[0047] Reference Figure 7 As a second embodiment of the second reset circuit 6, the second reset circuit 6 includes a third reset transistor T63; the third reset transistor T63 includes a first electrode connected to the second reset voltage, a second electrode connected to the first node A, and a control electrode connected to the third driving unit to receive the reset control signal Pscan2; wherein, in the first reset stage, the third driving unit outputs the reset control signal Pscan2 to drive the third reset transistor T63 to conduct, so as to reset the first node A through the second reset voltage; the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive one of the second transistor T2 and the first transistor T1 to conduct, so as to perform an anode reset on one of the first light-emitting element D1 and the second light-emitting element D2 through the second reset voltage of the first node A.
[0048] Combination Figure 3 and Figure 8 As an example, in the case of the first light-emitting mode, during the first reset phase, the first driving unit of the Na-th stage outputs the light-emitting selection signal of the Na-th stage to drive the second transistor T2 to turn off, and the first driving unit of the N-th stage outputs the light-emitting selection signal of the N-th stage to drive the first transistor T1 to turn on, so as to perform a separate anode reset on the first light-emitting element D1 through the second reset voltage of the first node A.
[0049] Combination Figure 5 As an example, in the case of the second light-emitting mode, during the first reset phase, the first driving unit of the Na-th stage outputs the light-emitting selection signal of the Na-th stage to drive the second transistor T2 to turn on, and the first driving unit of the N-th stage outputs the light-emitting selection signal of the N-th stage to drive the first transistor T1 to turn off, so as to perform a separate anode reset on the second light-emitting element D2 through the second reset voltage of the first node A.
[0050] Thus, by using the third reset transistor T63 and reusing the first transistor T1 and the second transistor T2, it is possible to individually reset the first light-emitting element D1 and the second light-emitting element D2.
[0051] Reference Figure 9 As a second implementation of the isolation circuit 3, the gate driver further includes a fourth driving unit; the isolation circuit 3 includes a fifth transistor T5, the fifth transistor T5 including a first electrode connected to the driving transistor Tr at the second node B, a second electrode connected to the first node A, and a control electrode connected to the fourth driving unit to access the isolation control signal EM3.
[0052] The second implementation of isolation circuit 3 differs from the first implementation in that, in this embodiment, the fifth transistor T5 is not controlled by the second driving unit, but by an independent fourth driving unit. The fourth driving unit outputs an isolation control signal EM3 to control the on / off state of the fifth transistor T5. Thus, the on / off state of the fifth transistor T5 can be adjusted independently of the third light-emitting control circuit 4, allowing the fifth transistor T5 to conduct during non-light-emitting periods to control the on / off state between the first node A and the second node B, thereby achieving synchronous reset of the first node A, the second node B, and the third node C.
[0053] Reference Figure 10 and Figure 11 In some embodiments, when the pixel driving unit operates in the first light-emitting mode, during the first reset phase, the fourth driving unit outputs an isolation control signal EM3 to drive the fifth transistor T5 to turn on, the first driving unit of the Na-th stage outputs a light-emitting selection signal of the Na-th stage to drive the second transistor T2 to turn off, and the first driving unit of the N-th stage outputs a light-emitting selection signal of the N-th stage to drive the first transistor T1 to turn on. This causes the first reset voltage of the second node B to reset the anode of the first light-emitting element D1 via the driving transistor Tr, the fifth transistor T5, and the first transistor T1. Thus, in the first light-emitting mode, the first reset phase not only resets the third node C and the second node B, but also resets the first node A through the turned-on fifth transistor T5 and resets the anode of the first light-emitting element D1 through the turned-on first transistor T1.
[0054] In some embodiments, when the pixel driving unit operates in the second light emission mode, during the first reset phase, the fourth driving unit outputs an isolation control signal EM3 to drive the fifth transistor T5 to turn on, the first driving unit of the Na-th stage outputs a light emission selection signal of the Na-th stage to drive the second transistor T2 to turn on, and the first driving unit of the N-th stage outputs a light emission selection signal of the N-th stage to drive the first transistor T1 to turn off. This causes the first reset voltage of the second node B to reset the anode of the second light-emitting element D2 via the driving transistor Tr, the fifth transistor T5, and the second transistor T2. Thus, in the second light emission mode, the first reset phase not only resets the third node C and the second node B, but also resets the first node A through the turned-on fifth transistor T5 and resets the anode of the second light-emitting element D2 through the turned-on second transistor T2.
[0055] In this way, a separate anode reset circuit is unnecessary, reducing the number of transistors required for the pixel driving unit. Furthermore, reusing the first light-emitting control circuit 1 and the second light-emitting control circuit 2 allows for targeted individual resets of the first light-emitting element D1 and the second light-emitting element D2.
[0056] Reference Figure 12 The difference between the second and first implementations of the isolation circuit 3 in the light-emitting stage is that, in the second implementation of the isolation circuit 3, the fifth transistor T5 needs to be turned on by the isolation control signal EM3. The principle of the rest is the same and will not be described again here.
[0057] Reference Figure 1 In some embodiments, the pixel driving unit further includes a data writing sub-circuit for writing a data voltage to the control electrode of the driving transistor Tr.
[0058] As an example of a data writing sub-circuit, the data writing sub-circuit includes a writing circuit 7, a reset circuit 8, and a connection circuit 9. The gate driver also includes a fifth driving unit, a sixth driving unit, and a seventh driving unit. The writing circuit 7 includes a seventh transistor T7, which includes a first electrode for receiving a data voltage, a second electrode connected to the second node B, and a control electrode connected to the fifth driving unit to receive the write control signal Pscan. The reset circuit 8 includes an eighth transistor T8, which includes a first electrode for receiving a reset voltage, a second electrode connected to the control electrode of the driving transistor Tr at the fourth node Q, and a control electrode connected to the sixth driving unit to receive the reset driving signal Nscan. The connection circuit 9 includes a ninth transistor T9, which includes a first electrode connected to the third node C, a second electrode connected to the fourth node Q, and a control electrode connected to the seventh driving unit to receive the connection control signal Nscan2.
[0059] As another example of the data writing sub-circuit, the data writing sub-circuit may also include a write transistor connected to the fourth node Q. The write transistor includes a first electrode that receives the data voltage, a second electrode that receives the fourth node Q, and a control electrode that receives the write control signal Pscan, so as to directly transmit the data voltage to the fourth node Q through the write transistor.
[0060] It should be noted that the data writing sub-circuit can also adopt other architectures that can write data voltage to the fourth node Q, without specific limitations here.
[0061] As an example, the write circuit 7 is used to write the data voltage output by the source driver to the control electrode of the drive transistor Tr. When the fifth drive unit outputs a low-level write control signal Pscan, the seventh transistor T7 is turned on, and the data voltage is transmitted sequentially through the seventh transistor T7, the second node B, the drive transistor Tr, and the ninth transistor T9 to the control electrode of the drive transistor Tr. The reset circuit 8 is used to reset the potential of the control electrode of the drive transistor Tr at the initial stage of the display cycle, eliminating the charge remaining in the fourth node Q after the previous frame is displayed, and ensuring the accurate writing of the data voltage for the next frame. When the sixth drive unit outputs a high-level reset drive signal Nscan, the eighth transistor T8 is turned on, pulling the potential of the fourth node Q to the reset voltage. The connection circuit 9 is used to connect the second electrode of the drive transistor Tr to the control electrode, realizing threshold voltage compensation of the drive transistor Tr. When the seventh drive unit outputs a high-level connection control signal Nscan2, the ninth transistor T9 is turned on, connecting the second node B and the fourth node Q.
[0062] Reference Figure 3 and 5 The display cycle of the pixel driving unit sequentially includes an initial phase t1, a reset phase t2, a data writing phase t3, an anode reset phase t4, and an emission phase t5. In the first emission mode and the second emission mode, the workflow of the initial phase t1, the reset phase t2, and the data writing phase t3 remains consistent. The workflow of the anode reset phase t4 and the emission phase t5 varies depending on the emission mode. The workflow of the anode reset phase t4 and the emission phase t5 can be found in the detailed description above and will not be repeated here.
[0063] In the initial stage t1, the sixth driving unit outputs a reset driving signal Nscan to drive the reset circuit 8 to turn on, transmitting the reset voltage to the control electrode of the driving transistor Tr to perform an initial reset of the control electrode of the driving transistor Tr and clear the charge remaining on the control electrode of the driving transistor Tr after the previous frame was displayed.
[0064] During the reset phase t2, the sixth drive unit outputs a reset drive signal Nscan to drive the eighth transistor T8 to turn on, and the seventh drive unit outputs a connection control signal Nscan2 to drive the ninth transistor T9 to turn on. At this time, the drive transistor Tr remains on after the initial reset, so that the reset voltage resets the third node C through the ninth transistor T9 and the eighth transistor T8, and resets the second node B through the drive transistor Tr.
[0065] During the data writing phase t3, the fifth driving unit outputs a write control signal Pscan, turning on the seventh transistor T7. The data voltage is then transmitted to the second node B through the seventh transistor T7. Simultaneously, the seventh driving unit continues to output a connection control signal Nscan2, keeping the ninth transistor T9 on and connecting the third node C to the control electrode of the driving transistor Tr. At this point, the data voltage at the second node B is transmitted to the control electrode of the driving transistor Tr through the driving transistor Tr and the ninth transistor T9. The control electrode potential of the driving transistor Tr is charged to the sum of the data voltage and the threshold voltage, completing the data voltage writing and threshold voltage compensation.
[0066] Reference Figure 13 , Figure 13 This is a schematic diagram of the architecture of the display device used in the display panel in the embodiments of this disclosure. The display device also includes a timing controller 300 and a source driver 400.
[0067] The display device includes a display area AA, which may include multiple scan lines G1 to Gn, multiple data lines intersecting the scan lines G1 to Gn, and multiple pixel driving units 100 respectively disposed in multiple areas defined by the intersections of the scan lines G1 to Gn and the data lines. Each pixel driving unit 100 is a dual-emitting-element pixel driving unit, including a first emitting-element D1 and a second emitting-element D2.
[0068] The timing controller 300 receives externally input image data and control signals, and performs preprocessing on the image data, such as format conversion and data sorting, to obtain data signals. Simultaneously, the timing controller 300 generates seven independent gate control signals, a clock signal, and a source control signal. The seven independent gate control signals are: light emission selection signal, light emission control signal EM2, reset control signal Pscan2, isolation control signal EM3, write control signal Pscan, reset drive signal Nscan, and connection control signal Nscan2. If... Figure 1 The pixel driving unit architecture shown allows the isolation control signal EM3 and the light emission control signal EM2 to be multiplexed using the same set of gate driving unit outputs.
[0069] Then, the data signal and source control signal are sent to the source driver 400, and the aforementioned gate control signals and clock signals are sent to the gate driver 200. The gate driver 200 integrates a first driving unit, a second driving unit, a third driving unit, a fourth driving unit, a fifth driving unit, a sixth driving unit, and a seventh driving unit. Each driving unit receives the corresponding control signal and clock signal from the timing controller 300, generates a row-by-row scanning gate driving signal, and transmits it sequentially through scan lines G1 to Gn to the corresponding row's pixel driving unit 100, independently controlling the on / off timing of each transistor within the pixel driving unit 100. After receiving the data signal and control signal from the timing controller 300, the source driver 400 stores the data signal in its internal register and outputs it synchronously according to the scan signal from the gate driver 200. The data voltage is written into the corresponding column's pixel driving unit 100 through the data line, ultimately realizing the image display.
[0070] According to a second aspect of this disclosure, a pixel driving circuit is provided, which includes the aforementioned display panel. This pixel driving circuit possesses all the beneficial effects of the aforementioned display panel, which will not be elaborated further herein.
[0071] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.
[0072] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0073] The embodiments, implementation methods and related technical features disclosed herein can be combined and substituted for each other without conflict.
[0074] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. A display panel, characterized in that, It includes a gate driver, a pixel driving unit connected to the gate driver, and a first light-emitting element and a second light-emitting element connected to the pixel driving unit; The gate driver includes a plurality of cascaded first driving units; The pixel driving unit includes a first light-emitting control circuit, a second light-emitting control circuit, and an isolation circuit; One end of the isolation circuit is used to connect to the driving current provided by the first voltage source, and the second end is connected to the first light-emitting control circuit and the second light-emitting control circuit at the first node. The first light-emitting control circuit is connected to the anode of the first light-emitting element, and the second light-emitting control circuit is connected to the anode of the second light-emitting element; The first light-emitting control circuit and the second light-emitting control circuit are respectively connected to the first driving unit at different levels; During the light-emitting phase of the display cycle of the pixel driving unit, the first driving unit drives either the first light-emitting control circuit or the second light-emitting control circuit to conduct.
2. The display panel according to claim 1, characterized in that, The first light-emitting control circuit includes a first transistor, and the second light-emitting control circuit includes a second transistor; The first transistor includes a first electrode connected to the first node, a second electrode connected to the first light-emitting element, and a control electrode connected to the first driving unit of the Nth stage to access the light-emitting selection signal of the Nth stage; The second transistor includes a first electrode connected to the first node, a second electrode connected to the second light-emitting element, and a control electrode connected to the first driving unit of the Na-th stage to access the light-emitting selection signal of the Na-th stage; wherein, N and a are positive integers; The first transistor and the second transistor are of different types.
3. The display panel according to claim 1, characterized in that, The value of a is less than or equal to 150.
4. The display panel according to claim 2, characterized in that: When the pixel driving unit is operating in the first light emission mode, during the light emission stage, the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage to drive the second transistor to turn off, and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive the first transistor to turn on, so that the first light emission element emits light. When the pixel driving unit operates in the second light emission mode, during the light emission stage, the first driving unit of the Na-th stage outputs the Na-th stage light emission selection signal to drive the second transistor to turn on, and the first driving unit of the N-th stage outputs the N-th stage light emission selection signal to drive the first transistor to turn off, so that the second light emission element emits light.
5. The display panel according to claim 4, characterized in that, The pixel driving unit further includes a third light-emitting control circuit and a driving transistor connected between the first voltage source and the isolation circuit; the gate driver includes a second driving unit; The driving transistor includes a first electrode connected to the second node of the third light-emitting control circuit and a second electrode connected to the third node of the isolation circuit; The third light-emitting control circuit includes a third transistor, which includes a first electrode connected to the first voltage source, a second electrode connected to the second node, and a control electrode connected to the second driving unit to receive the light-emitting control signal. During the light-emitting stage, the second driving unit outputs the light-emitting control signal to drive the third transistor to turn on, so that the driving current provided by the first voltage source is transmitted to the driving transistor. The pixel driving unit further includes a first reset circuit connected to the second node; the gate driver includes a third driving unit. The first reset circuit includes a fourth transistor, which includes a first electrode connected to a first reset voltage, a second electrode connected to the second node, and a control electrode connected to the third driving unit to receive a reset control signal. The display cycle of the pixel driving unit also includes a first reset phase before the light emission phase; in the first reset phase, the third driving unit outputs the reset control signal to drive the fourth transistor to turn on, so as to reset the second node through the first reset voltage.
6. The display panel according to claim 5, characterized in that, The isolation circuit includes a fifth transistor; the fifth transistor includes a first electrode connected to the driving transistor at the second node, a second electrode connected to the first node, and a control electrode connected to the second driving unit to access the light emission control signal; The pixel driving unit further includes a second reset circuit for resetting the anodes of the first light-emitting element and the second light-emitting element.
7. The display panel according to claim 6, characterized in that, The second reset circuit includes a first reset transistor and a second reset transistor; The first reset transistor includes a first electrode that receives a second reset voltage, a second electrode that is connected to the anode of the first light-emitting element, and a control electrode that is connected to the third driving unit to receive the reset control signal; The second reset transistor includes a first electrode that is connected to the second reset voltage, a second electrode that is connected to the anode of the second light-emitting element, and a control electrode that is connected to the third driving unit to receive the reset control signal; In the first reset phase, the third driving unit outputs the reset control signal to drive the first reset transistor and the second reset transistor to conduct, so as to perform anodizing reset on the first light-emitting element and the second light-emitting element respectively by the second reset voltage; During the light-emitting phase, the second driving unit outputs the light-emitting control signal to drive the fifth transistor to conduct, so as to transmit the driving current transmitted by the driving transistor to the first node.
8. The display panel according to claim 6, characterized in that, The second reset circuit includes a third reset transistor; The third reset transistor includes a first electrode that receives a second reset voltage, a second electrode that is connected to the first node, and a control electrode that is connected to the third driving unit to receive the reset control signal; In the first reset phase, the third driving unit outputs the reset control signal to drive the third reset transistor to conduct, so as to reset the first node through the second reset voltage; the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive one of the second transistor and the first transistor to conduct, so as to perform an anode reset on one of the first light-emitting element and the second light-emitting element through the second reset voltage of the first node.
9. The display panel according to claim 5, characterized in that, The isolation circuit includes a fifth transistor; the gate driver further includes a fourth driving unit. The fifth transistor includes a first electrode connected to the second node of the driving transistor, a second electrode connected to the first node, and a control electrode connected to the fourth driving unit to access an isolation control signal; When the pixel driving unit is operating in the first light emission mode, during the first reset phase, the fourth driving unit outputs the isolation control signal to drive the fifth transistor to turn on, the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage to drive the second transistor to turn off, and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive the first transistor to turn on, so that the first reset voltage of the second node resets the anode of the first light emission element through the driving transistor, the fifth transistor and the first transistor; When the pixel driving unit operates in the second light emission mode, during the first reset phase, the fourth driving unit outputs the isolation control signal to drive the fifth transistor to turn on, the first driving unit of the Na-th stage outputs the light emission selection signal of the Na-th stage to drive the second transistor to turn on, and the first driving unit of the N-th stage outputs the light emission selection signal of the N-th stage to drive the first transistor to turn off, so that the first reset voltage of the second node resets the anode of the second light emission element through the driving transistor, the fifth transistor, and the second transistor.
10. A pixel driving circuit, characterized in that, Includes the display panel as described in any one of claims 1 to 9.