A clock control circuit, a clock output device, and a display device

Abstract

The application discloses a clock control circuit, a clock output device and a display device, and relates to the technical field of sequential circuit, the clock control circuit comprises a shift register module and a plurality of gating units, the shift register module comprises a plurality of cascaded flip-flops, the flip-flop comprises a data input end, a data output end and a shift clock input end, a trigger signal is input into the data input end of the first flip-flop, the data output end of a previous flip-flop is connected with the data input end of a next flip-flop, and the shift clock input end of each flip-flop inputs a shift clock signal; the gating unit comprises a first input end, a second input end and a sub-clock output end, the first input end of each gating unit inputs the same main clock signal, the second input end of each gating unit is connected with the data output end of each flip-flop in one-to-one correspondence, and the sub-clock output end of the gating unit outputs a plurality of sub-clock signals after the main clock signal is gated. The scheme can effectively generate a plurality of clock signals, so as to guarantee the normal display of the display device.

Description

Technical Field

[0001] This invention relates to the field of timing circuit technology, and in particular to a clock control circuit, a clock output device, and a display device. Background Technology

[0002] Various display devices are widely used in consumer electronics products such as mobile phones, televisions, and laptops. In related technologies, the driving circuit of display devices requires multiple clock signals to control the display of the pixel array. Therefore, how to effectively generate multiple clock signals to ensure the normal display of the monitor is a key research focus for those skilled in the art. Summary of the Invention

[0003] The main objective of this invention is to provide a clock control circuit, a clock output device, and a display device, which aim to effectively generate multiple clock signals to ensure the normal display of the display device.

[0004] In one embodiment, the clock control circuit includes a shift register module and multiple gating units. The shift register module includes multiple cascaded flip-flops, each flip-flop having a data input terminal, a data output terminal, and a shift clock input terminal. The data input terminal of the first-stage flip-flop is used to input a trigger signal, the data output terminal of the preceding flip-flop is connected to the data input terminal of the following flip-flop, and the shift clock input terminal of each flip-flop is used to input a shift clock signal. Each gating unit includes a first input terminal, a second input terminal, and a sub-clock output terminal. The first input terminal of each gating unit is used to input the same master clock signal, the second input terminal of each gating unit is connected to the data output terminal of each flip-flop in a one-to-one correspondence, and the sub-clock output terminals of the multiple gating units are used to output multiple sub-clock signals after the master clock signal has been gating processed.

[0005] In one embodiment, each trigger can sequentially output an enable level according to the timing of the shift clock signal each time the trigger signal is received, so that each gating unit sequentially selects the master clock signal at different times by one shift clock cycle, so as to output multiple sub-clock signals in a time-division manner.

[0006] In one embodiment, the trigger signal is composed of multiple time-spaced single-pulse signals.

[0007] In one embodiment, the shift register module is provided with multiple shift register modules, and the data output terminal of the final stage flip-flop of the preceding shift register module is connected to the data input terminal of the first stage flip-flop of the following shift register module.

[0008] In one embodiment, the gating unit is an AND gate unit.

[0009] In one embodiment, the shift clock input of each of the flip-flops is connected to the same terminal that outputs the shift clock signal.

[0010] In one embodiment, the trigger is a D trigger.

[0011] In one embodiment, the shift register module and multiple gating units are integrated within the same chip.

[0012] The present invention also proposes a clock output device, which includes a control module and a clock control circuit as described above. The control module includes a main clock output terminal, a first control terminal and a second control terminal. The main clock output terminal is connected to the first input terminal of each of the gating units. The first control terminal is connected to the data input terminal of the first stage flip-flop. The second control terminal is connected to the shift clock input terminal of each of the flip-flops.

[0013] The present invention also proposes a display device, the display device including a display module and a clock output device as described above, the display module having multiple sub-clock input terminals, each of the sub-clock input terminals being connected one-to-one with the sub-clock output terminal of each selection unit of the clock control circuit.

[0014] In the technical solution of this invention, a trigger signal is input to the data input terminal of the first-stage flip-flop of the shift register module. Driven by the clock cycle of the shift clock signal, the trigger signal is shifted and transmitted stage by stage between each flip-flop, causing the data output terminals of each flip-flop to output enable levels sequentially. The enable level output by each flip-flop corresponds to the activation of a gating unit, performing time-division multiplexing of the same master clock signal to finally output multiple sub-clock signals with staggered timing.

[0015] Therefore, the solution of this invention can accurately divide a single complete master clock signal into multiple sub-clock signals with staggered timings. Each sub-clock is output only during the required time period, reducing unnecessary switching and lowering dynamic power consumption. Furthermore, within each cycle of receiving a trigger signal, the outputs of each sub-clock signal do not overlap, meaning only one clock is valid at any given time. This suppresses switching noise caused by multiple clocks running in parallel, simplifies timing constraints, ensures precise and controllable timing of clocks from the same source, and adapts to scenarios such as row-by-row or column-by-column time-division driving of display devices, effectively guaranteeing the normal display of the display device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an embodiment of the clock control circuit provided by the present invention; Figure 2 for Figure 1 Timing diagram of a clock control circuit corresponding to one embodiment; Figure 3 This is a schematic diagram of a structure of an embodiment of the display device provided by the present invention.

[0018] Explanation of reference numerals: 1000, display device; 100, clock output device; 10, clock control circuit; 1, shift register module; 11, trigger; 2, gating unit; 21, sub-clock output terminal; 30, control module; 400, display module; 401, sub-clock input terminal. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the present invention and are not intended to limit the present invention.

[0020] To better understand the technical solution of the present invention, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0021] Various display devices are widely used in various consumer electronics products such as mobile phones, televisions, and laptops.

[0022] In Micro-LED display driving scenarios, lamp driver chips have extremely high requirements for multiple clock signals with staggered timings.

[0023] In related technologies, the driving circuit of a display requires multiple clock signals to control the display of the pixel array. Therefore, how to effectively generate multiple clock signals to ensure the normal display of the monitor is a key research focus for those skilled in the art.

[0024] For example, generating multiple clock signals often requires multiple clock excitation sources. Using multiple clock excitation sources to generate clock signals results in a more complex circuit structure, which is not conducive to simplifying the circuit structure and reducing costs.

[0025] To address the aforementioned problems, this invention proposes a clock control circuit 10, a clock output device 100, and a display device 1000, which aim to effectively generate multiple clock signals to ensure the normal display of the display device 1000.

[0026] Reference Figures 1 to 3In one embodiment of the present invention, the clock control circuit 10 includes a shift register module 1 and a plurality of gating units 2. The shift register module 1 includes a plurality of cascaded flip-flops 11. Each flip-flop 11 includes a data input terminal, a data output terminal, and a shift clock input terminal. The data input terminal of the first flip-flop 11 is used to input a trigger signal SYN. ​​The data output terminal of the preceding flip-flop 11 is connected to the data input terminal of the following flip-flop 11. The shift clock input terminal of each flip-flop 11 is used to input a shift clock signal SCK. The gating unit 2 includes a first input terminal, a second input terminal, and a sub-clock output terminal 21. The first input terminal of each gating unit 2 is used to input the same master clock signal CLK. The second input terminal of each gating unit 2 is connected to the data output terminal of each flip-flop 11 in a one-to-one correspondence. The sub-clock output terminals 21 of the multiple gating units 2 are used to output multiple sub-clock signals after the master clock signal CLK has been gating processed.

[0027] The shift register module 1 is the core timing shift unit, composed of cascaded multi-stage flip-flops 11. It receives the trigger signal SYN and the shift clock signal SCK, realizing the step-by-step shift transmission of the signal and outputting multiple control levels with timing misalignment. The flip-flops 11 are sequential logic devices with data input terminals, data output terminals, and shift clock input terminals, and can latch and transmit level signals under clock control.

[0028] The gating unit 2 is a clock gating logic unit with a dual-input, single-output structure, used to select the main clock signal CLK for on / off based on the control level.

[0029] The trigger signal SYN is an externally input start pulse signal, which serves as the start command for a single shift timing sequence and is used to trigger a complete shift and clock gating process.

[0030] The shift clock signal SCK is a clock signal input to the shift clock input terminal of flip-flop 11, providing a unified clock for the shift operation of each flip-flop 11 and controlling the rate at which the trigger signal SYN is shifted and transmitted between multiple flip-flops 11.

[0031] The master clock signal CLK is the system's original reference clock signal, providing a unified clock source for all sub-clock signals. The sub-clock signals are multiple drive clock signals output from the master clock signal CLK after being time-division multiplexed and timing-misaligned by the gating unit, used to drive the display module 400. These multiple sub-clock signals are shown as CLK1, CLK2, CLK3 to CLK in the attached diagram. N .

[0032] The selected sub-clock signal can be a single clock pulse or a clock segment composed of multiple clock pulses, in order to meet the display control requirements of the display device 1000.

[0033] In the technical solution of this invention, the trigger signal SYN is input to the data input terminal of the first-stage flip-flop 11 of the shift register module 1. Driven by the shift clock signal SCK, the trigger signal SYN is shifted and transmitted stage by stage among the flip-flops 11, causing the data output terminals of each flip-flop 11 to output enable levels sequentially. The enable level output by each flip-flop 11 corresponds to the activation of a gating unit 2, which performs time-division gating processing on the same master clock signal CLK, and finally outputs multiple sub-clock signals with staggered timing.

[0034] Therefore, the solution of this invention can accurately divide a single complete master clock signal CLK into multiple sub-clock signals with staggered timings. Each sub-clock is output only during the required time period, reducing unnecessary switching and lowering dynamic power consumption. Furthermore, within each cycle of receiving the trigger signal SYN, the outputs of each sub-clock signal do not overlap, which can suppress switching noise generated by multiple clocks running in parallel, simplify timing constraints, and ensure precise and controllable timing of clocks from the same source. This adapts to scenarios such as row-by-row or column-by-column time-division driving of display devices 1000, effectively ensuring the normal display of display devices 1000.

[0035] Reference Figure 1 and Figure 2 In one embodiment of the present invention, each trigger 11 can sequentially output an enable level according to the beat of the shift clock signal SCK after each trigger edge of the trigger signal SYN, so that each gating unit 2 sequentially selects the main clock signal CLK by one shift clock cycle, so as to output multiple sub-clock signals in a time-division manner.

[0036] The enable level is the valid output signal of flip-flop 11 after shifting, such as a high-level signal, which is used to enable the corresponding gating unit 2 as the control condition for clock gating. The shift clock period is a single working cycle of the shift clock signal SCK, which is the smallest time unit for the timing misalignment of multiple sub-clocks. For example, the time period from t2 to t4 is the duration of one shift clock period.

[0037] In this embodiment, the output of the current round's multiple sub-clock signals is initiated by the first trigger edge of the trigger signal SYN. ​​At the rising or falling edge of each shift clock cycle, the enable level is passed from the current stage flip-flop 11 to the next stage flip-flop 11. Each flip-flop 11 outputs an enable level sequentially, causing the corresponding gating unit 2 to be activated sequentially. At any given time, only one sub-clock signal is in a valid output state, and adjacent signals are staggered by one complete shift clock cycle. This time-division output method, staggered by one shift clock cycle, ensures that the timing relationship of each sub-clock signal is clear and controllable, avoids the unreliability caused by simultaneous changes in multiple signals, and improves the reliability and stability of clock signal allocation.

[0038] In one embodiment of the control process of the present invention, at time t1, the trigger signal SYN generates a valid pulse trigger edge, which serves as the start signal for a clock output process; at this time, the shift clock signal SCK has not yet generated a valid edge, the shift register module 1 does not perform a shift operation, all gating units 2 are in the off state, and all sub-clock signals CLK1 to CLK... N No signal output.

[0039] At time t2, the shift clock signal SCK has a valid edge. The first-stage flip-flop 11 of the shift register module 1 samples and latches the trigger signal SYN. ​​The first-stage flip-flop 11 outputs a high-level enable level, which turns on the first gating unit 2. After the master clock signal CLK is selected by the first gating unit 2, it forms the sub-clock signal CLK1 at time t3, and the other sub-clock signals remain in a no-output state.

[0040] At time t4, the shift clock signal SCK generates a valid edge again, and the trigger signal SYN continues to shift to the subsequent flip-flop 11. The output level of the first-stage flip-flop 11 toggles to a low level, and the first gating unit 2 is turned off. The second-stage flip-flop 11 outputs a high-level enable level, and the second gating unit 2 is turned on. After the master clock signal CLK is selected by the second gating unit 2, it forms the sub-clock signal CLK2 at time t5, while the other sub-clock signals remain in a no-output state.

[0041] Similarly, the shift clock signal SCK continuously drives the shift register module 1, and the trigger signal SYN is passed step by step to enable the subsequent flip-flops 11 in turn, corresponding to CLK3 to CLK. N The outputs are sequentially divided into time-division multiplexes. After each shift is completed, the output of the previous stage flip-flop 11 flips to a low level, and the corresponding sub-clock signal stops being output. This allows multiple sub-clock signals to be output sequentially and staggered according to the shift clock cycle.

[0042] At time t6, the trigger signal SYN generates a valid trigger edge again, starting a new complete timing cycle; the previous round of shift gating process is completed, each sub-clock signal completes a round of time-division output, and the circuit repeats the working process from t1 to t6 to achieve periodic multi-channel time-division sub-clock signal output.

[0043] The effective triggering method for the shift clock signal SCK and the trigger signal SYN is not limited; any edge triggering form, such as rising edge triggering or falling edge triggering, can be used. As long as the enable level can be shifted and transferred in an orderly manner among the cascaded flip-flops 11 and multiple sub-clocks can be output in a time-division multiplexing manner, it falls within the protection scope of this invention. It should be noted that... Figure 2 This is only a timing diagram. The pulse width and time interval of each signal are only used to illustrate the logical relationship and do not represent the strict time ratio of the actual circuit.

[0044] Reference Figure 2 In one embodiment of the present invention, the trigger signal SYN is composed of multiple time-spaced single-pulse signals, each single-pulse signal being used to trigger the output of a round of multi-channel sub-clock signals.

[0045] In this embodiment, the trigger signal SYN consists of multiple time-spaced single-pulse signals. After entering the shift register module 1, the single pulse is sequentially transmitted along each cascaded flip-flop 11 under the action of the shift clock signal SCK. Using a single pulse as the trigger signal SYN effectively avoids the problem of simultaneous output of multiple flip-flops 11 due to continuous high-level input, ensuring that the enable level is transmitted sequentially in the shift register module 1 according to a predetermined rhythm, thereby enabling each selection unit 2 to sequentially select the main clock signal CLK in a predetermined order. At the same time, the single-pulse signal generation circuit is simple and can be provided by a button, microcontroller, or dedicated control chip, reducing the requirements for external control signals.

[0046] Reference Figure 1 In one embodiment of the present invention, the shift register module 1 is provided with multiple shift register modules, and the data output terminal of the final stage flip-flop 11 of the preceding shift register module 1 is connected to the data input terminal of the first stage flip-flop 11 of the following shift register module 1.

[0047] The first-stage flip-flop 11 is the first-stage flip-flop 11 in the cascaded link of a single shift register module 1, and is used to receive the trigger signal SYN. ​​The last-stage flip-flop 11 is the last-stage flip-flop 11 in the cascaded link of a single shift register module 1, and is responsible for transmitting the shift signal of this module to the subsequent modules.

[0048] In this embodiment, the number of sub-clock signal output channels can be further expanded by cascading multiple shift register modules 1. When the number of flip-flops 11 in a single shift register module 1 is insufficient to meet the requirements, the output of the last stage flip-flop 11 of the previous module is connected to the input of the first stage flip-flop 11 of the next module, so that the trigger signal SYN can be transmitted sequentially on a longer cascaded link, thereby realizing more sub-clock signal output channels. This modular design gives the circuit good scalability and can flexibly adapt to the needs of display devices 1000 of different sizes without redesigning the overall circuit structure.

[0049] Specifically, refer to Figure 1 The shift register module 1 consists of N cascaded flip-flops 11. When there are 2 shift register modules 1, there can be 2N flip-flops 11. At the same time, with 2N gating units 2, more sub-clock signals can be output.

[0050] Reference Figure 1 In one embodiment of the present invention, the gating unit 2 is an AND gate unit.

[0051] In this embodiment, an AND gate is used as the gating unit 2. Its first input is connected to the master clock signal CLK, and its second input is connected to the data output of the corresponding flip-flop 11. When the data output of the flip-flop 11 outputs a high-level enable signal, the AND gate transmits the master clock signal CLK to the sub-clock output 21 to output the sub-clock signal; when the flip-flop 11 outputs a low level, the master clock signal CLK of the corresponding AND gate is blocked. Using an AND gate to implement the gating function has the advantages of simple circuit structure, fast response speed, and low power consumption. Moreover, the AND gate is a basic logic gate in digital circuits, which is easy to integrate and implement, and helps to reduce chip area and manufacturing cost.

[0052] Reference Figure 1 In one embodiment of the present invention, the shift clock input terminal of each of the flip-flops 11 is connected to the same terminal that outputs the shift clock signal SCK.

[0053] In this embodiment, all flip-flops 11 share the same shift clock signal SCK at their shift clock inputs, ensuring that the state updates of each flip-flop 11 in the entire shift register module 1 are completely synchronized. Under the control of the same shift clock edge, each flip-flop 11 simultaneously latches the state of its respective data input to its data output, allowing the enable level to advance in an orderly manner along the cascaded link. Sharing the same shift clock signal SCK also simplifies clock routing, avoids phase deviation problems between multiple clock signals, and helps ensure the timing consistency of the circuit under high-frequency operating conditions.

[0054] Reference Figure 1 In one embodiment of the present invention, the trigger 11 is a D trigger.

[0055] In this embodiment, the D flip-flop has the advantages of simple structure and reliable function. The data output terminal of the D flip-flop follows the level state of the data input terminal when the clock edge arrives, and its timing logic is clear, making it suitable for constructing the basic unit of a shift register.

[0056] Reference Figure 1 and Figure 3 In one embodiment of the present invention, the shift register module 1 and the plurality of gating units 2 are integrated in the same chip.

[0057] In this embodiment, the shift register module 1 and the clock gating unit 2 are integrated into a single design. Compared with the circuit architecture built with discrete components, this effectively reduces external wiring, lowers line signal interference, and reduces the overall size of the circuit, thus meeting the miniaturization and high stability requirements of the display device 1000.

[0058] Reference Figure 1 and Figure 3 The present invention also proposes a clock output device 100, which includes a control module 30 and a clock control circuit 10 as described above. The control module 30 includes a main clock output terminal, a first control terminal and a second control terminal. The main clock output terminal is connected to the first input terminal of each of the gating units 2. The first control terminal is connected to the data input terminal of the first stage flip-flop 11. The second control terminal is connected to the shift clock input terminal of each of the flip-flops 11.

[0059] The clock output device 100 is a complete clock generator integrating the clock control circuit 10 and the control module 30, and can independently output controllable multiple sub-clocks. Since this clock output device 100 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0060] The control module 30, serving as the signal supply and control core of the entire device, generates the master clock signal CLK, the trigger signal SYN, and the shift clock signal SCK. It provides the same master clock signal CLK to all selection units 2 via the master clock output terminal, ensuring the consistency of the reference for each sub-clock signal. It outputs the trigger signal SYN via the first control terminal to control the start-up timing of the circuit clock output. It outputs a unified shift clock signal SCK via the second control terminal to drive the flip-flop 11 to complete the step-by-step shift operation. This device integrates signal generation and timing control functions, exhibiting high structural integration and simple control logic, and can stably output multiple well-defined time-division sub-clock signals.

[0061] Reference Figure 1 and Figure 3 The present invention also proposes a display device 1000, which includes a display module 400 and a clock output device 100 as described above. The display module 400 is provided with a plurality of sub-clock input terminals 401, and each of the sub-clock input terminals 401 is connected to a sub-clock output terminal 21 of each selection unit 2 of the clock control circuit 10 in a one-to-one correspondence.

[0062] The display device 1000 is a terminal device equipped with a clock output device 100 and a display module 400, which drives the pixel array display by relying on multiple time-division sub-clocks. Since the display device 1000 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0063] The display module 400 is a functional module for realizing image imaging, including a pixel driving circuit, which may be a Micro-LED pixel panel or other display panels that require time-division driving of the pixel array.

[0064] The clock output device 100 generates multiple time-division sub-clock signals, which are input one-to-one to the respective sub-clock input terminals 401 of the display module 400, providing precise time-division clock signals for the pixel array driving circuit of the display module 400. By using multiple time-staggered sub-clock signals, row-by-row and column-by-column time-division driving of the pixel array can be achieved, avoiding display drive crosstalk, effectively improving the clarity and stability of the displayed image, and ensuring high-quality imaging of the display device 1000.

[0065] The above are merely preferred embodiments of the present invention and do not limit the scope of protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A clock control circuit, characterized in that, include: The shift register module includes multiple cascaded flip-flops. Each flip-flop includes a data input terminal, a data output terminal, and a shift clock input terminal. The data input terminal of the first flip-flop is used to input a trigger signal. The data output terminal of the preceding flip-flop is connected to the data input terminal of the following flip-flop. The shift clock input terminal of each flip-flop is used to input a shift clock signal. Multiple gating units are provided, each gating unit including a first input terminal, a second input terminal, and a sub-clock output terminal. The first input terminal of each gating unit is used to input the same master clock signal, and the second input terminal of each gating unit is connected to the data output terminal of each flip-flop in a one-to-one correspondence. The sub-clock output terminals of the multiple gating units are used to output multiple sub-clock signals after the master clock signal has been gating processed.

2. The clock control circuit as described in claim 1, characterized in that, Each time the trigger signal is received, each trigger can output an enable level sequentially according to the beat of the shift clock signal, so that each gating unit sequentially selects the master clock signal at one shift clock cycle interval, so as to output multiple sub-clock signals in a time-division manner.

3. The clock control circuit as described in claim 2, characterized in that, The trigger signal consists of multiple single-pulse signals that are time-spaced.

4. The clock control circuit as described in any one of claims 1 to 3, characterized in that, The shift register module is provided with multiple shift register modules, and the data output terminal of the last stage flip-flop of the previous shift register module is connected to the data input terminal of the first stage flip-flop of the next shift register module.

5. The clock control circuit as described in any one of claims 1 to 3, characterized in that, The gating unit is an AND gate unit.

6. The clock control circuit as described in any one of claims 1 to 3, characterized in that, The shift clock input of each of the aforementioned flip-flops is connected to the same terminal that outputs the shift clock signal.

7. The clock control circuit as described in any one of claims 1 to 3, characterized in that, The trigger is a D trigger.

8. The clock control circuit as described in any one of claims 1 to 3, characterized in that, The shift register module and multiple gating units are integrated within the same chip.

9. A clock output device, characterized in that, include: The clock control circuit as described in any one of claims 1 to 8; The control module includes a master clock output terminal, a first control terminal, and a second control terminal. The master clock output terminal is connected to the first input terminal of each of the gating units. The first control terminal is connected to the data input terminal of the first-stage flip-flop. The second control terminal is connected to the shift clock input terminal of each of the flip-flops.

10. A display device, characterized in that, include: The clock output device as described in claim 9; The display module has multiple sub-clock input terminals, and each sub-clock input terminal is connected to a sub-clock output terminal of each selection unit of the clock control circuit.

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