Light emission control circuit, display panel, and display device

Abstract

The application discloses a light-emitting control circuit, a display panel and a display device, and belongs to the technical field of display. The light-emitting control circuit comprises an input control module, a transmission control module, an output module and a node potential control module. The input control module is used for controlling the potential of a first control end and a second control end. The transmission control module is used for controlling the potential of a third control end. The output module is used for outputting a first power signal or a second power signal as a light-emitting control signal according to the potential of the first control end, the potential of the third control end, a second power signal and a second clock signal. The node potential control module is used for transmitting the second power signal to an internal node of the node potential control module in response to the potential of the second control end, and transmitting the potential of the internal node to the first control end in response to the second clock signal. The storage module is connected to the internal node and connected to a fixed voltage signal, and is used for storing the potential of the internal node. The embodiment of the application can improve the reliability of the light-emitting control circuit, and further improve the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a light-emitting control circuit, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays and flat panel displays based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display devices. However, the reliability of current light-emitting control circuits is relatively poor, affecting the display effect of the display panel. Summary of the Invention

[0003] This invention provides a light-emitting control circuit, a display panel, and a display device to improve the reliability of the light-emitting control circuit, thereby improving the display effect of the display panel.

[0004] In a first aspect, embodiments of the present invention provide a light-emitting control circuit, comprising:

[0005] The input control module includes a first control terminal and a second control terminal, used to control the potential of the first control terminal and the second control terminal according to a first clock signal, an input signal and a first power supply signal;

[0006] A transmission control module is connected to the second control terminal and includes a third control terminal, used to control the potential of the third control terminal according to the potential of the second control terminal and a second clock signal;

[0007] The output module is connected to the first control terminal and the third control terminal respectively, and is used to output the first power signal or the second power signal as a light emission control signal according to the potential of the first control terminal, the potential of the third control terminal, the second power signal and the second clock signal.

[0008] A node potential control module is connected to the first control terminal and the second control terminal respectively. It is used to transmit the second power signal to the internal node of the node potential control module in response to the potential of the second control terminal, and to transmit the potential of the internal node to the first control terminal in response to the second clock signal.

[0009] A storage module, wherein a first end of the storage module is connected to the internal node, and a second end of the storage module is connected to a fixed voltage signal, and the storage module is used to store the potential of the internal node.

[0010] Optionally, the storage module includes a first capacitor; a first terminal of the first capacitor is connected to the internal node, and a second terminal of the first capacitor is connected to the fixed voltage signal.

[0011] Preferably, the first power signal or the second power signal is multiplexed into the fixed voltage signal.

[0012] Optionally, the transmission control module includes:

[0013] The first transmission unit is connected to the second control terminal and is used to control whether to transmit the second clock signal to the output terminal of the first transmission unit according to the potential of the second control terminal.

[0014] The second transmission unit is connected to the output terminal of the first transmission unit and the third control terminal respectively, and is used to control whether to transmit the potential of the output terminal of the first transmission unit to the third control terminal according to the second clock signal.

[0015] The output module includes:

[0016] The third transmission unit is connected to the first control terminal and the third control terminal respectively, and is used to control whether to transmit the second power signal to the third control terminal according to the potential of the first control terminal.

[0017] The first output unit is connected to the first control terminal and the light-emitting control output terminal of the light-emitting control circuit, respectively, and is used to control whether to transmit the first power signal to the light-emitting control output terminal as the light-emitting control signal according to the potential of the first control terminal and the second clock signal.

[0018] The second output unit is connected to the third control terminal and the light emission control output terminal respectively, and is used to control whether to transmit the second power signal to the light emission control output terminal as the light emission control signal according to the potential of the third control terminal.

[0019] Preferably, the first transmission unit includes: a first transistor and a second capacitor; the gate of the first transistor and the first terminal of the second capacitor are both connected to the second control terminal, the first electrode of the first transistor is connected to the second clock signal, and the second electrode of the first transistor and the second terminal of the second capacitor are both connected to the output terminal of the first transmission unit;

[0020] The second transmission unit includes: a second transistor; the gate of the second transistor is connected to the second clock signal, the first terminal of the second transistor is connected to the output terminal of the first transmission unit, and the second terminal of the second transistor is connected to the third control terminal;

[0021] The third transmission unit includes: a third transistor; the gate of the third transistor is connected to the first control terminal, the first terminal of the third transistor is connected to the second power supply signal, and the second terminal of the third transistor is connected to the third control terminal;

[0022] The first output unit includes: a fourth transistor and a third capacitor; the gate of the fourth transistor and the first terminal of the third capacitor are both connected to the first control terminal, the second terminal of the third capacitor is connected to the second clock signal, the first terminal of the fourth transistor is connected to the first power supply signal, and the second terminal of the fourth transistor is connected to the light emission control output terminal;

[0023] The second output unit includes a fifth transistor and a fourth capacitor; the gate of the fifth transistor and the first terminal of the fourth capacitor are both connected to the third control terminal, the second terminal of the fourth capacitor and the first terminal of the fifth transistor are both connected to the second power supply signal, and the second terminal of the fifth transistor is connected to the light emission control output terminal.

[0024] Optionally, the capacitance of the first capacitor is greater than the minimum value among the capacitances of the second capacitor, the third capacitor, and the fourth capacitor.

[0025] Optionally, the capacitance of the first capacitor is less than the maximum value among the capacitances of the second capacitor, the third capacitor, and the fourth capacitor.

[0026] Optionally, the node potential control module includes:

[0027] The fourth transmission unit is connected to the second control terminal and the internal node respectively, and is used to transmit the second power signal to the internal node in response to the potential of the second control terminal;

[0028] The fifth transmission unit is connected to the internal node and the first control terminal respectively, and is used to transmit the potential of the internal node to the first control terminal in response to the second clock signal;

[0029] Preferably, the fourth transmission unit includes: a sixth transistor; the gate of the sixth transistor is connected to the second control terminal, the first terminal of the sixth transistor is connected to the second power supply signal, and the second terminal of the sixth transistor is connected to the internal node;

[0030] The fifth transmission unit includes a seventh transistor; the gate of the seventh transistor is connected to the second clock signal, the first terminal of the seventh transistor is connected to the internal node, and the second terminal of the seventh transistor is connected to the first control terminal.

[0031] Optionally, the seventh transistor is a dual-gate transistor, which includes a first sub-transistor and a second sub-transistor connected in series between the internal node and the first control terminal, wherein the gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the second clock signal.

[0032] Optionally, the input control module includes:

[0033] An input unit, connected to the first control terminal, is used to control whether the input signal is transmitted to the first control terminal according to the first clock signal;

[0034] The sixth transmission unit, connected to the second control terminal, is used to control whether the first power signal is transmitted to the second control terminal according to the first clock signal;

[0035] The seventh transmission unit is connected to the first control terminal and the second control terminal respectively, and is used to control whether the first clock signal is transmitted to the second control terminal according to the potential of the first control terminal;

[0036] Preferably, the input unit includes: an eighth transistor; the gate of the eighth transistor is connected to the first clock signal, the first terminal of the eighth transistor is connected to the input signal, and the second terminal of the eighth transistor is connected to the first control terminal;

[0037] The sixth transmission unit includes: a ninth transistor; the gate of the ninth transistor is connected to the first clock signal, the first terminal of the ninth transistor is connected to the first power supply signal, and the second terminal of the ninth transistor is connected to the second control terminal;

[0038] The seventh transmission unit includes a tenth transistor; the gate of the tenth transistor is connected to the first control terminal, the first terminal of the tenth transistor is connected to the first clock signal, and the second terminal of the tenth transistor is connected to the second control terminal.

[0039] Secondly, embodiments of the present invention also provide a display panel, including: the light-emitting control circuit provided in any embodiment of the present invention.

[0040] Thirdly, embodiments of the present invention also provide a display device, including: a display panel provided in any embodiment of the present invention.

[0041] The light-emitting control circuit provided in this embodiment of the invention includes an input control module, a transmission control module, an output module, a node potential control module, and a storage module. Based on the input signal, various clock signals, and power signals, the input control module, transmission control module, and node potential control module can jointly control the potentials of the first control terminal and the third control terminal. The output module can control the potential of the light-emitting control signal based on the potentials of the first and third control terminals. The storage module maintains the potential of the internal nodes of the node potential control module, especially when the node potential control module cannot transmit the second power signal to the internal nodes. The storage module can stabilize the potential of the internal nodes, preventing them from being affected by other signals, thus stabilizing the working state of the node potential control module and ensuring the stability and correctness of the potential of the first control terminal. This allows the output module to output stably, avoiding abnormalities in the light-emitting control signal. In summary, this embodiment of the invention improves the reliability of the light-emitting control circuit, thereby enhancing the display effect of the display panel.

[0042] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of a light-emitting control circuit provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the driving timing of a light-emitting control circuit provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0053] This invention provides a light-emitting control circuit that can achieve stable output of light-emitting control signals and improve the reliability of the light-emitting control circuit. Figure 1 This is a schematic diagram of a light-emitting control circuit provided in an embodiment of the present invention. See also... Figure 1 The light emission control circuit includes: an input control module 10, a transmission control module 20, an output module 30, a node potential control module 40, and a storage module 50.

[0054] The input control module 10 includes a first control terminal N1 and a second control terminal N2. The input control module 10 controls the potentials of the first control terminal N1 and the second control terminal N2 according to a first clock signal ECK1, an input signal EIN, and a first power signal VGL. The transmission control module 20 is connected to the second control terminal N2 and includes a third control terminal N3. The transmission control module 20 controls the potential of the third control terminal N3 according to the potential of the second control terminal N2 and the second clock signal ECK2. The output module 30 is connected to both the first control terminal N1 and the third control terminal N3. The output module 30 outputs either the first power signal VGL or the second power signal VGH as a light emission control signal EM according to the potentials of the first control terminal N1, the third control terminal N3, the second power signal VGH, and the second clock signal ECK2. The node potential control module 40 is connected to the first control terminal N1 and the second control terminal N2 respectively. The node potential control module 40 is used to transmit the second power signal VGH to the internal node N4 in response to the potential of the second control terminal N2, and to transmit the potential of the internal node N4 to the first control terminal N1 in response to the second clock signal ECK2. The first terminal of the storage module 50 is connected to the internal node N4, and the second terminal of the storage module 50 is connected to a fixed voltage signal VC. The storage module 50 is used to store the potential of the internal node N4.

[0055] For example, both the first power supply signal VGL and the second power supply signal VGH are DC voltage signals with different potentials; for instance, the first power supply signal VGL has a low potential, and the second power supply signal VGH has a high potential. Both the first clock signal ECK1 and the second clock signal ECK2 can be clock signals that alternate between high and low potentials, and the on-state pulses of the first clock signal ECK1 and the second clock signal ECK2 are interleaved. For example, the low potential of the two clock signals can be equal to the potential of the first clock signal VGL, and the high potential of the two clock signals can be equal to the potential of the second power supply signal VGH.

[0056] For example, the control process of each functional module in the light-emitting control circuit can be:

[0057] The input control module 10 controls whether the input signal EIN is transmitted to the first control terminal N1 according to the first clock signal ECK1, thereby controlling the potential of the first control terminal N1. Also, the input control module 10 controls whether the first power signal VGL is transmitted to the second control terminal N2 according to the first clock signal ECK1; and the input control module 10 controls whether the first clock signal ECK1 is transmitted to the second control terminal N2 according to the potential of the first control terminal N1, thereby controlling the potential of the second control terminal N2.

[0058] For the node potential control module 40, for example, the first control node of the node potential control module 40 is connected to the second control terminal N2, the second control node is connected to the second clock signal ECK2, the input node is connected to the second power signal VGH, and the output node is connected to the first control terminal N1. The node potential control module 40 can, for example, control whether its input node and internal node N4 are connected according to the potential of the second control terminal N2, thereby controlling whether the second power signal VGH is transmitted to the internal node N4. The node potential control module 40 can also, for example, control whether its internal node N4 and output node are connected according to the second clock signal ECK2, thereby controlling whether the potential of the internal node N4 is transmitted to the first control terminal N1.

[0059] For example, the transmission control module 20 controls whether the second clock signal ECK2 is transmitted to the internal node of the transmission control module 20 according to the potential of the second control terminal N2, and controls whether the potential of the internal node of the transmission control module 20 is transmitted to the third control terminal N3 according to the second clock signal ECK2, thereby realizing the control of the potential of the third control terminal N3.

[0060] Output module 30, for example, can control whether the second power signal VGH is transmitted to the third control terminal N3 based on the potential of the first control terminal N1, control whether the first power signal VGL is output as the light-emitting control signal EM based on the potential of the first control terminal N1 and the second clock signal ECK2, and control whether the second power signal VGH is output as the light-emitting control signal EM based on the potential of the third control terminal N3. It can be understood that, based on the cooperation of each functional module, the light-emitting control circuit can achieve the shifted output of the input signal EIN. Specifically, under the joint control of input control module 10, node potential control module 40, and transmission control module 20, at most one of the first control terminal N1 and the third control terminal N3 is at the conduction potential of the transistor in the connected output module 30 at any given time, to avoid the simultaneous output of the second power signal VGH and the first power signal VGL.

[0061] The storage module 50 is used to store the potential of the internal node N4. Specifically, during the period when the potential of the second control terminal N2 is required to make the input node of the node potential control module 40 conduct with the internal node N4, so that the second power signal VGH is continuously transmitted to the internal node N4, if the potential of the second control terminal N2 fluctuates due to leakage of the transistor inside the input control module 10, causing the input node of the node potential control module 40 to disconnect from the internal node N4, the internal node N4 will not be able to receive the second power signal VGH. Without a potential maintenance measure, the potential of the internal node N4 is easily affected by coupling or other potentials. At this time, if the internal node N4 of the second clock signal controls the conduction between the output node and the output node of the potential control module 40, the potential transmitted from the internal node N4 to the first control terminal N1 cannot be guaranteed, thereby affecting the operation performed by the output module 30 corresponding to the potential of the first control terminal N1, such as causing the output module 30 to erroneously output the first power signal VGL, affecting the reliability of the light emission control circuit. In this embodiment, based on the storage function of the storage module 50, when the input node of the node potential control module 40 is disconnected from the internal node N4, the potential of the internal node N4 can be effectively stored. For example, when the input node of the node potential control module 40 is disconnected from the internal node N4 for some reason, the storage module 50 can stabilize the potential of the internal node N4 to the potential of the second power signal VGH. Thus, when the internal node N4 of the potential control module 40 is connected to the output node, the potential of the second power signal VGH can be stably transmitted to the first control terminal N1 to avoid malfunction of the output module 30 and improve the output stability of the light emission control circuit.

[0062] The light-emitting control circuit provided in this embodiment of the invention includes an input control module 10, a transmission control module 20, an output module 30, a node potential control module 40, and a storage module 50. Based on the input signal EIN, various clock signals, and power signals, the input control module 10, transmission control module 20, and node potential control module 40 can jointly control the potentials of the first control terminal N1 and the third control terminal N3. The output module 30 can control the potential of the light-emitting control signal EM based on the potentials of the first control terminal N1 and the third control terminal N3. The storage module 50 maintains the potential of the internal node N4 of the node potential control module 40, especially when the node potential control module 40 cannot transmit the second power signal VGH to the internal node N4. The storage module 50 can stabilize the potential of the internal node N4, preventing it from being affected by other signals, thus stabilizing the working state of the node potential control module 40 and ensuring the stable and correct potential of the first control terminal N1. This allows the output module 30 to output stably, preventing abnormalities in the light-emitting control signal EM. In summary, the embodiments of the present invention can improve the reliability of the light-emitting control circuit, thereby improving the display effect of the display panel.

[0063] Figure 2 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention. See also... Figure 2 Based on the above embodiments, optionally, the storage module 50 includes a first capacitor C1; the first end of the first capacitor C1 is connected to the internal node N4, and the second end of the first capacitor C1 is connected to a fixed voltage signal VC. This embodiment sets the storage module 50 to include a single capacitor, making the structure of the storage module 50 simple and easy to implement.

[0064] Based on the above embodiments, optionally, the fixed voltage signal VC can be an additionally provided DC voltage signal. Alternatively, any DC voltage signal connected to other functional modules in the light-emitting control circuit can be multiplexed into the fixed voltage signal VC to simplify the panel structure and wiring. Specifically, a first power signal VGL or a second power signal VGH can be multiplexed into the fixed voltage signal VC. For example, the second power signal VGH can be multiplexed into the fixed voltage signal VC.

[0065] See also Figure 2 Based on the above embodiments, optionally, the node potential control module 40 includes a fourth transmission unit 41 and a fifth transmission unit 42. The fourth transmission unit 41 is connected to the second control terminal N2 and the internal node N4, and is connected to a second power signal VGH; the fourth transmission unit 41 is used to transmit the second power signal VGH to the internal node N4 in response to the potential of the second control terminal N2. The fifth transmission unit 42 is connected to the internal node N4 and the first control terminal N1, and is connected to a second clock signal ECK2; the fifth transmission unit 42 is used to transmit the potential of the internal node N4 to the first control terminal N1 in response to the second clock signal ECK2. This embodiment sets the node potential control module 40 to include two transmission units, clarifying the control structure and control method of the node potential control module 40 for the potentials of the internal node N4 and the first control terminal N1.

[0066] Figure 3 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention. See also... Figure 3Based on the above embodiments, optionally, the input control module 10 includes: an input unit 11, a sixth transmission unit 12, and a seventh transmission unit 13. The input unit 11 is connected to the first control terminal N1 and receives a first clock signal ECK1 and an input signal EIN; the input unit 11 is used to control whether the input signal EIN is transmitted to the first control terminal N1 according to the first clock signal ECK1. The sixth transmission unit 12 is connected to the second control terminal N2 and receives the first clock signal ECK1 and a first power signal VGL; the sixth transmission unit 12 is used to control whether the first power signal VGL is transmitted to the second control terminal N2 according to the first clock signal ECK1. The seventh transmission unit 13 is connected to both the first control terminal N1 and the second control terminal N2 and receives the first clock signal ECK1; the seventh transmission unit 13 is used to control whether the first clock signal ECK1 is transmitted to the second control terminal N2 according to the potential of the first control terminal N1. This embodiment sets the input control module 10 to include an input unit 11 and two transmission units, and clarifies the method of controlling the potential of the first control terminal N1 according to the input signal EIN, the method of controlling the potential of the second control terminal N2 according to the first power signal VGL, and the method of controlling the potential of the second control terminal N2 according to the potential of the first control terminal N1.

[0067] The transmission control module 20 includes a first transmission unit 21 and a second transmission unit 22. The first transmission unit 21 is connected to a second control terminal N2 and receives a second clock signal ECK2. The first transmission unit 21 controls whether to transmit the second clock signal ECK2 to the output terminal of the first transmission unit 21 based on the potential of the second control terminal N2. The second transmission unit 22 is connected to the output terminal of the first transmission unit 21 and a third control terminal N3. The second transmission unit 22 controls whether to transmit the potential of the output terminal of the first transmission unit 21 to the third control terminal N3 based on the second clock signal ECK2. This embodiment sets the transmission control module 20 to include two transmission units, clarifying the control structure and control method of the transmission control module 20 for the potential of the third control terminal N3.

[0068] The output module 30 includes a third transmission unit 33, a first output unit 31, and a second output unit 32. The third transmission unit 33 is connected to both the first control terminal N1 and the third control terminal N3, and is connected to a second power signal VGH. The third transmission unit 33 controls whether to transmit the second power signal VGH to the third control terminal N3 based on the potential of the first control terminal N1. The first output unit 31 is connected to both the first control terminal N1 and the light-emitting control output terminal OUT of the light-emitting control circuit, and is connected to a second clock signal ECK2 and a first power signal VGL. The first output unit 31 controls whether to transmit the first power signal VGL to the light-emitting control output terminal OUT based on the potential of the first control terminal N1 and the second clock signal ECK2. The light-emitting control output terminal OUT outputs the light-emitting control signal EM. The second output unit 32 is connected to both the third control terminal N3 and the light-emitting control output terminal OUT, and is connected to the second power signal VGH. The second output unit 32 controls whether to transmit the second power signal VGH to the light-emitting control output terminal OUT as the light-emitting control signal EM based on the potential of the third control terminal N3. This embodiment sets the output module 10 to include a transmission unit and two output units, and clarifies the method of controlling the potential of the third control terminal N3 according to the potential of the first control terminal N1, and the method of controlling the potential of the light emission control signal EM according to the potential of the first control terminal N1 and the potential of the third control terminal N3.

[0069] The specific structure of each functional unit in the light-emitting control circuit is described below by way of example, but it is not intended to limit the present invention.

[0070] Figure 4 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention. See also... Figure 4 Based on the above embodiments, the specific structure of the light-emitting control circuit may optionally be as follows:

[0071] The input unit 11 includes an eighth transistor M8; the gate of the eighth transistor M8 is connected to a first clock signal ECK1, the first terminal of the eighth transistor M8 is connected to an input signal EIN, and the second terminal of the eighth transistor M8 is connected to a first control terminal N1. The eighth transistor M8 is used to transmit the input signal EIN to the first control terminal N1 when it is turned on according to the first clock signal ECK1.

[0072] The sixth transmission unit 12 includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to a first clock signal ECK1, the first terminal of the ninth transistor M9 is connected to a first power supply signal VGL, and the second terminal of the ninth transistor M9 is connected to a second control terminal N2. The ninth transistor M9 is used to transmit the first power supply signal VGL to the second control terminal N2 when it is turned on according to the first clock signal ECK1.

[0073] The seventh transmission unit 13 includes a tenth transistor M10; the gate of the tenth transistor M10 is connected to the first control terminal N1, the first terminal of the tenth transistor M10 is connected to the first clock signal ECK1, and the second terminal of the tenth transistor M10 is connected to the second control terminal N2. The tenth transistor M10 is used to transmit the first clock signal ECK1 to the second control terminal N2 when it is turned on according to the potential of the first control terminal N1.

[0074] The fourth transmission unit 41 includes a sixth transistor M6; the gate of the sixth transistor M6 is connected to the second control terminal N2, the first terminal of the sixth transistor M6 is connected to the second power supply signal VGH, and the second terminal of the sixth transistor M6 is connected to the internal node N4. The sixth transistor M6 is used to transmit the second power supply signal VGH to the internal node N4 when it is turned on according to the potential of the second control terminal N2.

[0075] The fifth transmission unit 42 includes a seventh transistor M7; the gate of the seventh transistor M7 is connected to the second clock signal ECK2, the first terminal of the seventh transistor M7 is connected to the internal node N4, and the second terminal of the seventh transistor M7 is connected to the first control terminal N1. The seventh transistor M7 is used to transmit the potential of the internal node N4 to the first control terminal N1 when it is turned on according to the second clock signal ECK2.

[0076] The first transmission unit 21 includes a first transistor M1 and a second capacitor C2. The gate of the first transistor M1 and the first terminal of the second capacitor C2 are both connected to a second control terminal N2. The first terminal of the first transistor M1 is connected to a second clock signal ECK2. The second terminal of the first transistor M1 and the second terminal of the second capacitor C2 are both connected to the output terminal of the first transmission unit 21. When the first transistor M1 is turned on according to the potential of the second control terminal N2, it transmits the second clock signal ECK2 to the output terminal of the first transmission unit 21. The second capacitor C2 is used to maintain the potential of the second control terminal N2.

[0077] The second transmission unit 22 includes a second transistor M2; the gate of the second transistor M2 is connected to a second clock signal ECK2, the first terminal of the second transistor M2 is connected to the output terminal of the first transmission unit 21, and the second terminal of the second transistor M2 is connected to a third control terminal N3. The second transistor M2 is used to transmit the potential of the output terminal of the first transmission unit 21 to the third control terminal N3 when it is turned on according to the second clock signal ECK2.

[0078] The third transmission unit 33 includes a third transistor M3; the gate of the third transistor M3 is connected to the first control terminal N1, the first terminal of the third transistor M3 is connected to the second power supply signal VGH, and the second terminal of the third transistor M3 is connected to the third control terminal N3. The third transistor M3 is used to transmit the second power supply signal VGH to the third control terminal N3 when it is turned on according to the potential of the first control terminal N1.

[0079] The first output unit 31 includes a fourth transistor M4 and a third capacitor C3. The gate of the fourth transistor M4 and the first terminal of the third capacitor C3 are both connected to the first control terminal N1. The second terminal of the third capacitor C3 is connected to the second clock signal ECK2. The first terminal of the fourth transistor M4 is connected to the first power supply signal VGL. The second terminal of the fourth transistor M4 is connected to the light-emitting control output terminal OUT. The fourth transistor M4 is used to transmit the first power supply signal VGL to the light-emitting control output terminal OUT when it is turned on according to the potential of the first control terminal N1. The third capacitor C3 is used to couple the voltage transition of the second clock signal ECK2 to the first control terminal N1, thereby controlling the conduction level of the fourth transistor M4.

[0080] The second output unit 32 includes a fifth transistor M5 and a fourth capacitor C4. The gate of the fifth transistor M5 and the first terminal of the fourth capacitor C4 are both connected to the third control terminal N3. The second terminal of the fourth capacitor C4 and the first terminal of the fifth transistor M5 are both connected to the second power supply signal VGH. The second terminal of the fifth transistor M5 is connected to the light-emitting control output terminal OUT. The fifth transistor M5 is used to transmit the second power supply signal VGH to the light-emitting control output terminal OUT when it is turned on according to the potential of the third control terminal N3. The fourth capacitor C4 is used to store (or maintain) the potential of the third control terminal N3.

[0081] Figure 5 This is a schematic diagram of the driving timing of a light-emitting control circuit provided in an embodiment of the present invention. The following is in conjunction with... Figure 4 and Figure 5 Taking the example that all transistors in the light-emitting control circuit are P-type transistors, the first power supply signal VGL has a low potential, and the second power supply signal VGH has a high potential, the working process of the light-emitting control circuit is illustrated by way of example.

[0082] See Figure 4 and Figure 5 The working process of the light-emitting control circuit includes:

[0083] In the first stage T1, the first clock signal ECK1 is at a low level, while the second clock signal ECK2 and the first input signal EIN are at a high level. The eighth transistor M8 and the ninth transistor M9 are turned on, while the seventh transistor M7 and the second transistor M2 are turned off. The high level of the first input signal EIN is transmitted to the first control terminal N1 through the eighth transistor M8, causing the tenth transistor M10, the third transistor M3, and the fourth transistor M4 to turn off. The low level of the first power supply signal VGL is transmitted to the second control terminal N2 through the ninth transistor M9, causing the sixth transistor M6 and the first transistor M1 to turn on. The high level of the second power supply signal VGH is transmitted to the internal node N4 through the sixth transistor M6, charging the first capacitor C1. Simultaneously, because the seventh transistor M7 is turned off, the high level of the internal node N4 is not transmitted to the first control terminal N1. Due to the storage function of the fourth capacitor C4, the third control terminal N3 maintains the potential from the previous stage (high level here), causing the fifth transistor M5 to turn off. Therefore, in the first stage T1, both the fifth transistor M5 and the fourth transistor M4 are turned off, and the light emission control signal EM remains at the potential of the previous stage (which is a low potential here).

[0084] In the second stage T2, the second clock signal ECK2 is at a low level, while the first clock signal ECK1 and the first input signal EIN are at a high level. The seventh transistor M7 and the second transistor M2 are turned on, while the eighth transistor M8 and the ninth transistor M9 are turned off. Due to the storage function of the second capacitor C2, the second control terminal N2 maintains the low level of the previous stage, causing the sixth transistor M6 and the first transistor M1 to turn on. The high level of the second power supply signal VGH is transmitted to the intermediate node N4 through the sixth transistor M6, and further to the first control terminal N1 through the seventh transistor M7, causing the tenth transistor M10, the third transistor M3, and the fourth transistor M4 to remain off. The low level of the second clock signal ECK2 is transmitted to the output terminal of the first transmission unit 21 through the first transistor M1, and further to the third control terminal N3 through the second transistor M2, causing the fifth transistor M5 to turn on. The second power supply signal VGH is transmitted to the light-emitting control output terminal OUT through the fifth transistor M5, and the light-emitting control signal EM becomes high.

[0085] In the third stage (T3), the first clock signal ECK1 is at a low level, while the second clock signal ECK2 and the first input signal EIN are at a high level. The eighth transistor M8 and the ninth transistor M9 are turned on, while the seventh transistor M7 and the second transistor M2 are turned off. Due to the storage function of the fourth capacitor C4, the third control terminal N3 remains at a low level from the previous stage, causing the fifth transistor M5 to remain on and the light-emitting control signal EM to remain at a high level. The on / off states of the remaining transistors are the same as in the first stage (T1) and will not be repeated here.

[0086] In stage T4, the first clock signal ECK1 is high, while the second clock signal ECK2 and the first input signal EIN are low. The eighth transistor M8 and the ninth transistor M9 are off, while the seventh transistor M7 and the second transistor M2 are on. Due to the storage function of the second capacitor C2, the second control terminal N2 maintains the low potential from the previous stage, causing the sixth transistor M6 and the first transistor M1 to turn on. The high potential of the second power supply signal VGH is transmitted to the intermediate node N4 through the sixth transistor M6, and further to the first control terminal N1 through the seventh transistor M7, causing the tenth transistor M10, the third transistor M3, and the fourth transistor M4 to remain off. The low potential of the second clock signal ECK2 is transmitted to the output terminal of the first transmission unit 21 through the first transistor M1, and further to the third control terminal N3 through the second transistor M2, causing the fifth transistor M5 to turn on. The high potential of the second power supply signal VGH is transmitted to the light-emitting control output terminal OUT through the fifth transistor M5, and the light-emitting control signal EM remains high.

[0087] In stage T5, the second clock signal ECK2 is at a high level, while the first clock signal ECK1 and the first input signal EIN are at a low level. The eighth transistor M8 and the ninth transistor M9 are turned on, while the seventh transistor M7 and the second transistor M2 are turned off. The low level of the first input signal EIN is transmitted to the first control terminal N1 through the eighth transistor M8, turning on the tenth transistor M10, the third transistor M3, and the fourth transistor M4. The low level of the first clock signal ECK1 is transmitted to the second control terminal N2 through the tenth transistor M10, turning on the sixth transistor M6 and the first transistor M1. The high level of the second power supply signal VGH is transmitted to the internal node N4 through the sixth transistor M6, but because the seventh transistor M7 is turned off, the high level of the internal node N4 is not transmitted to the first control terminal N1. The high level of the second clock signal ECK2 is transmitted to the output terminal of the first transmission unit 21 through the first transistor M1, but because the second transistor M2 is turned off, the potential at the output terminal of the first transmission unit 21 cannot be transmitted to the third control terminal N3. The high potential of the second power supply signal VGH is transmitted to the third control terminal N3 through the third transistor M3, causing the fifth transistor M5 to be turned off. The low potential of the first power supply signal VGL is transmitted to the light emission control output terminal OUT through the fourth transistor M4, causing the light emission control signal EM to go low.

[0088] In stage T6, the first clock signal ECK1 is high, while the second clock signal ECK2 and the first input signal EIN are low. The seventh transistor M7 and the second transistor M2 are turned on, while the eighth transistor M8 and the ninth transistor M9 are turned off. Due to the bootstrap effect of the third capacitor C3, as the second clock signal ECK2 goes low, the potential of the first control terminal N1 is coupled to a lower potential than in stage T5, allowing the fourth transistor M4 to conduct more fully, thus better transmitting the first power supply signal VGL to the light-emitting control output terminal OUT. Furthermore, the third transistor M3 and the tenth transistor M10 also remain on. The high potential of the first clock signal ECK1 is transmitted to the second control terminal N2 through the tenth transistor M10, causing N2 to change from low to high, controlling the sixth transistor M6 and the first transistor M1 to turn off. At this time, the low potential of the first control terminal N1 is transmitted to the internal node N4 through the seventh transistor M7. The high potential of the second power supply signal VGH is transmitted to the third control terminal N3 through the third transistor M3, keeping the fifth transistor M5 off. During this phase, the light emission control signal EM remains at a low potential.

[0089] The subsequent stages repeat the fifth stage T5 and the sixth stage T6, with the light emission control signal EM remaining at a low potential until the input signal EIN jumps to a high potential again.

[0090] In summary, the light-emitting control circuit provided in this embodiment of the invention can achieve shifted output of the input signal EIN.

[0091] As can be seen from the above analysis, in the first stage T1 to the fifth stage T5, the sixth transistor M6 remains in the conducting state, capable of transmitting the potential of the second power supply signal VGH to the internal node N4. However, in the stage where the first clock signal ECK1 is at a high potential, such as in the second stage T2, the second control terminal N2 is actually in a floating state, and the low potential of the second control terminal N2 is maintained by the second capacitor C2; and the high potential of the first control terminal N1 is supplied by the internal node N4. In the second stage T2, the tenth transistor M10 is turned off, and its gate is at a high potential, causing the tenth transistor M10 to withstand a large voltage stress. If the tenth transistor M10 is in the above-mentioned stress state for a long time, it will cause the threshold voltage of the tenth transistor M10 to drift positively, thereby increasing the leakage current of the tenth transistor M10, which in turn raises the potential of the second control terminal N2, causing the sixth transistor M6 to turn off, and causing the internal node N4 to lose its high potential source. In this case, if the first capacitor C1 is not set, due to the coupling effect of the third capacitor C3, the potential of the first control terminal N1 may be pulled low by the potential jump of the second clock signal ECK2, causing the fourth transistor M4 to turn on abnormally, resulting in the potential of the light emission control signal EM becoming low, causing the timing error of the light emission control signal EM, affecting the display effect, such as causing flickering.

[0092] In this embodiment, by setting a first capacitor C1, when the sixth transistor M6 is turned on, the first power signal VGH can charge the first capacitor C1. When the sixth transistor M6 is abnormally turned off due to leakage of the tenth transistor M10, the first capacitor C1 can act as a source for the internal node N4, keeping the internal node N4 at a high potential. This ensures that the potential of the first control terminal N1 is not significantly affected by the coupling effect of the third capacitor C3, thereby preventing the fourth transistor M4 from being mis-turned on. This results in a stable and correctly timed output light-emitting control signal EM, avoiding flickering and improving the display effect. It is understood that this light-emitting control circuit is particularly suitable for scenarios where PWM dimming is used under low brightness conditions on the display panel. Specifically, under low brightness requirements, PWM dimming is typically achieved by black-pinning (e.g., increasing the frequency of the high-potential pulse of the light-emitting control signal EM). For example, a duty cycle of approximately 90% for the high-potential pulse of the light-emitting control signal EM can achieve a display brightness of 2 nits. When using PWM dimming to achieve low brightness display, the first control terminal N1 needs to maintain a high potential for a long time. The tenth transistor M10 is in the off state for a long time and bears a large voltage stress, which is prone to threshold voltage drift. At this time, the first capacitor C1 is especially needed to stabilize the potential of the fourth node N4 to avoid display problems such as flickering.

[0093] Based on the above embodiments, optionally, the capacitance value of the first capacitor C1 can be set to be greater than the minimum value among the capacitance values ​​of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. This setting ensures that the capacitance value of the first capacitor C1 is sufficient, for example, to resist the pulling-down effect of the coupling effect of the third capacitor C3 on the first control terminal N1, thereby better stabilizing the potential of the first control terminal N1 of the internal node N4.

[0094] Based on the above embodiments, optionally, the capacitance value of the first capacitor C1 can be set to be less than the maximum value among the capacitance values ​​of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. This setting can effectively reduce the layout area of ​​the first capacitor C1 while ensuring a stable voltage, thereby reducing the bezel size of the display panel and avoiding the impact of a large capacitor on the circuit's operating speed, thus ensuring the performance of the light-emitting control circuit.

[0095] Figure 6 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention. See also... Figure 6 Based on the above embodiments, optionally, the seventh transistor M7 is a dual-gate transistor, comprising: a first sub-transistor M71 and a second sub-transistor M72 connected in series between the internal node N4 and the first control terminal N1. The gates of both the first sub-transistor M71 and the second sub-transistor M72 are connected to the second clock signal ECK2. This configuration can effectively reduce leakage current on the seventh transistor M7 and avoid the following situation when the first control terminal N1 is at a low potential and the seventh transistor M7 is turned off: due to the large voltage difference between the first control terminal N1 and the internal node N4, the leakage current of the seventh transistor M7 is severe, causing the potential of the first control terminal N1 to be pulled high, thereby affecting the normal output of the light emission control signal EM.

[0096] In summary, by optimizing the structural design of the light-emitting control circuit, the embodiments of the present invention can improve the output stability of the light-emitting control circuit, which is particularly beneficial for improving the problem of abnormal output of the light-emitting control signal under low brightness, solving the flickering problem, and improving the display effect of the display panel.

[0097] This invention also provides a display panel, including the light-emitting control circuit provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 7For example, the display panel may include cascaded multi-level light emission control circuits 100 to realize the step-by-step shifting output of each level of light emission control signal EM, and to provide light emission control signals EM to the multi-row pixel circuits in the display panel through each light emission control signal line. The light emission control circuit 100 is, for example, disposed in the non-display area NAA of the display panel, and the pixel circuit is, for example, disposed in the display area AA of the display panel.

[0098] The light-emitting control signal EM output by the current-level light-emitting control circuit 100 serves both as the control signal for the light-emitting control transistor in the corresponding row pixel circuit and as the input signal for the next-level light-emitting control circuit 100. Exemplarily, the display panel further includes: an input signal line 92 for providing a start input signal IN as the input signal for the first-level light-emitting control circuit 100; a first clock signal line and a second clock signal line for providing a first global clock signal CLK1 and a second global clock signal CLK2, respectively; and a first power signal line and a second power signal line for providing a first power signal VGL and a second power signal VGH, respectively. Each level of the light-emitting control circuit 100 is connected to both the first and second power signal lines. Furthermore, each level of the light-emitting control circuit 100 is alternately connected to the first clock signal line and the second clock signal line; specifically, the first global clock signal CLK1 can serve as the first clock signal for odd-numbered-level light-emitting control circuits 100 and the second clock signal for even-numbered-level light-emitting control circuits 100; the second global clock signal CLK2 can serve as the second clock signal for odd-numbered-level light-emitting control circuits 100 and the first clock signal for even-numbered-level light-emitting control circuits 100.

[0099] This invention also provides a display device, including the display panel provided in any embodiment of this invention, which has corresponding beneficial effects.

[0100] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A light emission control circuit, characterized by comprising: include: The input control module includes a first control terminal and a second control terminal, used to control the potential of the first control terminal and the second control terminal according to a first clock signal, an input signal and a first power supply signal; A transmission control module is connected to the second control terminal and includes a third control terminal, used to control the potential of the third control terminal according to the potential of the second control terminal and a second clock signal; The output module is connected to the first control terminal and the third control terminal respectively, and is used to output the first power signal or the second power signal as a light emission control signal according to the potential of the first control terminal, the potential of the third control terminal, the second power signal and the second clock signal. A node potential control module is connected to the first control terminal and the second control terminal respectively. It is used to transmit the second power signal to the internal node of the node potential control module in response to the potential of the second control terminal, and to transmit the potential of the internal node to the first control terminal in response to the second clock signal. A storage module, wherein a first end of the storage module is connected to the internal node, and a second end of the storage module is connected to a fixed voltage signal, and the storage module is used to store the potential of the internal node.

2. The light-emitting control circuit according to claim 1, characterized in that, The storage module includes a first capacitor; a first end of the first capacitor is connected to the internal node, and a second end of the first capacitor is connected to the fixed voltage signal. Preferably, the first power signal or the second power signal is multiplexed into the fixed voltage signal.

3. The light-emitting control circuit according to claim 2, characterized in that, The transmission control module includes: The first transmission unit is connected to the second control terminal and is used to control whether to transmit the second clock signal to the output terminal of the first transmission unit according to the potential of the second control terminal. The second transmission unit is connected to the output terminal of the first transmission unit and the third control terminal respectively, and is used to control whether to transmit the potential of the output terminal of the first transmission unit to the third control terminal according to the second clock signal. The output module includes: The third transmission unit is connected to the first control terminal and the third control terminal respectively, and is used to control whether to transmit the second power signal to the third control terminal according to the potential of the first control terminal. The first output unit is connected to the first control terminal and the light-emitting control output terminal of the light-emitting control circuit, respectively, and is used to control whether to transmit the first power signal to the light-emitting control output terminal as the light-emitting control signal according to the potential of the first control terminal and the second clock signal. The second output unit is connected to the third control terminal and the light emission control output terminal respectively, and is used to control whether to transmit the second power signal to the light emission control output terminal as the light emission control signal according to the potential of the third control terminal. Preferably, the first transmission unit includes: a first transistor and a second capacitor; the gate of the first transistor and the first terminal of the second capacitor are both connected to the second control terminal, the first electrode of the first transistor is connected to the second clock signal, and the second electrode of the first transistor and the second terminal of the second capacitor are both connected to the output terminal of the first transmission unit; The second transmission unit includes: a second transistor; the gate of the second transistor is connected to the second clock signal, the first terminal of the second transistor is connected to the output terminal of the first transmission unit, and the second terminal of the second transistor is connected to the third control terminal; The third transmission unit includes: a third transistor; the gate of the third transistor is connected to the first control terminal, the first terminal of the third transistor is connected to the second power supply signal, and the second terminal of the third transistor is connected to the third control terminal; The first output unit includes: a fourth transistor and a third capacitor; the gate of the fourth transistor and the first terminal of the third capacitor are both connected to the first control terminal, the second terminal of the third capacitor is connected to the second clock signal, the first terminal of the fourth transistor is connected to the first power supply signal, and the second terminal of the fourth transistor is connected to the light emission control output terminal; The second output unit includes a fifth transistor and a fourth capacitor; the gate of the fifth transistor and the first terminal of the fourth capacitor are both connected to the third control terminal, the second terminal of the fourth capacitor and the first terminal of the fifth transistor are both connected to the second power supply signal, and the second terminal of the fifth transistor is connected to the light emission control output terminal.

4. The light-emitting control circuit according to claim 3, characterized in that, The capacitance of the first capacitor is greater than the minimum value among the capacitances of the second capacitor, the third capacitor, and the fourth capacitor.

5. The light-emitting control circuit according to claim 3 or 4, characterized in that, The capacitance of the first capacitor is less than the maximum value among the capacitances of the second capacitor, the third capacitor, and the fourth capacitor.

6. The light-emitting control circuit according to claim 1, characterized in that, The node potential control module includes: The fourth transmission unit is connected to the second control terminal and the internal node respectively, and is used to transmit the second power signal to the internal node in response to the potential of the second control terminal; The fifth transmission unit is connected to the internal node and the first control terminal respectively, and is used to transmit the potential of the internal node to the first control terminal in response to the second clock signal; Preferably, the fourth transmission unit includes: a sixth transistor; the gate of the sixth transistor is connected to the second control terminal, the first terminal of the sixth transistor is connected to the second power supply signal, and the second terminal of the sixth transistor is connected to the internal node; The fifth transmission unit includes a seventh transistor; the gate of the seventh transistor is connected to the second clock signal, the first terminal of the seventh transistor is connected to the internal node, and the second terminal of the seventh transistor is connected to the first control terminal.

7. The light-emitting control circuit according to claim 6, characterized in that, The seventh transistor is a dual-gate transistor, which includes a first sub-transistor and a second sub-transistor connected in series between the internal node and the first control terminal. The gates of the first sub-transistor and the second sub-transistor are both connected to the second clock signal.

8. The light-emitting control circuit according to claim 1, characterized in that, The input control module includes: An input unit, connected to the first control terminal, is used to control whether the input signal is transmitted to the first control terminal according to the first clock signal; The sixth transmission unit, connected to the second control terminal, is used to control whether the first power signal is transmitted to the second control terminal according to the first clock signal; The seventh transmission unit is connected to the first control terminal and the second control terminal respectively, and is used to control whether the first clock signal is transmitted to the second control terminal according to the potential of the first control terminal; Preferably, the input unit includes: an eighth transistor; the gate of the eighth transistor is connected to the first clock signal, the first terminal of the eighth transistor is connected to the input signal, and the second terminal of the eighth transistor is connected to the first control terminal; The sixth transmission unit includes: a ninth transistor; the gate of the ninth transistor is connected to the first clock signal, the first terminal of the ninth transistor is connected to the first power supply signal, and the second terminal of the ninth transistor is connected to the second control terminal; The seventh transmission unit includes a tenth transistor; the gate of the tenth transistor is connected to the first control terminal, the first terminal of the tenth transistor is connected to the first clock signal, and the second terminal of the tenth transistor is connected to the second control terminal.

9. A display panel, characterized in that, include: The light-emitting control circuit according to any one of claims 1-8.

10. A display device, characterized in that, include: The display panel as claimed in claim 9.

Images