Pixel driving circuit, pixel driving method, display panel and display terminal
Patent Information
- Application Number
- CN202510551511.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]现有技术中，通过调整低频刷新模式下的电源电压，即调整ELVDD电压以及ELVSS电压来降低显示面板在低频刷新模式下的功耗，通过上述方法，虽然显示面板在低频刷新模式下的功耗能够降低，但却使得显示面板在低频刷新模式下的亮度与高频刷新模式下的亮度不同，从而影响用户的观看体验
[0030]根据本申请实施例提供的方案，像素驱动电路中，初始化晶体管包括第一至第三初始化晶体管，并在高频扫描模式下将利用第二参考电压对第一节点进行初始化，而在低频刷新模式下的写入帧则利用小于第二参考电压的第一参考电压对第一节点初始化，即低频刷新模式下驱动晶体管栅极电压小于高频刷新模式下驱动晶体管的栅极电压，而驱动晶体管栅极电压降低容易引起对充电电容充入过量电荷从而导致显示两端变大而引起屏闪问题，因此需要降低数据电压以避免对对充电电容过量充电，而为了保证发光阶段的驱动电流不变则需要降低第一电源电压，也就是在保证显示亮度不变(驱动电流不变)的同时降低了功耗(第一电源电压降低)。
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Figure CN123016904A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit, a pixel driving method, a display panel, and a display terminal. Background Technology
[0002] Low Temperature Polycrystalline Oxide (LTPO) display technology combines Low Temperature Polycrystalline Silicon (LTPS) technology with Indium Gallium Zinc Oxide (IGZO) technology, and is mainly used in OLED display panels. LTPO is a refresh rate adjustment technology that can adapt to the refresh rate of the display panel. By reducing the refresh rate, the power consumption of the display panel can be reduced, thus offering the advantage of energy saving.
[0003] Specifically, refresh rate adjustment usually refers to the ability of the display to use high-frequency refresh mode and low-frequency refresh mode. In high-frequency refresh mode, the refresh rate is typically above 100Hz, such as 120Hz or 144Hz, and some products can even reach 240Hz or higher. In low-frequency refresh mode, the refresh rate is usually below 60Hz, and for displaying static images, the refresh rate can even be as low as 1Hz.
[0004] In the prior art, the power consumption of the display panel in low-frequency refresh mode is reduced by adjusting the power supply voltage, namely adjusting the ELVDD voltage and ELVSS voltage. Although the power consumption of the display panel in low-frequency refresh mode can be reduced by the above method, the brightness of the display panel in low-frequency refresh mode is different from that in high-frequency refresh mode, thus affecting the user's viewing experience. Summary of the Invention
[0005] In view of this, embodiments of this application provide a pixel driving circuit, a pixel driving method, a display panel, and a display terminal to at least partially solve the above-mentioned problems.
[0006] According to a first aspect of the embodiments of this application, a pixel driving circuit is provided, which is used to drive a light-emitting unit in a high-frequency refresh mode and a low-frequency refresh mode. The pixel circuit includes a write transistor, a storage capacitor and a driving transistor.
[0007] The gate of the write transistor is electrically connected to the second scan signal terminal, the first terminal of the write transistor is electrically connected to the data signal terminal, the second terminal of the write transistor is coupled to the first node, and the write transistor is configured to write the data voltage input from the data signal terminal to the first terminal of the write transistor in response to the second scan signal input from the second scan signal terminal.
[0008] The first electrode of the storage capacitor is electrically connected to the first power supply voltage terminal, the second electrode of the storage capacitor is electrically connected to the first node, and the storage capacitor is configured to store the voltage of the first node.
[0009] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is coupled to the first power supply terminal, the second electrode of the driving transistor is coupled to the first electrode of the light-emitting unit, and the driving transistor is configured to generate a driving current according to the voltage of the first node and the first power supply voltage input to the first power supply terminal during the light-emitting phase.
[0010] The second electrode of the light-emitting unit is electrically connected to the second power supply voltage terminal, and the light-emitting unit emits light under the drive of the driving current;
[0011] The pixel driving circuit further includes a first initialization transistor, a second initialization transistor, and a third initialization transistor. The gate of the first initialization transistor is electrically connected to a first scan signal terminal. The gate of the second initialization transistor is electrically connected to a fourth scan signal terminal. The gate of the third initialization transistor is electrically connected to a fifth scan signal terminal. The first electrode of the first initialization transistor is electrically connected to a first reference voltage terminal. The second electrode of the first initialization transistor is electrically connected to the first node. The first electrodes of both the second and third initialization transistors are electrically connected to a second reference voltage terminal. The second electrode of the second initialization transistor is electrically connected to the first electrode of the light-emitting unit. The second electrode of the third initialization transistor is electrically connected to the first node.
[0012] The first initialization transistor is configured to write the first reference voltage input to the first reference voltage terminal into the first node in response to the first scan signal input to the first scan signal terminal in low-frequency refresh mode.
[0013] The second initialization transistor is configured to write the second reference voltage into the first electrode of the light-emitting unit in response to the fourth scan signal;
[0014] The third initialization transistor is configured to write the second reference voltage into the first node in response to the fifth scan pole signal input to the fifth scan signal segment;
[0015] In the low-frequency refresh mode where the first reference voltage is lower than the second reference voltage, the first power supply voltage input to the first power supply voltage terminal in the low-frequency refresh mode is less than the first power supply voltage input to the first power supply voltage terminal in the high-frequency refresh mode.
[0016] Optionally, the pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the light-emitting control signal terminal. The first electrode of the first light-emitting control transistor is electrically connected to the first power supply voltage terminal, and the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor so that the first electrode of the driving transistor is coupled to the first power supply voltage terminal. The first electrode of the second light-emitting control transistor is electrically connected to the second node, and the second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting unit.
[0017] Both the first light-emitting control transistor and the second light-emitting control transistor are configured to be turned on in response to a light-emitting control signal input at the light-emitting control signal terminal, such that the driving transistor and the light-emitting unit form a loop between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor is input to the light-emitting unit.
[0018] Optionally, the pixel driving circuit further includes a switching transistor, the gate of which is electrically connected to the third scan signal terminal, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second node.
[0019] The switching transistor is configured to turn on in response to the third scan signal, causing the potential of the first node to be written into the second node.
[0020] Optionally, the opening transistor, the first initialization transistor, and the third initialization transistor are N-type transistors, and the driving transistor, the writing transistor, the second initialization transistor, the first light-emitting control transistor, and the second light-emitting control transistor are P-type transistors.
[0021] Optionally, the switching transistor and the first initialization transistor are IGZO transistors, and the driving transistor, the writing transistor, the first light-emitting control transistor, the light-emitting control transistor, the second initialization transistor, and the third initialization transistor are low-temperature polycrystalline silicon transistors.
[0022] According to a second aspect of the embodiments of this application, a display panel is provided, the display panel including the pixel driving circuit described above.
[0023] According to a third aspect of the embodiments of this application, a display terminal is provided, the display terminal including a terminal device body and a display panel as described above disposed on the terminal device body.
[0024] According to a fourth aspect of the embodiments of this application, a pixel driving method based on the above-described pixel driving circuit is provided, wherein each low-frequency display frame in the low-frequency refresh mode of the pixel driving method includes a write frame and at least one hold frame, and the pixel driving method includes:
[0025] In high-frequency refresh mode, the first power supply voltage terminal receives the first power supply voltage at the first level. During the initialization phase, the fifth scan signal terminal receives the fifth scan signal to turn on the third initialization transistor so that the second reference voltage input to the second reference voltage terminal is written into the first node.
[0026] In low-frequency refresh mode, the first power supply voltage terminal receives the first power supply voltage at the second level, and during the initialization phase, the first scan signal terminal receives the first scan signal to turn on the first initialization transistor so that the first reference voltage input to the first reference voltage terminal is written into the first node.
[0027] Wherein, the first reference voltage is less than the second reference voltage, and the first level is greater than the second level.
[0028] Optionally, in the write frame of the low-frequency refresh mode, during the data writing stage, the second scan signal received by the second scan signal terminal turns on the write transistor so that the data voltage input by the data signal terminal is written to the first node; during the light emission stage, the light emission control signal terminal receives the light emission control signal so that the first light emission control transistor and the second light emission control transistor are turned on, so that the driving transistor and the light emission unit form a loop between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor is input to the light emission unit.
[0029] Optionally, in the hold frame of the low-frequency refresh mode, during the data writing phase, the second scan signal received by the second scan signal terminal causes the write transistor to turn off and not write data voltage to the first node; during the light emission phase, the light emission control signal terminal receives the light emission control signal to turn on the first light emission control transistor and the second light emission control transistor, so that the driving transistor and the light emission unit form a loop between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor is input to the light emission unit.
[0030] According to the solution provided in the embodiments of this application, in the pixel driving circuit, the initialization transistor includes first to third initialization transistors. In the high-frequency scanning mode, the first node is initialized using a second reference voltage. In the low-frequency refresh mode, the first node is initialized using a first reference voltage that is lower than the second reference voltage. That is, in the low-frequency refresh mode, the gate voltage of the driving transistor is lower than the gate voltage of the driving transistor in the high-frequency refresh mode. The reduction of the gate voltage of the driving transistor can easily cause excessive charge to be charged into the charging capacitor, which will cause the display to become larger and cause screen flicker. Therefore, it is necessary to reduce the data voltage to avoid overcharging the charging capacitor. In order to ensure that the driving current in the light-emitting stage remains unchanged, it is necessary to reduce the first power supply voltage. That is, while ensuring that the display brightness remains unchanged (driving current remains unchanged), the power consumption is reduced (first power supply voltage is reduced). Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0032] Figure 1 This is a schematic diagram of an exemplary structure of a pixel driving circuit in the prior art;
[0033] Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;
[0034] Figure 3 for Figure 3 The timing diagram of the pixel driving circuit is shown.
[0035] Figure 4 This is a schematic diagram of the frame structure of a display panel according to an embodiment of this application;
[0036] Figure 5 This is a schematic diagram of the frame structure of a display panel according to an embodiment of this application. Detailed Implementation
[0037] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.
[0038] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in the embodiments of this application refers to and includes any or all possible combinations of one or more associated listed items.
[0039] Furthermore, when an element or layer is referred to as being "on" another element or layer, "connected to," or "bonded to" another element or layer, the element or layer may be directly on the other element or layer, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers.
[0040] The terms First, Second, etc., are used to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or part from another element, component, region, layer, and / or part.
[0041] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0042] LTPO display technology is mainly used in OLED display panels. LTPO is a refresh rate adjustment technology that can adapt to the refresh rate of the display panel. By reducing the refresh rate, the power consumption of the display panel can be reduced, thus having the advantage of saving power.
[0043] In existing technologies, the power consumption of the display panel in low-frequency refresh mode is reduced by adjusting the power supply voltage, specifically the ELVDD and ELVSS voltages. While this method reduces power consumption in low-frequency refresh mode, it also causes a difference in brightness between the low-frequency and high-frequency refresh modes, thus affecting the user's viewing experience. The following explains why adjusting the power supply voltage in low-frequency refresh mode affects the brightness of the display panel.
[0044] Figure 1 A pixel driving circuit, namely the 7T1C circuit, is shown, such as Figure 1 As shown, the pixel driving circuit is used to drive the light-emitting unit OLED to emit light. The pixel driving circuit includes a driving transistor T1, a writing transistor T2, a switching transistor T3, a first initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, and a storage capacitor Cst.
[0045] Specifically, such as Figure 1 In the pixel driving circuit shown, the connection relationships of each transistor, storage capacitor Cst, and light-emitting unit OLED are as follows:
[0046] The first electrode of the storage capacitor Cst is electrically connected to the first power supply terminal ELVDD, and the second electrode is electrically connected to the first node N1.
[0047] The first electrode of the OLED light-emitting unit is electrically connected to the second electrode of the second light-emitting control transistor T6, and the second electrode is electrically connected to the second power supply voltage terminal ELVSS.
[0048] The gate of the driving transistor T1 is electrically connected to the first node N1, the first terminal is electrically connected to the second terminal of the writing transistor T2 and the second terminal of the first light-emitting control transistor T5, and the second terminal is electrically connected to the second node N2.
[0049] The gate of the write transistor T2 is electrically connected to the second scan signal terminal S2, and the first terminal is electrically connected to the data signal terminal Vdata.
[0050] The gate of the switching transistor T3 is electrically connected to the third scan signal terminal S3, the first terminal is electrically connected to the first node N1, and the second terminal is electrically connected to the second node N2.
[0051] The gate of the first initialization transistor T4 is electrically connected to the first scan signal terminal S1, the first terminal is electrically connected to the first reset signal terminal Vref1, and the second terminal is electrically connected to the first node N1.
[0052] The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal EM, and the first terminal is electrically connected to the first power supply voltage terminal ELVDD.
[0053] The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal terminal EM, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the first electrode of the light-emitting unit OLED.
[0054] The gate of the second initialization transistor T7 is electrically connected to the fourth scan signal terminal S4, the first terminal is electrically connected to the second reset signal terminal Vref2, and the second terminal is electrically connected to the first electrode of the light-emitting unit OLED.
[0055] like Figure 1 The pixel driving circuit shown has three stages for its light emission process: initialization stage, data writing stage, and light emission stage.
[0056] During the initialization phase, the first scan signal terminal S1 receives the first scan signal, which turns on the first initialization transistor T4, thereby writing the first reset voltage Vref1 input to the first reset signal terminal into the first node N1, thus initializing the voltage on the storage capacitor Cst, clearing the residual voltage of the storage capacitor Cst of the previous frame display, and also initializing the gate voltage of the driving transistor T1.
[0057] During the data writing phase, the second scan signal terminal S2 receives the second scan signal, causing the writing transistor T2 to turn on, so that the data signal Vdata is written to the first node N1, that is, written to the gate of the driving transistor T1 and charging the storage capacitor Cst, causing the gate potential of the driving transistor T1 to rise, so that the gate-source voltage |Vgs| of the driving transistor T1 becomes smaller and smaller, and the current becomes smaller and smaller. When Vgs = Vth, the driving transistor T1 turns off, and the charging ends. At this time, the voltage of the gate of the driving transistor T1 is Vdata - |Vth|.
[0058] During the light-emitting stage, the light-emitting control signal terminal EM receives the light-emitting control signal, causing both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to conduct. This allows the first power supply ELVDD to be written into the driving transistor T1. Based on the source-drain voltage of the driving transistor T1, the source-drain current of the driving transistor T1, i.e., the driving current Ids, is calculated as W / 2LμC. ox (VDD-Vdata) 2 That is, the OLED light-emitting unit has a driving current of Ids = W / 2LμC ox (VDD-Vdata.2) 2 Under the condition of emission, W is the channel width of driving transistor T1, L is the channel length of driving transistor T1, μ represents the carrier mobility of the channel of driving transistor T1, and C ox It refers to the capacitance per unit area, and VDD refers to the first power supply voltage provided by the first power supply voltage terminal ELVDD.
[0059] Specifically, such as Figure 1As shown, the power consumption reduction of LTPO display panels mainly targets the low-frequency scanning mode. In the low-frequency scanning mode, each low-frequency display frame includes a write frame and at least one hold frame. Only the write frame writes the data signal Vdata, while the hold frame does not. In existing technologies, to reduce power consumption, the voltage of the first power supply voltage terminal ELVDD is usually reduced at a certain moment within the low-frequency display frame cycle. According to the calculation formula of the drive current Ids mentioned above, reducing the voltage of the first power supply voltage terminal ELVDD can reduce power consumption, but it will also affect the display brightness, causing screen flicker. Similarly, adjusting the second power supply voltage ELVSS will reduce power consumption but will also affect the display brightness.
[0060] Based on the above-mentioned technical problems, this application proposes a pixel driving circuit, a pixel driving method, a display panel, and a display terminal, which reduces the power consumption of the LTPO display panel without affecting the display brightness.
[0061] This embodiment provides a pixel driving circuit, which is used to drive the light-emitting unit in both high-frequency refresh mode and low-frequency refresh mode, such as... Figure 2 As shown, the pixel driving circuit provided in this embodiment includes a write transistor T2, a storage capacitor Cst, a driving transistor T1, a first initialization transistor T4, a second initialization transistor T7, and a third initialization transistor.
[0062] The gate of the write transistor T2 is electrically connected to the second scan signal terminal, the first terminal of the write transistor T2 is electrically connected to the data signal terminal, the second terminal of the write transistor T2 is coupled to the first node N1, and the write transistor T2 is configured to write the data voltage Vdata input from the data signal terminal to the first terminal of the write transistor T2 in response to the second scan signal input from the second scan signal terminal.
[0063] The first electrode of the storage capacitor Cst is electrically connected to the first power supply voltage terminal, the second electrode of the storage capacitor Cst is electrically connected to the first node N1, and the storage capacitor Cst is configured to store the voltage of the first node N1.
[0064] The gate of the driving transistor T1 is electrically connected to the first node N1, the first electrode of the driving transistor T1 is coupled to the first power supply terminal, the second electrode of the driving transistor T1 is coupled to the first electrode of the light-emitting unit, and the driving transistor T1 is configured to generate a driving current during the light-emitting phase based on the voltage of the first node N1 and the first power supply voltage ELVDD input to the first power supply terminal.
[0065] The second electrode of the light-emitting unit is electrically connected to the second power supply voltage terminal, and the light-emitting unit emits light under the drive of the driving current.
[0066] It should be noted that the voltage of the gate of the driving transistor T1, the voltage of the second electrode of the storage capacitor Cst, and the voltage of the first node N1 are consistent. For example, writing a certain voltage to the first node N1 means that the voltage is also written to the voltage of the gate of the driving transistor T1 and the voltage of the second electrode of the storage capacitor Cst at the same time. This will not be repeated in the following description.
[0067] The gate of the first initialization transistor T4 is electrically connected to the first scan signal terminal. The gate of the second initialization transistor T7 is electrically connected to the fourth scan signal terminal. The gate of the third initialization transistor T8 is electrically connected to the fifth scan signal terminal. The first electrode of the first initialization transistor T4 is electrically connected to the first reference voltage Vref1 terminal. The second electrode of the first initialization transistor T4 is electrically connected to the first node N1. The first electrodes of the second initialization transistor T7 and the third initialization transistor T8 are both electrically connected to the second reference voltage Vref2 terminal. The second electrode of the second initialization transistor T7 is electrically connected to the first electrode of the light-emitting unit. The second electrode of the third initialization transistor T8 is electrically connected to the first node N1.
[0068] The first initialization transistor T4 is configured to write the first reference voltage Vref1, input to the first reference voltage Vref1 terminal, to the first node N1 in response to the first scan signal input at the first scan signal terminal during a write frame in low-frequency refresh mode. That is, during a write frame in low-frequency refresh mode, the first initialization transistor T4 initializes the potential of the first node N1 using the first reference voltage Vref1.
[0069] The second initialization transistor T7 is configured to write the second reference voltage Vref2 into the first electrode of the light-emitting unit in response to the fourth scan signal. That is, the second initialization transistor T7 initializes the potential of the first electrode of the light-emitting unit using the second reference voltage Vref2.
[0070] The third initialization transistor T8 is configured to write the second reference voltage Vref2 into the first node N1 in response to the fifth scan pole signal input to the fifth scan signal segment. That is, in the low-frequency refresh mode, the third initialization transistor T8 initializes the potential of the first node N1 using the second reference voltage Vref2.
[0071] Wherein, the first reference voltage Vref1 is lower than the second reference voltage Vref2, and the first power supply voltage ELVDD input to the first power supply voltage terminal in the low frequency refresh mode is less than the first power supply voltage ELVDD input to the first power supply voltage terminal in the high frequency refresh mode.
[0072] In the pixel driving circuit provided in this embodiment, the initialization transistors include first to third initialization transistors T8. In high-frequency scanning mode, the first node N1 is initialized using the second reference voltage Vref2. In low-frequency refresh mode, the write frame is initialized using the first reference voltage Vref1, which is lower than the second reference voltage Vref2. That is, the gate voltage of the driving transistor T1 in low-frequency refresh mode is lower than the gate voltage of the driving transistor T1 in high-frequency refresh mode. The reduction of the gate voltage of the driving transistor T1 can easily cause excessive charge to be charged into the charging capacitor, resulting in the display terminals becoming larger and causing screen flicker. Therefore, it is necessary to reduce the data voltage Vdata to avoid overcharging the charging capacitor. In order to ensure that the driving current in the light-emitting stage remains unchanged, it is necessary to reduce the first power supply voltage ELVDD. That is, while ensuring that the display brightness remains unchanged (driving current remains unchanged), the power consumption is reduced (first power supply voltage ELVDD is reduced).
[0073] like Figure 2 As shown, the pixel driving circuit provided in this embodiment further includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The gates of both the first and second light-emitting control transistors are electrically connected to a light-emitting control signal terminal. The first electrode of the first light-emitting control transistor T5 is electrically connected to a first power supply voltage terminal, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of a driving transistor T1, thus coupling the first electrode of the driving transistor T1 to the first power supply voltage terminal. The first electrode of the second light-emitting control transistor T6 is electrically connected to a second node N2, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting unit. Both the first and second light-emitting control transistors T5 and T6 are configured to conduct in response to a light-emitting control signal input at the light-emitting control signal terminal, thereby forming a loop between the driving transistor T1 and the light-emitting unit between the first and second power supply voltage terminals, so that the driving current of the driving transistor T1 is input to the light-emitting unit.
[0074] It should be noted that the first electrode and the second electrode of each transistor in this application refer to the source and the drain, respectively. Depending on whether the transistor is N-type or P-type, the first electrode corresponds to the source or the drain, respectively.
[0075] like Figure 2 As shown, the pixel driving circuit provided in this embodiment includes a switching transistor T3. The gate of the switching transistor T3 is electrically connected to the third scan signal terminal, the first terminal of the switching transistor T3 is electrically connected to the first node N1, and the second terminal of the switching transistor T3 is electrically connected to the second node N2. The switching transistor T3 is configured to, in response to the third scan signal being turned on, cause the potential of the first node N1 to be written into the second node N2.
[0076] like Figure 2As shown, in the pixel driving circuit provided in this embodiment, the opening transistor, the first initialization transistor T4 and the third initialization transistor T8 are N-type transistors, and the driving transistor T1, the writing transistor T2, the second initialization transistor T7, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type transistors.
[0077] like Figure 2 As shown, in the pixel driving circuit provided in this embodiment, the switching transistor T3 and the first initialization transistor T4 are IGZO transistors, and the driving transistor T1, the writing transistor T2, the first light-emitting control transistor T5, the light-emitting control transistor, the second initialization transistor T7, and the third initialization transistor T8 are low-temperature polysilicon transistors.
[0078] Based on the same inventive concept, this application also provides a pixel driving method, which is based on the pixel driving circuit in the above embodiments. The pixel driving method provided in this embodiment will be described below in conjunction with the pixel driving circuit in the above embodiments.
[0079] The pixel driving method provided in this embodiment includes a low-frequency refresh mode where each low-frequency display frame comprises a write frame and at least one hold frame. The pixel driving method includes:
[0080] In high-frequency refresh mode, the first power supply voltage terminal receives the first power supply voltage ELVDD at the first level. During the initialization phase, the fifth scan signal terminal receives the fifth scan signal, which turns on the third initialization transistor T8 so that the second reference voltage Vref2 input at the second reference voltage Vref2 terminal is written into the first node N1.
[0081] In low-frequency refresh mode, the first power supply voltage terminal receives the first power supply voltage ELVDD at the second level, and during the initialization phase, the first scan signal terminal receives the first scan signal to turn on the first initialization transistor T4 so that the first reference voltage Vref1 input at the first reference voltage Vref1 terminal is written into the first node N1.
[0082] Among them, the first reference voltage Vref1 is less than the second reference voltage Vref2, and the first level is greater than the second level.
[0083] The pixel driving method provided in this embodiment initializes the first node N1 using the second reference voltage Vref2 in high-frequency scanning mode, while the write frame in low-frequency refresh mode initializes the first node N1 using the first reference voltage Vref1, which is lower than the second reference voltage Vref2. That is, the gate voltage of the driving transistor T1 in low-frequency refresh mode is lower than the gate voltage of the driving transistor T1 in high-frequency refresh mode. The reduction of the gate voltage of the driving transistor T1 can easily cause excessive charge to be charged into the charging capacitor, resulting in the display terminals becoming larger and causing screen flicker. Therefore, it is necessary to reduce the data voltage Vdata to avoid overcharging the charging capacitor. In order to ensure that the driving current in the light-emitting stage remains unchanged, it is necessary to reduce the first power supply voltage ELVDD. That is, while ensuring that the display brightness remains unchanged (driving current remains unchanged), the power consumption is reduced (first power supply voltage ELVDD is reduced).
[0084] Specifically, in the pixel driving method provided in this embodiment, during the write frame in low-frequency refresh mode, in the data writing stage, the second scan signal received by the second scan signal terminal causes the write transistor T2 to be turned on, so that the data voltage Vdata input by the data signal terminal is written to the first node N1; in the light emission stage, the light emission control signal terminal receives the light emission control signal, causing the first light emission control transistor T5 and the second light emission control transistor T6 to be turned on, so that the driving transistor T1 and the light emission unit form a loop between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor T1 is input to the light emission unit.
[0085] Specifically, in the pixel driving method provided in this embodiment, during the holding frame in low-frequency refresh mode, in the data writing stage, the second scan signal received by the second scan signal terminal causes the writing transistor T2 to turn off and not write the data voltage Vdata to the first node N1; in the light emission stage, the light emission control signal terminal receives the light emission control signal to turn on the first light emission control transistor T5 and the second light emission control transistor T6, so that the driving transistor T1 and the light emission unit form a loop between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor T1 is input to the light emission unit.
[0086] Figure 3 A timing diagram of the pixel driving circuit in the above embodiment is shown. The following is in conjunction with... Figure 2 and Figure 3 , based on Figure 2 The pixel driving method of the pixel driving circuit shown will be explained.
[0087] In low-frequency refresh mode, each low-frequency display frame includes one write frame and at least one hold frame. For example, if the refresh rate of the display panel in high-frequency refresh mode is 120Hz, and the refresh rate in low-frequency scan mode is 20Hz, then each low-frequency display frame in low-frequency refresh mode includes one write frame and five hold frames. Of course, the refresh rate in low-frequency refresh mode is not limited to 20Hz; it can also be 10Hz, even as low as 1Hz, or 40Hz or 60Hz, etc.
[0088] Specifically, the write frame includes an initialization phase, a data writing phase, and a light emission phase. It should be noted that, theoretically, there can be no time interval between the initialization phase and the data writing phase, or between the data writing phase and the light emission phase. However, in actual display products, although the time required for the potential changes of the gate and source / drain terminals of the transistors in the pixel circuit, as well as the two electrodes of the storage capacitor Cst, is very short, the potential changes still require time. Therefore, to prevent the potential in the pixel driving circuit from being substandard due to the lack of time intervals, time intervals are set between the initialization phase and the data writing phase, and between the data writing phase and the light emission phase.
[0089] During the initialization phase M1 of the write frame, the light emission control signal EM is at a high level, causing the first light emission control transistor T5 and the second light emission control transistor T6 to turn off; while the first scan signal is at a high level, causing the first initialization transistor T4 to turn on, thereby writing the first reference voltage Vref1 into the first node N1. At this time, the gate voltage of the driving transistor T1 is the first reference voltage Vref1.
[0090] During the data writing phase M2 of the write frame, the light emission control signal EM is still at a high level, causing the first light emission control transistor T5 and the second light emission control transistor T6 to be disconnected; the second scan signal is at a low level. Since the write transistor T2 is an N-type transistor, when the second scan signal is at a low level, the write transistor T2 is turned on, thereby writing the data voltage Vdata to the first node N1, that is, writing the data voltage Vdata to the gate of the drive transistor T1 and charging the storage capacitor Cst. During this process, the gate potential of the drive transistor T1 increases, causing the gate-source voltage |Vgs| of the drive transistor T1 to become smaller and smaller. When the gate-source voltage Vgs of the drive transistor T1 = Vth, the drive transistor T1 is turned off, and the charging ends. At this time, the voltage of the gate of the drive transistor T1 is Vdata-|Vth|, where Vth is the threshold voltage of the drive transistor T1. During this data writing phase, the third scan signal is at a high level, which turns on the switching transistor T3, thereby writing the potential of the first stage into the second electrode of the driving crystal; the fourth scan signal is at a low level. Since the second initialization transistor T7 is an N-type transistor, when the fourth scan signal is at a low level, the second initialization transistor T7 turns on, thereby writing the second reference voltage Vref2 into the first electrode of the light-emitting unit.
[0091] During the light-emitting phase M3 of the frame writing process, the light-emitting control signal is at a low level. Since both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are N-type transistors, both transistors are turned on, causing the first power supply ELVDD to be written to the driving transistor T1. Based on the source-drain voltage of the driving transistor T1, the source-drain current of the driving transistor T1, i.e., the driving current Ids, is calculated as W / 2LμC. ox (VDD-Vdata) 2 That is, the OLED light-emitting unit has a driving current of Ids = W / 2LμC ox (VDD-Vdata) 2 It emits light under certain conditions.
[0092] The value of the first reference voltage Vref1 should take into account the charging requirements of the charging capacitor and the adjustment range of the data voltage Vdata. The specific value of the first reference voltage Vref1 should not be too small to avoid the first node N1 potential being too low, resulting in insufficient charging time for the storage capacitor Cst during the data writing stage, which would cause the gate potential of the driving transistor T1 to be lower than the preset voltage. Specifically, since the potential of the first node N1 is also written to the second terminal of the driving transistor T1 during the data writing stage, the voltage of the second terminal of the driving transistor T1 is also lower than the preset value, making the Vds difference larger, thereby increasing the driving current Ids and thus increasing the display brightness. At the same time, the difference between the first reference voltage Vref1 and the data voltage Vdata should not be less than the threshold voltage Vth of the driving transistor T1; otherwise, the driving transistor T1 will not be fully turned on, which will reduce the display brightness.
[0093] Specifically, the holding frame also includes an initialization phase, a data writing phase, and a light emission phase.
[0094] During the initialization phase M1' of the holding frame, the light emission control signal EM is at a high level, causing the first light emission control transistor T5 and the second light emission control transistor T6 to turn off; while the fifth scan signal is at a low level, causing the third initialization transistor T8 to turn off, and the potential of the first node N1 remains at the voltage Vdata-|Vth| of the aforementioned written frame.
[0095] During the data writing phase M2' of the holding frame, the light emission control signal EM remains high, causing the first light emission control transistor T5 and the second light emission control transistor T6 to turn off. The second scan signal is high, and since the write transistor T2 is an N-type transistor, it turns off when the second scan signal is high, meaning no data voltage Vdata is written to the first node N1. During this data writing phase, the third scan signal is low, causing the switching transistor T3 to turn off. The fourth scan signal is low, and since the second initialization transistor T7 is an N-type transistor, it turns on when the fourth scan signal is low, thereby writing the second reference voltage Vref2 to the first electrode of the light-emitting unit.
[0096] During the light-emitting phase M3' of the holding frame, the light-emitting control signal is at a low level. Since both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are N-type transistors, both transistors are turned on, causing the first power supply ELVDD to be written to the driving transistor T1. Based on the source-drain voltage of the driving transistor T1, the source-drain current of the driving transistor T1, i.e., the driving current Ids, is W / 2LμC. ox (VDD-Vdata) 2That is, the OLED light-emitting unit has a driving current of Ids = W / 2LμC ox (VDD-Vdata) 2 It emits light under certain conditions.
[0097] Since the voltages of the gate, source, and drain of the holding frame driving transistor T1 are the same as those of the written frame, the display brightness remains unchanged. Furthermore, in low-frequency refresh mode, the first power supply voltage ELVDD input to the first power supply voltage terminal is lower than that in high-frequency refresh mode, thus effectively reducing power consumption in low-frequency refresh mode.
[0098] Based on the same inventive concept, embodiments of this application also provide a display panel, such as... Figure 4 As shown, the display panel provided in this embodiment includes the pixel driving circuit of any of the above embodiments, and has the beneficial effects of the pixel driving circuit in the above embodiments, which will not be repeated here.
[0099] Based on the same inventive concept, embodiments of this application also provide a display terminal, such as... Figure 5 As shown, the display terminal provided in this embodiment includes a terminal device body and a display panel disposed on the terminal device body as described in the above embodiment, and has the beneficial effects of the display panel in the above embodiment, which will not be repeated here.
[0100] An exemplary display terminal, such as Figure 5 As shown, it includes a terminal device body 200 and a display panel 100. The display panel 100 is disposed on the terminal device body 200 and electrically connected to the terminal device body 200. The display panel 100 is the display panel described in the foregoing embodiments, used to display static or dynamic images.
[0101] For example, the above-mentioned display terminal can be implemented in the form of various electronic devices such as mobile phones, tablet computers, handheld computers, and PADs.
[0102] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.
Claims
1. A pixel driving circuit, using The pixel circuit includes a write transistor, a storage capacitor, and a drive transistor for driving the light-emitting unit in both high-frequency refresh mode and low-frequency refresh mode. The gate of the write transistor is electrically connected to the second scan signal terminal, the first terminal of the write transistor is electrically connected to the data signal terminal, the second terminal of the write transistor is coupled to the first node, and the write transistor is configured to write the data voltage input from the data signal terminal to the first terminal of the write transistor in response to the second scan signal input from the second scan signal terminal. The first electrode of the storage capacitor is electrically connected to the first power supply voltage terminal, the second electrode of the storage capacitor is electrically connected to the first node, and the storage capacitor is configured to store the voltage of the first node. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is coupled to the first power supply terminal, the second electrode of the driving transistor is coupled to the first electrode of the light-emitting unit, and the driving transistor is configured to generate a driving current according to the voltage of the first node and the first power supply voltage input to the first power supply terminal during the light-emitting phase. The second electrode of the light-emitting unit is electrically connected to the second power supply voltage terminal, and the light-emitting unit emits light under the drive of the driving current; The pixel driving circuit is characterized in that it further includes a first initialization transistor, a second initialization transistor, and a third initialization transistor. The gate of the first initialization transistor is electrically connected to a first scan signal terminal, the gate of the second initialization transistor is electrically connected to a fourth scan signal terminal, and the gate of the third initialization transistor is electrically connected to a fifth scan signal terminal. The first electrode of the first initialization transistor is electrically connected to a first reference voltage terminal, and the second electrode of the first initialization transistor is electrically connected to the first node. The first electrodes of both the second and third initialization transistors are electrically connected to a second reference voltage terminal. The second electrode of the second initialization transistor is electrically connected to the first electrode of the light-emitting unit, and the second electrode of the third initialization transistor is electrically connected to the first node. The first initialization transistor is configured to write the first reference voltage input to the first reference voltage terminal into the first node in response to the first scan signal input to the first scan signal terminal in low-frequency refresh mode. The second initialization transistor is configured to write the second reference voltage into the first electrode of the light-emitting unit in response to the fourth scan signal; The third initialization transistor is configured to write the second reference voltage into the first node in response to the fifth scan pole signal input to the fifth scan signal segment; In the low-frequency refresh mode where the first reference voltage is lower than the second reference voltage, the first power supply voltage input to the first power supply voltage terminal in the low-frequency refresh mode is less than the first power supply voltage input to the first power supply voltage terminal in the high-frequency refresh mode.
2. The pixel driving circuit according to claim 1, characterized in that, It also includes a first light-emitting control transistor and a second light-emitting control transistor. The gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to the light-emitting control signal terminal. The first electrode of the first light-emitting control transistor is electrically connected to the first power supply voltage terminal, and the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor so that the first electrode of the driving transistor is coupled to the first power supply voltage terminal. The first electrode of the second light-emitting control transistor is electrically connected to the second node, and the second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting unit. Both the first light-emitting control transistor and the second light-emitting control transistor are configured to be turned on in response to a light-emitting control signal input at the light-emitting control signal terminal, such that the driving transistor and the light-emitting unit form a loop between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor is input to the light-emitting unit.
3. The pixel driving circuit according to claim 2, characterized in that, It also includes a switching transistor, the gate of which is electrically connected to the third scan signal terminal, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second node; The switching transistor is configured to turn on in response to the third scan signal, causing the potential of the first node to be written into the second node.
4. The pixel driving circuit according to claim 3, characterized in that, The opening transistor, the first initialization transistor, and the third initialization transistor are N-type transistors, while the driving transistor, the writing transistor, the second initialization transistor, the first light-emitting control transistor, and the second light-emitting control transistor are P-type transistors.
5. The pixel driving circuit according to claim 3, characterized in that, The switching transistor and the first initialization transistor are 1 GZO transistors, and the driving transistor, the writing transistor, the first light-emitting control transistor, the light-emitting control transistor, the second initialization transistor, and the third initialization transistor are low-temperature polycrystalline silicon transistors.
6. A display panel, characterized in that, Includes the pixel driving circuit according to any one of claims 1-5.
7. A display terminal, characterized in that, The display terminal includes a terminal device body and a display panel as described in claim 7 disposed on the terminal device body.
8. A pixel driving method based on the pixel driving circuit according to any one of claims 1-5, characterized in that, The pixel driving method includes a low-frequency refresh mode where each low-frequency display frame comprises a write frame and at least one hold frame. The pixel driving method includes: In high-frequency refresh mode, the first power supply voltage terminal receives the first power supply voltage at the first level. During the initialization phase, the fifth scan signal terminal receives the fifth scan signal to turn on the third initialization transistor so that the second reference voltage input to the second reference voltage terminal is written into the first node. In low-frequency refresh mode, the first power supply voltage terminal receives the first power supply voltage at the second level, and during the initialization phase, the first scan signal terminal receives the first scan signal to turn on the first initialization transistor so that the first reference voltage input to the first reference voltage terminal is written into the first node. Wherein, the first reference voltage is less than the second reference voltage, and the first level is greater than the second level.
9. The pixel driving method according to claim 8, characterized in that, In the write frame of low-frequency refresh mode, during the data writing stage, the second scan signal received by the second scan signal terminal turns on the write transistor so that the data voltage input by the data signal terminal is written to the first node. During the light-emitting stage, the light-emitting control signal terminal receives a light-emitting control signal, which turns on the first light-emitting control transistor and the second light-emitting control transistor, so that the driving transistor and the light-emitting unit form a circuit between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor is input to the light-emitting unit.
10. The pixel driving method according to claim 8, characterized in that, Frame retention in low refresh rate mode During the data writing phase, the second scan signal received by the second scan signal terminal causes the write transistor to turn off and prevents the first node from writing data voltage; During the light-emitting stage, the light-emitting control signal terminal receives the light-emitting control signal, causing the first light-emitting control transistor and the second light-emitting control transistor to turn on, so that the driving transistor and the light-emitting unit form a circuit between the first power supply voltage terminal and the second power supply voltage terminal, so that the driving current of the driving transistor is input to the light-emitting unit.