Pixel circuit, display panel, display device and display driving method

Abstract

The application relates to a pixel circuit, a display panel, a display device and a display driving method. The pixel circuit comprises a driving module, a data writing module and a parasitic capacitance control module. One end of the parasitic capacitance control module is used for receiving an anode voltage, and the other end is used for being connected or not connected with an anode of a light-emitting element under the control of a parasitic capacitance control signal; in the case that a pre-display gray scale is less than or equal to a set gray scale threshold value, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to be connected with the anode of the light-emitting element, so that the parasitic capacitance control module is connected in series with a parasitic capacitance in the light-emitting element. The application can make the display of the organic light-emitting diode have smaller display brightness difference and more uniform display color in the case of low gray scale display.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit, display panel, display device, and display driving method. Background Technology

[0002] Organic light-emitting diodes (OLEDs) have a sandwich structure, where organic light-emitting materials exist between the anode and cathode. Therefore, the sandwich structure of an OLED can also be understood as a capacitor structure.

[0003] The light-emitting principle of OLEDs is that when an appropriate voltage is applied, holes in the positive electrode and electrons in the cathode are injected into the anode and cathode respectively in the form of current, and then move in opposite directions under the influence of the electric field to combine in the light-emitting layer. During the combination process, electrons release energy in the form of photons, thus producing light emission. Therefore, the light-emitting speed of OLEDs mainly depends on the current injection and recombination rates, as well as the performance of the light-emitting material. However, the presence of parasitic capacitance affects the current injection process. Especially when OLED displays are used for low grayscale displays, the capacitor charging speed of OLEDs is very slow, resulting in problems such as large differences in display brightness and uneven color display.

[0004] How to achieve smaller brightness differences and more uniform colors in OLED displays with low grayscale levels remains an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a pixel circuit, a display panel, a display device, and a display driving method.

[0006] In a first aspect, this application provides a pixel circuit, including: a driving module, a data writing module, and a parasitic capacitance control module;

[0007] The driving module has one end for receiving the anode voltage and the other end connected to the anode of the light-emitting element, and is used to output driving current to drive the light-emitting element to emit light.

[0008] The data writing module has one end for receiving data and the other end connected to the driver module;

[0009] The parasitic capacitance control module has one end for receiving the anode voltage and the other end for connecting or disconnecting from the anode of the light-emitting element under the control of the parasitic capacitance control signal.

[0010] When the pre-display grayscale is less than or equal to the set grayscale threshold, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element.

[0011] In one embodiment, the parasitic capacitance control module includes: a capacitor and a capacitance control transistor;

[0012] One plate of the capacitor is one end of the parasitic capacitance control module, and the other plate of the capacitor is connected to the first end of the capacitor control transistor.

[0013] The second terminal of the capacitor control transistor is the other terminal of the parasitic capacitance control module;

[0014] The control terminal of the capacitor control transistor is used to receive the parasitic capacitance control signal.

[0015] In one embodiment, one electrode of the capacitor is disposed on the anode metal layer of the array substrate, and the other electrode of the capacitor is disposed on an adjacent metal layer of the anode metal layer near the substrate.

[0016] In one embodiment, the capacitance value of the new parasitic capacitor formed by connecting the capacitor in series with the parasitic capacitor is negatively correlated with the rated driving current of the light-emitting element.

[0017] In one embodiment, when the pre-display grayscale is greater than a set grayscale threshold, the parasitic capacitance control signal controls the parasitic capacitance control module to connect to the anode of the light-emitting element.

[0018] In one embodiment, when the pre-display grayscale is less than or equal to a set grayscale threshold, the parasitic capacitance control signal is used to control the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element before the data writing stage.

[0019] The parasitic capacitance control signal is also used to control the other end of the parasitic capacitance control module to disconnect from the anode of the light-emitting element before the data writing phase begins, and the connection is maintained for a preset duration.

[0020] Secondly, this application provides a driving method for a pixel circuit, the pixel circuit comprising: a driving module, a data writing module, and a parasitic capacitance control module;

[0021] The driving module has one end for receiving the anode voltage and the other end connected to the anode of the light-emitting element, and is used to output driving current to drive the light-emitting element to emit light.

[0022] The data writing module has one end for receiving data and the other end connected to the driver module;

[0023] The parasitic capacitance control module has one end for receiving the anode voltage and the other end for connecting or disconnecting from the anode of the light-emitting element under the control of the parasitic capacitance control signal.

[0024] When the pre-displayed grayscale is less than or equal to the set grayscale threshold, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element.

[0025] The method includes:

[0026] When the pre-display grayscale is less than or equal to the set grayscale threshold, the other end of the parasitic capacitance control module is connected to the anode of the light-emitting element based on the parasitic capacitance control signal, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element.

[0027] In one embodiment, the method further includes:

[0028] If the pre-display grayscale is less than or equal to the set grayscale threshold, before the data writing stage begins, based on the parasitic capacitance control signal, the other end of the parasitic capacitance control module is controlled to connect to the anode of the light-emitting element.

[0029] The connection is maintained for a preset duration, and before the data writing phase begins, the other end of the parasitic capacitance control module is disconnected from the anode of the light-emitting element.

[0030] Thirdly, this application provides a display panel, including the pixel circuit as described in the first aspect, and further including an array substrate;

[0031] The pixel circuit is disposed on the array substrate.

[0032] Fourthly, this application provides a display device including a display panel as described in the third aspect.

[0033] In the pixel circuit provided in this embodiment, the parasitic capacitance control module receives the anode voltage of the light-emitting element. When the pre-display grayscale is less than or equal to a set grayscale threshold, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element, so that the parasitic capacitance control module and the parasitic capacitance of the light-emitting element are connected in series. Referring to the above description, the parasitic capacitance of the light-emitting element is reduced, allowing the light-emitting element to enter the light-emitting area more quickly. Therefore, in the case of low grayscale display, the light-emitting element enters the light-emitting area more quickly, reducing the display brightness difference of the OLED display and making the display color more uniform. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a pixel circuit according to one embodiment;

[0036] Figure 2 This is a schematic diagram of the pixel circuit structure in another embodiment;

[0037] Figure 3 This is a schematic diagram of the pixel circuit in yet another embodiment;

[0038] Figure 4 This is a schematic diagram of the pixel circuit structure in another embodiment;

[0039] Figure 5 This is a schematic diagram of the structure of an array substrate according to one embodiment;

[0040] Figure 6 This is a timing diagram of the control signals in one embodiment;

[0041] Figure 7 This is a flowchart illustrating a display driving method according to one embodiment;

[0042] Figure 8 This is a schematic diagram of the structure of a display panel according to one embodiment;

[0043] Figure 9 This is a schematic diagram of the structure of a display device according to one embodiment;

[0044] Explanation of reference numerals in the attached figures:

[0045] 10. Pixel circuit; 200. Driving module; 300. Data writing module; 400. Parasitic capacitance control module; 401. Capacitor control transistor; 20. Light-emitting element; 21. Parasitic capacitance; 30. Array substrate; 31. Anode metal layer; 32. Substrate; 33. Active layer; 34. First metal layer; 35. Second metal layer; 36. Third metal layer; 37. Fourth metal layer; 38. First via; 39. Second via; 40. Display panel; 50. Display device. Detailed Implementation

[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0049] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0050] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0051] When used herein, the singular forms of “a,” “an,” and “the / that” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0052] When an OLED display is used to display at low grayscale, the parasitic capacitance of the OLED charges very slowly, resulting in problems such as large differences in display brightness and uneven display colors.

[0053] Based on this, this application provides a pixel circuit. The pixel circuit includes a driving module, a data writing module, and a parasitic capacitance control module. The parasitic capacitance control module receives the anode voltage of the light-emitting element. When the pre-display grayscale is less than or equal to a set grayscale threshold, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element, thus connecting the parasitic capacitance control module in series with the parasitic capacitance in the light-emitting element. Therefore, in low grayscale (low current driving the light-emitting element) display, since the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element, it can be considered that a new parasitic capacitance is formed through series connection, and the series effect makes the capacitance value of the new parasitic capacitance smaller. Thus, by reducing the parasitic capacitance of the light-emitting element, the light-emitting element enters the light-emitting area more quickly. In low grayscale display, the light-emitting element enters the light-emitting area more quickly, reducing the brightness difference of the OLED display and making the displayed color more uniform.

[0054] Figure 1 This is a schematic diagram of the structure of the pixel circuit 10 in some embodiments of this application. In some embodiments, the pixel circuit 10 includes a driving module 200, a data writing module 300, and a parasitic capacitance control module 400.

[0055] The driving module 200 has one end for receiving the anode voltage (ELVDD as shown in the figure) and the other end connected to the anode of the light-emitting element 20. The driving module 200 outputs a driving current to drive the light-emitting element 20 to emit light. ELVSS shown in the figure represents the cathode voltage.

[0056] For easier understanding, please refer to Figure 2The illustrated 7T1C pixel circuit may include a driving module 200 comprising a driving transistor T1. A first terminal of the driving transistor T1 receives the anode voltage, a second terminal is connected to the light-emitting element 20, and a control terminal is connected to the other plate of the first capacitor Cst in the threshold compensation module. One plate of the first capacitor Cst in the threshold compensation module receives the anode voltage. The second terminal of the driving transistor T1 outputs a driving current to drive the light-emitting element 20 to emit light. Figure 2 The driving transistor T1 shown is a P-type transistor, which conducts under low voltage and turns off under high voltage. This driving transistor T1 can also be set to an N-type transistor according to actual needs; this embodiment does not impose any limitation. An N-type transistor conducts under high voltage and turns off under low voltage. The driving module 200 may also include other transistors, as long as they can achieve the above functions; this embodiment does not impose any limitation.

[0057] The data writing module 300 has one end for receiving data and the other end connected to the driver module 200. The data writing module 300 receives a data write signal VData to receive data Data. When the data writing module 300 is on, it is connected to the driver module 200.

[0058] For easier understanding, please refer to Figure 2 The illustrated 7T1C pixel circuit may include a data writing module 300 that includes a data writing transistor T2. The control terminal of the data writing transistor T2 receives a control signal Scan2, its first terminal receives data Data, and its second terminal is connected to the first terminal of the driving transistor T1. The control signal Scan2 controls whether the data writing transistor T2 is turned on. Figure 2 The data writing transistor T2 shown is a P-type transistor, which is turned on when the voltage level is low and turned off when the voltage level is high. Correspondingly, if the control signal Scan2 is low, the data writing transistor T2 is turned on; if the control signal Scan2 is high, the data writing transistor T2 is turned off. The data writing transistor T2 can also be set to an N-type transistor according to actual needs; this embodiment does not limit its use. N-type transistors are turned on when the voltage level is high and turned off when the voltage level is low. The data writing module 300 may also include other transistors, as long as they can achieve the above functions; this embodiment does not limit their use.

[0059] The parasitic capacitance control module 400 has one end for receiving the anode voltage and the other end for connecting or disconnecting from the anode of the light-emitting element 20 under the control of the parasitic capacitance 21 control signal. When the pre-display grayscale is less than or equal to a set grayscale threshold, the parasitic capacitance 21 control signal controls the other end of the parasitic capacitance control module 400 to connect to the anode of the light-emitting element 20, so that the parasitic capacitance control module 400 is connected to the parasitic capacitance 21 (C shown in the figure) in the light-emitting element 20. OLED (in series)

[0060] In other words, when the parasitic capacitance control module 400 is not connected to the anode of the light-emitting element 20, the voltage across the parasitic capacitor 21 in the light-emitting element 20 remains unchanged. After the parasitic capacitance control module 400 is connected to the anode of the light-emitting element 20, it is equivalent to being connected in series with the parasitic capacitor 21. The parasitic capacitance control module 400 and the parasitic capacitor 21 form a new parasitic capacitance through series connection, and the series effect makes the capacitance value of the new parasitic capacitor smaller. Therefore, by reducing the parasitic capacitance 21 of the light-emitting element 20, the light-emitting element 20 enters the light-emitting area more quickly.

[0061] Figure 2 The pixel circuit 10 shown also includes a reset module, a light emission control module, and a threshold compensation module. The reset module includes transistors T4 and T7. The light emission control module includes transistors T5 and T6. The threshold compensation module includes a first capacitor Cst and a compensation transistor T3.

[0062] In this reset module, the control terminals of transistors T4 and T7 both receive the reset control signal Scan1. The first terminal of transistor T4 is connected to the other plate of the first capacitor Cst, and the second terminal of transistor T4 receives the reset voltage Vref1. The first terminal of transistor T7 receives the reset voltage Vref2, and the second terminal is connected to the anode of the light-emitting element 20. When transistor T4 is turned on under the control of the reset control signal Scan1, the first capacitor Cst and the control terminal of the driving transistor T1 receive the reset voltage Vref1. When transistor T7 is turned on under the control of the reset control signal Scan1, the anode of the light-emitting element 20 receives the reset voltage Vref2.

[0063] In this light-emitting control module, the control terminals of transistors T5 and T6 are both used to receive the light-emitting control signal (EMIT). The first terminal of transistor T5 receives the anode voltage, and its second terminal is connected to the second terminal of data writing transistor T2 via node N2, and also to the first terminal of driving transistor T1 via node N2. The first terminal of transistor T6 is connected to the second terminal of driving transistor T1 via node N3, and its second terminal is connected to the anode of light-emitting element 20, and also to the second terminal of transistor T7. After transistors T5 and T6 are turned on under the control of the light-emitting control signal, light-emitting element 20 emits light.

[0064] In this threshold voltage compensation module, one plate of the first capacitor Cst receives the anode voltage, and the other plate is connected to the first terminal of the compensation transistor T3. The second terminal of the compensation transistor T3 is connected to the anode of the light-emitting element 20, and its control terminal receives the control signal Scan2, which controls whether the compensation transistor T3 is turned on. When the compensation transistor T3 is turned on, the voltage output at the other plate of the first capacitor Cst is used to compensate for the threshold voltage of the driving module 200. When the control signal Scan2 is low, the compensation transistor T3 is turned on. When the control signal Scan2 is high, the compensation transistor T3 is turned off. As the operating time increases, the drive current output by the driving module 200 decreases, so the threshold compensation module needs to output a compensation voltage to compensate for the threshold voltage Vth of the driving module 200, thereby compensating for the drive current output by the driving module 200 and maintaining the normal display of the light-emitting element 20.

[0065] The pixel circuit 10 includes a reset phase, a data writing phase, and a light-emitting phase. In the reset phase, transistors T4 and T7 are both turned on under the action of the reset control signal Scan1. In the data writing phase, data writing transistor T2, driving transistor T1, and compensation transistor are all turned on under the action of the control signal Scan2, and the threshold voltage compensation module compensates for the threshold voltage Vth of the driving module 200. In the light-emitting phase, transistors T1, T5, and T6 are all turned on under the action of the light-emitting control signal, thereby causing the light-emitting element 20 to emit light.

[0066] Figure 2 The pixel circuit 10 shown is for illustrative purposes only and does not impose structural limitations on the pixel circuit 10 provided in this embodiment. The pixel circuit 10 can also be an 8T1C pixel circuit. Figure 2 The transistors shown are all P-type transistors, but they can also be set to N-type transistors according to actual needs. This embodiment does not limit them.

[0067] The parasitic capacitance control module 400 provided in this embodiment operates during the non-light-emitting phase to control whether the other end of the parasitic capacitance control module 400 is connected to or not connected to the anode of the light-emitting element 20.

[0068] In summary, in the pixel circuit 10 provided in this embodiment, the parasitic capacitance control module 400 is used to receive the anode voltage of the light-emitting element 20. When the pre-display grayscale is less than or equal to a set grayscale threshold, the parasitic capacitance 21 control signal controls the other end of the parasitic capacitance control module 400 to connect to the anode of the light-emitting element 20, so that the parasitic capacitance control module 400 and the parasitic capacitance 21 of the light-emitting element 20 are connected in series. Referring to the above description, the parasitic capacitance of the light-emitting element 20 is reduced, allowing the light-emitting element 20 to enter the light-emitting area more quickly. Therefore, in the case of low grayscale display, the light-emitting element 20 enters the light-emitting area more quickly, reducing the display brightness difference of the OLED display and making the display color more uniform.

[0069] In some embodiments, please refer to Figure 3 The circuit diagram shown illustrates that the parasitic capacitance control module 400 includes a capacitor C and a capacitor control transistor 401.

[0070] One plate of capacitor C is one end of the parasitic capacitance control module 400, used to receive the anode voltage. The other plate of capacitor C is connected to the first end of the capacitor control transistor 401. The second end of the capacitor control transistor 401 is the other end of the parasitic capacitance control module 400, connected to the anode of the light-emitting element 20. The control terminal of the capacitor control transistor 401 is used to receive the control signal of the parasitic capacitance 21.

[0071] The capacitance value of capacitor C can be greater than or equal to the parasitic capacitance 21 (C shown in the figure). OLED The capacitance value of the parasitic capacitor 21 can also be smaller than the capacitance value of the parasitic capacitor 21. This embodiment does not impose any limitation on this.

[0072] It is understandable that when two capacitors are connected in series, the total capacitance follows a specific formula: 1 / C = 1 / C1 + 1 / C2, where C represents the total capacitance, and C1 and C2 represent the individual capacitances of the two capacitors connected in series. From this formula, it can be seen that when two capacitors are connected in series, the total capacitance will be less than the capacitance of either individual capacitor, C1 or C2. That is, the total capacitance C and the parasitic capacitance 21 (C...) OLED After being connected in series, the new parasitic capacitance on the light-emitting element 20 will be smaller than the parasitic capacitance 21 (C). OLED This reduces the parasitic capacitance value of the light-emitting element 20, thereby lowering the parasitic capacitance of the light-emitting element 20.

[0073] The capacitor-controlled transistor 401 can be a P-type transistor as shown in the figure, which conducts when the voltage level is low and when the voltage level is high. Alternatively, the capacitor-controlled transistor 401 can be an N-type transistor, which conducts when the voltage level is high and when the voltage level is low.

[0074] For ease of understanding, please refer to the following: Figure 2 The 7T1C pixel circuit 10 shown forms Figure 4 The pixel circuit 10 shown. Figure 4 In the pixel circuit 10 shown, after the capacitor control transistor 401 (T8) is turned on under the action of the parasitic capacitor 21 control signal Scan3, the capacitor C and the parasitic capacitor 21 (C OLED ) in series. In the case of low grayscale display, the capacitor C and the parasitic capacitor 21 (C OLED After being connected in series, the new parasitic capacitance on the light-emitting element 20 will be smaller than the parasitic capacitance 21 (C). OLED This reduces the parasitic capacitance value of the light-emitting element 20, thereby lowering the parasitic capacitance of the light-emitting element 20.

[0075] For example, when the pre-display grayscale is greater than the set grayscale threshold (high grayscale display), the capacitor transistor may not be connected to the anode of the light-emitting element 20, that is, there is no need to reduce the parasitic capacitance 21 of the light-emitting element 20.

[0076] In the pixel circuit 10 provided in this embodiment, after the capacitor control transistor 401 is turned on under the control signal of the parasitic capacitor 21, the capacitor C and the parasitic capacitor 21 (C OLED ) in series. In the case of low grayscale display, the capacitor C and the parasitic capacitor 21 (C OLED After being connected in series, the new parasitic capacitance on the light-emitting element 20 will be smaller than the parasitic capacitance 21 (C). OLED This reduces the parasitic capacitance value of the light-emitting element 20, thereby lowering the parasitic capacitance of the light-emitting element 20.

[0077] In some embodiments, one electrode of the capacitor C is disposed on the anode metal layer 31 of the array substrate 30, and the other electrode of the capacitor is disposed on an adjacent metal layer of the anode metal layer 31 near the substrate 32. The array substrate 30 includes the pixel circuit 10, as well as light-emitting units and driving circuits connected to the pixel circuit 10. The driving circuit is connected to the pixel circuit 10 and provides electrical signals to the pixel circuit 10 to drive the light-emitting units to emit light. These driving circuits are typically located in the edge region of the array substrate 30 and are connected to the pixel circuit 10 via wires.

[0078] Please see Figure 5The illustrated structural diagram of the array substrate 30 shows that the array substrate 30 includes an anode metal layer 31, a substrate 32, and active layer 33 (Poly), with each metal layer as shown: a first metal layer 34, a second metal layer 35, a third metal layer 36, and a fourth metal layer 37. The fourth metal layer 37 is the adjacent metal layer of the anode metal layer 31 to the substrate 32. A first via 38 is provided between the third metal layer 36 and the second metal layer 35. A second via 39 is provided between the fourth metal layer 37 and the first metal layer 36. One electrode of the capacitor is disposed on the anode metal layer 31, and the other electrode can be disposed on the fourth metal layer 37. This simplifies the structure of the capacitor C and reduces the manufacturing cost of the pixel circuit 10.

[0079] In some embodiments, the capacitor C and the parasitic capacitor 21 (C OLED The capacitance value of the new parasitic capacitance formed after being connected in series is negatively correlated with the rated drive current of the light-emitting element 20.

[0080] It is understandable that red (R), green (G), and blue (B) materials correspond to the OLEDs that display red, green, and blue colors in an OLED display, respectively. During the OLED deposition process, differences in capacitance occur between OLEDs using different light-emitting materials, resulting in differences in display brightness and uneven color distribution on the OLED display.

[0081] R / G / B light-emitting element 20 has original parasitic capacitance 21 (C OLED This will affect the rated drive current. Parasitic capacitance 21 (C) OLED The larger the value of , the larger the rated driving current, and the greater the current required to drive the light-emitting elements into the light-emitting area. To enable the R / G / B light-emitting elements to simultaneously enter the light-emitting area, the original parasitic capacitance 21 (C) needs to be addressed. OLED The large light-emitting element 20 makes the capacitance value of the new parasitic capacitance the same as the original parasitic capacitance 21 (C). OLED The difference between the two is greater, and the new parasitic capacitance is smaller, allowing the light-emitting element 20 to enter the light-emitting area more quickly. In contrast, the original parasitic capacitance 21 (C...) OLED The small light-emitting element 20 makes the capacitance value of the new parasitic capacitance the same as the original parasitic capacitance 21 (C). OLEDThe smaller the difference between the two, the smaller the capacitance of the new parasitic capacitor, allowing the light-emitting element 20 to enter the light-emitting area more quickly. For example, if the rated driving current of the light-emitting element G is larger, then by setting the capacitance value of capacitor C, the capacitance value of the new parasitic capacitor is made smaller, and the light-emitting element G enters the light-emitting area at a first speed. Conversely, if the rated driving current of the light-emitting element R is smaller, then by designing the capacitance value of capacitor C, the capacitance value of the new parasitic capacitor is made smaller, and the light-emitting element G enters the light-emitting area at a second speed. The first speed is greater than the second speed.

[0082] In this way, the light-emitting element 20 with a large rated drive current can enter the light-emitting area faster, and the light-emitting element 20 with a small rated drive current can enter the light-emitting area relatively quickly, allowing different light-emitting elements 20 to enter the light-emitting area simultaneously. Especially in the case of low grayscale display, by controlling the light-emitting elements 20 with different rated drive currents to enter the light-emitting area simultaneously, the color accuracy of low grayscale display can be effectively improved.

[0083] It should be noted that, as described above, by designing the capacitance value of capacitor C, the capacitance value of the new parasitic capacitance can be controlled.

[0084] In the pixel circuit 10 provided in this embodiment, by designing the capacitance value of capacitor C, the capacitance value of the new parasitic capacitor formed by the capacitor and the parasitic capacitor 21 connected in series is negatively correlated with the rated driving current of the light-emitting element 20. Therefore, it is possible to control light-emitting elements 20 with different rated driving currents to simultaneously enter the light-emitting area, effectively improving the color accuracy of low grayscale displays.

[0085] In some embodiments, to enable the light-emitting element 20 to enter the light-emitting area more quickly, when the pre-display grayscale is greater than a set grayscale threshold, the parasitic capacitance 21 control signal controls the parasitic capacitance control module 400 to connect to the anode of the light-emitting element 20. That is, in the case of high grayscale display, the parasitic capacitance control module 400 is still connected in series with the parasitic capacitance 21 of the light-emitting element 20, thereby making the new parasitic capacitance value of the light-emitting element 20 smaller, and enabling the light-emitting element 20 to enter the light-emitting area more quickly.

[0086] In some embodiments, combined with Figure 4 ,right Figure 6 The timing diagrams of each signal shown are illustrated when the pre-display grayscale is less than or equal to the set grayscale threshold.

[0087] When the reset control signal Scan1 is set to low, the pixel circuit 10 enters the reset phase. When the control signal Scan2 is set to low, the pixel circuit 10 enters the data writing phase. When the light emission control signal Emit is set to low, the pixel circuit 10 enters the light emission phase. It should be noted that when the light emission control signal Emit shown in the figure is continuously set to high, the pixel circuit 10 is in the non-light emission phase.

[0088] The parasitic capacitance 21 control signal Scan3 is used to control the connection between the other end of the parasitic capacitance control module 400 and the anode of the light-emitting element 20 before the data writing stage. That is, before the data writing stage, the parasitic capacitance 21 control signal Scan3 is set to a low level to turn on the capacitor control transistor 401 (T8), and the capacitor C and parasitic capacitance 21 (C... OLED By connecting the parasitic capacitance control module 400 in series with the anode of the light-emitting element 20, it is easier for the light-emitting element 20 to enter the light-emitting area. The connection between the parasitic capacitance control module 400 and the anode of the light-emitting element 20 is maintained for a preset time. Before the data writing phase begins, the parasitic capacitance 21 control signal Scan3 is also used to control the other end of the parasitic capacitance control module 400 to disconnect from the anode of the light-emitting element 20. As shown in the figure, before the data writing phase begins, the parasitic capacitance 21 control signal Scan3 is set to a high level, thereby turning off the capacitor control transistor 401 (T8), disconnecting the capacitor C from the anode of the light-emitting element 20, and also disconnecting the parasitic capacitance 21 (T8). OLED Disconnect between ( ).

[0089] Optionally, as shown in the figure, after the reset phase begins, the parasitic capacitance 21 control signal Scan3 is set to a low level, and after the reset phase ends, the parasitic capacitance 21 control signal Scan3 remains at a low level.

[0090] One embodiment of this application also provides a method for driving a pixel circuit. The pixel circuit may be the pixel circuit 10 provided in any of the preceding embodiments.

[0091] Please see Figure 7 The flowchart shown illustrates that the display driving method includes:

[0092] Step 701: When the pre-displayed grayscale is less than or equal to the set grayscale threshold, the other end of the parasitic capacitance control module is connected to the anode of the light-emitting element based on the parasitic capacitance control signal, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element.

[0093] It is understandable that the parasitic capacitance control module 400 is used to receive the anode voltage of the light-emitting element 20. When the pre-display gray level is less than or equal to the set gray level threshold, if the parasitic capacitance 21 control signal controls the other end of the parasitic capacitance control module 400 to be connected to the anode of the light-emitting element 20, the parasitic capacitance control module 400 can be connected in series with the parasitic capacitance 21 in the light-emitting element 20.

[0094] In the case of low grayscale (small current driving light-emitting element) display, since the parasitic capacitance control module 400 is connected in series with the parasitic capacitance 21 in the light-emitting element 20, it can be regarded as forming a new parasitic capacitance through series connection. The series connection effect makes the capacitance value of the new parasitic capacitance smaller.

[0095] Therefore, the method provided in this embodiment reduces the parasitic capacitance 21 of the light-emitting element 20, allowing the light-emitting element 20 to enter the light-emitting area more quickly. In the case of low grayscale display, the faster entry of the light-emitting element 20 into the light-emitting area reduces the brightness difference of the OLED display screen, resulting in more uniform display colors.

[0096] In some embodiments, the display driving method further includes:

[0097] Step 1: When the pre-display grayscale is less than or equal to the set grayscale threshold, before the data writing stage begins, based on the parasitic capacitance control signal, control the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element.

[0098] Step two: Maintain the connection for a preset time and disconnect the other end of the parasitic capacitance control module from the anode of the light-emitting element before the data writing phase begins.

[0099] Combination Figure 4 and Figure 6 By setting the reset control signal Scan1 low, the pixel circuit 10 enters the reset phase. By setting the control signal Scan2 low, the pixel circuit 10 enters the data writing phase. By setting the light emission control signal Emit low, the pixel circuit 10 enters the light emission phase.

[0100] Before the data writing phase, the other end of the parasitic capacitance control module 400 is connected to the anode of the light-emitting element 20 based on the parasitic capacitance 21 control signal Scan3. That is, before the data writing phase, the parasitic capacitance 21 control signal Scan3 is set to a low level to turn on the capacitor control transistor 401 (T8), and the capacitor C and parasitic capacitance 21 (C... OLED By connecting them in series, the light-emitting element 20 can more easily enter the light-emitting area.

[0101] The connection between the parasitic capacitance control module 400 and the anode of the light-emitting element 20 is maintained for a preset time. Before the data writing phase begins, based on the parasitic capacitance 21 control signal Scan3, the other end of the parasitic capacitance control module 400 is disconnected from the anode of the light-emitting element 20. As shown in the figure, before the data writing phase begins, the parasitic capacitance 21 control signal Scan3 is set to a high level, thereby turning off the capacitor control transistor 401 (T8), disconnecting the capacitor C from the anode of the light-emitting element 20, and also disconnecting the parasitic capacitance 21 (T8) from the anode of the light-emitting element 20. OLED Disconnect between ( ).

[0102] One embodiment of this application also provides a display panel 40. Please refer to... Figure 8 The schematic diagram shown is of a display panel 40, which includes a pixel circuit 10 as provided in any of the preceding embodiments, and also includes an array substrate 30. The pixel circuit 10 is disposed on the array substrate 30.

[0103] In some embodiments, one electrode of the capacitor C in the pixel circuit 10 is disposed on the anode metal layer 31 of the array substrate 30, and the other electrode of the capacitor is disposed on an adjacent metal layer of the anode metal layer 31 near the substrate 32. The array substrate 30 includes the pixel circuit 10, as well as light-emitting units and driving circuits connected to the pixel circuit 10. The driving circuits are connected to the pixel circuit 10 and provide electrical signals to the pixel circuit 10 to drive the light-emitting units to emit light. These driving circuits are typically located in the edge region of the array substrate 30 and are connected to the pixel circuit 10 via wires.

[0104] Please see Figure 5 The illustrated schematic diagram of the array substrate 30 shows that the array substrate 30 includes an anode metal layer 31, a substrate 32, and active layer 33 (Poly), as shown in the figure, a first metal layer 34, a second metal layer 35, a third metal layer 36, and a fourth metal layer 37. The fourth metal layer 37 is the adjacent metal layer of the anode metal layer 31 to the substrate 32. A first via 38 is provided between the third metal layer 36 and the second metal layer 35. A second via 39 is provided between the fourth metal layer 37 and the first metal layer 36. One electrode of the capacitor is disposed in the anode metal layer 31, and the other electrode can be disposed in the fourth metal layer 37. This simplifies the structure of the capacitor C and reduces the manufacturing cost of the pixel circuit 10.

[0105] One embodiment of this application also provides a display device 50. Please refer to... Figure 9The schematic diagram shown illustrates a display device 50, which includes a display panel 40 as provided in the above embodiment. This display device 50 can be, for example, a mobile phone, tablet computer, laptop computer, or vehicle-mounted display; this embodiment does not limit the scope of the device.

[0106] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The module consists of a driver module, a data writing module, and a parasitic capacitance control module. The driving module has one end for receiving the anode voltage and the other end connected to the anode of the light-emitting element, and is used to output driving current to drive the light-emitting element to emit light. The data writing module has one end for receiving data and the other end connected to the driver module; The parasitic capacitance control module has one end for receiving the anode voltage and the other end for connecting or disconnecting from the anode of the light-emitting element under the control of the parasitic capacitance control signal. When the pre-display grayscale is less than or equal to the set grayscale threshold, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element.

2. The pixel circuit according to claim 1, characterized in that, The parasitic capacitance control module includes: a capacitor and a capacitance control transistor; One plate of the capacitor is one end of the parasitic capacitance control module, and the other plate of the capacitor is connected to the first end of the capacitor control transistor. The second terminal of the capacitor control transistor is the other terminal of the parasitic capacitance control module; The control terminal of the capacitor control transistor is used to receive the parasitic capacitance control signal.

3. The pixel circuit according to claim 2, characterized in that, One electrode of the capacitor is disposed on the anode metal layer of the array substrate, and the other electrode of the capacitor is disposed on an adjacent metal layer on the side of the anode metal layer close to the substrate.

4. The pixel circuit according to claim 2, characterized in that, The capacitance value of the new parasitic capacitor formed by the capacitor connected in series with the parasitic capacitor is negatively correlated with the rated driving current of the light-emitting element.

5. The pixel circuit according to any one of claims 1-4, characterized in that, When the pre-display grayscale is greater than the set grayscale threshold, the parasitic capacitance control signal controls the parasitic capacitance control module to connect to the anode of the light-emitting element.

6. The pixel circuit according to any one of claims 1-4, characterized in that, When the pre-display grayscale is less than or equal to the set grayscale threshold, the parasitic capacitance control signal is used to control the other end of the parasitic capacitance control module to be connected to the anode of the light-emitting element before the data writing stage. The parasitic capacitance control signal is also used to control the other end of the parasitic capacitance control module to disconnect from the anode of the light-emitting element before the data writing phase begins, and the connection is maintained for a preset duration.

7. A driving method for a pixel circuit, characterized in that, The pixel circuit includes: a driving module, a data writing module, and a parasitic capacitance control module; The driving module has one end for receiving the anode voltage and the other end connected to the anode of the light-emitting element, and is used to output driving current to drive the light-emitting element to emit light. The data writing module has one end for receiving data and the other end connected to the driver module; The parasitic capacitance control module has one end for receiving the anode voltage and the other end for connecting or disconnecting from the anode of the light-emitting element under the control of the parasitic capacitance control signal. When the pre-displayed grayscale is less than or equal to the set grayscale threshold, the parasitic capacitance control signal controls the other end of the parasitic capacitance control module to connect to the anode of the light-emitting element, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element. The method includes: When the pre-display grayscale is less than or equal to the set grayscale threshold, the other end of the parasitic capacitance control module is connected to the anode of the light-emitting element based on the parasitic capacitance control signal, so that the parasitic capacitance control module is connected in series with the parasitic capacitance in the light-emitting element.

8. The method according to claim 7, characterized in that, The method further includes: If the pre-display grayscale is less than or equal to the set grayscale threshold, before the data writing stage begins, based on the parasitic capacitance control signal, the other end of the parasitic capacitance control module is controlled to connect to the anode of the light-emitting element. The connection is maintained for a preset duration, and before the data writing phase begins, the other end of the parasitic capacitance control module is disconnected from the anode of the light-emitting element.

9. A display panel, characterized in that, Including the pixel circuit as described in any one of claims 1-6, and further including an array substrate; The pixel circuit is disposed on the array substrate.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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