Display panel and display device

Abstract

This application provides a display panel and a display device. A plurality of first data traces of the display panel are disposed within at least two conductive layers in a non-display area. A plurality of second data traces are used to connect pixel columns. The plurality of first data traces and the plurality of second data traces are electrically connected in a one-to-one correspondence. The plurality of first data traces are arranged in a second order, which is at least partially different from the first order. The first data traces are used to access at least two short-circuit test signals during the screen testing phase of the display panel. Different short-circuit test signals are used to drive two adjacent pixel units in the first order, respectively. Furthermore, in the second order, two adjacent first data traces within the same conductive layer are used to access different short-circuit test signals. By adjusting the arrangement order of the first data traces, it is ensured that adjacent traces in the same layer are accessed with different short-circuit test signals, which is beneficial for accurately detecting whether there is a short circuit in the same layer's fan-out lines.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and display device. Background Technology

[0002] Active-matrix organic light-emitting diode (AMOLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current display products needs to be improved. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and display device that aims to solve the problem of low performance of display products in traditional technologies.

[0005] A first aspect of this application provides a display panel, the display panel including a display area and a non-display area, the non-display area surrounding the display area, the display area having multiple pixel columns arranged in a first-order sequence; wherein, a portion of pixels in the nth pixel column and the (n+1)th pixel column combine to form a pixel unit, where n is a positive integer; the display panel includes:

[0006] Multiple data traces, including multiple first data traces and multiple second data traces, wherein the multiple first data traces are disposed in at least two conductive layers in the non-display area, and the multiple second data traces are disposed in the display area and used to connect the pixel column; the multiple first data traces and the multiple second data traces are electrically connected in a one-to-one correspondence; wherein the multiple first data traces are arranged in a second order, and the second order is at least partially different from the first order;

[0007] Wherein, the first data trace is used to access at least two short-circuit test signals during the screen testing phase of the display panel, and different short-circuit test signals are used to drive two adjacent pixel units in the first sequence respectively, and in the second sequence of the plurality of first data traces, two adjacent first data traces in the same conductive layer are used to access different short-circuit test signals.

[0008] In some embodiments of this application, two adjacent first data traces in the second sequence are disposed in different conductive layers.

[0009] In some embodiments of this application, the at least two conductive layers include a first conductive layer and a second conductive layer, the first data trace of the odd-numbered column is disposed on the first conductive layer, and the first data trace of the even-numbered column is disposed on the second conductive layer.

[0010] In some embodiments of this application, the at least two short-circuit test signals include a first signal and a second signal. The first signal is used to drive the m-th pixel unit, and the second signal is used to drive the (m+1)-th pixel unit, where m is a positive integer. Among the first signal and the second signal, one is a high-level signal and the other is a low-level signal.

[0011] In some embodiments of this application, the display area is provided with multiple pixel rows, the pixel rows and the pixel columns are arranged alternately, and each pixel unit has at least two pixel rows.

[0012] In some embodiments of this application, each pixel unit has two rows of pixels, and each pixel unit includes at least one red pixel, at least one green pixel, and at least one blue pixel.

[0013] In some embodiments of this application, at least one of the nth pixel column and the (n+1)th pixel column includes a red pixel and a blue pixel, and the other includes two green pixels. The red pixel, the blue pixel, and the two green pixels are arranged adjacent to each other to form a pixel unit.

[0014] In some embodiments of this application, the multiple pixel columns are arranged in the least repetition order, which is GRGBBGRGBGRG, where GRGBBGRGBGRG is the arrangement order of pixels in the multiple pixel rows; wherein G represents green pixels, R represents red pixels, and B represents blue pixels.

[0015] In some embodiments of this application, the at least two pixel rows include a first pixel row and a second pixel row. The first pixel row is located closer to the area where the first data trace is located than the second pixel row. GRGBBGRGBGRG represents the arrangement order of pixels in the second pixel row.

[0016] In some embodiments of this application, the first data trace and its corresponding second data trace are connected through a cable exchange hole located at the edge of the non-display area.

[0017] A second aspect of this application also provides a display device, including the display panel as described above.

[0018] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The above-described display panel and display device include a display area and a non-display area, the non-display area surrounding the display area, and a plurality of pixel columns arranged in a first-order sequence within the display area; wherein, a portion of pixels in the nth pixel column and the (n+1)th pixel column combine to form a pixel unit, where n is a positive integer; the display panel includes a plurality of data traces, including a plurality of first data traces and a plurality of second data traces, the plurality of first data traces being disposed within at least two conductive layers in the non-display area, and the plurality of second data traces being disposed within the display area and used to connect the pixel columns; the plurality of first data traces and the plurality of second data traces are electrically connected in a one-to-one correspondence. In this application, multiple first data traces are arranged in a second order, which is at least partially different from the first order. The first data traces are used to access at least two short-circuit test signals during the display panel's screen testing phase. Different short-circuit test signals are used to drive two adjacent pixel units in the first order, respectively. Furthermore, in the second order, two adjacent first data traces within the same conductive layer are used to access different short-circuit test signals. By adjusting the arrangement order of the first data traces, this application ensures that adjacent traces on the same layer are connected to different short-circuit test signals, which is beneficial for accurately detecting whether there is a short circuit in the same layer's fan-out lines. It also helps avoid increasing the screen's chin height due to multiple trace changes. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0020] Figure 2 A schematic diagram of the structure of a display panel provided for a related technology of this application;

[0021] Figure 3 Another structural schematic diagram of a display panel provided for a related technology of this application;

[0022] Figure 4 A schematic diagram of the structure of a display panel provided for another related technology of this application;

[0023] Figure 5 Another structural schematic diagram of a display panel provided for another related technology of this application;

[0024] Figure 6 Another structural schematic diagram of a display panel provided for another related technology of this application;

[0025] Figure 7 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application;

[0026] Figure 8This is a schematic diagram of the structure of a display panel provided in another embodiment of this application.

[0027] Specific element symbol explanations: 100 - display area, 110 - red pixel, 120 - green pixel, 130 - blue pixel, 200 - non-display area, 300 - first data trace, 400 - second data trace. Detailed Implementation

[0028] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0029] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0030] It should be understood that the terms "length", "width", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0032] As display technology continues to evolve towards narrow bezels and high screen-to-body ratios, in FIAA (Fan-out in AA) technology, the arrangement order of data traces in sequential FIAA strictly corresponds to the arrangement order of pixel columns, such as RGBG. In reverse FIAA, the arrangement order of data traces differs from the pixel column arrangement order; for example, the conventional reverse FIAA arrangement is GRGBBGGRGRBG. Because conventional reverse FIAA does not require multiple trace changes to adjust the data transmission order, it effectively avoids the increase in screen chin height caused by line bends. This makes it more competitive in balancing narrow bezel design and screen size control, and it is gradually becoming the industry's preferred solution.

[0033] In the manufacturing process of display panels, the screen testing stage is a crucial step in ensuring product quality. Among these steps, short-circuit detection of data traces within the conductive layers (such as metal layers M1 and M2) in non-display areas using short-circuit detection circuits (such as the CT2 circuit) is an essential process. Traditional testing principles are based on signal differentiation logic: adjacent data traces on the same layer are connected to different short-circuit test signals (such as high-level signal D1 and low-level signal D2). Under normal conditions without short circuits, the display will show a regular pattern of alternating black and white or specific colors. If a short circuit occurs between the two traces, the mixing of different signals will cause abnormalities in the display (such as uneven brightness or color distortion), allowing for the identification of defects through visual inspection or photoelectric sensors.

[0034] However, in the reverse FIAA scheme of related technologies, the pixel column arrangement breaks the traditional RGBG order and instead adopts a non-traditional color arrangement logic (such as a reverse arrangement of the smallest repeating unit GRGBBGGRGRBG). This unconventional pixel column arrangement directly leads to the incompatibility of the wiring order of data traces in the conductive layer of the non-display area with traditional detection logic—adjacent data traces on the same layer may be forced to connect to the same test signal due to the reverse order of the pixel columns. For example, in a certain reverse FIAA design, two adjacent M1 layer data traces both correspond to the green pixel column (G column), and both are connected to the D1 signal during detection. At this time, even if the two traces are short-circuited, the display will still maintain the normal green pixel brightness state because the signals are the same, and the detection mechanism cannot be triggered. The existence of this detection loophole makes it impossible for the reverse FIAA scheme to effectively screen out short-circuit defects on the same layer during the manufacturing process, causing defective products to flow into subsequent stages, which not only increases repair costs but may also affect the display reliability of the end product.

[0035] Traditional detection relies on signal differentiation between adjacent traces. However, reverse arrangement causes adjacent traces to correspond to the same color pixel column in terms of physical location or logical relationship, forcing the detection signals to tend to be consistent. This directly restricts the application of reverse FIAA technology in high-end display products, especially for new panel technologies such as OLED and MiniLED, which have extremely high requirements for detection accuracy. Therefore, how to achieve signal differentiation between adjacent data traces on the same layer under the reverse FIAA architecture has become an urgent problem to be solved in the display industry.

[0036] Based on this, this application makes improvements to the relevant display panel and display device.

[0037] Please see Figure 1 , Figure 1A schematic diagram of the structure of the display panel of this embodiment is shown. The display panel of this embodiment includes a display area 100 and a non-display area 200. The non-display area 200 is arranged around the display area 100. Multiple pixel columns are arranged in the display area 100 in first order. Among them, some pixels on the nth pixel column and the (n+1)th pixel column are combined to form a pixel unit, where n is a positive integer. The display panel includes multiple data traces, including multiple first data traces 300 and multiple second data traces 400. The multiple first data traces 300 are disposed in at least two conductive layers in the non-display area 200, and the multiple second data traces 400 are disposed in the display area 100 and used to connect pixel columns. The multiple first data traces 300 and the multiple second data traces 400 are electrically connected in a one-to-one correspondence. The multiple first data traces 300 are arranged in a second sequence, which is at least partially different from the first sequence. The first data traces 300 are used to access at least two short-circuit test signals during the screen testing phase of the display panel. Different short-circuit test signals are used to drive two adjacent pixel units in the first sequence, and when the multiple first data traces 300 are in the second sequence, two adjacent first data traces 300 in the same conductive layer are used to access different short-circuit test signals.

[0038] It needs to be explained that the display area 100 refers to the area in the display panel used to display images, which consists of pixel units arranged in a regular pattern; the non-display area 200 is the edge area surrounding the display area 100, mainly used for laying out the first data trace 300, scan lines, and other driving circuits. A pixel column is a set of pixels arranged along a specific direction within the display area 100. The first-order arrangement means that the pixel columns are arranged sequentially according to the original design logic of the display panel (such as the conventional RGBG color order), where the nth pixel column and the (n+1)th pixel column form a pixel unit by combining some pixels, for example, by combining the red (R), green (G), and blue (B) pixels of two adjacent columns into a display unit.

[0039] The first data trace 300 is a conductive line within the non-display area 200 used for transmitting image data. It is distributed across at least two conductive layers (such as metal layers M1 and M2) and electrically connected to each pixel column. The second data trace 400 is a conductive line within the display area 100 used for transmitting image data. The second sequence arrangement refers to a difference between the arrangement order of the first data traces 300 in the non-display area 200 and the first sequence of the pixel columns, for example, by adjusting the trace order through line swapping. The short-circuit test signal (such as D1 and D2) is an excitation signal used during the screen testing phase to detect whether the first data traces 300 within the same conductive layer are short-circuited. When adjacent first data traces 300 are connected to different signals, a short circuit will cause signal mixing and manifest as a display abnormality.

[0040] Please refer to the relevant technologies. Figure 2 and Figure 3 , Figure 2 A schematic diagram of the structure of a display panel provided by a related technology is shown. Figure 3 Another structural schematic diagram of a display panel provided by a related technology is shown. For example... Figure 2 and Figure 3 As shown, the first data trace 300 is arranged in FIAA order, and the pixel columns are usually arranged in a specific color order (such as RGBG). Figure 3 As shown, the first and second pixel columns combine to form the first pixel unit, the third and fourth pixel columns combine to form the second pixel unit, the fifth and sixth pixel columns combine to form the third pixel unit, and the seventh and eighth pixel columns combine to form the fourth pixel unit. The short-circuit test signals include data1 (D1) and data2 (D2). During the short-circuit test, D1 is provided to the first and third pixel units, and D2 is provided to the second and fourth pixel units. For example, D1 is a low-level signal, and D2 is a high-level signal. If the first and third pixel units display a dark image, and the second and fourth pixel units display a white image, then it is determined that no short circuit occurs on the same layer. If display clutter occurs, then a short circuit occurs on the same layer.

[0041] However, to maintain the order of the first data trace 300, multiple trace swapping operations are often required. Multiple swapping means more space is needed to arrange the swapping paths, directly leading to a significant increase in the height of the screen's chin, making it difficult to meet the current market demand for narrow-bezel display panels. Specifically, in a display panel, data needs to be transmitted from the driver chip to the pixel end to drive the pixels to emit light. For the FIAA RGBG pixel arrangement, the first data trace 300 must ensure that the red (R), green (G), blue (B), and green (G) pixels receive their corresponding signals accurately in sequence. Because this order is not naturally compatible with the underlying architecture of some display technologies, in non-display areas 200 (such as near the screen's chin), the first data trace 300 often needs to be adjusted multiple times. For example, the order of the data signals drawn from the chip may not be consistent with the RGBG arrangement order, requiring adaptation by swapping traces between different conductive layers (such as M1, M2, etc.). Each cable change requires additional space for vias, adapters, etc., which occupies more space in the vertical direction (corresponding to the height of the chin), thus increasing the chin height. Display panel manufacturing has strict wiring rules to ensure signal integrity and avoid short circuits. In sequential FIAA, multiple cable changes dramatically increase the wiring complexity of the non-display area 200. The traces of different conductive layers must ensure signal transmission quality while isolating each other. For example, a specific spacing must be maintained between adjacent traces, and sufficient space must be reserved between layers when multiple traces are stacked vertically. These additional space requirements accumulate, resulting in an increase in the vertical dimension of the screen in the chin area.

[0042] In another related technology, please refer to Figures 4 to 6 , Figure 4 A schematic diagram of the structure of a display panel provided in another related technology is shown. Figure 5 Another structural schematic diagram of a display panel provided in another related technology is shown. Figure 5 Another structural schematic diagram of a display panel provided in another related technology is shown.

[0043] Figure 4 The diagram illustrates inserting one minimum repeating unit of a data trace arrangement into two minimum repeating units, with the arrow indicating the insertion direction of the data trace.

[0044] The first data trace 300 is arranged in reverse FIAA order. In the non-display area 200, the first data trace 300 no longer needs to be arranged strictly according to the pixel column order, avoiding the extensive trace swapping operations required to maintain the order as in sequential FIAA. This provides an advantage in controlling the screen's chin height and is more conducive to achieving a narrow bezel design. During the screen testing phase of the display panel, it is necessary to detect short circuits in the same layer of the first data trace 300 within the conductive layer of the non-display area 200. The usual testing method is to connect two adjacent first data traces 300 in the same layer to different short-circuit test signals (such as D1 and D2). Under normal circumstances, the display image presents a specific state when there is no short circuit. When a short circuit occurs, the display image will appear abnormal due to the mixing of different signals, thus indicating a short-circuit defect. However, as... Figure 6 In the reverse FIAA design shown, due to the unconventional arrangement of pixel units, adjacent first data traces 300 in the conductive layer of the non-display area 200 may be connected to the same test signal. As a result, even if a short circuit occurs between these two first data traces 300, the display will not show any abnormalities because the signals are identical, rendering the short circuit detection mechanism ineffective and posing a significant risk of missed detections. This presents a major challenge to the quality control of the display panel.

[0045] Understandably, this application addresses the issue of adjacent first data traces 300 within the same conductive layer being connected to different short-circuit test signals (such as D1 and D2) in the second sequential arrangement. This avoids the problem of identical signals for adjacent traces on the same layer due to abnormal pixel unit arrangement in the reverse-order FIAA design. When a short circuit occurs on a trace on the same layer, the mixing of different signals directly leads to abnormal display, thereby accurately identifying the short-circuit location, significantly improving the defect detection rate during screen testing, and reducing the risk of missed detections. Furthermore, unlike sequential FIAA, this application only requires adjusting the order of the first data traces 300 through partial trace replacement, eliminating the need for large-scale line adjustments in bending areas. This avoids the increase in screen chin height caused by multiple trace replacements, maintaining the advantages of a narrow bezel design while solving the compatibility problem between the detection mechanism and size control, aligning with the current display industry's pursuit of an extreme screen-to-body ratio.

[0046] In some embodiments of this application, two adjacent first data traces 300 in the second sequence are disposed in different conductive layers.

[0047] It should be explained that the pixel columns in the display area 100 are arranged in a first order (such as the conventional RGBG order). A portion of the pixels in the nth and (n+1)th pixel columns are combined into a single pixel unit (such as a GR pixel unit or a GB pixel unit). In the multi-layer conductive layers of the non-display area 200, each conductive layer is evenly distributed with first data traces 300, and each first data trace 300 corresponds one-to-one with a pixel column. Unlike the first order of the pixel columns, the arrangement order of the first data traces 300 in the non-display area 200 is adjusted through cross-layer trace switching. For example, the first data trace 300 of the first pixel column is located in layer M1, the first data trace 300 of the second pixel column crosses over to layer M2, the first data trace 300 of the third pixel column returns to layer M1, and so on, forming a cross-layer trace structure with alternating "M1-M2-M1-M2" distribution. At this point, the two adjacent first data traces 300 in the second sequence (such as the traces corresponding to the first and second columns) are located in the M1 and M2 layers respectively, belonging to different conductive layers.

[0048] It is understandable that when the first data traces 300 are distributed across different conductive layers, the interlayer insulating medium (such as a dielectric layer) can effectively isolate the electromagnetic field coupling of adjacent traces. Furthermore, the cross-layer distribution of traces disperses the dense first data traces 300, originally concentrated on a single conductive layer, across multiple layers, reducing the trace density of a single conductive layer and minimizing the manufacturing difficulties and short-circuit risks caused by line congestion. For example, in related technologies, the M1 layer in reverse FIAA may require multiple consecutive adjacent traces, while this embodiment, through cross-layer trace switching, allows the M1 layer to only arrange traces in odd-numbered pixel columns, and the M2 layer to arrange traces in even-numbered pixel columns, increasing the spacing between traces in each layer and facilitating line isolation in the manufacturing process.

[0049] In some embodiments of this application, at least two conductive layers include a first conductive layer and a second conductive layer, with the first data trace 300 of the odd-numbered column disposed on the first conductive layer and the first data trace 300 of the even-numbered column disposed on the second conductive layer.

[0050] It is understandable that the first data path 300 of the odd-numbered columns can be the first data path 300 of the 1st, 3rd, 5th, and so on for the pixel columns. The first data path 300 of the even-numbered columns can be the first data path 300 of the 2nd, 4th, 6th, and so on for the pixel columns.

[0051] In some embodiments of this application, at least two short-circuit test signals include a first signal and a second signal. The first signal is used to drive the m-th pixel unit, and the second signal is used to drive the (m+1)-th pixel unit, where m is a positive integer. Among the first signal and the second signal, one is a high-level signal and the other is a low-level signal.

[0052] It needs to be explained that the first signal is used to drive the m-th pixel unit of the display area 100 (m is a positive integer), and the second signal is used to drive the (m+1)-th pixel unit. The two are logically mutually exclusive signals, that is, when one is a high-level signal, the other is a low-level signal (for example, the first signal is high-level (H) and the second signal is low-level (L), or vice versa).

[0053] It is understandable that in the conductive layer of the non-display area 200, after the first data traces 300 are arranged in a second order, adjacent first data traces 300 within the same conductive layer are connected to the first signal and the second signal, respectively. For example, in the first conductive layer, the first column of first data traces 300 is connected to the first signal (H), the third column is connected to the second signal (L), the fifth column is connected to the first signal (H), and so on, forming an alternating "HLHL" signal distribution; in the second conductive layer, the second column is connected to the second signal (L), the fourth column is connected to the first signal (H), and the sixth column is connected to the second signal (L), forming an alternating "LHL" distribution.

[0054] Specifically, since adjacent first data traces 300 in the same conductive layer are connected to mutually exclusive high and low level signals, when there is no short circuit between them, the corresponding pixel unit in the display area 100 presents a normal picture with alternating "bright-dark" (such as the H signal driving the pixel to light up and the L signal driving the pixel to turn off); if a short circuit occurs in the same layer, the high and low level signals of adjacent traces mix, causing the corresponding pixel unit to have abnormal brightness (such as both being bright or both being dark), thereby accurately identifying the short circuit location.

[0055] In some embodiments of this application, a plurality of pixel rows are provided in the display area 100, and the pixel rows and pixel columns are alternately arranged, with each pixel unit having at least two pixel rows.

[0056] It needs to be explained that pixel columns extend vertically (e.g., longitudinally) and are arranged in first order (e.g., RGBG color order). A portion of pixels from two adjacent columns (the nth column and the (n+1th column) form a pixel unit. Pixel rows extend horizontally (e.g., laterally) and intersect the pixel columns perpendicularly. Each pixel unit contains at least two rows of pixels (e.g., 2 rows, 3 rows, etc.). For example, a pixel unit can be composed of pixels from the first row of the nth column, the second row of the nth column, the first row of the (n+1th)th column, and the second row of the (n+1th)th column, forming a 2×2 pixel matrix unit.

[0057] Understandably, multiple rows of pixels within the same pixel unit are driven by the same set of first data traces 300 (e.g., the first data traces 300 of the nth column and the (n+1th)th column are respectively connected to specific signals), ensuring that the pixels in each row of the unit respond to the signals synchronously and avoiding brightness or color differences caused by row driving delays. For example, in a 2×2 pixel unit, both rows of pixels are connected to the same signal combination (e.g., D1 / D2), which can present a uniform brightness or color mode and improve image uniformity.

[0058] In some embodiments of this application, each pixel unit has two rows of pixels, and each pixel unit includes at least one red pixel 110, at least one green pixel 120 and at least one blue pixel 130.

[0059] It should be explained that each pixel unit is formed by the intersection of two adjacent pixel columns (the nth column and the (n+1th column) and two pixel rows (the kth row and the (k+1th row)), containing at least one red pixel 110 (R), one green pixel 120 (G), and one blue pixel 130 (B). For example, the kth row of the nth column contains the green pixel 120 (G), and the (k+1th row) of the nth column contains the red pixel 110 (R); the kth row of the (n+1th column) contains the blue pixel 130 (B), and the (k+1th row) of the (n+1th column) contains the green pixel 120 (G); forming the smallest display unit containing the three colors R, G, and B (such as the GR-GB combination). In the conductive layer of the non-display area 200, the first data trace 300 of the nth column drives the two rows of pixels (G, R) in the nth column, and the first data trace 300 of the (n+1th column) drives the two rows of pixels (B, G) in the (n+1th column). The first data trace 300 is arranged in a second order (e.g., odd and even columns are separated into conductive layers) to ensure that adjacent traces within the same conductive layer are connected to different short-circuit test signals (e.g., D1, D2).

[0060] Understandably, each pixel unit integrates R, G, and B color pixels, which can independently present complete colors to meet the requirements of full-color display. At the same time, the first data trace 300 of adjacent columns is connected to mutually exclusive short-circuit test signals (e.g., the nth column is connected to D1, and the (n+1)th column is connected to D2). When a short circuit occurs in the traces on the same layer, the pixels in both rows will exhibit abnormal colors or brightness due to signal mixing (e.g., G and R pixels are simultaneously bright / dark), ensuring that the detection signal covers the entire pixel unit and avoiding missed detections.

[0061] In some embodiments of this application, at least one of the nth pixel column and the (n+1)th pixel column includes a red pixel 110 and a blue pixel 130, and the other includes two green pixels 120. The red pixel 110, the blue pixel 130 and the two green pixels 120 are arranged adjacent to each other to form a pixel unit.

[0062] Please refer to the embodiments described in this application. Figure 7 and Figure 8 , Figure 7 A schematic diagram of the display panel provided in this embodiment is shown. Figure 8 A schematic diagram of the display panel provided in this embodiment is shown. Figure 7 The arrows in the diagram indicate the direction of changing the lines from the conventional reverse FIAA (GRGBBGGRGRBG) to the arrangement order (second order) in this embodiment. It can be seen that only a small portion of the data routing positions are needed, without having to change all the lines as with sequential FIAA. Therefore, the number of line changing structures can be reduced, thereby reducing the chin height.

[0063] like Figure 8 The pixel arrangement shown avoids the situation where adjacent first data traces 300 on the same layer are connected to the same short-circuit test signal. In this embodiment, the multiple pixel columns are arranged in the least repetition order, which is GRGBBGRGBGRG. GRGBBGRGBGRG is the arrangement order of pixels in multiple pixel rows; where G is green pixel 120, R is red pixel 110, and B is blue pixel 130.

[0064] It is understandable that by adopting the minimum repetition order arrangement in this application, there is no need to forcibly adjust the RGBG order of the pixel columns as in sequential FIAA. Instead, the GRGBBGRGBGRG reverse order is adapted simply by rearranging the traces within the conductive layer, avoiding the increase in chin height caused by multiple trace changes. Furthermore, in related technologies, the GRGBBGGRGRBG reverse order in FIAA faces the problem of adjacent first data traces 300 on the same layer receiving the same test signal. The GRGBBGRGBGRG reverse order in this application does not have this problem.

[0065] In some embodiments of this application, at least two pixel rows include a first pixel row and a second pixel row. The first pixel row is set closer to the area where the first data trace 300 is located than the second pixel row. GRGBBGRGBGRG represents the arrangement order of pixels in the second pixel row.

[0066] Understandably, in the second pixel row, the pixel columns are arranged in the smallest repeating order GRGBBGRGBGRG (G is green pixel 120, R is red pixel 110, B is blue pixel 130), specifically: G, R, G, B, B, G, R, G, B, G, R, G (a total of 12 columns, forming a periodic repeating unit).

[0067] In some embodiments, on the first pixel row, the pixel columns are arranged in the least repeating order GBGRRGBGRGBG.

[0068] In some embodiments, the conductive layer is made of a metallic material.

[0069] In some embodiments, the first data trace 300 is electrically connected to the pixels in the display area 100 via the second data trace 400.

[0070] It should be explained that a first data trace 300 is arranged in the non-display area 200, made of a metallic material (such as copper or aluminum), and is disposed in at least two conductive layers (such as layers M1 and M2) for transmitting image data signals from the driver chip. The first data trace 300 is arranged in a second order, which is at least partially different from the first order arrangement of the pixel columns in the display area 100, for example, by a cross-layer distribution of odd and even columns (odd columns in layer M1 and even columns in layer M2).

[0071] A second data trace 400 is provided within the display area 100 for ultimately transmitting signals to the pixel unit. The second data trace 400 is electrically connected to the first data trace 300 in the non-display area 200 through a via structure (such as a wire-changing hole). Specifically, the first data trace 300 penetrates the insulating dielectric layer through a via at the edge of the non-display area 200, forming a vertical conduction path with the second data trace 400 within the display area 100. The second data trace 400 extends along the pixel column direction and is directly connected to the thin-film transistor (TFT) of the pixel unit, driving the red (R), green (G), and blue (B) sub-pixels within the pixel to emit light.

[0072] In some embodiments, the first data trace 300 and its corresponding second data trace 400 are connected via a cable exchange hole located at the edge of the non-display area 200.

[0073] Furthermore, in order to better implement the display panel in any of the above embodiments, based on the above display panel, this application embodiment also provides a display device, including the display panel as described above.

[0074] In some embodiments, the display area 100 includes a light-transmitting display area, and at least a portion of the second data traces 400 are located in the light-transmitting display area. The display device also includes a photosensitive element, which is located on the display surface opposite to the light-transmitting display area of ​​the display panel. The photosensitive element can be an image acquisition device such as a camera, an optical fingerprint recognition module, an ambient light sensor, or other components capable of sensing light. Positioning the photosensitive element on the display surface opposite to the light-transmitting display area of ​​the display panel reduces the thickness of the display device. Furthermore, by appropriately adjusting the position of the photosensitive element and the corresponding trace arrangement of the display area 100, the display area 100 of the display panel can achieve higher light transmittance and a more suitable screen-to-body ratio.

[0075] In some embodiments, the display device further includes a driver chip electrically connected to the first data trace 300. The display area includes a first display area, a second display area, and an nth display area, and the plurality of first data traces 300 are respectively connected to the first display area, the second display area, and the nth display area.

[0076] Specifically, the driver chip can be electrically connected to the first data trace 300 corresponding to the first display area, the second display area, and the nth display area to output a drive signal to the first data trace 300 to drive the display panel to display.

[0077] In some embodiments, the display device may be a mobile phone, tablet, desktop computer, laptop computer, wearable device, automotive screen, sensor device, etc.

[0078] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0079] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0080] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0081] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0082] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area, the non-display area surrounding the display area, and the display area containing multiple pixel columns arranged in a first-order sequence; wherein, a portion of pixels from the nth pixel column and the (n+1)th pixel column combine to form a pixel unit, where n is a positive integer; the display panel includes: Multiple data traces, including multiple first data traces and multiple second data traces, wherein the multiple first data traces are disposed within at least two conductive layers in the non-display area, and the multiple second data traces are disposed in the display area and used to connect the pixel column; the multiple first data traces and the multiple second data traces are electrically connected in a one-to-one correspondence; wherein the multiple first data traces are arranged in a second order, and the second order is at least partially different from the first order; Wherein, the first data trace is used to access at least two short-circuit test signals during the screen testing phase of the display panel, and different short-circuit test signals are used to drive two adjacent pixel units in the first sequence respectively, and in the second sequence of the plurality of first data traces, two adjacent first data traces in the same conductive layer are used to access different short-circuit test signals.

2. The display panel according to claim 1, characterized in that, In the second sequence, two adjacent first data traces are located in different conductive layers.

3. The display panel according to claim 2, characterized in that, The at least two conductive layers include a first conductive layer and a second conductive layer, with the first data trace of the odd-numbered column disposed on the first conductive layer and the first data trace of the even-numbered column disposed on the second conductive layer.

4. The display panel according to claim 1, characterized in that, The at least two short-circuit test signals include a first signal and a second signal. The first signal is used to drive the m-th pixel unit, and the second signal is used to drive the (m+1)-th pixel unit, where m is a positive integer. One of the first signal and the second signal is a high-level signal, and the other is a low-level signal.

5. The display panel according to claim 1, characterized in that, The display area has multiple pixel rows, which are staggered with the pixel columns. Each pixel unit has at least two pixel rows.

6. The display panel according to claim 5, characterized in that, Each pixel unit has two rows of pixels, and each pixel unit includes at least one red pixel, at least one green pixel, and at least one blue pixel.

7. The display panel according to claim 6, characterized in that, At least one of the nth pixel column and the (n+1)th pixel column includes a red pixel and a blue pixel, and the other includes two green pixels. The red pixel, the blue pixel, and the two green pixels are arranged adjacent to each other to form a pixel unit.

8. The display panel according to claim 5, characterized in that, The multiple pixel columns are arranged in the least repetition order, which is GRGBBGRGBGRG, where GRGBBGRGBGRG is the arrangement order of pixels in the multiple pixel rows; wherein G represents green pixels, R represents red pixels, and B represents blue pixels.

9. The display panel according to claim 8, characterized in that, The at least two pixel rows include a first pixel row and a second pixel row. The first pixel row is set closer to the area where the first data trace is located than the second pixel row. GRGBBGRGBGRG is the arrangement order of pixels in the second pixel row.

10. The display panel according to claim 9, characterized in that, The first data trace and its corresponding second data trace are connected through a switching hole located at the edge of the non-display area.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 10.

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