Scan driving circuit and display device

Abstract

The application discloses a scanning driving circuit and a display device. The circuit comprises a plurality of cascaded shift registers; the shift register comprises: a stage transmission control module, which is used for controlling the potential of a first output end and a second output end according to an input signal; a stage transmission output module, which is used for providing a first clock signal or a first potential signal to an output end of the stage transmission output module in response to the potential of the first output end and the second output end; a frequency control module, a first connection end of which is connected to the second output end, an input end of which is connected to a frequency control signal, and a control end of which is connected to the output end of the stage transmission output module; and a scanning output module, which is used for outputting the first clock signal or the first potential signal to an output end of the scanning output module in response to the potential of a second connection end and the first output end. The coupling voltage generated by the potential jump of the first clock signal acts on the stage transmission output module or the scanning output module, so that the stage transmission output module and the scanning output module are more fully opened, and the display unevenness problem caused by the step voltage is solved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to scanning drive circuits and display devices. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is developing rapidly, and the demand for power reduction in the end market is growing stronger. By reducing the frequency of non-critical display areas according to user scenarios, power consumption can be reduced without affecting the user experience. This is a new technological direction driving OLED displays, and therefore, multi-frequency partitioning technology is particularly important.

[0003] However, existing display panels are prone to uneven display when performing multi-frequency display in different zones, which is detrimental to the display. Summary of the Invention

[0004] This invention provides a scanning drive circuit and a display device to solve the problem of uneven display when displaying multiple frequencies in different zones, thereby improving the display effect.

[0005] According to one aspect of the present invention, a scan driving circuit is provided, comprising: a plurality of cascaded shift registers;

[0006] The shift register includes:

[0007] A cascade control module is used to control the potential of the first and second output terminals of the cascade control module according to the input signal connected to the input terminal of the shift register.

[0008] A stage output module is connected to the first output terminal and the second output terminal respectively, and is used to provide a first clock signal or a first potential signal to the output terminal of the stage output module in response to the potential of the first output terminal and the second output terminal; the output terminal of the stage output module is connected to the input terminal of the next stage shift register.

[0009] A frequency switching control module, wherein the first connection terminal of the frequency switching control module is connected to the second output terminal, the input terminal of the frequency switching control module is connected to a frequency control signal, and the control terminal of the frequency switching control module is connected to the output terminal of the stage transmission output module;

[0010] The scanning output module is connected to the second connection terminal and the first output terminal of the frequency switching control module, respectively, and is used to output the first clock signal or the first potential signal to the output terminal of the scanning output module in response to the potential of the second connection terminal and the first output terminal; the frequency switching control module is used to control the potential of the second connection terminal according to the stage transmission signal output by the stage transmission output module and the frequency control signal, so as to control the frequency of the scanning signal output by the scanning output module.

[0011] Optionally, the frequency switching control module includes:

[0012] An output control unit, connected between the first connection terminal and the second connection terminal, is used to control whether to connect the first connection terminal and the second connection terminal according to the potential of the control terminal of the output control unit;

[0013] A first isolation unit is connected to the output terminal of the stage transmission module. A first terminal of the first isolation unit receives the frequency control signal, and a second terminal of the first isolation unit is connected to the control terminal of the output control unit. The first isolation unit is used to respond to the stage transmission signal and cut off the transmission path of the frequency control signal to the control terminal of the output control unit.

[0014] Optionally, the output control unit includes a first transistor, the first terminal of the first transistor is connected to the first connection terminal, the second terminal of the first transistor is connected to the second connection terminal, and the gate of the first transistor is connected to the second terminal of the first isolation unit;

[0015] The first isolation unit includes a second transistor, the first terminal of the second transistor is connected to the frequency control signal, the second terminal of the second transistor is connected to the control terminal of the output control unit, and the gate of the second transistor is connected to the output terminal of the stage transmission module.

[0016] Optionally, the scan output module includes: a second isolation unit and a down-frequency output unit;

[0017] The first end of the second isolation unit is connected to the control terminal of the output control unit, and the second end of the second isolation unit is connected to the control terminal of the down-frequency output unit. The second isolation unit is used to isolate the control terminal of the output control unit and the control terminal of the down-frequency output unit.

[0018] The first terminal of the frequency reduction output unit is connected to a second potential signal, and the second terminal of the frequency reduction output unit is connected to the output terminal of the scan output module. The frequency reduction output unit is used to turn on or off according to the potential of the control terminal of the output control unit, and the on / off state of the frequency reduction output unit is different from the on / off state of the output control unit. The potential of the second potential signal is the same as the potential of the first potential signal. The first potential signal is the cutoff potential of the scan signal, and the cutoff potential is the potential for controlling the functional module connected to the scan signal to turn off.

[0019] Optionally, the first potential signal and the second potential signal are provided by different ports of the power supply chip that provides the first potential signal and the second potential signal;

[0020] Optionally, the second isolation unit includes a third transistor and a first capacitor. The first terminal of the third transistor is connected to the control terminal of the output control unit, the second terminal of the third transistor is connected to the control terminal of the down-frequency output unit, and the gate of the third transistor is connected to the first potential signal.

[0021] The first terminal of the first capacitor is connected to the first potential signal, and the second terminal of the first capacitor is connected to the control terminal of the frequency reduction output unit.

[0022] Optionally, the frequency reduction output unit includes a fourth transistor, the first terminal of the fourth transistor is connected to the second potential signal, the second terminal of the fourth transistor is connected to the output terminal of the scan output module, and the gate of the fourth transistor is connected to the second terminal of the second isolation unit.

[0023] Optionally, the first control terminal of the scanning output module is connected to the first output terminal, and the second control terminal of the scanning output module is connected to the second connection terminal;

[0024] The scan drive circuit further includes a scan control module, which is connected to the second control terminal of the scan output module. The scan control module is used to transmit the first clock signal to the second control terminal of the scan output module in response to the potential of the first output terminal.

[0025] Optionally, the scan control module includes a fifth transistor, the first terminal of which is connected to the first clock signal, the second terminal of which is connected to the second connection terminal, and the gate of which is connected to the first output terminal.

[0026] Optionally, the scan output module includes:

[0027] The first output unit has a control terminal connected to the first output terminal and is used to transmit the first potential signal to the output terminal of the scanning output module in response to the potential of the first output terminal.

[0028] The second output unit, whose control terminal is connected to the second connection terminal, is used to transmit the first clock signal to the output terminal of the scan output module in response to the potential of the second connection terminal.

[0029] Optionally, the first output unit includes a sixth transistor, a seventh transistor, and a second capacitor. The first terminal of the sixth transistor is connected to the first potential signal, the second terminal of the sixth transistor is connected to the output terminal of the scan output module, and the gate of the sixth transistor is connected to the first output terminal.

[0030] The first terminal of the seventh transistor is connected to the second clock signal, the second terminal of the seventh transistor is connected to the first terminal of the second capacitor, the gate of the seventh transistor is connected to the first output terminal, and the second terminal of the second capacitor is connected to the first output terminal.

[0031] Optionally, the second output unit includes an eighth transistor and a third capacitor. The first terminal of the eighth transistor is connected to the first clock signal, the second terminal of the eighth transistor is connected to the output terminal of the scan output module, the gate of the eighth transistor is connected to the second connection terminal, the first terminal of the third capacitor is connected to the first clock signal, and the second terminal of the third capacitor is connected to the second connection terminal.

[0032] Optionally, the operation of the display panel where the scanning driving circuit is located includes a display stage and a non-display stage. The scanning output module further includes a first test unit, which is connected to the control terminal of the second output unit. The first test unit is used to turn off in response to a reset signal in the display stage and to turn on in response to the reset signal in the non-display stage, so as to transmit the first potential signal to the control terminal of the second output unit.

[0033] The first test unit includes a ninth transistor, the first terminal of the ninth transistor is connected to the first potential signal, the second terminal of the ninth transistor is connected to the control terminal of the second output unit, and the gate of the ninth transistor is connected to the reset signal;

[0034] Optionally, the scanning output module further includes a first protection unit, a first end of which is connected to the first output end, a second end of which is connected to the control end of the first output unit, and the control end of the first protection unit is connected to the first potential signal.

[0035] The first protection unit includes a tenth transistor, the first terminal of which is connected to the first output terminal, the second terminal of which is connected to the control terminal of the first output unit, and the gate of which is connected to the first potential signal.

[0036] Optionally, the stage transmission output module includes:

[0037] The third output unit, whose control terminal is connected to the first output terminal, is used to respond to the potential of the first output terminal and transmit the first potential signal to the output terminal of the stage transmission module.

[0038] The fourth output unit, whose control terminal is connected to the second output terminal, is used to transmit the first clock signal to the output terminal of the stage transmission module in response to the potential of the second output terminal.

[0039] Optionally, the third output unit includes an eleventh transistor, a twelfth transistor, and a fourth capacitor. The first terminal of the eleventh transistor is connected to the first potential signal, the second terminal of the eleventh transistor is connected to the output terminal of the stage transmission module, and the gate of the eleventh transistor is connected to the first output terminal.

[0040] The first terminal of the twelfth transistor is connected to the second clock signal, the second terminal of the twelfth transistor is connected to the first terminal of the fourth capacitor, the gate of the twelfth transistor is connected to the first output terminal, and the second terminal of the fourth capacitor is connected to the first output terminal.

[0041] Optionally, the fourth output unit includes a thirteenth transistor and a fifth capacitor. The first terminal of the thirteenth transistor is connected to the first clock signal, the second terminal of the thirteenth transistor is connected to the output terminal of the stage transmission module, the gate of the thirteenth transistor is connected to the second output terminal, the first terminal of the fifth capacitor is connected to the first clock signal, and the second terminal of the fifth capacitor is connected to the second output terminal.

[0042] Optionally, the operation of the display panel where the scanning driving circuit is located includes a display stage and a non-display stage. The level transmission output module further includes a second test unit, which is connected to the control terminal of the fourth output unit. The second test unit is used to turn off in response to a reset signal during the display stage and to turn on in response to the reset signal during the non-display stage, so as to transmit the first potential signal to the control terminal of the fourth output unit.

[0043] The second test unit includes a fourteenth transistor, the first terminal of which is connected to the first potential signal, the second terminal of which is connected to the control terminal of the fourth output unit, and the gate of which is connected to the reset signal.

[0044] Optionally, the cascade control module includes:

[0045] The first input unit is connected to the first output terminal and is used to transmit the input signal to the first output terminal in response to the first clock signal.

[0046] The second input unit has a first terminal connected to the first potential signal, which is used to transmit the first potential signal to the second terminal of the second input unit in response to the first clock signal.

[0047] A control unit is connected between the second terminal of the second input unit and the second output terminal, and is used to control the potential of the second output terminal according to the second clock signal and the potential of the second terminal of the second input unit;

[0048] The first node control unit is connected to the second terminal of the second input unit and is used to transmit the first clock signal to the second terminal of the second input unit in response to the potential of the first output terminal.

[0049] The second node control unit is connected to the second output terminal and is used to transmit the first clock signal to the second output terminal in response to the potential of the first output terminal.

[0050] Optionally, the transmission control module further includes a second protection unit, the first end of which is connected to the first input unit, the second end of which is connected to the first output unit, and the control end of which is connected to the first potential signal.

[0051] The second protection unit includes a fifteenth transistor, the first terminal of which is connected to the first input unit, the second terminal of which is connected to the first output terminal, and the gate of which is connected to the first potential signal.

[0052] Optionally, the transmission control module further includes a third protection unit, the first end of which is connected to the second end of the second input unit, the second end of which is connected to the control unit, and the control end of which is connected to the first potential signal;

[0053] The third protection unit includes a sixteenth transistor, the first terminal of which is connected to the second terminal of the second input unit, the second terminal of which is connected to the control unit, and the gate of which is connected to the first potential signal.

[0054] Optionally, the first input unit includes a seventeenth transistor, the first terminal of the seventeenth transistor is connected to the input signal, the second terminal of the seventeenth transistor is connected to the first output terminal, and the gate of the seventeenth transistor is connected to the first clock signal;

[0055] Optionally, the second input unit further includes an eighteenth transistor, the first terminal of which is connected to the first potential signal, the second terminal of which is connected to the control unit, and the gate of which is connected to the first clock signal;

[0056] Optionally, the control unit includes a nineteenth transistor, a sixth capacitor, and a twentieth transistor. The first terminal of the nineteenth transistor is connected to a second clock signal, the second terminal of the nineteenth transistor is connected to the first terminal of the twentieth transistor, the gate of the nineteenth transistor is connected to the second terminal of the second input unit, the second terminal of the twentieth transistor is connected to the second output terminal, the gate of the twentieth transistor is connected to the second clock signal, the first terminal of the sixth capacitor is connected to the second terminal of the second input unit, and the second terminal of the sixth capacitor is connected to the first terminal of the twentieth transistor.

[0057] Optionally, the first node control unit includes a twenty-first transistor, the first terminal of the twenty-first transistor is connected to the first clock signal, the second terminal of the twenty-first transistor is connected to the second terminal of the second input unit, and the gate of the twenty-first transistor is connected to the first output terminal;

[0058] Optionally, the second node control unit includes a twenty-second transistor, the first terminal of the twenty-second transistor is connected to the first clock signal, the second terminal of the twenty-second transistor is connected to the second output terminal, and the gate of the twenty-second transistor is connected to the first output terminal;

[0059] Optionally, the operation of the display panel where the scanning driving circuit is located includes a display stage and a non-display stage. The transmission control module further includes a third test unit, which is connected to the first output terminal. The third test unit is used to turn off in response to a reset signal in the display stage and to turn on in response to the reset signal in the non-display stage, so as to transmit the first potential signal to the first output terminal.

[0060] The third test unit includes a 23rd transistor, the first terminal of the 23rd transistor is connected to the first clock signal, the second terminal of the 23rd transistor is connected to the first output terminal, and the gate of the 23rd transistor is connected to the reset signal.

[0061] Optionally, the input terminals of the frequency switching control modules in each of the shift registers are connected to the same frequency control signal;

[0062] The frequency control signal maintains a constant potential in some display frames and undergoes potential jumps in some display frames, so that the frequencies of the scan signals output by at least two shift registers are different;

[0063] When the scan signal output by the shift register at this stage does not require an output pulse, the potential transition time of the frequency control signal is located before the pulse of the transmission signal output by the shift register at this stage.

[0064] According to another aspect of the present invention, a display device is also provided, comprising: a pixel circuit and at least one scanning driving circuit as described in any of the preceding claims.

[0065] Optionally, the display device further includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, wherein the start pulses of the signals transmitted by the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are output sequentially; the shift register includes a first clock signal terminal and a second clock signal terminal, wherein the first clock signal terminal is used to provide a first clock signal, and the second clock signal terminal is used to provide a second clock signal;

[0066] The first clock signal terminal of the 4k+1 level shift register is connected to the first clock signal line, and the second clock signal terminal of the 4k+1 level shift register is connected to the second clock signal line;

[0067] The first clock signal terminal of the 4k+2 level shift register is connected to the second clock signal line, and the second clock signal terminal of the 4k+2 level shift register is connected to the third clock signal line;

[0068] The first clock signal terminal of the 4k+3 level shift register is connected to the third clock signal line, and the second clock signal terminal of the 4k+3 level shift register is connected to the fourth clock signal line;

[0069] The first clock signal terminal of the 4k+4th stage shift register is connected to the fourth clock signal line, and the second clock signal terminal of the 4k+4th stage shift register is connected to the first clock signal line; K is an integer greater than or equal to 0;

[0070] Optionally, each shift register is connected to two rows of pixel circuits, and the functional modules in the two rows of pixel circuits that are connected to the shift registers are the same.

[0071] The technical solution of this invention uses a cascade control module to control the output of cascade signals from the cascade output modules, which are then used as inputs to the next-level shift registers. The pulse frequencies of the cascade signals output by each shift register are identical, ensuring that even if the pulse frequency of the scan signal output by the current-level shift register changes, it will not affect the output of the scan signal by the next-level shift register. A frequency-switching control module controls the frequency of the scan signal output by the scan output module to achieve multi-frequency display in zones. Simultaneously, both the cascade output modules that output cascade signals and the scan output modules that output scan signals are connected to a first clock signal. This first clock signal exhibits high and low potential transitions, causing voltage coupling through these transitions to the control terminals of the cascade output modules and the scan output modules. This allows the cascade output modules or scan output modules to be fully opened, enabling the complete output of the potential on the first clock signal to the output terminals of either the cascade output modules or the scan output modules. This results in a smooth waveform for the scan signal, resolving the problem of uneven display caused by voltage steps and improving the display effect.

[0072] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 This is a schematic diagram of the structure of a shift register;

[0075] Figure 2 The waveform of the scan signal output by the shift register;

[0076] Figure 3 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention;

[0077] Figure 4 A driving timing diagram for a display panel provided in an embodiment of the present invention;

[0078] Figure 5This is a schematic diagram of a shift register provided in an embodiment of the present invention;

[0079] Figure 6 This is a potential waveform diagram of the control terminal of a down-frequency output unit when a scanning drive circuit does not have a second isolation unit.

[0080] Figure 7 The potential waveform diagram of the control terminal of the down-frequency output unit in the scanning drive circuit provided in the embodiment of the present invention;

[0081] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0082] Figure 9 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0083] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0084] Figure 11 A driving timing diagram of a display device provided in an embodiment of the present invention;

[0085] Figures 12-19 These are working state diagrams of the shift register operating in the first to eighth stages of the first working mode, as provided in the embodiments of the present invention.

[0086] Figure 20 This is a driving timing diagram for another display device provided in an embodiment of the present invention;

[0087] Figure 21 This is a working state diagram of a shift register operating in a second working mode, provided as an embodiment of the present invention. Detailed Implementation

[0088] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0089] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0090] As described in the background section, display devices capable of multi-frequency display in partitions suffer from uneven display. The inventors discovered that this is due to a voltage step in the scanning signal generated by the scanning drive circuit, which affects the screen's display performance. Specifically, Figure 1 This is a schematic diagram of a shift register. Figure 2 The waveform of the scan signal output by the shift register is shown in the reference diagram. Figure 1 and Figure 2 , Figure 1 The diagram only shows, by way of example, the input transistor M0, the first output transistor M1, the second output transistor M2, the third output transistor M3, and the fourth output transistor M4 in the shift register. All five transistors are PMOS transistors. The first output transistor M1 and the third output transistor M3 are both connected to the first potential signal VGL1, and the second output transistor M2 and the fourth output transistor M4 are both connected to the third potential signal VGH. The first potential signal VGL1 and the third potential signal VGH are high and low potentials of each other. The input transistor M0 turns on in response to the first potential signal VGL1 of the first clock signal SCK1 to transmit the first potential signal VGL1 in the input signal SIN to node A. However, because the gate and source potentials of the input transistor M0 are the same, the input transistor M0 is not fully turned on, resulting in the potential VA written to node A being VA = VGL1 + |Vth0|, where Vth0 is the threshold voltage of the input transistor M0. The first output transistor M1 is not fully turned on, resulting in a step voltage b in the output transmission signal Carry, where step voltage b = VGL1 + |Vth0| + |Vth1|, where Vth1 is the threshold voltage of the first output transistor M1. Similarly, the scan signal OUT also has a step voltage. The threshold voltage of the transistor changes due to the influence of light, temperature, etc., making the step voltage unstable and causing uneven display.

[0091] To address the aforementioned technical problems, embodiments of the present invention provide a scanning drive circuit that uses the coupling voltage generated by the potential jump of the first clock signal to act on the stage transmission output module or the scanning output module, thereby enabling both to be fully opened and directly outputting the first potential signal, avoiding the existence of step voltage, and solving the problem of uneven display caused by the existence of step voltage.

[0092] Figure 3 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention, with reference to... Figure 3 The scan drive circuit includes: multiple cascaded shift registers 1;

[0093] Shift register 1 includes:

[0094] The cascade control module 11 is used to control the potential of the first output terminal N1 and the second output terminal N2 of the cascade control module 11 according to the input signal connected to the input terminal of the shift register 1.

[0095] The stage output module 12 is connected to the first output terminal N1 and the second output terminal N2 respectively, and is used to respond to the potential of the first output terminal N1 and the second output terminal N2 to provide the first clock signal SCK1 or the first potential signal VGL1 to the output terminal of the stage output module 12; the output terminal of the stage output module 12 is connected to the input terminal of the next stage shift register.

[0096] Frequency switching control module 13, the first connection terminal Q1 of frequency switching control module 13 is connected to the second output terminal N2, the input terminal of frequency switching control module 13 is connected to the frequency control signal SW, and the control terminal of frequency switching control module 13 is connected to the output terminal of stage transmission output module 12;

[0097] The scan output module 14 is connected to the second connection terminal Q2 and the first output terminal N1 of the frequency switching control module 13, respectively. It responds to the potentials of the second connection terminal Q2 and the first output terminal N1 by outputting either the first clock signal SCK1 or the first potential signal VGL1 to the output terminal of the scan output module 14. The frequency switching control module 13 controls the potential of the second connection terminal Q2 based on the stage transmission signal output by the stage transmission output module 12 and the frequency control signal SW, thereby controlling the frequency of the scan signal output from the output terminal of the scan output module 14.

[0098] This embodiment exemplifies a cascaded first-stage shift register 1-1 and a second-stage shift register 1-2. The input of the first-stage shift register 1-1 is connected to the first-stage input signal SIN1. The shift signal output by the first-stage shift register 1-1 is denoted as the first-stage shift signal Carry1, and is used as the input signal to the second-stage shift register 1-2. The input signal to the second-stage shift register 1-2 is denoted as the second-stage input signal SIN2. The scan signal output by the first-stage shift register 1-1 is denoted as the first-stage scan signal OUT1, and is output to the pixel row connected to the first-stage shift register 1-1. The scan signal output by the second-stage shift register 1-2 is denoted as the second-stage scan signal OUT2, and is output to the pixel row connected to the second-stage shift register 1-2, and so on.

[0099] In this embodiment, both the intermediate transmission output module 12 and the scan output module 14 can be considered as switching modules, each including two control terminals. The first control terminal of the intermediate transmission output module 12 can be connected to the first output terminal N1, and in response to the potential of the first output terminal N1, the first potential signal VGL1 is connected to the output terminal of the intermediate transmission output module 12. The second control terminal is connected to the second output terminal N2, and in response to the potential of the second output terminal N2, the first clock signal SCK1 is connected to the output terminal of the intermediate transmission output module 12, thereby realizing the transmission of the first potential signal VGL1 or the first clock signal SCK1 to the output terminal of the intermediate transmission output module 12 to form an intermediate transmission signal. The scan output module 14 also includes two control terminals. The first control terminal is connected to the first output terminal N1, and in response to the potential of the first output terminal N1, the scan output module 14 connects the first potential signal VGL1 to the output terminal of the scan output module 14. The second control terminal of the scan output module 14 is connected to the second connection terminal Q2, and in response to the potential of the second connection terminal Q2, the first clock signal SCK1 is connected to the output terminal of the scan output module 14. In one optional implementation, taking the N-type transistor as an example, the transistor included in the functional module of the pixel circuit connected to the scan output module 14 is an N-type transistor. The on-state potential of the scan signal is high and the off-state potential is low. In this embodiment, the first potential signal VGL is low and the first clock signal SCK1 includes a pulse with a high potential. The scan output module 14 responds to the potential of its two control terminals by alternately outputting the first potential signal VGL1 and the first clock signal SCK1 to form a scan signal including low and high potentials. The same applies to the stage transmission output module 12, which will not be described in detail here.

[0100] For the stage transmission output module 12, the two output terminals of the stage transmission control module 11 can be connected to the two control terminals of the stage transmission output module 12 respectively, so that the stage transmission control module 11 controls the stage transmission output module 12 to output the stage transmission signal by controlling the potential of the first output terminal N1 and the second output terminal N2. For example, the first output terminal N1 can be connected to the first control terminal of the stage transmission output module 12, and the second output terminal N2 can be connected to the second control terminal of the stage transmission output module 12. Based on the potential control of the first output terminal N1 and the second output terminal N2 by the stage transmission control module 11, the stage transmission output module 12 can realize the shifted output of the input signal conduction pulse. The potential of the conduction pulse of the input signal is the same as the conduction potential of the scanning signal.

[0101] Each shift register 1 is cascaded through the stage output module 12, enabling the step-by-step shifting and output of the conduction pulse of the first-stage input signal SIN1. This provides a high-frequency cascaded signal sequence with the same frequency as the first-stage input signal SIN1, providing conditions for each stage scan output module 14 to select whether to output the conduction pulse based on the frequency cutting control module 13. The frequency of the first-stage input signal SIN1 can be understood as the pulse frequency of its conduction pulse.

[0102] The second connection terminal Q2 of the frequency switching control module 13 can be connected to the second control terminal of the scan output module 14, so that the frequency switching control module 13 controls whether the scan output module 14 outputs the on-state potential of the scan signal by controlling the potential of the second connection terminal Q2. The two output terminals of the transmission control module 11 can be connected to the first connection terminal Q1 of the frequency switching control module 13 and the first control terminal of the scan output module 14, respectively.

[0103] Frequency switching control module 13 can control the scanning output module 14 to operate in the following two modes:

[0104] In the first operating mode, during the stage where the stage transmission output module 12 outputs the conduction potential, the frequency switching control module 13 remains on. Then, the potential of the second output terminal N2 can be transmitted to the second connection terminal Q2, which can control the scan output module 14 to output the first clock signal SCK1. At this time, the first clock signal SCK1 outputs the conduction potential, so that both the stage transmission signal and the scan signal have conduction pulses.

[0105] In the second operating mode, during the stage where the stage transmission output module 12 outputs the on-state potential, the frequency switching control module 13 remains off, preventing the potential of the second output terminal N2 from being transmitted to the second connection terminal Q2. Therefore, the scan output module 14 cannot be controlled to output the on-state potential transmitted by the first clock signal SCK1 at this time. The scan signal of this stage remains at the off-state potential and will not jump to the on-state potential. Thus, only the stage transmission signal contains on-state pulses, while the scan signal does not.

[0106] When a certain stage of the shift register 1 operates in the first operation mode in every display frame, the frequency of the stage transmission signal output by the shift register 1 is the same as the frequency of the scan signal; when a certain stage of the shift register 1 operates in the second operation mode in at least part of the display frames, the frequency of the scan signal output by the shift register 1 is lower than the frequency of the stage transmission signal output by the shift register 1.

[0107] Exemplarily, for any scan signal, the scan signal is transmitted through a signal line to the functional module related to the data writing process in the pixel circuit of the corresponding row. When a certain stage of the shift register 1 operates in the first operation mode, since the scan signal includes a turn-on pulse, the pixel circuit of the corresponding row can be controlled to perform data writing, so that the current frame of the pixel circuit of this row is a refresh frame; and when a certain stage of the shift register 1 operates in the second operation mode, since the scan signal does not include a turn-on pulse, the pixel circuit of the corresponding row cannot perform data writing, so that the current frame of the pixel circuit of this row is a hold frame. Therefore, the frequency of the scan signal determines the data refresh frequency of the pixel circuit. Based on this, the frequency of each stage of scan signal can be controlled by controlling the operation mode of each stage of the shift register 1 in each display frame, and by controlling the frequencies of at least two stages of scan signals to be different, the display device can realize partitioned and frequency-divided display in the column direction.

[0108] Figure 4 is a driving timing diagram of a display panel provided by an embodiment of the present invention, Figure 4 taking a three-split screen as an example, the display panel includes a first display area A1, a second display area A2 and a third display area A3 arranged along the column direction, and the refresh frequencies of the three display areas are, for example, f1, f2 and f1 in sequence, where f1<f2. Exemplarily, f1 may be 60Hz, and f2 may be 120Hz. Taking that each display area corresponds to three stages of shift registers as an example, Figure 4 shows the first stage scan signal OUT1 output by the first stage shift register to the ninth stage scan signal OUT9 output by the ninth stage shift register, and the first stage shift signal Carry1 output by the first stage shift register to the ninth stage shift signal Carry9 output by the ninth stage shift register. The fourth to sixth stage shift registers corresponding to the second display area A2 are set to operate in the first operation mode in every display frame, that is, the scan signal output in each display frame all includes a turn-on pulse, and the first to third stage shift registers corresponding to the first display area A1 and the seventh to ninth stage shift registers corresponding to the third display area A3 operate in the first operation mode in part of the display frames, and operate in the second operation mode in part of the display frames. In the display frames where the shift registers operate in the second operation mode, the scan signals output by the shift registers do not include a turn-on pulse.

[0109] The frequency switching control module 13 includes an intermediate node. It controls whether the frequency control signal SW can be transmitted to the intermediate node via a cascaded signal, and further controls whether the first connection terminal Q1 and the second connection terminal Q2 are connected via the potential of the intermediate node. For example, when the cascaded signal is at a conducting potential, the input terminal of the frequency switching control module 13 is disconnected from the intermediate node, preventing the frequency control signal SW from being transmitted to the intermediate node; when the cascaded signal is at a cutoff potential, the frequency control signal SW can be transmitted to the intermediate node. Furthermore, when the intermediate node is at one of high or low potentials, the first connection terminal Q1 and the second connection terminal Q2 are connected; when the intermediate node is at the other potential, the first connection terminal Q1 and the second connection terminal Q2 are disconnected. Therefore, during the phase when the cascaded signal remains at a conducting potential, since the input terminal of the frequency switching control module 13 remains disconnected from the intermediate node, the potential change of the frequency control signal SW during this phase is not transmitted to the intermediate node. The intermediate node maintains the potential provided by the frequency control signal SW before the cascaded signal transitions to a conducting potential. Therefore, in order to control the working mode of shift register 1 at this stage, the frequency control signal needs to be converted to the potential required by the intermediate node before the output conduction potential of the cascade signal at this stage.

[0110] like Figure 4 As shown, in display frame F2, the frequency control signal SW jumps to a high level before the first-stage transmission signal Carry1 outputs a high level. This high level can be transmitted to the intermediate node of the frequency switching control module 13 of the first-stage shift register. After the first-stage transmission signal Carry1 outputs a high level, the input terminal of the frequency switching control module 13 of the first-stage shift register is disconnected from the intermediate node, which remains at a high level. This disconnects the first connection terminal Q1 and the second connection terminal Q2 in the first-stage shift register, and the first-stage shift register operates in the second operating mode. The output terminal of the shift output module 14 does not output a high level. Correspondingly, the frequency control signal SW jumps to a low level before the fourth-stage transmission signal Carry4 outputs a high level. This low level can be transmitted to the intermediate node of the frequency switching control module 13 of the fourth-stage shift register. However, since the input terminal of the frequency switching control module 13 of the first-stage shift register is still disconnected from the intermediate node under the control of the first-stage transmission signal Carry1, this low level will not be transmitted to the intermediate node of the frequency switching control module 13 of the first-stage shift register. After the fourth-stage shift register outputs a high-level signal (Carry4), the input of the frequency switching control module 13 of the fourth-stage shift register is disconnected from the intermediate node, which remains at a low level. This connects the first connection terminal Q1 and the second connection terminal Q2 in the fourth-stage shift register, putting the fourth-stage shift register into its first operating mode. The output of the scan output module 14 can then output a high-level pulse. The operating principle of the seventh-stage shift register in its second operating mode is the same as that of the first-stage shift register and will not be described further here.

[0111] In this embodiment, the input terminals of both the scan output module 14 and the stage transmission output module 12 are connected to the first clock signal. Taking the scan output module 14 as an example, the scan output module 14 outputs the first clock signal SCK1 in response to either a high or low potential of the second connection terminal Q2, and outputs the first potential signal VGL1 in response to either a high or low potential of the first output terminal N1. In this embodiment, the first clock signal SCK1 is output in response to a low potential of the second connection terminal Q2, and the first potential signal VGL1 is output in response to a low potential of the first output terminal N1. In the first operating mode, when the output potential of the transmission signal or scan signal jumps from the on-state potential to the off-state potential, the first clock signal SCK1 also undergoes a potential jump from a high potential to a low potential. Due to the presence of parasitic capacitance, the potential jump at the input terminal of the scan output module 14 affects the potential at the control terminal connected to the second connection terminal Q2 in the scan output module 14, pulling down the potential at the control terminal connected to the second connection terminal Q2. This results in the gate potential of the transistor connecting the first clock signal SCK1 and the output terminal of the scan output module 14 being lower than the source potential, allowing the transistor to be turned on more fully to output the low potential of the first clock signal SCK1, ensuring that there is no step voltage when the scan signal jumps from a high potential to a low potential.

[0112] The technical solution of this invention uses a cascade control module to control the output of cascade signals from the cascade output modules, which are then used as inputs to the next-level shift registers. The pulse frequencies of the cascade signals output by each shift register are identical, ensuring that even if the pulse frequency of the scan signal output by the current-level shift register changes, it will not affect the output of the scan signal by the next-level shift register. A frequency-switching control module controls the frequency of the scan signal output by the scan output module to achieve multi-frequency display in zones. Simultaneously, both the cascade output modules that output cascade signals and the scan output modules that output scan signals are connected to a first clock signal. This first clock signal exhibits high and low potential transitions, causing voltage coupling through these transitions to the control terminals of the cascade output modules and the scan output modules. This allows the cascade output modules or scan output modules to be fully opened, enabling the complete output of the potential on the first clock signal to the output terminals of either the cascade output modules or the scan output modules. This results in a smooth waveform for the scan signal, resolving the problem of uneven display caused by voltage steps and improving the display effect.

[0113] Figure 5 This is a schematic diagram of a shift register provided in an embodiment of the present invention, with reference to... Figure 5 The frequency switching control module 13 includes:

[0114] The output control unit 131 is connected between the first connection terminal Q1 and the second connection terminal Q2, and is used to control whether to connect the first connection terminal Q1 and the second connection terminal Q2 according to the potential of the control terminal of the output control unit 131.

[0115] The scan output module 14 includes a first control terminal and a second control terminal. The first control terminal of the scan output module 14 is connected to the first output terminal N1, and the second control terminal of the scan output module 14 is connected to the second connection terminal Q2. The output control unit 131 is a switching unit that responds to the potential of its own control terminal to turn on or off. When on, it connects the first connection terminal Q1 and the second connection terminal Q2 to transmit the potential of the first connection terminal Q1 to the second control terminal of the scan output module 14, and when off, it disconnects the first connection terminal Q1 and the second connection terminal Q2. When the scan signal corresponding to the current shift register does not need to be down-frequency reduced, when the output potential of the stage transmission signal of the current shift register is high, the potential output of the corresponding first clock signal SCK1 is also high. The output control unit 131 responds to the potential of its own control terminal to turn on, connecting the first connection terminal Q1 and the second connection terminal Q2, thereby transmitting the potential output of the second output terminal N2 to the scan output module 14, so that the scan output module 14 responds to the potential of its own second control terminal to output the on-state potential of the first clock signal SCK1. When the scan signal corresponding to the shift register at this stage needs to be down-frequency, when the output of the stage transmission signal output by the shift register at this stage is at a high potential, the output control unit 131 responds to the potential turn-off of its own control terminal to cut off the potential between the first connection terminal Q1 and the second connection terminal Q2, so that the second control terminal of the scan output module 14 still maintains the potential of the previous stage and cannot output the on potential of the first clock signal SCK1, thereby reducing the frequency of the scan signal.

[0116] The first isolation unit 132 has its control terminal connected to the output terminal of the stage transmission module 12. The first terminal of the first isolation unit 132 is connected to the frequency control signal SW, and the second terminal of the first isolation unit 132 is connected to the control terminal of the output control unit 131. The first isolation unit 132 is used to respond to the stage transmission signal Carry and cut off the transmission path of the frequency control signal SW to the control terminal of the output control unit 131.

[0117] For example, for any display frame, if the scan signal OUT needs to output a conduction pulse within that display frame, the frequency control signal SW within that display frame can maintain the potential of the output control unit 131 at which it is turned on, so that the output control unit 131 is turned on when the stage transmission output module 12 outputs a conduction potential. If the scan signal OUT does not need to output a conduction pulse within a certain display frame, the frequency control signal SW within that display frame will have a potential jump, so that the output control unit 131 is turned off when the stage transmission output module 12 outputs a conduction potential.

[0118] Continue to refer to Figure 5 Optionally, the scan output module 14 includes a second isolation unit 141 and a down-frequency output unit 142; the control terminal of the output control unit 131 is used as the intermediate node of the frequency cutting control module 13.

[0119] The first end of the second isolation unit 141 is connected to the control end of the output control unit 131, and the second end of the second isolation unit 141 is connected to the control end of the down-frequency output unit 142. The second isolation unit 141 is used to isolate the control end of the output control unit 131 and the control end of the down-frequency output unit 142.

[0120] The first terminal of the frequency reduction output unit 142 is connected to the second potential signal VGL2, and the second terminal of the frequency reduction output unit 142 is connected to the output terminal of the scan output module 14. The frequency reduction output unit 142 is used to turn on or off according to the potential of the control terminal of the output control unit 131, and the on / off state of the frequency reduction output unit 142 is different from the on / off state of the output control unit 131. The potential of the second potential signal VGL2 is the same as the potential of the first potential signal VGL1. The first potential signal VGL1 is the cutoff potential of the scan signal. The cutoff potential is the potential of the function module that controls the access to the scan signal to turn off.

[0121] The down-frequency output unit 142 is a switching unit. After being turned on, it transmits the second potential signal VGL2 to the output terminal of the scan output module 14. In the current display frame, when the scan signal OUT does not need to output a conduction pulse, when the shift signal Carry outputs a conduction potential, the output control unit 131 responds to the potential of the intermediate node QN1 to turn off, and the down-frequency output unit 142 responds to the potential of the intermediate node QN1 to turn on, thereby providing the second potential signal VGL2 to the output terminal of the scan output module 14, so that the scan signal OUT always maintains the cut-off potential and does not output a conduction pulse.

[0122] Figure 6 This is a potential waveform diagram of the control terminal of a frequency-down output unit in a scanning drive circuit when a second isolation unit is not provided. Figure 7 This is a potential waveform diagram of the control terminal of the down-frequency output unit in the scanning drive circuit provided in an embodiment of the present invention. Figure 6 and Figure 7 The horizontal axis represents time, and the vertical axis represents voltage values. If the second isolation unit 141 is not included in the scanning drive circuit, the control terminal of the down-conversion output unit 142 is directly connected to the control terminal of the output control unit 131, i.e., the intermediate node QN1. The intermediate node QN1 is in a floating state, while the first connection terminal Q1 and the second connection terminal Q2 have high and low potential changes. Due to the parasitic capacitance of the output control unit 131 itself, the potential of the control terminal of the output control unit 131 exhibits ripple fluctuations, such as... Figure 6 As shown. The second isolation unit 141 includes at least one normally open transistor. By setting the second isolation unit 142 to isolate the control terminal of the output control unit 131 from the control terminal of the down-frequency output unit 142, the influence of the potential of other nodes on the control terminal of the output control unit 131 is shielded, thereby improving voltage ripple, such as... Figure 7 As shown.

[0123] Optionally, the first potential signal VGL1 and the second potential signal VGL2 are provided by different ports of the power supply chip that provides the first potential signal VGL1 and the second potential signal VGL2.

[0124] If the frequency of the scan signal OUT of a certain display area is lower than that of the other display areas, then no conduction pulse will be output in some display frames in that display area. That is, there is at least one display frame in which the shift signal Carry output by the shift register corresponding to each pixel row of the display area is at a high potential. In this display frame, the down-frequency output unit 142 outputs the second potential signal VGL2 to the output terminal of the scan output module 14. For example, if the display area includes 30 pixel rows, then in one display frame, the scan signal OUT connected to the 30 pixel rows will not have a conduction pulse. That is, in this display frame, the second potential signal VGL2 needs to carry 30 pixel rows, which is a large load and affects the potential of the second potential signal VGL2. If the first potential signal VGL1 and the second potential signal VGL2 are output from the same power chip port, then because the second potential signal VGL2 connected to the down-frequency output unit 142 has a large load, it will also affect the potential of the first potential signal VGL1, reducing the reliability of the scan drive circuit. In this embodiment, the first potential signal VGL1 and the second potential signal VGL2 are provided by different ports of the power supply chip that provides the first potential signal VGL1 and the second potential signal VGL2. This can avoid the high load of the second potential signal VGL2 affecting the first potential signal VGL1 and improve the reliability of the circuit.

[0125] Continue to refer to Figure 5 Optionally, the scan drive circuit further includes a scan control module 15, which is connected to the second control terminal of the scan output module 14. The scan control module 15 is used to transmit the first clock signal SCK1 to the second control terminal of the scan output module 15 in response to the potential of the first output terminal N1.

[0126] The first terminal of the scan control module 15 is connected to the first clock signal SCK1. The second terminal of the scan control module 15 is connected to the second control terminal of the scan output module 14. The control terminal of the scan control module 15 is connected to the first control terminal of the scan output module 14. The scan control module 15 is a switch module that responds to the potential of its own control terminal to turn on or off, and connects its first terminal and second terminal after turning on.

[0127] Continue to refer to Figure 5 Optionally, the scan output module 14 includes:

[0128] The first output unit 143 has its control terminal connected to the first output terminal N1 and is used to transmit the first potential signal VGL1 to the output terminal of the scan output module 14 in response to the potential of the first output terminal N1.

[0129] The second output unit 144 has its control terminal connected to the second connection terminal Q2. It is used to transmit the first clock signal SCK1 to the output terminal of the scan output module 14 in response to the potential of the second connection terminal Q2.

[0130] The first terminal of the first output unit 143 is connected to the first potential signal VGL1, and the second terminal of the first output unit 143 is connected to the output terminal of the scan output module 14. The first output unit 143 is a switching unit used to respond to the potential turn-on and turn-off of its own control terminal, and provides the first potential signal VGL1 to the output terminal of the scan output module 14 when it is on. The first terminal of the second output unit 144 is connected to the first clock signal SCK1, and the second terminal is connected to the output terminal of the scan output module 14. The second output unit 144 is a switching unit used to respond to the potential turn-on and turn-off of its own control terminal, and provides the first clock signal SCK1 to the output terminal of the scan output module 14 when it is on.

[0131] Continue to refer to Figure 5 Optionally, the transmission output module 12 includes:

[0132] The third output unit 121 has its control terminal connected to the first output terminal N1 and is used to respond to the potential of the first output terminal N1 and transmit the first potential signal VGL1 to the output terminal of the stage transmission module 12.

[0133] The fourth output unit 122 is connected to the control terminal of the second output terminal N2 and is used to transmit the first clock signal SCK1 to the output terminal of the stage transmission module 12 in response to the potential of the second output terminal N2.

[0134] The first terminal of the third output unit 121 is connected to the first potential signal VGL1, and the second terminal is connected to the output terminal of the stage transmission output module 12. The third output unit 121 is a switching unit that responds to the potential of its own control terminal to turn on or off, and transmits the first potential signal VGL1 to the output terminal of the stage transmission output module 12 when it is on. The first terminal of the fourth output unit 122 is connected to the first clock signal SCK1, and the second terminal is connected to the output terminal of the stage transmission output module 12. It responds to the potential of its own control terminal to turn on or off, and transmits the first clock signal SCK1 to the output terminal of the stage transmission output module 12 when it is on.

[0135] Continue to refer to Figure 5 Optionally, the transmission control module 11 includes:

[0136] The first input unit 111 is connected to the first output terminal N1 and is used to transmit the input signal SIN to the first output terminal N1 in response to the first clock signal SCK1. Specifically, the first input unit 111 is a switching unit, with the first terminal receiving the input signal SIN, the second terminal connected to the first output terminal N1, and the control terminal receiving the first clock signal SCK1 to respond to the potential on or off of its own control terminal, and transmitting the input signal SIN to the first output terminal N1 when it is on.

[0137] The second input unit 112 has a first terminal connected to a first potential signal VGL1, which is used to transmit the first potential signal VGL1 to the second terminal in response to the first clock signal SCK1. Specifically, the second input unit 112 is a switch unit that turns on or off in response to the first clock signal SCK1 connected to its own control terminal, and transmits the first potential signal VGL1 to its own second terminal when it is on.

[0138] Control unit 113 is connected between the second terminal of the second input unit 112 and the second output terminal N2, and is used to control the potential of the second output terminal N2 according to the second clock signal SCK2 and the potential of the second terminal of the second input unit 112. Control unit 113 may include two control terminals, one of which is connected to the second clock signal SCK2, and the other is connected to the second terminal of the second input unit 112, and controls the potential of the second output terminal N2 according to the potential of the two control terminals.

[0139] The first node control unit 114 is connected to the second terminal of the second input unit 112 and is used to transmit the first clock signal SCK1 to the second terminal of the second input unit 112 in response to the potential of the first output terminal N1. The first terminal of the first node control unit 114 is connected to the first clock signal SCK1, the second terminal is connected to the second terminal of the second input unit 112, and the control terminal is connected to the first output terminal N1. The first node control unit 114 is a switching unit that responds to the potential of its own control terminal to turn on or off, and transmits the first clock signal SCK1 to the second terminal of the second input unit 112 when it is on.

[0140] The second node control unit 115 is connected to the second output terminal N2 and is used to transmit the first clock signal SCK1 to the second output terminal N2 in response to the potential of the first output terminal N1. The first terminal of the second node control unit 115 is connected to the first clock signal SCK1, the second terminal is connected to the second output terminal N2, and the control terminal is connected to the first output terminal N1. The second node control unit 115 is a switching unit, and when it is turned on, it transmits the first clock signal SCK1 to the second output terminal N2.

[0141] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 8 For corresponding Figure 5 A specific structure, see reference Figure 5 and Figure 8 The output control unit 131 includes a first transistor T1, the first terminal of the first transistor T1 is connected to the first connection terminal Q1, the second terminal of the first transistor T1 is connected to the second connection terminal Q2, and the gate of the first transistor T1 is connected to the second terminal of the first isolation unit 132.

[0142] The first isolation unit 132 includes a second transistor T2. The first terminal of the second transistor T2 is connected to the frequency control signal SW. The second terminal of the second transistor T2 is connected to the control terminal of the output control unit 131. The gate of the second transistor T2 is connected to the output terminal of the stage transmission module 12.

[0143] The second isolation unit 141 includes a third transistor T3 and a first capacitor C1. The first terminal of the third transistor T3 is connected to the control terminal of the output control unit 131, the second terminal of the third transistor T3 is connected to the control terminal QN of the down-frequency output unit 142, and the gate of the third transistor T3 is connected to the first potential signal VGL1.

[0144] The first terminal of the first capacitor C1 is connected to the first potential signal VGL1, and the second terminal of the first capacitor C1 is connected to the control terminal QN of the frequency reduction output unit 142.

[0145] The down-frequency output unit 142 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the second potential signal VGL2. The second terminal of the fourth transistor T4 is connected to the output terminal of the scan output module 14. The gate of the fourth transistor T4 is connected to the second terminal of the second isolation unit 141.

[0146] The scanning control module 15 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the first clock signal SCK1, the second terminal of the fifth transistor T5 is connected to the second connection terminal Q2, and the gate of the fifth transistor T5 is connected to the first output terminal N1.

[0147] The first output unit 143 includes a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The first terminal of the sixth transistor T6 is connected to the first potential signal VGL1, the second terminal of the sixth transistor T6 is connected to the output terminal of the scan output module 14, and the gate of the sixth transistor T6 is connected to the first output terminal N1.

[0148] The first terminal of the seventh transistor T7 is connected to the second clock signal SCK2, the second terminal of the seventh transistor T7 is connected to the first terminal of the second capacitor C2, the gate of the seventh transistor T7 is connected to the first output terminal N1, and the second terminal of the second capacitor C2 is connected to the first output terminal N1.

[0149] The second output unit 144 includes an eighth transistor T8 and a third capacitor C3. The first terminal of the eighth transistor T8 is connected to the first clock signal SCK1, the second terminal of the eighth transistor T8 is connected to the output terminal of the scan output module 14, the gate of the eighth transistor T8 is connected to the second connection terminal Q2, the first terminal of the third capacitor C3 is connected to the first clock signal SCK1, and the second terminal of the third capacitor C3 is connected to the second connection terminal Q2.

[0150] The third output unit 121 includes an eleventh transistor T11, a twelfth transistor T12 and a fourth capacitor C4. The first terminal of the eleventh transistor T11 is connected to the first potential signal VGL1, the second terminal of the eleventh transistor T11 is connected to the output terminal of the stage transmission output module 12, and the gate of the eleventh transistor T11 is connected to the first output terminal N1.

[0151] The first terminal of the twelfth transistor T12 is connected to the second clock signal SCK2, the second terminal of the twelfth transistor T12 is connected to the first terminal of the fourth capacitor C4, the gate of the twelfth transistor T12 is connected to the first output terminal N1, and the second terminal of the fourth capacitor C4 is connected to the first output terminal N1.

[0152] The fourth output unit 122 includes a thirteenth transistor T13 and a fifth capacitor C5. The first terminal of the thirteenth transistor T13 is connected to the first clock signal SCK1, the second terminal of the thirteenth transistor T13 is connected to the output terminal of the stage output module 12, the gate of the thirteenth transistor T13 is connected to the second output terminal N2, the first terminal of the fifth capacitor C5 is connected to the first clock signal SCK1, and the second terminal of the fifth capacitor C5 is connected to the second output terminal N2.

[0153] The first input unit 111 includes a seventeenth transistor T17. The first terminal of the seventeenth transistor T17 is connected to the input signal SIN, the second terminal of the seventeenth transistor T17 is connected to the first output terminal N1, and the gate of the seventeenth transistor T17 is connected to the first clock signal SCK1.

[0154] The second input unit 112 also includes an eighteenth transistor T18. The first terminal of the eighteenth transistor T18 is connected to the first potential signal VGL1, the second terminal of the eighteenth transistor T18 is connected to the control unit 113, and the gate of the eighteenth transistor T18 is connected to the first clock signal SCK1.

[0155] The control unit 113 includes a nineteenth transistor, a sixth capacitor C6, and a twentieth transistor T20. The first terminal of the nineteenth transistor is connected to a second clock signal SCK2, and its second terminal is connected to the first terminal of the twentieth transistor T20. The gate of the nineteenth transistor is connected to the second terminal of the second input unit 112, i.e., the second terminal of the eighteenth transistor T18. The second terminal of the twentieth transistor T20 is connected to the second output terminal N2, and its gate is connected to the second clock signal SCK2. The first terminal of the sixth capacitor C6 is connected to the second terminal of the second input unit 112, and its second terminal is connected to the first terminal of the twentieth transistor T20. In this embodiment, the nineteenth transistor is exemplarily shown as a dual-gate transistor including a first sub-transistor T191 and a second sub-transistor T192. For specific connection relationships, see [details omitted]. Figure 8 , will not be described in detail.

[0156] The first node control unit 114 includes a twenty-first transistor T21. The first terminal of the twenty-first transistor T21 is connected to the first clock signal SCK1, the second terminal of the twenty-first transistor T21 is connected to the second terminal of the second input unit 112, and the gate of the twenty-first transistor T21 is connected to the first output terminal N1.

[0157] The second node control unit 115 includes a twenty-second transistor T22. The first terminal of the twenty-second transistor T22 is connected to the first clock signal SCK1, the second terminal of the twenty-second transistor T22 is connected to the second output terminal N2, and the gate of the twenty-second transistor T22 is connected to the first output terminal N1.

[0158] Figure 5 or Figure 8 The specific working process of the scanning drive circuit shown will be described later, please refer to the following text.

[0159] exist Figure 5 or Figure 8 Based on the scan driving circuit shown, embodiments of the present invention can also provide other forms of scan driving circuits, specifically, Figure 9 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention, with reference to... Figure 9 The scan output module 14 further includes a first protection unit 145. The first terminal of the first protection unit 145 is connected to the first output terminal N1, and the second terminal of the first protection unit 145 is connected to the control terminal of the first output unit 143. The control terminal of the first protection unit 145 is connected to a first potential signal VGL1. The first output unit 143 is connected to the first output terminal N1 through the first protection unit 145, and the control terminal of the scan control module 15 is also connected to the first output terminal N1 through the first protection unit 145. The first protection unit 145 includes a tenth transistor T10. The first electrode of the tenth transistor T10 is connected to the first output terminal N1, and the second electrode of the tenth transistor T10 is connected to the control terminal of the first output unit 143. The gate of the tenth transistor T10 is connected to the first potential signal VGL1.

[0160] The transmission control module 11 also includes a second protection unit 116. The first terminal of the second protection unit 116 is connected to the first input unit 111, and the second terminal of the second protection unit 116 is connected to the first output terminal N1. The control terminal of the second protection unit 116 is connected to a first potential signal VGL1. The second terminal of the first input unit 111 can serve as the first output terminal N1. The second protection unit 116 includes a fifteenth transistor T15. The first electrode of the fifteenth transistor T15 is connected to the second terminal of the first input unit 111, and the second electrode of the fifteenth transistor T15 is connected to the first output terminal N1. The gate of the fifteenth transistor T15 is connected to the first potential signal VGL1.

[0161] The transmission control module 11 also includes a third protection unit 117. The first terminal of the third protection unit 117 is connected to the second terminal of the second input unit 112, and the second terminal of the third protection unit 117 is connected to the control unit 113. The control terminal of the third protection unit 117 is connected to a first potential signal VGL1. The third protection unit 117 includes a sixteenth transistor T16. The first electrode of the sixteenth transistor T16 is connected to the second terminal of the second input unit 112, and the second electrode of the sixteenth transistor T16 is connected to the control unit 113. The gate of the sixteenth transistor T16 is connected to the first potential signal VGL1. The control unit 113 is connected to the second terminal of the second input unit 112 through the third protection unit 117.

[0162] Figure 9 The three protection units shown have similar functions. In this embodiment, the second protection unit 116 is used as an example for explanation, and the other two will not be described in detail. Referring to the fourth stage t4 described below, due to the coupling effect of the fourth capacitor C4, the gate potential of the eleventh transistor T11 will be coupled to an extremely low potential lower than the first potential signal VGL1. By setting the second protection unit 116, the transmission of this extremely low potential to the first terminal of the second protection unit 116 can be prevented, thus preventing the transistors connected to the first terminal of the second protection unit 116 from being damaged due to excessive voltage stress. Specifically, the conduction condition of the fifteenth transistor T15 is that its gate-source voltage difference is less than its threshold voltage. When the gate of the eleventh transistor T11 is coupled to an extremely low potential, if it is transmitted through the fifteenth transistor T15 to the first terminal of the second protection unit 116, the gate-source voltage difference of the fifteenth transistor T15 will be greater than its threshold voltage, failing to meet the conduction condition of the fifteenth transistor T15, causing the fifteenth transistor T15 to turn off. Therefore, the transmission of this extremely low potential to the first terminal N11 of the second protection unit 116 can be blocked.

[0163] Continue to refer to Figure 9 The operation of the display panel where the scanning drive circuit is located includes a display stage and a non-display stage. The scanning output module 14 also includes a first test unit 146, which is connected to the control terminal of the second output unit 144. It is used to turn off in response to the reset signal RST in the display stage and to turn on in response to the reset signal RST in the non-display stage, so as to transmit the first potential signal VGL1 to the control terminal of the second output unit 144. The first test unit 146 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the first potential signal VGL1, the second terminal of the ninth transistor T9 is connected to the control terminal of the second output unit 144, and the gate of the ninth transistor T9 is connected to the reset signal RST.

[0164] The stage transmission output module 12 also includes a second test unit 123, which is connected to the control terminal of the fourth output unit 122. The second test unit 123 is used to turn off in response to the reset signal RST during the display stage and to turn on in response to the reset signal RST during the non-display stage, so as to transmit the first potential signal VGL1 to the control terminal of the fourth output unit 122. The second test unit 123 includes a fourteenth transistor T14. The first terminal of the fourteenth transistor T14 is connected to the first potential signal VGL1, the second terminal of the fourteenth transistor T14 is connected to the control terminal of the fourth output unit 122, and the gate of the fourteenth transistor T14 is connected to the reset signal RST.

[0165] The transmission control module 11 also includes a third test unit 118, which is connected to the first output terminal N1. During the display phase, the third test unit 118 is turned off in response to the reset signal RST, and during the non-display phase, it is turned on in response to the reset signal RST to transmit the first potential signal VGL1 to the first output terminal N1. The third test unit 118 includes a twenty-third transistor T23. The first terminal of the twenty-third transistor T23 is connected to the first clock signal SCK1, the second terminal of the twenty-third transistor T23 is connected to the first output terminal N1, and the gate of the twenty-third transistor T23 is connected to the reset signal RST.

[0166] The three test units function similarly; we will take one, such as the first test unit 146, as an example for functional description. During the display phase of the display panel, the scan drive circuit outputs a scan signal to control the display area of ​​the display panel to display normally. The non-display phase of the display panel can be the power-on startup phase or the phase where the display phase ends for fault detection after an abnormality occurs in the displayed image. In the non-display phase, the ninth transistor T9 responds to the reset signal RST and conducts to transmit the first potential signal VGL1 to the gate of the eighth transistor T8, thereby controlling the eighth transistor T8 to conduct. When the eighth transistor T8 is normal, it should output the first clock signal SCK1 to the output terminal of the scan output module 14. Therefore, by comparing the scan signal and the first clock signal SCK1, if the waveforms are the same, it is determined that the eighth transistor T8 is not faulty; if the waveforms are inconsistent, it is determined that the eighth transistor T8 is faulty and cannot correctly output the first clock signal SCK1.

[0167] In a display device that includes a scanning drive circuit, such as Figure 10 As shown, Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, with reference to... Figure 10 The display device includes a first clock signal line L1, a second clock signal line L2, a third clock signal line L3, and a fourth clock signal line L4. The start pulses of the signals transmitted by the first clock signal line L1, the second clock signal line L2, the third clock signal line L3, and the fourth clock signal line L4 are output sequentially. The shift register includes a first clock signal terminal and a second clock signal terminal. The first clock signal terminal is used to provide a first clock signal SCK1, and the second clock signal terminal is used to provide a second clock signal SCK2.

[0168] The first clock signal terminal of the 4k+1 stage shift register is connected to the first clock signal line L1, and the second clock signal terminal of the 4k+1 stage shift register is connected to the second clock signal line L2.

[0169] The first clock signal terminal of the 4k+2 level shift register is connected to the second clock signal line L2, and the second clock signal terminal of the 4k+2 level shift register is connected to the third clock signal line L3.

[0170] The first clock signal terminal of the 4k+3 level shift register is connected to the third clock signal line L3, and the second clock signal terminal of the 4k+3 level shift register is connected to the fourth clock signal line L4.

[0171] The first clock signal terminal of the 4k+4th stage shift register is connected to the fourth clock signal line L4, and the second clock signal terminal of the 4k+4th stage shift register is connected to the first clock signal line L1; K is an integer greater than or equal to 0.

[0172] In this embodiment, each stage shift register is connected to two rows of pixel circuits, and the functional modules connected to the shift registers in the two rows of pixel circuits are identical. For example, the display panel includes 2800 rows of pixels, and every two rows of pixels (PIX) are connected to the same shift register 1. The output terminal Pout of the scan output module of shift register 1 provides the same scan signal to the corresponding two connected rows of pixels, such as providing a data write scan signal SN to the control terminal of the data write module in the pixel circuit. The shift signal Carry output from the previous stage serves as the input signal SIN for the next stage. The shift register also includes a reset terminal Reset, connected to the reset signal line RST1 of the display device. The reset signal line RST1 is used to provide a reset signal. The input signal SIN of the first-stage shift register is provided by the input signal line IN.

[0173] Figure 11 A driving timing diagram for a display device provided in an embodiment of the present invention is applicable to... Figure 10 The display device shown, and Figure 10 For the specific structure of shift register 1 in the display device, please refer to [link / reference]. Figure 9 In this embodiment, taking shift register 1 as an example where all transistors except the fourth transistor T4 are P-type transistors, and the scanning signal has a high on-state and a low off-state potential, the following example is used. Figure 11 The diagram illustrates the waveforms of the first-level data write scan signal SN1, the second-level data write scan signal SN2, the third-level data write scan signal SN3, and the fourth-level data write scan signal SN4. Figures 12-19These are working state diagrams of the shift register operating in the first to eighth stages of the first working mode according to embodiments of the present invention. The working process of the display panel in the first working mode includes the first stage t1 to the eighth stage t8. In this embodiment, the working process of the first-stage shift register is used as an example to divide the first stage t1 to the eighth stage t8. The first-stage shift register corresponds to the signals on the first clock signal line L1 and the second clock signal line L2. The first clock signal line L1 provides the first clock signal SCK1 to the first-stage shift register, and the second clock signal line L2 provides the second clock signal SCK2 to the second-stage shift register. In this embodiment, the second terminal of the seventeenth transistor T17 is designated as the first node N3, the second terminal of the eighteenth transistor T18 is designated as the second node N4, the second terminal of the sixteenth transistor T16 is designated as the third node N5, the gate of the sixth transistor T6 is designated as the fourth node T6, and the gate of the eighth transistor T8 is designated as the fifth node N7. Reference Figures 9-19 The operation of the scan drive circuit in the first working mode includes:

[0174] In the first stage t1, the input signal SIN and the first clock signal SCK1 are both at low potentials. The low potential of the first clock signal SCK1 controls the seventeenth transistor T17 and the eighteenth transistor T18 to turn on, so as to write the low potential into the scan drive circuit, making the first node N3, the first output terminal N1, the second node N4, and the third node N5 all at low potentials. The nineteenth transistor T19 responds to the low potential of the third node N5 and turns on, the second clock signal SCK2 is at a low potential, and controls the twentieth transistor T20 to turn on, thereby transmitting the low potential of the second clock signal SCK2 written by the turned nineteenth transistor to the second output terminal N2. The thirteenth transistor T13 responds to the low potential of the second output terminal N2 and turns on to output the low potential transmitted by the first clock signal SCK1. The eleventh transistor T11 responds to the low potential of the first output terminal N1 and turns on to output the first potential signal VGL1, and the shift signal Carry is output at a low potential. When the frequency control signal SW is low, the second transistor T2 turns on in response to the low potential of the shift signal Carry, transmitting the low potential of the frequency control signal SW to the intermediate node QN1. The first transistor T1 turns on in response to the low potential of the intermediate node QN1, transmitting the potential of the second output terminal N2 to the fifth node N7. The eighth transistor T8 turns on in response to the low potential of the fifth node N7, outputting the low potential of the first clock signal SCK1. The low potential of the intermediate node QN1 is transmitted to the gate of the fourth transistor T4 via the third transistor T3, controlling the fourth transistor T4 to turn off. The potential of the first output terminal N1 is transmitted to the fourth node N6, controlling the sixth transistor T6 to turn on. The first potential signal VGL1 is output to the output terminal of the scan output module via the turned-on sixth transistor T6. Therefore, in the first stage t1, the first-level data write scan signal SN1 outputs a low potential.

[0175] In the second stage t2, the input signal SIN and the second clock signal SCK2 are both at low potentials, and the first clock signal SCK1 is at a high potential. The seventeenth transistor T17 and the eighteenth transistor T18 are both turned off in response to the high potential of the first clock signal SCK1. The first output terminal N1 maintains the low potential of the first stage t1. The twenty-first transistor T21 and the twenty-second transistor T22 are turned on in response to the low potential of the first output terminal N1, so as to write the high potential of the first clock signal SCK1 into the second node N4 and the second output terminal N2 respectively. The high potential of the second node N4 is transmitted to the third node N5 through the turned-on sixteenth transistor. The first sub-transistor T19-1 and the second sub-transistor T19-2 are turned off in response to the high potential of the third node N5. The thirteenth transistor T13 is turned off in response to the high potential of the second output terminal N2. The eleventh transistor T11 is turned on in response to the low potential of the first output terminal N1, so as to output the first potential signal VGL1 to the output terminal of the shift output module. That is, in the second stage t2, the shift signal Carry is at a low potential. The second transistor T2 turns on in response to the low potential of the shift signal Carry, so as to write the low potential of the frequency control signal SW into the intermediate node QN1. The first transistor T1 turns on in response to the low potential of the intermediate node QN1. The fourth transistor T4 turns off in response to the low potential of the intermediate node QN1. The high potential of the second output terminal N2 is transmitted to the fifth node N7 through the first transistor T1. The eighth transistor T8 turns off in response to the high potential of the fifth node N7. The output terminal of the scan output module maintains the output of the first potential signal VGL1, that is, the first-level data write scan signal SN1 is at a low potential.

[0176] In the third stage t3, based on the second stage t2, the second clock signal SCK2 is high, and the twentieth transistor T20 is turned off in response to the high potential of the second clock signal SCK2. Other states are the same as in the second stage t2 and remain unchanged. The first-level data write scan signal SN1 is low.

[0177] In the fourth stage t4, the input signal SIN is high, the first clock signal SCK1 is low, and the second clock signal SCK2 is high. The seventeenth transistor T17 and the eighteenth transistor T18 turn on in response to the low level of the first clock signal SCK1, transmitting the high level of the input signal SIN to the first node N3 and the first potential signal VGL1 to the second node N4, respectively. The high level of the first node N3 is transmitted to the first output terminal N1 via the turned-on fifteenth transistor T15. The eleventh transistor T11 turns off in response to the high level of the first output terminal N1. The high level of the first output terminal N1 is transmitted to the fourth node N6 via the tenth transistor T10, and the sixth transistor T6 turns off in response to the high level of the fourth node N6. The second node N4 transmits a low potential to the third node N5 via the sixteenth transistor 16. The first sub-transistor T19-1 and the second sub-transistor T19-2 turn on in response to the low potential of the third node N5. The twentieth transistor T20 turns off in response to the high potential of the second clock signal SCK2. The twenty-first transistor T21 and the twenty-second transistor T22 turn off in response to the high potential of the first output terminal N1. At the second output terminal N2, there is no high potential output at this time. The first clock signal SCK1 is at a low potential. The first output terminal N1 is coupled by the fifth capacitor C5, and the potential drops from a high potential to a low potential. The thirteenth transistor T13 turns on to transmit the low potential of the first clock signal SCK1 to the output terminal of the shift output module, and the shift signal Carry presents a low potential. The second transistor T2 turns on in response to the low potential of the shift signal Carry, transmitting the low potential of the frequency control signal SW to the intermediate node QN1. The first transistor T1 turns on in response to the low potential of the intermediate node QN1, and the low potential of the second output terminal N2 is transmitted to the fifth node N7 via the first transistor T1. The eighth transistor T8 turns on in response to the low potential of the fifth node N7, so as to transmit the first clock signal SCK1 to the output terminal of the scan output module. The potential of the first-stage data write scan signal SN1 is low.

[0178] In the fifth stage t5, the second clock signal SCK2 jumps from a high level to a low level, and the second output terminal N2 remains at a low level. Everything else is the same as in the fourth stage t4, with no change. The potential of the scan signal is low.

[0179] In stage t6, the first clock signal SCK1 is high. The seventeenth transistor T17 and the eighteenth transistor T18 turn off in response to the high potential of the first clock signal SCK1. The first output terminal N1 remains high. The eleventh transistor T11 turns off in response to the high potential of the first output terminal N1. The sixth transistor T6 turns off in response to the high potential of the fourth node N6. The second output terminal N2 maintains the low potential of stage t5. The thirteenth transistor T13 turns on in response to the potential of the second output terminal N2, outputting the high potential of the first clock signal SCK1 to the output terminal of the shift output module, making the shift signal Carry high. The second transistor T2 turns off in response to the high potential of the shift signal Carry. The intermediate node QN1 maintains the low potential of the previous stage, allowing the first transistor T1 to continue conducting. The fourth transistor T4 turns off in response to the potential of its own gate. The low potential of the second output terminal N2 is transmitted to the fifth node N7 via the first transistor T1. The eighth transistor T8 turns on in response to the potential of the fifth node N7 to transmit the high potential of the first clock signal SCK1 to the output terminal of the scan output module, and the scan signal OUT is at a high potential.

[0180] In the seventh stage t7, both the first clock signal SCK1 and the second clock signal SCK2 are at a high level. The second output terminal N2 and the gate of the eighth transistor T8 maintain the low potential of the sixth stage t6. The eighth transistor T8 continues to conduct in order to transmit the high potential of the first clock signal SCK1 to the output terminal of the scan output module, and the scan signal OUT is at a high potential.

[0181] In stage t8, the first clock signal SCK1 changes from high to low. Transistors T17 and T18 turn on in response to the low potential of SCK1, transmitting the low potential of the input signal SIN to the first output terminal N1 and the first potential signal VGL1 to the second node N4, respectively. Transistor T11 turns on in response to the low potential of the first output terminal N1, transmitting the first potential signal VGL1 to the output terminal of the shift output module. Transistors T21 and T22 turn on in response to the low potential of the first output terminal N1, transmitting the potential of the first clock signal SCK1 to the second node N4 and the second output terminal N2, respectively. Transistor T13 turns on in response to the low potential of the second output terminal N2, transmitting the first clock signal SCK1 to the output terminal of the shift output module. The shift signal Carry is simultaneously input from the low potential of the first clock signal SCK1 and the low potential of the first potential signal VGL1, resulting in a low-potential shift signal. The second transistor T2 turns on in response to the low potential of the shift signal Carry, so as to output the low potential of the frequency control signal SW to the intermediate node QN1. The first transistor T1 turns on in response to the low potential of the intermediate node QN1. The low potential of the second output terminal N2 is transmitted to the gate of the eighth transistor T8 through the first transistor T1. The eighth transistor T8 turns on in response to the low potential of the first clock signal SCK1 to the output terminal of the scan output module. The sixth transistor T6 turns on in response to the low potential of the fourth node N6, so as to transmit the first clock signal SCK1 to the output terminal of the scan output module. The scan signal OUT is input simultaneously by the low potential of the first clock signal SCK1 and the low potential of the first potential signal VGL1. The scan signal OUT is at a low potential.

[0182] After stage t8, the first clock signal SCK1 and the second clock signal SCK2 alternately output high and low potentials. The specific process is similar to that described above and will not be repeated here. The shift signal Carry and the scan signal OUT remain at low potentials.

[0183] Figure 20 This is a driving timing diagram for another display device provided in an embodiment of the present invention. Figure 20 This is a timing diagram showing the display device operating in its second operating mode. Figure 21 This invention provides a working state diagram of a shift register operating in a second working mode, and in this embodiment, the scanning signal OUT output from the third-stage and fourth-stage shift registers is down-frequency processed as an example. Optionally, the input terminals of the frequency switching control modules in each stage of the shift register are connected to the same frequency control signal SW;

[0184] The frequency control signal SW maintains a constant potential in some display frames and undergoes potential jumps in some display frames, so that the frequencies of the scan signals output by at least two shift registers are different;

[0185] When the scan signal output by the shift register at this stage does not require an output pulse, the potential transition time of the frequency control signal SW is located before the pulse of the stage transmission signal output by the shift register at this stage.

[0186] refer to Figure 21 If the potential transition time of the frequency control signal SW coincides with the pulse start time of the shift signal Carry output by this stage shift register, then the second transistor T2 will turn off in response to the high potential of the shift signal Carry, and will be unable to transmit the high potential of the frequency control signal SW to the intermediate node QN1. The fourth transistor T4 remains off, and the first transistor T1 remains on. When the shift signal Carry outputs a high potential, the potential of the second output terminal N2 is transmitted to the gate of the eighth transistor T8, so that the eighth transistor T8 outputs the high potential of the first clock signal SCK1 to the output terminal of the scan output module, and the third-stage data write scan signal SN3 cannot be pulled low. Therefore, the potential transition time of the frequency control signal SW is before the pulse of the stage transmission signal output by this stage shift register. In this embodiment, taking a single-level shift register connecting two rows of pixels as an example, when the scan signal is down-clocked, the frequency control signal SW performs a potential jump on the row of pixels to be down-clocked, corresponding to one row of time. The width of the frequency control signal is the sum of the number of rows to be down-clocked and the number of rows corresponding to the time preceding the time. In this embodiment, 4 rows are down-clocked, plus 1 row of time preceding the time, for a total of 5 rows of high-level time for the frequency control signal SW. When the frequency control signal SW jumps to a high level, the scan signal begins to down-clock, and the frequency control signal SW is at a high level. The high-level input of the frequency control signal SW is connected to the gate of the intermediate node QN1 and the eighth transistor T8. The first transistor T1 is turned off, and the fourth transistor T4 is turned on. The turned-on fourth transistor T4 transmits the second potential signal VGL2 to the output terminal of the scan output module, and the third-level data write scan signal SN3 is at a low level. The high potential that the third-level data write scan signal SN3 should output is output as a low potential through the frequency control signal SW, thereby achieving the effect of frequency down-clocking.

[0187] The present invention also provides a display device, including a pixel circuit and at least one scanning driving circuit in any of the above embodiments. The beneficial effects of the display device are the same as those of the scanning driving circuit, and will not be described again here.

[0188] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0189] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scanning drive circuit, characterized in that, include: Multiple cascaded shift registers; The shift register includes: A cascade control module is used to control the potential of the first and second output terminals of the cascade control module according to the input signal connected to the input terminal of the shift register. A stage output module is connected to the first output terminal and the second output terminal respectively, and is used to provide a first clock signal or a first potential signal to the output terminal of the stage output module in response to the potential of the first output terminal and the second output terminal; the output terminal of the stage output module is connected to the input terminal of the next stage shift register. A frequency switching control module, wherein the first connection terminal of the frequency switching control module is connected to the second output terminal, the input terminal of the frequency switching control module is connected to a frequency control signal, and the control terminal of the frequency switching control module is connected to the output terminal of the stage transmission output module; The scanning output module is connected to the second connection terminal and the first output terminal of the frequency switching control module, respectively, and is used to output the first clock signal or the first potential signal to the output terminal of the scanning output module in response to the potential of the second connection terminal and the first output terminal; the frequency switching control module is used to control the potential of the second connection terminal according to the stage transmission signal output by the stage transmission output module and the frequency control signal, so as to control the frequency of the scanning signal output by the scanning output module.

2. The scanning drive circuit according to claim 1, characterized in that, The frequency switching control module includes: An output control unit, connected between the first connection terminal and the second connection terminal, is used to control whether to connect the first connection terminal and the second connection terminal according to the potential of the control terminal of the output control unit; A first isolation unit is connected to the output terminal of the stage transmission module. A first terminal of the first isolation unit receives the frequency control signal, and a second terminal of the first isolation unit is connected to the control terminal of the output control unit. The first isolation unit is used to respond to the stage transmission signal and cut off the transmission path of the frequency control signal to the control terminal of the output control unit. Preferably, the output control unit includes a first transistor, the first electrode of the first transistor is connected to the first connection terminal, the second electrode of the first transistor is connected to the second connection terminal, and the gate of the first transistor is connected to the second terminal of the first isolation unit; The first isolation unit includes a second transistor, the first terminal of the second transistor is connected to the frequency control signal, the second terminal of the second transistor is connected to the control terminal of the output control unit, and the gate of the second transistor is connected to the output terminal of the stage transmission module.

3. The scanning drive circuit according to claim 2, characterized in that, The scan output module includes: a second isolation unit and a frequency reduction output unit; The first end of the second isolation unit is connected to the control terminal of the output control unit, and the second end of the second isolation unit is connected to the control terminal of the down-frequency output unit. The second isolation unit is used to isolate the control terminal of the output control unit and the control terminal of the down-frequency output unit. The first terminal of the frequency reduction output unit is connected to a second potential signal, and the second terminal of the frequency reduction output unit is connected to the output terminal of the scan output module. The frequency reduction output unit is used to turn on or off according to the potential of the control terminal of the output control unit, and the on / off state of the frequency reduction output unit is different from the on / off state of the output control unit. The potential of the second potential signal is the same as the potential of the first potential signal. The first potential signal is the cutoff potential of the scan signal, and the cutoff potential is the potential for controlling the functional module connected to the scan signal to turn off. Preferably, the first potential signal and the second potential signal are provided by different ports of the power supply chip that provides the first potential signal and the second potential signal; Preferably, the second isolation unit includes a third transistor and a first capacitor. The first terminal of the third transistor is connected to the control terminal of the output control unit, the second terminal of the third transistor is connected to the control terminal of the down-frequency output unit, and the gate of the third transistor is connected to the first potential signal. The first terminal of the first capacitor is connected to the first potential signal, and the second terminal of the first capacitor is connected to the control terminal of the frequency reduction output unit. Preferably, the frequency reduction output unit includes a fourth transistor, the first terminal of the fourth transistor is connected to the second potential signal, the second terminal of the fourth transistor is connected to the output terminal of the scan output module, and the gate of the fourth transistor is connected to the second terminal of the second isolation unit.

4. The scanning drive circuit according to claim 1, characterized in that, The first control terminal of the scanning output module is connected to the first output terminal, and the second control terminal of the scanning output module is connected to the second connection terminal; The scan drive circuit further includes: a scan control module, which is connected to the second control terminal of the scan output module. The scan control module is used to transmit the first clock signal to the second control terminal of the scan output module in response to the potential of the first output terminal. Preferably, the scanning control module includes a fifth transistor, the first terminal of the fifth transistor is connected to the first clock signal, the second terminal of the fifth transistor is connected to the second connection terminal, and the gate of the fifth transistor is connected to the first output terminal.

5. The scanning drive circuit according to claim 4, characterized in that, The scan output module includes: The first output unit has a control terminal connected to the first output terminal and is used to transmit the first potential signal to the output terminal of the scanning output module in response to the potential of the first output terminal. The second output unit, whose control terminal is connected to the second connection terminal, is used to transmit the first clock signal to the output terminal of the scan output module in response to the potential of the second connection terminal. Preferably, the first output unit includes a sixth transistor, a seventh transistor, and a second capacitor. The first terminal of the sixth transistor is connected to the first potential signal, the second terminal of the sixth transistor is connected to the output terminal of the scan output module, and the gate of the sixth transistor is connected to the first output terminal. The first terminal of the seventh transistor is connected to the second clock signal, the second terminal of the seventh transistor is connected to the first terminal of the second capacitor, the gate of the seventh transistor is connected to the first output terminal, and the second terminal of the second capacitor is connected to the first output terminal. Preferably, the second output unit includes an eighth transistor and a third capacitor. The first terminal of the eighth transistor is connected to the first clock signal, the second terminal of the eighth transistor is connected to the output terminal of the scan output module, the gate of the eighth transistor is connected to the second connection terminal, the first terminal of the third capacitor is connected to the first clock signal, and the second terminal of the third capacitor is connected to the second connection terminal. Preferably, the operation of the display panel where the scanning driving circuit is located includes a display stage and a non-display stage. The scanning output module further includes a first test unit, which is connected to the control terminal of the second output unit. The first test unit is used to turn off in response to a reset signal in the display stage and to turn on in response to the reset signal in the non-display stage, so as to transmit the first potential signal to the control terminal of the second output unit. The first test unit includes a ninth transistor, the first terminal of the ninth transistor is connected to the first potential signal, the second terminal of the ninth transistor is connected to the control terminal of the second output unit, and the gate of the ninth transistor is connected to the reset signal; Preferably, the scanning output module further includes a first protection unit, a first end of the first protection unit is connected to the first output terminal, a second end of the first protection unit is connected to the control terminal of the first output unit, and the control terminal of the first protection unit is connected to the first potential signal; The first protection unit includes a tenth transistor, the first terminal of which is connected to the first output terminal, the second terminal of which is connected to the control terminal of the first output unit, and the gate of which is connected to the first potential signal.

6. The scanning drive circuit according to claim 1, characterized in that, The level transmission output module includes: The third output unit, whose control terminal is connected to the first output terminal, is used to respond to the potential of the first output terminal and transmit the first potential signal to the output terminal of the stage transmission module. The fourth output unit, whose control terminal is connected to the second output terminal, is used to transmit the first clock signal to the output terminal of the stage transmission module in response to the potential of the second output terminal. Preferably, the third output unit includes an eleventh transistor, a twelfth transistor, and a fourth capacitor. The first terminal of the eleventh transistor is connected to the first potential signal, the second terminal of the eleventh transistor is connected to the output terminal of the stage transmission module, and the gate of the eleventh transistor is connected to the first output terminal. The first terminal of the twelfth transistor is connected to the second clock signal, the second terminal of the twelfth transistor is connected to the first terminal of the fourth capacitor, the gate of the twelfth transistor is connected to the first output terminal, and the second terminal of the fourth capacitor is connected to the first output terminal. Preferably, the fourth output unit includes a thirteenth transistor and a fifth capacitor. The first terminal of the thirteenth transistor is connected to the first clock signal, the second terminal of the thirteenth transistor is connected to the output terminal of the stage transmission module, the gate of the thirteenth transistor is connected to the second output terminal, the first terminal of the fifth capacitor is connected to the first clock signal, and the second terminal of the fifth capacitor is connected to the second output terminal. Preferably, the operation of the display panel where the scanning driving circuit is located includes a display stage and a non-display stage. The stage transmission output module further includes a second test unit, which is connected to the control terminal of the fourth output unit. The second test unit is used to turn off in response to a reset signal in the display stage and to turn on in response to the reset signal in the non-display stage, so as to transmit the first potential signal to the control terminal of the fourth output unit. The second test unit includes a fourteenth transistor, the first terminal of which is connected to the first potential signal, the second terminal of which is connected to the control terminal of the fourth output unit, and the gate of which is connected to the reset signal.

7. The scanning drive circuit according to claim 1, characterized in that, The cascade control module includes: The first input unit is connected to the first output terminal and is used to transmit the input signal to the first output terminal in response to the first clock signal. The second input unit has a first terminal connected to the first potential signal, which is used to transmit the first potential signal to the second terminal of the second input unit in response to the first clock signal. A control unit is connected between the second terminal of the second input unit and the second output terminal, and is used to control the potential of the second output terminal according to the second clock signal and the potential of the second terminal of the second input unit; The first node control unit is connected to the second terminal of the second input unit and is used to transmit the first clock signal to the second terminal of the second input unit in response to the potential of the first output terminal. The second node control unit is connected to the second output terminal and is used to transmit the first clock signal to the second output terminal in response to the potential of the first output terminal. Preferably, the transmission control module further includes a second protection unit, the first end of which is connected to the first input unit, the second end of which is connected to the first output unit, and the control end of which is connected to the first potential signal. The second protection unit includes a fifteenth transistor, the first terminal of which is connected to the first input unit, the second terminal of which is connected to the first output terminal, and the gate of which is connected to the first potential signal. Preferably, the transmission control module further includes a third protection unit, the first end of which is connected to the second end of the second input unit, the second end of which is connected to the control unit, and the control end of the third protection unit is connected to the first potential signal; The third protection unit includes a sixteenth transistor, the first terminal of which is connected to the second terminal of the second input unit, the second terminal of which is connected to the control unit, and the gate of which is connected to the first potential signal. Preferably, the first input unit includes a seventeenth transistor, the first terminal of the seventeenth transistor is connected to the input signal, the second terminal of the seventeenth transistor is connected to the first output terminal, and the gate of the seventeenth transistor is connected to the first clock signal; Preferably, the second input unit further includes an eighteenth transistor, the first terminal of the eighteenth transistor is connected to the first potential signal, the second terminal of the eighteenth transistor is connected to the control unit, and the gate of the eighteenth transistor is connected to the first clock signal; Preferably, the control unit includes a nineteenth transistor, a sixth capacitor, and a twentieth transistor. The first terminal of the nineteenth transistor is connected to a second clock signal, the second terminal of the nineteenth transistor is connected to the first terminal of the twentieth transistor, the gate of the nineteenth transistor is connected to the second terminal of the second input unit, the second terminal of the twentieth transistor is connected to the second output terminal, the gate of the twentieth transistor is connected to the second clock signal, the first terminal of the sixth capacitor is connected to the second terminal of the second input unit, and the second terminal of the sixth capacitor is connected to the first terminal of the twentieth transistor. Preferably, the first node control unit includes a twenty-first transistor, the first terminal of the twenty-first transistor is connected to the first clock signal, the second terminal of the twenty-first transistor is connected to the second terminal of the second input unit, and the gate of the twenty-first transistor is connected to the first output terminal; Preferably, the second node control unit includes a twenty-second transistor, the first terminal of the twenty-second transistor is connected to the first clock signal, the second terminal of the twenty-second transistor is connected to the second output terminal, and the gate of the twenty-second transistor is connected to the first output terminal; Preferably, the operation of the display panel where the scanning driving circuit is located includes a display stage and a non-display stage. The transmission control module further includes a third test unit, which is connected to the first output terminal. The third test unit is used to turn off in response to a reset signal in the display stage and to turn on in response to the reset signal in the non-display stage, so as to transmit the first potential signal to the first output terminal. The third test unit includes a 23rd transistor, the first terminal of the 23rd transistor is connected to the first clock signal, the second terminal of the 23rd transistor is connected to the first output terminal, and the gate of the 23rd transistor is connected to the reset signal.

8. The scanning drive circuit according to claim 1, characterized in that, The input terminals of the frequency switching control modules in each of the shift registers are connected to the same frequency control signal; The frequency control signal maintains a constant potential in some display frames and undergoes potential jumps in some display frames, so that the frequencies of the scan signals output by at least two shift registers are different; When the scan signal output by the shift register at this stage does not require an output pulse, the potential transition time of the frequency control signal is located before the pulse of the transmission signal output by the shift register at this stage.

9. A display device, characterized in that, include: The pixel circuit and at least one scan drive circuit according to any one of claims 1-8.

10. The display device according to claim 9, characterized in that, It also includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The start pulses of the signals transmitted by the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are output sequentially. The shift register includes a first clock signal terminal and a second clock signal terminal. The first clock signal terminal is used to provide a first clock signal, and the second clock signal terminal is used to provide a second clock signal. The first clock signal terminal of the 4k+1 level shift register is connected to the first clock signal line, and the second clock signal terminal of the 4k+1 level shift register is connected to the second clock signal line; The first clock signal terminal of the 4k+2 level shift register is connected to the second clock signal line, and the second clock signal terminal of the 4k+2 level shift register is connected to the third clock signal line; The first clock signal terminal of the 4k+3 level shift register is connected to the third clock signal line, and the second clock signal terminal of the 4k+3 level shift register is connected to the fourth clock signal line; The first clock signal terminal of the 4k+4th stage shift register is connected to the fourth clock signal line, and the second clock signal terminal of the 4k+4th stage shift register is connected to the first clock signal line; K is an integer greater than or equal to 0; Preferably, each shift register is connected to two rows of pixel circuits, and the functional modules in the two rows of pixel circuits that are connected to the shift registers are the same.

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