Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a display area and a non-display area, a substrate and a driving layer, the driving layer is arranged on one side of the substrate, and the driving layer comprises a pixel driving circuit located in the display area and a scan driving circuit located at least partially in the non-display area; the scan driving circuit is connected to the pixel driving circuit located in the display area through a wire matching connection; the scan driving circuit comprises an input module and a driving module; a connecting part between the input module and the driving module comprises a first potential node; the input module comprises a first transistor module; the first transistor module is configured to have a double-gate structure and is electrically connected to the first potential node; and the input module inputs a first input signal to a control end of the driving module. The first transistor module configured to have a double-gate structure can reduce a leakage current, so that the scan driving circuit can stably output a high level and display abnormalities can be avoided.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] AMOLED (Active Matrix Organic Light-Emitting Diode) is widely used in electronic devices. With increasing display requirements, the demand for high screen-to-body ratios is growing, necessitating a reduction in the bezels around the display area. Currently, GIP (Gate Drive IC In Panel) technology is considered a direction for achieving narrow bezels. However, current gate-integrated drivers cannot stably output high levels, leading to abnormal voltage output and display issues. Furthermore, current ICs generally have high power consumption. Summary of the Invention

[0003] To overcome the problems mentioned above, the purpose of this application is to provide a display panel and display device, and a scanning driving circuit to reduce the power consumption of the IC.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A display panel comprising:

[0006] The display area and at least part of the non-display area located on one side of the periphery of the display area.

[0007] The display panel includes a substrate and a driving layer.

[0008] The driving layer is disposed on one side of the substrate, and includes a pixel driving circuit located in the display area and a scan driving circuit located at least partially in the non-display area. The scan driving circuit is connected to the pixel driving circuit located in the display area via wiring matching.

[0009] The scanning driving circuit includes an input module and a driving module. The connection between the input module and the driving module includes a first potential node. The input module includes a first transistor module, which is configured to have a dual-gate structure and is electrically connected to the first potential node.

[0010] The input module inputs a first input signal to the control terminal of the drive module, and the drive module is configured to output a signal to the matching pixel drive circuit in response to the first input signal.

[0011] In one embodiment, the scan driving circuit includes a first scan driving circuit and a second scan driving circuit. The second scan driving circuit provides a scan signal to the matched pixel driving circuit through a scan line. Corresponding to the conduction potential duration of the scan signal, the first scan driving circuit transmits a data voltage to the pixel driving circuit through a corresponding data line.

[0012] In one embodiment, the first scanning drive circuit and / or the second scanning drive circuit are disposed on the border areas on both sides of the display area or in the middle of the display area.

[0013] In one embodiment, the pixel driving circuit is an LTPO type driving circuit;

[0014] Preferably, the pixel driving circuit has a topology of 8T1C or 8T2C.

[0015] In one embodiment, the input module includes a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5, and an eighth transistor T8.

[0016] The first transistor module includes a fourth transistor T4 and a ninth transistor T9.

[0017] The second terminal of the first transistor T1 is electrically connected to the voltage source SIN, and the first terminal of the first transistor T1 is electrically connected to the second terminal of the second transistor T2, the gate of the fourth transistor T4, the gate of the ninth transistor T9, and the first terminal of the eighth transistor T8.

[0018] The first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3;

[0019] The first electrode of the third transistor T3 is electrically connected to a constant high potential VHG.

[0020] The gate of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4, the first terminal of the fifth transistor T5, and the first potential node N1.

[0021] The second terminal of the fourth transistor T4 is electrically connected to the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 is connected to the timing signal SCK1;

[0022] The gate of the first transistor T1 is controlled by timing signal SCK1, and the gate of the second transistor T2 is controlled by timing signal SCK2; the gate of the eighth transistor T8 is electrically connected to a constant low potential VGL.

[0023] The second electrode of the fifth transistor T5 is electrically connected to a constant low potential VGL, and the gate of the fifth transistor T5 is electrically connected to the timing signal SCK1.

[0024] The second terminal of the ninth transistor T9 is electrically connected to the timing signal SCK1.

[0025] In one embodiment, the driving module includes a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0026] The second terminal of the first capacitor C1 is electrically connected to the constant high potential VHG and the first terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is electrically connected to the output terminal OUT.

[0027] The first terminal of the first capacitor C1 is electrically connected to the gate of the sixth transistor T6;

[0028] The first terminal of the seventh transistor T7 is electrically connected to the output terminal OUT and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the gate of the seventh transistor T7 and the second terminal of the eighth transistor T8. The second capacitor C2 serves as a bootstrap capacitor. The second terminal of the seventh transistor T7 is connected to the timing signal SCK2.

[0029] In one embodiment, the driving module includes an output terminal and a second transistor module.

[0030] The second transistor module is configured with a dual-gate structure and is electrically connected to the output terminal. It is connected to the pixel driving circuit located in the display area via a wiring match. The pixel driving circuit is an LTPO type driving circuit.

[0031] In one embodiment, the driving module includes a sixth transistor T6, a second transistor module, a first capacitor C1 and a second capacitor C2, and the second transistor module includes a seventh transistor T7 and a tenth transistor T10.

[0032] The second terminal of the first capacitor C1 is electrically connected to the constant high potential VHG and the first terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is electrically connected to the output terminal.

[0033] The first terminal of the first capacitor C1 is electrically connected to the gate of the sixth transistor T6;

[0034] The first terminal of the seventh transistor T7 is electrically connected to the output terminal OUT and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the gate of the seventh transistor T7, the second terminal of the eighth transistor T8, and the gate of the tenth transistor T10. The second terminal of the seventh transistor T7 is electrically connected to the first terminal of the tenth transistor T10. The second terminal of the tenth transistor T10 is connected to the timing signal SCK2.

[0035] In one embodiment, the timing signals SCK1 and SCK2 are out of phase, with a phase difference of 180°.

[0036] Based on the same inventive concept, this application proposes a display device that includes the aforementioned display panel.

[0037] The advantages of this invention are as follows:

[0038] This invention discloses a display panel that, through a topological improvement of its scanning drive circuit, specifically by incorporating a first transistor module with a dual-gate structure in the input module and electrically connected to a first potential node, reduces leakage current. This allows the scanning drive circuit to stably output a high level, preventing display abnormalities. Furthermore, a ninth transistor is placed at the fourth transistor of the first transistor module to form a dual-gate structure, further reducing leakage current and stabilizing the voltage at the first potential node of the drive module. This stabilizes the voltage applied to the gate of the sixth transistor T6 in the drive module, making it less prone to being turned off (this off / cutoff is triggered by a rise in the voltage at the first potential node). This ensures the scanning drive circuit can stably output a high level, preventing display abnormalities. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A schematic diagram of the topology of an existing scanning circuit that controls data writing;

[0041] Figure 2 This is a schematic diagram of the display panel structure according to an embodiment of this application;

[0042] Figure 3 This is a cross-sectional schematic diagram of the display panel according to an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the topology of a scanning circuit for controlling data writing according to an embodiment of this application;

[0044] Figure 5 for Figure 4 A schematic diagram of the driving timing;

[0045] Figure 6 This is a schematic diagram of the topology of the matching pixel driving circuit for the scanning circuit that controls data writing in an embodiment of this application.

[0046] Figure 7 This is a topological schematic diagram of a scanning circuit for controlling data writing according to another embodiment of this application. Detailed Implementation

[0047] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0048] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0049] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, there may be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or as being indirectly "installed to" or "connected to" another component via an intermediate component.

[0051] Overview

[0052] As described in the background section, the power consumption of the DDIC (Display Driver IC) has always been a primary concern for AMOLED display panels.

[0053] The applicant's research on current mainstream AMOLED display panels revealed that in the current mainstream pixel driving circuits (such as the 8T1C topology), low-frequency operation is widespread, and the power consumption of the scanning circuit (GIP circuit) used to control data writing accounts for a relatively large proportion of the total power consumption. The currently mainstream topology is 8T2C (i.e., a structure of 8 transistors and 2 capacitors, such as...). Figure 1 As shown in the figure, the current power consumption reduction measure for this type of circuit is to reduce the frequency of the CLK signal by 1 / 4, 1 / 8 and higher under the low frequency holding frame, and pull the CLK signal high so that the CLK signal does not need to frequently switch between high and low voltage at low frequency, thereby reducing power consumption.

[0054] During the analysis of the circuit topology, the applicant also discovered that the current frequency reduction measures, after reliability analysis (RA), cause the threshold voltage Vth of transistor T4 to be easily forward biased, resulting in increased leakage current. The voltage of node N1 is raised, affecting the gate voltage of the sixth transistor T6. The sixth transistor T6 is easily turned off / cut off, thus failing to output a stable high level (outputting CK signal when the circuit is working, and outputting a high level / VGH when it is not working), resulting in abnormal voltage output and abnormal screen display.

[0055] Based on the applicant's findings, an improvement is made to the existing scanning circuit (GIP circuit) used to control data writing, proposing a scanning drive circuit that can reduce leakage current, achieve frequency reduction measures, and reduce power consumption (reducing power consumption in low-frequency applications).

[0056] This application proposes a scan driving circuit, comprising an input module, a driving module, and a correction module. The input module is connected to the driving module and inputs a first input signal to the control terminal of the driving module. The connection between the input module and the driving module includes a first potential node, and the control terminal of the driving module is connected to the first potential node. The correction module is connected to the first potential node and is used to control the first potential node to maintain a control voltage. The correction module includes a first capacitor, one end of which is connected to the control terminal of the driving module. The scan driving circuit outputs a CK signal when operating and a VHG signal when not operating. Topology optimization of the input module stabilizes the voltage at the first potential node, enabling the first scan driving circuit to stably output a high level.

[0057] This application proposes a display panel with the aforementioned scanning driving circuit. The display panel includes a display area and at least a non-display area located on one side of the display area's periphery. The display panel includes a substrate and a driving layer. The driving layer is disposed on one side of the substrate and includes a pixel driving circuit located in the display area and a scanning driving circuit located at least partially in the non-display area. The scanning driving circuit is connected to the pixel driving circuit (LTPO type driving circuit) located in the display area via a wiring match. The scanning driving circuit includes an input module and a driving module. The connection between the input module and the driving module includes a first potential node. The input module includes a first transistor module configured with a dual-gate structure, electrically connected to the first potential node. The input module inputs a first input signal to the control terminal of the driving module. The driving module is configured to output a signal to the matched pixel driving circuit in response to the first input signal. The first transistor module is configured with a dual-gate structure to reduce leakage current and ensure a stable high-level output. At low frequencies, the GIP signal controlling data writing only needs to be written once per frame, while the hold frame does not require output, thereby reducing the power consumption of the DDIC (Driver Display Chip) in low-frequency situations during the hold frame stage. Furthermore, a second transistor module with a dual-gate structure is incorporated into the drive module to reduce leakage current, enabling the scan drive circuit to stably output a high level and preventing display abnormalities. A transistor is also placed at the seventh transistor position of the second transistor module to form a dual-gate structure, further reducing leakage current and preventing the seventh transistor from accidentally turning off. This ensures the scan drive circuit can stably output a high level, preventing display abnormalities and reducing costs.

[0058] This application proposes a display panel with the aforementioned scan driving circuit. The display panel includes a display area and a non-display area located at least on one side of the periphery of the display area. The display panel also includes a substrate, a driving layer, and a light-emitting functional layer. The substrate covers the display area and the non-display area, and the driving layer is disposed on one side of the substrate. The driving layer includes a pixel driving circuit located in the display area, which is matched and connected to corresponding pixels to drive light-emitting modules to emit light, and a scan driving circuit disposed in the non-display area. The pixel driving circuit adopts an LTPO type driving circuit. The scan driving circuit includes a scan driving circuit for providing scan signals to the pixel driving circuit and a scan driving circuit for transmitting data voltage to the corresponding pixel driving circuit to realize data writing. In this embodiment, the scan driving circuit for providing scan signals to the pixel driving circuit (also called the second scan driving circuit) and the scan driving circuit for transmitting data voltage to the corresponding pixel driving circuit to realize data writing (also called the first scan driving circuit) are disposed separately. In other embodiments, they can be integrated together. By optimizing the scan drive circuit, a stable high-level output is ensured. At low frequencies, the GIP signal controlling data writing only needs to be written once per frame, while no output is required for the hold frame. This reduces the power consumption of the DDIC (Driver Display Chip) in low-frequency scenarios during the hold frame stage. A ninth transistor T9 is placed at the second terminal of the fourth transistor T4 to reduce leakage current and stabilize the gate voltage of the sixth transistor T6. This makes the sixth transistor T6 less prone to accidental triggering (turn-off / cut-off), leading to abnormal output and thus reducing the power consumption of the DDIC (Driver Display Chip) in low-frequency scenarios (such as 60Hz, 50Hz, 45Hz, 40Hz, 35Hz, 30Hz, 25Hz, 20Hz, 15Hz, 10Hz, 5Hz, 1Hz).

[0059] The scanning drive circuit, display panel, and display device proposed in this application will now be described with reference to the accompanying drawings.

[0060] like Figure 2 The above is a schematic diagram of the display panel according to an embodiment of this application.

[0061] The display panel 100 includes a display area 110 (also called area AA) and a non-display area 120 (also called area A) located at least on one side of the periphery of the display area 110. The non-display area 120 is provided with a border area 121 and a bonding area 122, the bonding area being used to mount an analog driver IC and bonding components in subsequent processes.

[0062] The display area 110 includes an array of light-emitting units, each of which includes multiple pixels, such as red pixels, green pixels, and blue pixels. In this embodiment, the arrangement of the red, green, and blue pixels is not limited. Each pixel is matched with a pixel driving circuit and a light-emitting module.

[0063] like Figure 3 As shown Figure 2 A cross-sectional view of the display panel.

[0064] In the thickness direction (z direction) of the display panel, the display panel includes a substrate 130, a driving layer 140 and a light-emitting functional layer 150.

[0065] The substrate 130 covers the display area and the non-display area. It is a flexible substrate and the material can be selected from polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET). The substrate 130 can also be a rigid substrate, such as glass.

[0066] The driving layer 140 is disposed on one side of the substrate 130. The driving layer 140 includes a pixel driving circuit located in the display area, which is matched and connected to the corresponding pixel to drive the light-emitting module to emit light, and a scanning driving circuit disposed in the non-display area. The pixel driving circuit adopts an LTPO type driving circuit. It should be noted that the display panel may also include other functional structures. For example, the display panel may also include an identification structure to have fingerprint recognition functionality. For example, the identification structure may be a touch panel or a touch layer. The touch panel can be bonded into the display panel to facilitate a thinner and lighter design of the display panel.

[0067] The driving layer includes a stacked semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and an interlayer insulating film layer disposed between adjacent conductive film layers. The combination of traces in the semiconductor layer and the first metal layer forms a transistor; the combination of traces in the first metal layer and the second metal layer forms a storage capacitor; multiple signal lines with different orientations are provided in the third and fourth metal layers, or in the second, third, and fourth metal layers. Corresponding signal lines are electrically connected to the transistors and storage capacitors, thereby forming a pixel driving circuit in the display area, as well as scan lines, data lines, and a scan driving circuit.

[0068] In one embodiment, the scan driving circuit includes a first scan driving circuit and a second scan driving circuit. The first scan driving circuit is used for data writing (also known as data voltage writing), and the second scan driving circuit is used for outputting a gate scan signal. In practical applications, the scan driving circuit also includes a reset driving circuit and an EM driving circuit, which are existing technologies and will not be described in detail here.

[0069] The second scan driving circuit includes cascaded shift registers, each connected to a corresponding scan line, which provides a scan signal to the corresponding row of pixels. Each column of pixels is connected to a corresponding data line, which is electrically connected to the second scan driving circuit. The second shift register provides a scan signal to the pixel driving circuit through the scan line. Corresponding to the duration of the on-potential of the scan signal, the first scan driving circuit transmits data voltage to the corresponding pixel driving circuit through the corresponding data line to realize data writing. Each pixel is displayed according to the data voltage. This is prior art and will not be described in detail here.

[0070] In one embodiment, the first scan driving circuit and / or the second scan driving circuit may be disposed on the side of the driving layer below the pixel driving circuit, such as in the middle of the display area of ​​the display panel. The first scan driving circuit and / or the second scan driving circuit may also be located in the border area on both sides of the display area.

[0071] In one embodiment, the first scan driving circuit includes an input module, a driving module, and a correction module. The input module is connected to the driving module and inputs a first input signal to the control terminal of the driving module. The connection between the input module and the driving module includes a first potential node, and the control terminal of the driving module is connected to the first potential node. The correction module is connected to the first potential node and is used to control the first potential node to maintain a control voltage. The correction module includes a first capacitor, one end of which is connected to the control terminal of the driving module. The circuit outputs a CK signal when it is working and a VHG signal when it is not working. By optimizing the topology of the input module, the voltage at the first potential node is stabilized, preventing the sixth transistor T6 in the driving module from being easily turned off / cut off (this turning off / cutoff is caused by the voltage of the first potential node N1 being raised), thus enabling the first scan driving circuit to stably output a high level.

[0072] The first scan driving circuit proposed in this application will now be described in detail with reference to the accompanying drawings, such as... Figure 4 The diagram shows the topology of the first scan drive circuit of this application.

[0073] The first scan drive circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2 (abbreviated as 9T2C). The combination of the fourth transistor T4 and the ninth transistor T9 is called the first transistor module, wherein:

[0074] The second terminal of the first transistor T1 is electrically connected to a voltage source (SIN), which can be either a low or high potential. The first terminal of the first transistor T1 is electrically connected to the second terminal of the second transistor T2, the gate of the fourth transistor T4, the gate of the ninth transistor T9, and the first terminal of the eighth transistor T8.

[0075] The first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3.

[0076] The first electrode of the third transistor T3 is electrically connected to a constant high potential VHG.

[0077] The gate of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4, the first terminal of the fifth transistor T5, the first potential node N1, the first terminal of the first capacitor C1, and the gate of the sixth transistor T6.

[0078] The second terminal of the first capacitor C1 is electrically connected to the constant high potential VHG and the first terminal of the sixth transistor T6. The first capacitor C1 is used to stabilize the voltage of the gate of TFT6.

[0079] The second electrode of the sixth transistor T6 is electrically connected to the output terminal OUT.

[0080] The first terminal of the seventh transistor T7 is electrically connected to the output terminal OUT and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the gate of the seventh transistor T7 and the second terminal of the eighth transistor T8. The second capacitor C2 acts as a bootstrap capacitor (the second capacitor C2 is used to reduce the voltage at the gate of the seventh transistor TFT7) to ensure that the seventh transistor T7 is turned on.

[0081] The second terminal of the fourth transistor T4 is electrically connected to the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 is connected to the timing signal SCK1.

[0082] The gate of the first transistor T1 is controlled by timing signal SCK1, and the gate of the second transistor T2 is controlled by timing signal SCK2. The second terminal of the seventh transistor T7 is connected to timing signal SCK2.

[0083] The gate of the eighth transistor T8 is electrically connected to a constant low potential (VGL).

[0084] The second terminal of the fifth transistor T5 is electrically connected to a constant low potential (VGL). The gate of the fifth transistor T5 is electrically connected to the timing signal SCK1. The second terminal of the ninth transistor T9 is electrically connected to the timing signal SCK1. This design places the ninth transistor T9 at the second terminal of the fourth transistor T4. The combination of the fourth transistor T4 and the ninth transistor T9 forms a dual-gate structure, reducing leakage current. The voltage of the first potential node N1 is stable, and the sixth transistor T6 is less likely to be turned off / cut off. This first scan drive circuit can stably output a high level, enabling the entire circuit SCK (a collective term for SCK1 / SCK2) to achieve a 1 / 4, 1 / 8, or even higher frequency reduction measure to reduce the power consumption of the DDIC (reducing the power consumption of the DDIC at low frequencies). This first scan drive circuit can be matched with the current mainstream 8T1C / 8T2C type pixel drive circuit (LTPO type). Compared to the current 8T2C type GIP circuit, which maintains a high-frequency operation of 120Hz, the 8T2C type GIP circuit does not need to maintain output operation in low-frequency applications (such as 60Hz, 50Hz, 45Hz, 40Hz, 35Hz, 30Hz, 25Hz, 20Hz, 15Hz, 10Hz, 5Hz, 1Hz). The SCK signal does not need frequent high / low voltage switching at low frequencies (infrequent switching reduces power consumption). Therefore, the applicant proposes to improve the input module by placing a ninth transistor at the fourth transistor T4. T9 (combined to form a structure similar to a dual-gate transistor) stabilizes the voltage of the first potential node N1, making it less likely for the sixth transistor T6 to be turned off. This allows the first scan drive circuit to stably output a high level (while the current 8T2C type GIP scan drive circuit, after RA evaluation, is prone to forward bias in its fourth transistor T4, leading to increased leakage current, raising the voltage of the first potential node N1, and turning off / cutting off the sixth transistor T6, resulting in an unstable high level output). This, in turn, enables the SCK signal to achieve a 1 / 4, 1 / 8, or even higher frequency reduction measure, reducing power consumption in low-frequency applications. In this embodiment, the signals are described as follows: SIN (Start Input Signal), the start pulse signal: triggers the start operation of the shift register in the trigger circuit, marking the beginning of a frame scan. Timing requirements dictate that it must be strictly synchronized with the SCK1 / SCK2 clock signals to avoid scan misalignment, and matched with VGH / VGL (e.g., high level for VGH, low level for VGL). SCK1 / SCK2 (Shift Clock 1 / 2) clock drive signals: provide alternating clock pulses for the shift register, control the row-by-row output of the gate drive signals. SCK1 and SCK2 are usually out of phase (180° phase difference) to achieve the step-by-step scan timing.VGH (Gate High Voltage), high-level drive voltage: used to turn on the TFT (thin-film transistor) in the pixel unit, enabling it to conduct for data writing; VGL (Gate Low Voltage), low-level turn-off voltage: ensures the TFT is completely turned off during non-operating phases, preventing leakage current from causing display abnormalities. In these examples, by setting the SCK1 / SCK2 signals, when the LTPO type pixel driving circuit is in the hold frame phase, the GIP signal controlling data writing only needs to be written to the frame output once in low-frequency mode, thereby reducing the power consumption of the DDIC (Driver Display Chip) in low-frequency situations during the hold frame phase.

[0085] The driving timing of the first scan driving circuit is as follows: Figure 5 As shown, the data refresh cycle includes write frames and hold frames. In the hold frame stage, the frequency is reduced by the above method, which can reduce the power consumption of the DDIC (Driver Display Chip) in the low-frequency situation of the hold frame stage.

[0086] like Figure 6 The diagram shows a topology of the mainstream 8T1C type pixel driving circuit.

[0087] A schematic diagram of the pixel driving circuit topology. The pixel driving circuit includes: a driving module, a data writing module, a threshold compensation module, a first initialization module, a second initialization module, a third initialization module, and a light-emitting module. The driving module generates a driving current based on the voltage at the control terminal to drive the light-emitting module to emit light. The data writing module is used to write data voltage to the control terminal of the driving module. The driving module includes a first transistor T10, the first terminal of which is connected to the second terminal of transistor T50 and the third initialization module transistor. The first terminal of transistor T50 is electrically connected to the storage capacitor C1 and the ELVDD terminal. The second terminal of the first transistor T10 is connected to the first terminal of transistor T60 and the second initialization module. The second terminal of transistor T60 is connected to the second initialization module and the light-emitting module. The data writing module includes a second transistor T20. The threshold compensation module includes a third transistor module 30, which includes two transistors. The first initialization module includes a fourth transistor module 40, which includes two transistors. The second initialization module includes a seventh transistor T70. The third initialization module includes an eighth transistor T80. The storage capacitor module includes a storage capacitor C10. The working principle of this pixel driving circuit (“8T1C”) is existing technology and will not be described in detail here. This pixel driving circuit is an LTPO (Low Temperature Polysilicon Oxide) driving circuit. In this pixel driving circuit (“8T2C”), two storage capacitors (data storage capacitors) are used, or one capacitor is used as the storage capacitor (data storage capacitor) and the other capacitor is used as a dynamic compensation capacitor, located between the second terminal of the first transistor T10 (to adjust the source potential of the first transistor T10 and offset the threshold drift) and the data scan line.

[0088] As Figure 4 Variations of the implementation method are as follows Figure 7 The diagram shows a topology of a first scan driving circuit according to another embodiment of this application.

[0089] The first scan drive circuit includes:

[0090] The transistors are: first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, ninth transistor T9, tenth transistor T10, first capacitor C1, and second capacitor C2. The combination of seventh transistor T7 and tenth transistor T10 is called the second transistor module, wherein:

[0091] The second terminal of the first transistor T1 is electrically connected to a voltage source (SIN), which can be either a low or high potential. The first terminal of the first transistor T1 is electrically connected to the second terminal of the second transistor T2, the gate of the fourth transistor T4, the gate of the ninth transistor T9, and the first terminal of the eighth transistor T8.

[0092] The first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3.

[0093] The first electrode of the third transistor T3 is electrically connected to a constant high potential VHG.

[0094] The gate of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4, the first terminal of the fifth transistor T5, the first potential node N1, the first terminal of the first capacitor C1, and the gate of the sixth transistor T6.

[0095] The second terminal of the first capacitor C1 is electrically connected to the constant high potential VHG and the first terminal of the sixth transistor T6. The first capacitor C1 is used to store the data voltage of the gate of TFT6.

[0096] The second electrode of the sixth transistor T6 is electrically connected to the output terminal OUT.

[0097] The first terminal of the seventh transistor T7 is electrically connected to the output terminal OUT and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the gate of the seventh transistor T7 and the second terminal of the eighth transistor T8. The second capacitor C2 acts as a bootstrap capacitor (the second capacitor C2 is used to store the data voltage of the gate of TFT7), boosting the voltage of the seventh transistor T7.

[0098] The second terminal of the fourth transistor T4 is electrically connected to the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 is connected to the timing signal SCK1.

[0099] The gate of the first transistor T1 is controlled by timing signal SCK1, and the gate of the second transistor T2 is controlled by timing signal SCK2. The second terminal of the seventh transistor T7 is connected to timing signal SCK2.

[0100] The gate of the tenth transistor T10 is electrically connected to the gate of the seventh transistor T7 and the second terminal of the second capacitor C2. The first terminal of the tenth transistor T10 is electrically connected to the second terminal of the seventh transistor T7. The second terminal of the tenth transistor T10 is electrically connected to the timing signal SCK2.

[0101] The gate of the eighth transistor T8 is electrically connected to a constant low potential (VGL).

[0102] The second terminal of the fifth transistor T5 is electrically connected to a constant low potential (VGL). The gate of the fifth transistor T5 is electrically connected to the timing signal SCK1. The second terminal of the ninth transistor T9 is electrically connected to the timing signal SCK1. This design places the ninth transistor T9 at the second terminal of the fourth transistor T4 and the tenth transistor T10 at the seventh transistor T7. The combination of the fourth transistor T4 and the ninth transistor T9 forms a dual-gate structure, reducing leakage current and stabilizing the voltage of the first potential node N1. The sixth transistor T6 is less likely to be turned off / cut off. The combination of the seventh transistor T7 and the tenth transistor T10 forms a dual-gate structure, preventing leakage current from occurring after reliability analysis (RA) and causing output abnormalities. This allows the first scan drive circuit to stably output a high level. During the holding frame stage, the entire scan drive circuit SCK (a collective term for SCK1 / SCK2) implements a 1 / 3, 2, or even higher frequency reduction measure to reduce the power consumption of DDIC (reducing the power consumption of DDIC at low frequencies, such as 60Hz, 50Hz, 45Hz, 40Hz, 35Hz, 30Hz, 25Hz, 20Hz, 15Hz, 10Hz, 5Hz, 1Hz). The first scan drive circuit can be matched with the LTPO type pixel drive circuit with the topology of 8T1C / 8T2C to reduce power consumption in low frequency applications and has a lower risk after reliability analysis (RA).

[0103] This embodiment provides a display device including the aforementioned display panel, which includes any type of scanning drive circuit. The display device includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-book readers, televisions, access control systems, smart landline phones, control consoles, and in-vehicle display devices (such as in-vehicle widescreen displays). Preferably, the scanning drive circuit may include a first scanning drive circuit and a second scanning drive circuit. The second scanning drive circuit provides a scanning signal to a matched pixel drive circuit via a scan line. Corresponding to the conduction potential duration of the scanning signal, the first scanning drive circuit transmits data voltage to the pixel drive circuit via a corresponding data line, which can reduce the power consumption of the DDIC (Driver Display Chip) in low-frequency situations during the hold-frame stage. At low frequencies, the GIP signal controlling data writing only needs to be written once for frame output, while the holding frame does not need to be output. Based on this, this application proposes to set a ninth transistor T9 at the second terminal of the fourth transistor T4, or simultaneously set a ninth transistor T9 at the second terminal of the fourth transistor T4 and a tenth transistor T10 at the seventh transistor T7, to reduce leakage current and stabilize the voltage of the first potential node N1 (the gate of the sixth transistor T6). The stable voltage applied to the gate of the sixth transistor T6 makes it less likely for the sixth transistor T6 to be turned off / cut off (this being turned off / cut off is caused by the voltage of the first potential node N1 being raised). The combination of the seventh transistor T7 and the tenth transistor T10 forms a dual-gate structure to prevent leakage current from occurring after reliability analysis (RA), which would lead to output abnormalities, so that the first scan drive circuit can stably output a high level.

[0104] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0105] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized in that, include: The display area and at least part of the non-display area located on one side of the periphery of the display area. The display panel includes a substrate and a driving layer. The driving layer is disposed on one side of the substrate, and includes a pixel driving circuit located in the display area and a scan driving circuit located at least partially in the non-display area. The scan driving circuit is connected to the pixel driving circuit located in the display area via wiring matching. The scanning driving circuit includes an input module and a driving module. The connection between the input module and the driving module includes a first potential node. The input module includes a first transistor module, which is configured to have a dual-gate structure and is electrically connected to the first potential node. The input module inputs a first input signal to the control terminal of the drive module, and the drive module is configured to output a signal to the matching pixel drive circuit in response to the first input signal.

2. The display panel as described in claim 1, characterized in that, The scanning drive circuit includes a first scanning drive circuit and a second scanning drive circuit. The second scanning drive circuit provides a scanning signal to the matched pixel drive circuit through a scanning line. Corresponding to the conduction potential duration of the scanning signal, the first scanning drive circuit transmits data voltage to the pixel drive circuit through a corresponding data line.

3. The display panel as described in claim 2, characterized in that, The first scanning drive circuit and / or the second scanning drive circuit are disposed in the border areas on both sides of the display area or in the middle of the display area.

4. The display panel as described in claim 1, characterized in that, The pixel driving circuit is an LTPO type driving circuit; Preferably, the pixel driving circuit has a topology of 8T1C or 8T2C.

5. The display panel as described in any one of claims 1-4, characterized in that, The input module includes a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5, and an eighth transistor T8. The first transistor module includes a fourth transistor T4 and a ninth transistor T9. The second terminal of the first transistor T1 is electrically connected to the voltage source SIN, and the first terminal of the first transistor T1 is electrically connected to the second terminal of the second transistor T2, the gate of the fourth transistor T4, the gate of the ninth transistor T9, and the first terminal of the eighth transistor T8. The first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3; The first electrode of the third transistor T3 is electrically connected to a constant high potential VHG. The gate of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4, the first terminal of the fifth transistor T5, and the first potential node N1. The second terminal of the fourth transistor T4 is electrically connected to the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 is connected to the timing signal SCK1; The gate of the first transistor T1 is controlled by timing signal SCK1, and the gate of the second transistor T2 is controlled by timing signal SCK2; the gate of the eighth transistor T8 is electrically connected to a constant low potential VGL. The second electrode of the fifth transistor T5 is electrically connected to a constant low potential VGL, and the gate of the fifth transistor T5 is electrically connected to the timing signal SCK1. The second terminal of the ninth transistor T9 is electrically connected to the timing signal SCK1.

6. The display panel as described in claim 5, characterized in that, The driving module includes a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The second terminal of the first capacitor C1 is electrically connected to the constant high potential VHG and the first terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is electrically connected to the output terminal OUT. The first terminal of the first capacitor C1 is electrically connected to the gate of the sixth transistor T6; The first terminal of the seventh transistor T7 is electrically connected to the output terminal OUT and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the gate of the seventh transistor T7 and the second terminal of the eighth transistor T8. The second capacitor C2 serves as a bootstrap capacitor. The second terminal of the seventh transistor T7 is connected to the timing signal SCK2.

7. The display panel as described in claim 5, characterized in that, The driving module includes an output terminal and a second transistor module. The second transistor module is configured with a dual-gate structure and is electrically connected to the output terminal. It is connected to the pixel driving circuit located in the display area via a wiring match. The pixel driving circuit is an LTPO type driving circuit.

8. The display panel as described in claim 7, characterized in that, The driving module includes a sixth transistor T6, a second transistor module, a first capacitor C1 and a second capacitor C2, and the second transistor module includes a seventh transistor T7 and a tenth transistor T10. The second terminal of the first capacitor C1 is electrically connected to the constant high potential VHG and the first terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is electrically connected to the output terminal. The first terminal of the first capacitor C1 is electrically connected to the gate of the sixth transistor T6; The first terminal of the seventh transistor T7 is electrically connected to the output terminal OUT and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the gate of the seventh transistor T7, the second terminal of the eighth transistor T8, and the gate of the tenth transistor T10. The second terminal of the seventh transistor T7 is electrically connected to the first terminal of the tenth transistor T10. The second terminal of the tenth transistor T10 is connected to the timing signal SCK2.

9. The display panel as described in claim 5, characterized in that, Timing signals SCK1 and SCK2 are out of phase, with a phase difference of 180°.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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