Display panel and display device

Abstract

The display panel and the display device are provided, the display area includes a first display area and a second display area located on opposite sides of the first display area in a first direction, the non-display area includes a first frame area and a second frame area located on opposite sides of the second display area in a second direction, a plurality of pixel unit columns include a plurality of second pixel unit columns located in the second display area, at least part of a plurality of demultiplexers is located in the second frame area and on a side of the corresponding second pixel unit column away from the display area in the second direction, a plurality of first compensation capacitor groups are located in the first frame area and on a side of the corresponding second pixel unit column away from the display area in the second direction, and a plurality of second compensation capacitor groups are located in the second frame area and between the corresponding second pixel unit column and the demultiplexer, so that the area of the first frame area can be reduced by arranging the first compensation capacitor groups and the second compensation capacitor groups, and narrow frame can be realized.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products. "Screen ratio" has become a relatively important performance parameter of display devices. Narrow bezels or even full-screen displays have become a new trend in the development of OLED display products. Therefore, narrow bezels or even bezel-less designs are receiving more and more attention in the design of OLED display products. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is to provide a display panel and a display device. The display panel has a narrow bezel.

[0004] The present invention discloses a display panel including a display area and a non-display area at least partially surrounding the display area. The display area includes a first display area and a second display area, the second display area being located on opposite sides of the first display area in a first direction. The non-display area includes a first border area and a second border area, the first border area and the second border area being located on opposite sides of the second display area in a second direction, the first direction intersecting the second direction.

[0005] Multiple pixel unit columns are arranged along the second direction in the display area, the multiple pixel unit columns including multiple first pixel unit columns located in the first display area and multiple second pixel unit columns located in the second display area;

[0006] Multiple demultiplexers are provided, at least a portion of which are located in the second border area. The demultiplexers are located on the side of the corresponding second pixel unit column away from the display area in the second direction, and the demultiplexers are electrically connected to the corresponding second pixel unit column.

[0007] Multiple first compensation capacitor groups are located in the first border area, and the first compensation capacitor groups are located on the side of the corresponding second pixel unit column away from the display area in the second direction. The first compensation capacitor groups are electrically connected to the corresponding second pixel unit column.

[0008] Multiple second compensation capacitor groups are located in the second border area. The second compensation capacitor groups are located on the side of the corresponding second pixel unit column away from the display area in the second direction and on the side of the multiplexer close to the corresponding second pixel unit column. The second compensation capacitor groups are electrically connected to the corresponding second pixel unit column.

[0009] In one embodiment, each pixel unit column includes a plurality of sub-pixel columns arranged along the first direction, and each sub-pixel column includes a plurality of sub-pixels arranged along the second direction;

[0010] Preferably, the number of sub-pixels in each sub-pixel column within the same pixel unit column is the same, while the number of sub-pixels in each sub-pixel column within different pixel unit columns is not entirely the same;

[0011] Preferably, the number of sub-pixels in each sub-pixel column is the same in each of the first pixel unit columns;

[0012] Preferably, the number of sub-pixels in each sub-pixel column of the first pixel unit column is greater than the number of sub-pixels in each sub-pixel column of the second pixel unit column;

[0013] Preferably, the number of sub-pixels in each sub-pixel column within each second pixel unit column is not exactly the same, but the number of sub-pixels in each sub-pixel column within the same second pixel unit column is the same;

[0014] Preferably, the number of sub-pixels in each sub-pixel column of the second pixel unit column closer to the first display area is greater than the number of sub-pixels in each sub-pixel column of the second pixel unit column farther from the first display area.

[0015] In one embodiment, the display panel further includes:

[0016] Multiple data signal line groups are arranged along the first direction in the display area, and the data signal line groups are electrically connected to the corresponding pixel unit columns.

[0017] The plurality of data signal line groups include a first data signal line group located in the first display area and a second data signal line group located in the second display area. The first data signal line group is electrically connected to the first pixel unit column, and the second data signal line group is electrically connected to the second pixel unit column.

[0018] Preferably, each of the data signal line groups includes a plurality of data signal lines arranged along a majority first direction, the data signal lines being electrically connected to the corresponding sub-pixel column;

[0019] Preferably, the data signal lines in the same group of data signal lines have the same extension length;

[0020] Preferably, the extension length of the data signal line in the first data signal line group is greater than the extension length of the data signal line in the second data signal line group;

[0021] Preferably, the extension length of the data signal line in the second data signal line group closer to the first display area is greater than the extension length of the data signal line in the second data signal line group farther from the first display area.

[0022] In one embodiment, each of the first compensation capacitor groups includes a plurality of upper compensation capacitors arranged along the second direction, the upper compensation capacitors being electrically connected to the corresponding sub-pixel column;

[0023] Preferably, the compensation capacitor shown is electrically connected to the corresponding data signal line;

[0024] Preferably, each of the second compensation capacitor groups includes a plurality of lower compensation capacitors arranged along the second direction, and the upper compensation capacitors are electrically connected to the corresponding sub-pixel column;

[0025] Preferably, the lower compensation capacitor is electrically connected to the corresponding data signal line;

[0026] Preferably, both the upper compensation capacitor and the upper compensation capacitor are strip-shaped extending along the first direction.

[0027] In one embodiment, the capacitance values ​​of the first compensation capacitor group and / or the second compensation capacitor group are negatively correlated with the number of pixel units in the second pixel unit column;

[0028] Preferably, the capacitance values ​​of the upper compensation capacitor and / or the lower compensation capacitor are negatively correlated with the number of sub-pixels in the sub-pixel column.

[0029] In one embodiment, the upper compensation capacitor includes a first plate and a second plate, the first plate and the second plate are on different layers and insulated from each other, and the first plate is disposed on the same layer as the data signal line and is electrically connected to the data signal line.

[0030] Preferably, the lower compensation capacitor includes a third plate and a fourth plate, the third plate and the fourth plate are on different layers and insulated from each other, the third plate is disposed on the same layer as the data signal line and is electrically connected to the data signal line;

[0031] Preferably, the first electrode plate of the upper compensation capacitor and the third electrode plate of the lower compensation capacitor are disposed in the same layer;

[0032] Preferably, the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor are disposed in the same layer, or the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor are disposed in different layers.

[0033] In one embodiment, the display panel further includes a substrate and at least two metal layers disposed on the substrate, wherein the first electrode and the second electrode of the upper compensation capacitor are respectively located in different metal layers, and the third electrode and the fourth electrode of the lower compensation capacitor are respectively located in different metal layers;

[0034] Preferably, the orthographic projections of the first and second plates of the upper compensation capacitor on the substrate at least partially overlap, and the orthographic projections of the third and fourth plates of the lower compensation capacitor on the substrate at least partially overlap.

[0035] Preferably, the at least two metal layers include a first metal layer and a second metal layer, the second metal layer is located on the side of the first metal layer away from the substrate, the first electrode of the upper compensation capacitor and the third electrode of the lower compensation capacitor are both located in the first metal layer, and the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor are both located in the second metal layer.

[0036] Preferably, the second plates of the plurality of upper compensation capacitors are connected as one unit, and the fourth plates of the plurality of lower compensation capacitors are connected as one unit;

[0037] Preferably, the at least two metal layers further include a third metal layer, the third metal layer being located on the side of the first metal layer closer to the substrate, the first electrode of the upper compensation capacitor and the third electrode of the lower compensation capacitor being located in the first metal layer, and the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor being located in the third metal layer.

[0038] Alternatively, the second electrode of the upper compensation capacitor may be located in the second metal layer, and the fourth electrode of the lower compensation capacitor may be located in the third metal layer.

[0039] Alternatively, the second electrode of the upper compensation capacitor may be located in the third metal layer, and the fourth electrode of the lower compensation capacitor may be located in the second metal layer.

[0040] In one embodiment, the display panel further includes:

[0041] Multiple fan-out signal lines, at least a portion of each fan-out signal line is located in the display area, the fan-out signal line is electrically connected to the corresponding multiplexer, and the multiplexer is electrically connected to the multiple data signal lines in the corresponding data signal line group;

[0042] Preferably, each of the fan-out signal lines includes a first fan-out segment extending along the second direction and a second fan-out segment extending along the second direction, the second fan-out segment being electrically connected to the corresponding multiplexer.

[0043] In one embodiment, the display panel further includes:

[0044] Multiple connection signal line groups are located in the second frame area, and the connection signal line groups are connected to the corresponding second compensation capacitor group and the multiplexer;

[0045] Preferably, each connection signal line group includes a plurality of connection signal lines arranged along a first direction, the connection signal lines being connected to a corresponding lower compensation capacitor and a multiplexer.

[0046] Based on the same inventive concept, this disclosure also provides a display device, which includes a display panel as described above.

[0047] Compared with the prior art, the display panel and display device provided in this disclosure, by setting a second compensation capacitor group and a second compensation capacitor group on the upper and lower sides of the second pixel unit column respectively, can, on the one hand, achieve the effect of compensating the capacitance of the data line group corresponding to the second pixel unit column, and the voltage fluctuation of the data line group corresponding to the pixel unit column of the second display area is the same as that of the data line group corresponding to the pixel unit column of the first display area under the influence of the first compensation capacitor group and the second compensation capacitor group; on the other hand, it can reduce the area of ​​the first border area, which is conducive to achieving a narrow border. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art;

[0050] Figure 2 A schematic diagram of the display panel provided in this application embodiment;

[0051] Figure 3 A schematic diagram of pixel unit arrangement provided in the embodiments of this application;

[0052] Figure 4 This application provides a schematic diagram of a portion of the structure of a display panel. Figure 1 ;

[0053] Figure 5 This application provides a schematic diagram of a portion of the structure of a display panel. Figure 2 ;

[0054] Figure 6 This application provides a schematic diagram of a portion of the structure of a display panel. Figure 3 ;

[0055] Figure 7 A partial cross-sectional view of the display panel provided in the embodiments of this application. Figure 1 ;

[0056] Figure 8 A partial cross-sectional view of the display panel provided in the embodiments of this application. Figure 2 ;

[0057] Figure 9 A partial cross-sectional view of the display panel provided in the embodiments of this application. Figure 3 . Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0059] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0060] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0061] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0062] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, an intermediate component may exist on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or indirectly "installed to" or "connected to" another component via an intermediate component.

[0063] refer to Figure 1 In related technologies, when the display panel is an irregularly shaped display panel, the number of pixel units P in each pixel unit column is not completely the same, and the length of the data line groups connecting each pixel unit P0 is also not completely the same. This results in different loads on data line groups of different lengths, leading to differences in load capacitance and thus different signal delay times between them. Inconsistent signal delay times can degrade image quality, causing problems such as water ripples and uneven brightness. Currently, most solutions involve setting up compensation capacitor groups in the upper R-corner bezel area of ​​the display panel to compensate for the capacitance of the corresponding data line groups, thereby reducing the capacitance difference between the data line groups corresponding to different pixel unit columns of the display panel, improving the consistency of the input signal, and improving display quality. However, compensation capacitor groups are usually only set in the upper bezel area B0 (set in the upper R-corner bezel area), and in order to reduce the impact of parasitic capacitance generated by adjacent compensation capacitor groups on the data line groups, the width of the compensation capacitor group is limited by the spacing between adjacent data line groups, resulting in a generally long length of the compensation capacitor group. This leads to a larger overall area of ​​the upper bezel area B0 of the display panel (especially the upper R-corner bezel area), which significantly reduces the screen-to-body ratio of the display panel.

[0064] As mentioned earlier, with technological advancements, there are increasing demands for narrower bezels on display panels. Therefore, to meet these demands, continuous improvement of the layout of the non-display area (NAA) of the display panel is necessary. In particular, for display panels with irregular contours, achieving narrow bezels requires significantly more design effort compared to conventional rectangular display panels, resulting in a more compact and aesthetically pleasing layout.

[0065] refer to Figures 2-9Therefore, this application provides a display panel and a display device. The display panel includes a display area AA and a non-display area NAA surrounding the display area AA. The display area AA includes a first display area A1 and a second display area A2. The second display area A2 is located on opposite sides of the first display area A1 in a first direction (X direction). The non-display area NAA includes a first border area B1 and a second border area B2. The first border area B1 and the second border area B2 are respectively located on opposite sides of the second display area A2 in a second direction (Y direction). The display panel also includes a plurality of pixel unit columns 10, a plurality of multiplexers 20, and a plurality of first... The system includes a compensation capacitor group 30 and multiple second compensation capacitor groups 40. Multiple pixel unit columns 10 are arranged along a first direction (X direction) in the display area AA, intersecting with a second direction (Y direction). The multiple pixel unit columns 10 include multiple first pixel unit columns 10A located in the first display area A1 and multiple second pixel unit columns 10B located in the second display area A2. At least a portion of multiple demultiplexers 20 are located in the second border area B2. The demultiplexers 20 are located on the side of the corresponding pixel unit column 10 away from the display area AA in the second direction (Y direction). The corresponding pixel unit column 10 is electrically connected; multiple first compensation capacitor groups 30 are located in the first border area B1, and the first compensation capacitor groups 30 are located on the side of the corresponding second pixel unit column 10B away from the display area AA in the second direction (Y direction), and the first compensation capacitor groups 30 are electrically connected to the corresponding second pixel unit column 10B; multiple second compensation capacitor groups 40 are located in the second border area B2, and the second compensation capacitor groups are located on the side of the corresponding second pixel unit column 10B away from the display area AA in the second direction (Y direction) and on the side of the multiplexer 20 close to the corresponding second pixel unit column 10B, the second compensation... The compensation capacitor group 40 is electrically connected to the corresponding second pixel unit column 10B. In this embodiment, the second compensation capacitor group 40 and the second compensation capacitor group 40 are respectively provided on the upper and lower sides of the second pixel unit column 10B (i.e., opposite sides in the second direction (Y direction)). On the one hand, it can play the role of compensating the capacitance of the data line group corresponding to the second pixel unit column. Moreover, the voltage fluctuation of the data line group corresponding to the pixel unit column of the second display area is the same as that of the data line group corresponding to the pixel unit column of the first display area under the influence of the first compensation capacitor group and the second compensation capacitor group. On the other hand, it can reduce the area of ​​the first border area, which is conducive to achieving a narrow border.

[0066] Next, combine Figures 2-6 This application describes the display panel provided in the embodiments of the present application.

[0067] The display panel includes a display area AA and a border area surrounding the display area AA. The display area AA includes a first display area A1 (also called the main display area AA) and a second display area A2 (also called the edge display area AA). The second display area A2 is located on opposite sides of the first display area A1 in the first direction (X direction). The border area includes a first border area B1 (also called the first corner area) and a second border area B2 (also called the second corner area). The first border area B1 and the second border area B2 are located on opposite sides of the second display area A2 in the second direction (Y direction). The first direction (X direction) intersects with the second direction (Y direction). The border area also includes a third border area B3 (also called the bound border area). The third border area B3 is located on one side of the first display area A1 in the second direction (Y direction) and is connected to the second border area B2.

[0068] The display area AA of the display panel may include multiple pixel units 100 arranged in an array. That is, the display area AA includes multiple pixel units arranged along a first direction (X direction) and multiple pixel units arranged along a second direction (Y direction). It can also be understood as multiple columns of pixel units arranged along the first direction (X direction). Each column of pixel units 10 includes multiple pixel units 100 arranged along the second direction (Y direction). The number of pixel units 100 in each column of pixel units 10 in the first display area A1 is equal, while the number of pixel units 100 in each column of pixel units 10 in the second display area A2 is not completely equal.

[0069] For example, the plurality of pixel unit columns 10 include a plurality of first pixel unit columns 10A located in the first display area A1 and a plurality of second pixel unit columns 10B located in the second display area A2, wherein the number of pixel units 100 in each of the first pixel unit columns 10A is the same, the number of pixel units in the second pixel unit columns 10B is not exactly the same, the number of pixel units 100 in the first pixel unit columns 10A is greater than the number of pixel units 100 in the second pixel unit columns 10B, the number of pixel units 100 in the second pixel unit columns 10B closer to the first display area A1 is greater than the number of pixel units 100 in the second pixel unit columns 10B farther from the first display area A1, and the number of pixel units 100 in the second pixel unit columns 10B gradually decreases along the direction closer to the non-display area NAA.

[0070] refer to Figure 4In an optional embodiment, each pixel unit column 10 includes a plurality of sub-pixel columns 11 arranged along a first direction (X direction), and each sub-pixel column 11 includes a plurality of sub-pixels 110 arranged along a second direction (Y direction). The number of sub-pixels 110 in each sub-pixel column 11 of the same pixel unit column 10 is the same, the number of sub-pixels 110 in each sub-pixel column 11 of different pixel unit columns 10 is not completely the same, the color of the emitted light from each sub-pixel column 11 of the same pixel unit column 10 is different, and the color of the emitted light from each sub-pixel 110 of the same sub-pixel column 11 is the same.

[0071] The number of sub-pixels 110 in each sub-pixel column 11 of each first pixel unit column 10A is the same. The number of sub-pixels 110 in each sub-pixel column 11 of the first pixel unit column 10A is greater than the number of sub-pixels 110 in each sub-pixel column 11 of the second pixel unit column 10B. The number of sub-pixels 110 in each sub-pixel column 11 of each second pixel unit column 10B is not completely the same. The number of sub-pixels 110 in each sub-pixel column 11 of the same second pixel unit column 10B is the same. In different second pixel unit columns 10B, the number of sub-pixels 110 in each sub-pixel column 11 of the second pixel unit column 10B closer to the first display area A1 is greater than the number of sub-pixels 110 in each sub-pixel column 11 of the second pixel unit column 10B farther from the first display area A1 is greater than the number of sub-pixels 110 in each sub-pixel column 11 of the second pixel unit column 10B further ...

[0072] For example, each pixel unit column 10 includes a first sub-pixel column 11R emitting a first color light, a second sub-pixel column 11B emitting a second color light, and a third sub-pixel column 11G emitting a third color light. The first sub-pixel column 11R includes multiple first sub-pixels 110R arranged along a second direction (Y direction) and emitting the first color light. The second sub-pixel column 11B includes multiple second sub-pixels 110B arranged along a second direction (Y direction) and emitting the second color light. The third sub-pixel column 11G includes multiple third sub-pixels 110G arranged along a second direction (Y direction) and emitting the third color light. For example, the first sub-pixel 110R may be a red sub-pixel emitting red light, the second sub-pixel 110B may be a blue sub-pixel emitting blue light, and the third sub-pixel 110G may be a green sub-pixel emitting green light.

[0073] It should be noted that each sub-pixel 110 in this application may include a pixel driving circuit and a light-emitting unit. The pixel driving circuit is connected to the scan signal line, the data signal line 51, and the light-emitting signal line, respectively. Under the control of the scan signal line and the light-emitting signal line, the pixel driving circuit receives the data signal transmitted by the data signal line 51 and outputs a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel 110 is connected to the corresponding pixel driving circuit, and the pixel driving circuit drives the corresponding light-emitting unit to emit light of a corresponding brightness.

[0074] refer to Figure 6 In one embodiment, the display area AA of the display panel further includes a plurality of data signal line groups 50 arranged along a first direction (X direction). The data signal line groups 50 are electrically connected to the corresponding pixel unit columns 10. The plurality of data signal line groups 50 include a plurality of first data signal line groups 50A located in the first display area A1 and a plurality of second data signal line groups 50B located in the second display area A2. The first data signal line groups 50A are electrically connected to the corresponding first pixel unit columns 10A, and the second data signal line groups 50B are electrically connected to the corresponding second pixel unit columns 10B.

[0075] refer to Figure 6 In an optional embodiment, each data signal line group 50 includes a plurality of data signal lines 51. Each data signal line 51 is connected to each sub-pixel 110 of the corresponding sub-pixel column 11. The data signal lines 51 are used to provide display data to the display area AA. It can be understood that the data signal lines 51 are electrically connected to the pixel driving circuit and are used to transmit display data to the pixel driving circuit, thereby driving the sub-pixel 110 unit 100 in the display area AA to turn on and off through the pixel driving circuit. Since the number of sub-pixels 110 in each sub-pixel column 11 is not exactly the same, the extension length of the data signal line 51 connecting the sub-pixels 110 in each sub-pixel column 11 is also not exactly the same. Along the direction close to the border area, the number of sub-pixels 110 in the sub-pixel column 11 located in the second display area A2 gradually decreases, and the length of the data signal line 51 in the second display area A2 also gradually shortens, resulting in differences in the voltage load of each data signal line 51, which affects the display effect of the display panel. Therefore, in this application, an upper compensation capacitor and a lower compensation capacitor are respectively provided at both ends of the data signal line 51 in the first direction (X direction) in the second display area A2 to reduce the difference in the voltage load of each data signal line 51 and improve the display effect of the display panel.

[0076] For example, each data signal line group 50 includes a first data signal line 51R, a second data signal line 51B, and a third data signal line 51G arranged along a first direction (X direction), wherein the first data signal line 51R is electrically connected to a plurality of first sub-pixels 110R in the first sub-pixel column 11R, the second data signal line 51B is electrically connected to a plurality of second sub-pixels 110B in the second sub-pixel column 11B, and the third data signal line 51G is electrically connected to a plurality of third sub-pixels 110G in the third sub-pixel column 11G.

[0077] In one embodiment, the data signal line 51 of the display area AA needs to be electrically connected to the fan-out signal line 60 output from the integrated circuit (IC) located at the bonding bit. Typically, one fan-out signal line 60 is connected to one data signal line 51, increasing the number of wirings in the non-display area NAA of the display panel. Therefore, in this embodiment, to further reduce the number of wirings in the non-display area NAA, multiple demultiplexers 20 (Demuxes) are provided in the non-display area NAA, wherein at least some of the multiple demultiplexers 20 (Demuxes) are located in the second border area B2. Each demultiplexer 20 in the second border area B2 is located on the side of the corresponding second pixel unit column 10B away from the display area AA in the second direction (Y direction), and each demultiplexer 20 is electrically connected to the corresponding second pixel unit column 10B. Furthermore, each demultiplexer 20 is electrically connected to the corresponding second pixel unit column 10B through a data signal line group 50. In this embodiment, by setting the demultiplexer 20, one fan-out signal line 60 can be electrically connected to multiple data signal lines 51, specifically taking a 1:3 Demux as an example. Here, 1:3 means that one fan-out signal line 60 is electrically connected to three data signal lines 51 through one demultiplexer 20. For example, by setting one demultiplexer 20, one fan-out signal line 60 can be simultaneously electrically connected to the first data signal line 51R, the second data signal line 51B, and the third data signal line 51G. This design further reduces the number of wirings in the non-display area NAA, thereby effectively reducing the area of ​​the border area.

[0078] Taking wearable products as an example, due to their small size, the capacitance difference between adjacent columns of data signal line groups 50 is significant. Therefore, it is necessary to compensate for the capacitance of at least some columns of data signal line groups 50 to control the capacitance difference between columns within a small range. For example, Figure 2 and Figure 3 As shown in the schematic diagram of a wearable watch, multiple first compensation capacitor groups 30 and multiple second compensation capacitor groups 40 can be respectively set in the first frame area B1 and the second frame area B2 of the circular wearable watch to perform capacitance compensation on the corresponding data signal line group 50.

[0079] refer to Figures 2-6In one embodiment, the display panel includes a plurality of first compensation capacitor groups 30 and a plurality of second compensation capacitor groups 40, wherein the first compensation capacitor groups 30 and the second compensation capacitor groups 40 are respectively located on opposite sides of the second pixel unit column 10B in the second direction (Y direction). This design can reduce the design space for capacitor compensation and achieve the effect of reducing the bezel.

[0080] Specifically, the first compensation capacitor group 30 is disposed in the first border area B1, and each first compensation capacitor group 30 is located on the side of the corresponding second pixel unit column 10B away from the display area AA in the second direction (Y direction). Each first compensation capacitor group 30 is electrically connected to the corresponding second pixel unit column 10B, which can also be understood as each first compensation capacitor group 30 being electrically connected to the corresponding second data signal line group 50. Multiple second compensation capacitor groups 40 are located in the second border area B2, and each compensation unit is located on the side of the corresponding second pixel unit column 10B away from the display area AA in the second direction (Y direction) and is located near the corresponding second pixel unit column 10B in the demultiplexer 20. On one side of 0B, each second compensation capacitor group 40 is electrically connected to the corresponding second pixel unit column 10B. This can also be understood as each second compensation capacitor group 40 being electrically connected to the corresponding second data signal line group 50. In this embodiment, second compensation capacitor groups 40 and second compensation capacitor groups 40 are respectively provided on the upper and lower sides of the second pixel unit column 10B (i.e., opposite sides in the second direction (Y direction)). On the one hand, this can compensate for the capacitance of the data signal line group 50. Furthermore, the voltage fluctuation of the data line group corresponding to the pixel unit column 10 in the second display area A2 is affected by the first compensation capacitor group 30 and the second compensation capacitor group 40, similar to that of the data line group corresponding to the pixel unit column 10 in the first display area A1. On the other hand, it can reduce the area of ​​the first border area B1, which is beneficial for achieving a narrow border.

[0081] refer to Figures 2-6 In one optional embodiment, each first compensation capacitor group 30 includes a plurality of upper compensation capacitors 31, each upper compensation capacitor 31 being electrically connected to a corresponding data signal line 51, and the upper compensation capacitor 31 being used to perform capacitance compensation on the data signal line 51; each second compensation capacitor group 40 includes a plurality of lower compensation capacitors 41, each lower compensation capacitor 41 being electrically connected to a corresponding data signal line 51, and the compensation capacitors being used to perform capacitance compensation on the data signal line 51; furthermore, the upper compensation capacitors 31 and the lower compensation capacitor 31 are both strip-shaped extending along a first direction (X direction).

[0082] Furthermore, since the number of pixel units 100 in each pixel unit column 10 of the second display area A2 is not exactly the same, the extension length of each data line group in the corresponding second display area A2 is also not exactly the same. In order to reduce the difference in voltage load of each data signal line 51, the resistance values ​​of each first compensation capacitor group 30 and / or second compensation capacitor group 40 in this embodiment are not exactly the same. Among them, the capacitance value of the first compensation capacitor group 30 of each pixel unit column 10 is negatively correlated with the number of pixel units 100 in that pixel unit column 10, and / or the resistance value of the second compensation capacitor group 40 of each pixel unit column 10 is also negatively correlated with the number of pixel units 100 in that pixel unit column 10. The capacitance value of the compensation capacitor group 40 is negatively correlated with the number of pixel units 100 in the pixel unit column 10. It can be understood that the more pixel units 100 there are in the second pixel unit column 10B located in the second display area A2, the smaller the capacitance value of the first compensation capacitor group 30 and / or the second compensation capacitor group 40 corresponding to the second pixel unit column 10B. Conversely, the fewer pixel units 100 there are in the second pixel unit column 10B located in the second display area A2, the larger the capacitance value of the first compensation capacitor group 30 and / or the second compensation capacitor group 40 corresponding to the second pixel unit column 10B.

[0083] It should be noted that in this embodiment, the fewer the number of sub-pixels 110 connected to the data signal lines 51 corresponding to the lower compensation capacitor 41 and / or the upper compensation capacitor 31, the larger the compensation load value of the lower compensation capacitor 41 and / or the upper compensation capacitor 31. By using lower compensation capacitors 41 and / or upper compensation capacitors 31 with different compensation load values ​​to compensate for data signal lines 51 with different numbers of sub-pixels 110, the load on different data signal lines 51 becomes uniform, avoiding display differences and ensuring display quality.

[0084] For example, the plurality of upper compensation capacitors 31 include a first upper compensation capacitor 31R corresponding to the first sub-pixel column 11R, a second upper compensation capacitor 31B corresponding to the second sub-pixel column 11B, and a third upper compensation capacitor 31G corresponding to the third sub-pixel column 11G. The first upper compensation capacitor 31R is electrically connected to the first data signal line 51R, the second upper compensation capacitor 31B is electrically connected to the second data signal line 51B, and the third upper compensation capacitor 31G is electrically connected to the third data signal line 51G. The plurality of lower compensation capacitors 41 include a first lower compensation capacitor 41R corresponding to the first sub-pixel column 11R, a second lower compensation capacitor 41B corresponding to the second sub-pixel column 11B, and a third lower compensation capacitor 41G corresponding to the third sub-pixel column 11G. The first lower compensation capacitor 41R is electrically connected to the first data signal line 51R, the second lower compensation capacitor 41B is electrically connected to the second data signal line 51B, and the third lower compensation capacitor 41G is electrically connected to the third data signal line 51G.

[0085] refer to Figures 7-9Furthermore, the upper compensation capacitor 31 includes a first plate C1 and a second plate C2. The first plate C1 and the second plate C2 are in different layers and insulated from each other. The first plate C1 is in the same layer as the data signal line and is electrically connected to the data signal line 51. The lower compensation capacitor 41 includes a third plate C3 and a fourth plate C4. The third plate C3 and the fourth plate C4 are in different layers and insulated from each other. The third plate C3 is in the same layer as the data signal line and is electrically connected to the data signal line 51.

[0086] Furthermore, the second plates C2 of multiple upper compensation capacitors 31 are connected as one unit. Specifically, different data signal lines 51 are connected to the first plates C1 of different upper compensation capacitors to avoid display panel malfunctions caused by short circuits in different data signal lines. Simultaneously, connecting the second plates C2 of multiple upper compensation capacitors as one unit not only makes full use of the space in the first bezel area to arrange the second plates C2, maximizing the capacitance value of the upper compensation capacitors, but also simplifies the manufacturing process of the second plates C2 of multiple upper compensation capacitors. Similarly, the fourth plates C4 of multiple lower compensation capacitors are connected as one unit. Specifically, different data signal lines are connected to the third plates C3 of different lower compensation capacitors to avoid display panel malfunctions caused by short circuits in different data signal lines. Simultaneously, connecting the fourth plates C4 of multiple lower compensation capacitors as one unit not only makes full use of the space in the second bezel area to arrange the fourth plates C4, maximizing the capacitance value of the lower compensation capacitors, but also simplifies the manufacturing process of the second plates C2 of multiple lower compensation capacitors.

[0087] refer to Figures 7-9 In one embodiment, in a direction perpendicular to the surface of the display panel, the display panel includes a substrate 200 and at least two metal layers stacked on the substrate 200. The first electrode C1 and the second electrode C2 of the upper compensation capacitor are located in different metal layers, and the third electrode C3 and the fourth electrode C4 of the lower compensation capacitor are located in different metal layers.

[0088] refer to Figure 7In one optional embodiment, at least two metal layers include a first metal layer M1 and a second metal layer M2. The second metal layer M2 is located on the side of the first metal layer M1 facing away from the substrate 200. A first insulating layer 300 is disposed between the first metal layer M1 and the second metal layer M2. The first metal layer M1 may be the gate of a thin-film transistor in a pixel driving circuit. The data signal line is located on the first metal layer M1. The first electrode C1 of the upper compensation capacitor and the third electrode C3 of the lower compensation capacitor are located on the first metal layer M1. The second electrode C2 of the upper compensation capacitor and the fourth electrode C4 of the lower compensation capacitor are located on the second metal layer M2. The orthographic projection of the first electrode C1 on the substrate 200 at least partially overlaps with the orthographic projection of the second electrode C2 on the substrate 200. The first insulating layer 300 serves as a dielectric layer, thereby forming the upper compensation capacitor. The orthographic projection of the third electrode C3 on the substrate 200 at least partially overlaps with the orthographic projection of the fourth electrode C4 on the substrate 200. The first insulating layer 300 serves as a dielectric layer, thereby forming the lower compensation capacitor.

[0089] refer to Figure 8 In another optional embodiment, at least two metal layers include a first metal layer M1, a second metal layer M2, and a third metal layer M3. The second metal layer M2 is located on the side of the first metal layer M1 away from the substrate 200, and the third metal layer M3 is located on the side of the first metal layer M1 close to the substrate 200. A first insulating layer 300 is disposed between the first metal layer M1 and the second metal layer M2, and a second insulating layer 400 is disposed between the first metal layer M1 and the third metal layer M3. The first metal layer M1 may be the gate of the thin-film transistor in the pixel driving circuit, and the third metal layer M3 may be a shielding layer. The shielding layer is located between the active layer of the thin-film transistor in the pixel driving circuit and the substrate 200, which can prevent the light from the backlight from shining on the active layer of the thin-film transistor, thereby reducing the leakage current of the thin-film transistor. The data signal line is located in the first metal layer M1, wherein the first plate C1 of the upper compensation capacitor and the third plate C3 of the lower compensation capacitor are located in the first metal layer, the second plate C2 of the upper compensation capacitor and the fourth plate C4 of the lower compensation capacitor are located in the third metal layer M3, and the orthographic projection of the first plate C1 on the substrate 200 at least partially overlaps with the orthographic projection of the second plate C2 on the substrate 200, and the second insulating layer 400 serves as the dielectric layer, thereby forming the upper compensation capacitor; the orthographic projection of the third plate C3 on the substrate 200 at least partially overlaps with the orthographic projection of the fourth plate C4 on the substrate 200, and the second insulating layer 400 serves as the dielectric layer, thereby forming the lower compensation capacitor.

[0090] refer to Figure 9In another optional embodiment, the data signal line is located in the first metal layer M1, wherein the first electrode C1 of the upper compensation capacitor and the third electrode C3 of the lower compensation capacitor are located in the first metal layer M1, the second electrode C2 of the upper compensation capacitor is located in the second metal layer M2, and the fourth electrode C4 of the lower compensation capacitor is located in the third metal layer M3. The orthographic projection of the first electrode C1 onto the substrate 200 at least partially overlaps with the orthographic projection of the second electrode C2 onto the substrate 200. A first insulating layer 300 serves as the dielectric layer, thereby forming the upper compensation capacitor. The orthographic projection of the third electrode C3 onto the substrate 200 at least partially overlaps with the orthographic projection of the fourth electrode C4 onto the substrate 200. The upper compensation capacitor is formed by stacking the first electrode C1 on the substrate 200 and the second insulating layer 400 as the dielectric layer. Alternatively, the second electrode C2 of the upper compensation capacitor can be located on the third metal layer M3, and the fourth electrode C4 of the lower compensation capacitor can be located on the second metal layer M2. The orthogonal projection of the first electrode C1 on the substrate 200 and the orthogonal projection of the second electrode C2 on the substrate 200 overlap at least partially. The upper compensation capacitor is formed by stacking the first electrode C1 on the substrate 200 and the orthogonal projection of the third electrode C3 on the substrate 200 overlap at least partially. The lower compensation capacitor is formed by stacking the first insulating layer 300 as the dielectric layer.

[0091] refer to Figures 4-5 In one embodiment, the display panel further includes a plurality of connection signal line groups 70, which are located in the second frame area B2. Each connection signal line group 70 is connected to a corresponding second compensation capacitor group 40 and a multiplexer 20. Each connection signal line group 70 includes a plurality of connection signal lines 71 arranged along the second direction (Y direction). Each connection signal line 71 is connected to a corresponding second compensation capacitor, and the connection signal lines 71 in the same connection signal line group 70 are connected to a multiplexer 20.

[0092] For example, each connection signal line group 70 includes a first connection signal line 71R, a second connection signal line 71B, and a third connection signal line 71G spaced apart along a first direction (X direction), wherein the first connection signal line 71R is connected to a first lower compensation capacitor 41R, the second connection signal line 71B is connected to a second lower compensation capacitor 41B, and the third connection signal line 71G is connected to a third lower compensation capacitor 41G.

[0093] refer to Figures 4-5In one embodiment, to achieve a narrow bezel design for the display panel, the fan-out signal line 60 is routed in the display area AA, and the source fan-out signal is output from the source integrated circuit (Source IC). The fanout signal line enters the display area AA and is electrically connected to the data signal line 51 of the display area AA. Therefore, at least a portion of the fanout signal line 60 in the application is located in the display area AA. The fanout signal line 60 includes a first fanout segment 71 extending along a first direction (X direction) and a second fanout segment 62 extending along a second direction (Y direction). One end of the first fanout segment 71 is electrically connected to the data signal line 51. Further, one end of the first fanout segment 71 is electrically connected to the data signal line 51 through a multiplexer 20; the other end is electrically connected to one end of the second fanout segment 62; the other end of the second fanout segment 62 extends to the bezel area of ​​the display panel and is electrically connected to the source integrated circuit (SourceIC). This design can further realize a narrow bezel of the display panel, so that the second bezel area B2 only has the second compensation capacitor group 40 and GIP connection.

[0094] Based on the same inventive concept, this disclosure also provides a display device, which includes the display panel provided in this application. The display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and vehicle-mounted display devices; this application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel in the above 30 embodiments; these descriptions will not be repeated here.

[0095] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0096] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area that at least partially surrounds the display area. The display area includes a first display area and a second display area, the second display area being located on opposite sides of the first display area in a first direction. The non-display area includes a first border area and a second border area, the first border area and the second border area being located on opposite sides of the second display area in a second direction, the first direction intersecting the second direction. Multiple pixel unit columns are arranged along the second direction in the display area, the multiple pixel unit columns including multiple first pixel unit columns located in the first display area and multiple second pixel unit columns located in the second display area; Multiple demultiplexers are provided, at least a portion of which are located in the second border area. The demultiplexers are located on the side of the corresponding second pixel unit column away from the display area in the second direction, and the demultiplexers are electrically connected to the corresponding second pixel unit column. Multiple first compensation capacitor groups are located in the first border area, and the first compensation capacitor groups are located on the side of the corresponding second pixel unit column away from the display area in the second direction. The first compensation capacitor groups are electrically connected to the corresponding second pixel unit column. Multiple second compensation capacitor groups are located in the second border area. The second compensation capacitor groups are located on the side of the corresponding second pixel unit column away from the display area in the second direction and on the side of the multiplexer close to the corresponding second pixel unit column. The second compensation capacitor groups are electrically connected to the corresponding second pixel unit column.

2. The display panel as described in claim 1, characterized in that, Each of the pixel unit columns includes a plurality of sub-pixel columns arranged along the first direction, and each of the sub-pixel columns includes a plurality of sub-pixels arranged along the second direction; Preferably, the number of sub-pixels in each sub-pixel column within the same pixel unit column is the same, while the number of sub-pixels in each sub-pixel column within different pixel unit columns is not entirely the same; Preferably, the number of sub-pixels in each sub-pixel column is the same in each of the first pixel unit columns; Preferably, the number of sub-pixels in each sub-pixel column of the first pixel unit column is greater than the number of sub-pixels in each sub-pixel column of the second pixel unit column; Preferably, the number of sub-pixels in each sub-pixel column within each second pixel unit column is not exactly the same, but the number of sub-pixels in each sub-pixel column within the same second pixel unit column is the same; Preferably, the number of sub-pixels in each sub-pixel column of the second pixel unit column closer to the first display area is greater than the number of sub-pixels in each sub-pixel column of the second pixel unit column farther from the first display area.

3. The display panel as described in claim 2, characterized in that, The display panel also includes: Multiple data signal line groups are arranged along the first direction in the display area, and the data signal line groups are electrically connected to the corresponding pixel unit columns. The plurality of data signal line groups include a first data signal line group located in the first display area and a second data signal line group located in the second display area. The first data signal line group is electrically connected to the first pixel unit column, and the second data signal line group is electrically connected to the second pixel unit column. Preferably, each of the data signal line groups includes a plurality of data signal lines arranged along a majority first direction, the data signal lines being electrically connected to the corresponding sub-pixel column; Preferably, the data signal lines in the same group of data signal lines have the same extension length; Preferably, the extension length of the data signal line in the first data signal line group is greater than the extension length of the data signal line in the second data signal line group; Preferably, the extension length of the data signal line in the second data signal line group closer to the first display area is greater than the extension length of the data signal line in the second data signal line group farther from the first display area.

4. The display panel as described in claim 3, characterized in that, Each of the first compensation capacitor groups includes a plurality of upper compensation capacitors arranged along the second direction, the upper compensation capacitors being electrically connected to the corresponding sub-pixel column; Preferably, the compensation capacitor shown is electrically connected to the corresponding data signal line; Preferably, each of the second compensation capacitor groups includes a plurality of lower compensation capacitors arranged along the second direction, and the upper compensation capacitors are electrically connected to the corresponding sub-pixel column; Preferably, the lower compensation capacitor is electrically connected to the corresponding data signal line; Preferably, both the upper compensation capacitor and the upper compensation capacitor are strip-shaped extending along the first direction.

5. The display panel as described in claim 4, characterized in that, The capacitance values ​​of the first compensation capacitor group and / or the second compensation capacitor group are negatively correlated with the number of pixel units in the second pixel unit column; Preferably, the capacitance values ​​of the upper compensation capacitor and / or the lower compensation capacitor are negatively correlated with the number of sub-pixels in the sub-pixel column.

6. The display panel as described in claim 4, characterized in that, The upper compensation capacitor includes a first plate and a second plate. The first plate and the second plate are on different layers and are insulated from each other. The first plate is disposed on the same layer as the data signal line and is electrically connected to the data signal line. Preferably, the lower compensation capacitor includes a third plate and a fourth plate, the third plate and the fourth plate are on different layers and insulated from each other, the third plate is disposed on the same layer as the data signal line and is electrically connected to the data signal line; Preferably, the first electrode plate of the upper compensation capacitor and the third electrode plate of the lower compensation capacitor are disposed in the same layer; Preferably, the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor are disposed in the same layer, or the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor are disposed in different layers.

7. The display panel as described in claim 6, characterized in that, The display panel further includes a substrate and at least two metal layers disposed on the substrate. The first and second plates of the upper compensation capacitor are located in different metal layers, and the third and fourth plates of the lower compensation capacitor are located in different metal layers. Preferably, the orthographic projections of the first and second plates of the upper compensation capacitor on the substrate at least partially overlap, and the orthographic projections of the third and fourth plates of the lower compensation capacitor on the substrate at least partially overlap. Preferably, the at least two metal layers include a first metal layer and a second metal layer, the second metal layer is located on the side of the first metal layer away from the substrate, the first electrode of the upper compensation capacitor and the third electrode of the lower compensation capacitor are both located in the first metal layer, and the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor are both located in the second metal layer. Preferably, the second plates of the plurality of upper compensation capacitors are connected as one unit, and the fourth plates of the plurality of lower compensation capacitors are connected as one unit; Preferably, the at least two metal layers further include a third metal layer, the third metal layer being located on the side of the first metal layer closer to the substrate, the first electrode of the upper compensation capacitor and the third electrode of the lower compensation capacitor being located in the first metal layer, and the second electrode of the upper compensation capacitor and the fourth electrode of the lower compensation capacitor being located in the third metal layer. Alternatively, the second electrode of the upper compensation capacitor may be located in the second metal layer, and the fourth electrode of the lower compensation capacitor may be located in the third metal layer. Alternatively, the second electrode of the upper compensation capacitor may be located in the third metal layer, and the fourth electrode of the lower compensation capacitor may be located in the second metal layer.

8. The display panel as described in claim 3, characterized in that, The display panel also includes: Multiple fan-out signal lines, at least a portion of each fan-out signal line is located in the display area, the fan-out signal line is electrically connected to the corresponding multiplexer, and the multiplexer is electrically connected to the multiple data signal lines in the corresponding data signal line group; Preferably, each of the fan-out signal lines includes a first fan-out segment extending along the second direction and a second fan-out segment extending along the second direction, the second fan-out segment being electrically connected to the corresponding multiplexer.

9. The display panel as claimed in claim 1, characterized in that, The display panel also includes: Multiple connection signal line groups are located in the second frame area, and the connection signal line groups are connected to the corresponding second compensation capacitor group and the multiplexer; Preferably, each connection signal line group includes a plurality of connection signal lines arranged along a first direction, the connection signal lines being connected to a corresponding lower compensation capacitor and a multiplexer.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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