Display panel and pixel driving circuit

Abstract

The application provides a display panel and a pixel driving circuit, and belongs to the technical field of display driving. The display panel comprises a driving transistor, a first light-emitting control circuit, a second light-emitting control circuit, a third light-emitting control circuit and a reset circuit; the first electrode of the driving transistor is connected with the first light-emitting control circuit and the reset circuit at a first node, and the second electrode is connected with the second light-emitting control circuit at a second node; the second light-emitting control circuit and the third light-emitting control circuit are connected at a third node, the first light-emitting control circuit and the second light-emitting control circuit are respectively driven by different gate driving signals, the first light-emitting control circuit is driven to be disconnected and the second light-emitting control circuit is driven to be turned on in a light-emitting path reset stage, so that the reset circuit synchronously resets the first node, the second node and the third node, thereby multiple reset circuits are not needed to be arranged.

Description

Technical Field

[0001] This application relates to the field of display driver technology, and in particular to a display panel and pixel driving circuit. Background Technology

[0002] With the popularization of mobile smart terminals, users' demand for privacy protection of display panels is increasing. Privacy protection for display panels can be achieved by controlling the light emission state of different light-emitting elements in the display area to switch the display mode. That is, the pixel driving unit is used to drive the privacy light-emitting element and the non-privacy light-emitting element respectively.

[0003] Currently, the method of implementing privacy mode through pixel driving unit has two light emission paths, namely privacy light emission element and non-privacy light emission element. Therefore, in the reset phase of each frame image display, a reset circuit needs to be set for each node on the light emission path.

[0004] Therefore, simplifying the circuit structure of the pixel driving unit that supports privacy protection is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a display panel to at least partially solve the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including a gate driver, a pixel driving unit connected to the gate driver, and a first light-emitting element and a second light-emitting element connected to the pixel driving unit; The pixel driving unit includes a driving transistor, a first light-emitting control circuit, a second light-emitting control circuit, a third light-emitting control circuit, and a reset circuit. The first electrode of the driving transistor is connected to the first light-emitting control circuit and the reset circuit at a first node, and the second electrode is connected to the second light-emitting control circuit at a second node; The second light-emitting control circuit and the third light-emitting control circuit are connected to the third node, the first light-emitting element is connected between the third node and the first power line, and the second light-emitting element is connected between the third light-emitting control circuit and the first power line. The first light-emitting control circuit and the second light-emitting control circuit are driven by different gate driving signals. During the light-emitting path reset phase of the pixel driving unit, the reset circuit is turned on and drives the first light-emitting control circuit to turn off and the second light-emitting control circuit to turn on through the gate driving signals, so that the reset circuit can synchronously reset the first node, the second node and the third node.

[0007] Optionally, the gate driver includes a first driving unit connected to the first light-emitting control circuit, a second driving unit connected to the second light-emitting control circuit, a third driving unit connected to the third light-emitting control circuit, and a fourth driving unit connected to the reset circuit. The first light-emitting control circuit includes a first transistor, the second light-emitting control circuit includes a second transistor, the third light-emitting control circuit includes a third transistor, and the reset circuit includes a fourth transistor; The first transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a control electrode connected to the first driving unit to receive a first driving signal; The second transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a control electrode connected to the second driving unit to receive a second driving signal; The third transistor includes a first electrode connected to the third node, a second electrode connected to the second light-emitting element, and a control electrode connected to the third driving unit to receive a third driving signal; The fourth transistor includes a first electrode for receiving a reset voltage, a second electrode connected to the first node, and a control electrode connected to the fourth driving unit for receiving a reset driving signal.

[0008] Optionally, during the light-emitting path reset phase, the first driving unit outputs the first driving signal to control the first transistor to turn off, the fourth driving unit outputs the reset driving signal to control the fourth transistor to turn on, and the second driving unit outputs the second driving signal to control the second transistor to turn on, so that the reset voltage is sequentially transmitted to the first node, the second node, and the third node to reset the first node, the second node, and the third node.

[0009] Optionally, the gate driver further includes a fifth driving unit and a sixth driving unit; the pixel driving unit further includes a write circuit connected to the first node and a connection circuit for controlling the on / off state between the second node and the control electrode of the driving transistor; The write circuit includes a fifth transistor, which includes a first electrode connected to the data line, a second electrode connected to the first node, and a control electrode connected to the fifth driving unit to access the write control signal. The connection circuit includes a sixth transistor, which includes a first electrode connected to the second node, a second electrode connected to the driving transistor at the fourth node, and a control electrode connected to the sixth driving unit to receive a connection control signal.

[0010] Optionally, the display cycle of the pixel driving unit further includes a data writing stage; in the data writing stage, the fifth driving unit outputs the write control signal to control the fifth transistor to turn on, and the sixth driving unit outputs the connection control signal to control the sixth transistor to turn on, so that the data voltage transmitted on the data line is transmitted to the fourth node through the fifth transistor and the sixth transistor.

[0011] Optionally, the display cycle of the pixel driving unit further includes a privacy light emission phase, which is after the light emission path reset phase; During the privacy-protected light-emitting phase, the first driving unit outputs a first driving signal to control the first transistor to turn on, the second driving unit outputs a second driving signal to control the second transistor to turn on, the driving transistor turns on according to the data voltage written by the fourth node, causing the first light-emitting element to emit light based on the data voltage, and the third driving unit outputs a third driving signal to control the third transistor to turn off, causing the second light-emitting element to not emit light.

[0012] Optionally, the display cycle of the pixel driving unit further includes a shared light emission phase, which is after the light emission path reset phase; During the shared light-emitting phase, the first driving unit outputs a first driving signal to control the first transistor to turn on, the second driving unit outputs a second driving signal to control the second transistor to turn on, the driving transistor turns on according to the data voltage written by the fourth node, and the third driving unit outputs a third driving signal to control the third transistor to turn on, so that the first light-emitting element and the second light-emitting element emit light according to the data voltage.

[0013] Optionally, the pixel driving unit further includes a reset circuit; the gate driver further includes a seventh driving unit. The reset circuit includes a seventh transistor, which includes a first electrode that receives a reset voltage, a second electrode that is connected to the fourth node, and a control electrode that is connected to the seventh driving unit to receive a reset driving signal. The display cycle of the pixel driving unit also includes an initial phase before the data writing phase; in the initial phase, the seventh driving unit outputs a reset driving signal to control the seventh transistor to turn on, so that the reset voltage is output to the fourth node to reset the fourth node.

[0014] Optionally, the display cycle of the pixel driving unit further includes a transistor reset phase between the data writing phase and the initialization phase; During the transistor reset phase, the seventh driving unit outputs a reset driving signal to control the seventh transistor to turn on, and the sixth driving unit outputs the connection control signal to control the sixth transistor to turn on. The driving transistor turns on according to the reset voltage, so that the reset voltage is transmitted to the fourth node via the seventh transistor, then to the second node via the sixth transistor, and finally to the first node via the driving transistor, so as to reset the first node, the second node, and the fourth node.

[0015] According to a second aspect of this application, a pixel driving circuit is provided, including a driving transistor, a reset circuit, a first light-emitting control circuit, a second light-emitting control circuit, and a third light-emitting control circuit. The first electrode of the driving transistor is connected to the first light-emitting control circuit and the reset circuit at a first node, and the second electrode is connected to the second light-emitting control circuit at a second node; The second light-emitting control circuit and the third light-emitting control circuit are connected to the third node, the first light-emitting element is connected between the third node and the first power line, and the second light-emitting element is connected between the third light-emitting control circuit and the first power line. The first light-emitting control circuit and the second light-emitting control circuit are driven by different gate drive signals. During the light-emitting path reset phase, the reset circuit is turned on and drives the first light-emitting control circuit to turn off and the second light-emitting control circuit to turn on through the gate drive signals, so that the reset circuit can synchronously reset the first node, the second node and the third node.

[0016] In summary, in this application, during the light-emitting path reset phase, the reset circuit can be driven to reset the first node first, and then the driving transistor can be used to reset the second node. Since the first and second light-emitting control circuits are driven by different gate drive signals, the first light-emitting control circuit can be driven to disconnect independently, thus disconnecting the line between the first node and the second power supply line used to provide drive current. Therefore, no drive current flows to the light-emitting element during the light-emitting path reset phase. The second light-emitting control circuit can then be driven to conduct independently, connecting the line between the second and third nodes, so that the potential of the second node can be used to continue resetting the third node. Furthermore, the third light-emitting control circuit can control the anode of the second light-emitting element to be reset using the potential of the third node or not, to adapt to the reset requirements of privacy displays. Thus, synchronous reset of the first, second, and third nodes can be achieved without the need for separate reset circuits for each node.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a circuit connection diagram of the pixel driving unit provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the current flow of the pixel driving unit in the light emission path reset stage provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of the current flow of the pixel driving unit during the data writing stage provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of the current flow of the pixel driving unit in the privacy light emission stage provided in the exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of the current flow of the pixel driving unit in the shared light emission stage provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the current flow of the pixel driving unit during the transistor reset stage in an exemplary embodiment of this disclosure; Figure 7 This is another circuit connection diagram of the pixel driving unit provided in the exemplary embodiments of this disclosure; Figure 8 This is a timing diagram of the pixel driving unit provided in the exemplary embodiment of this disclosure in privacy mode; Figure 9 This is a timing diagram of the pixel driving unit provided in the exemplary embodiments of this disclosure in non-peeping mode; Figure 10 This is a schematic diagram illustrating a display panel application scenario in an exemplary embodiment of this disclosure.

[0021] Explanation of reference numerals in the attached figures: 10, pixel driving unit; Tr, driving transistor; 1, first light-emitting control circuit; 2, second light-emitting control circuit; 3, third light-emitting control circuit; 4, reset circuit; 5, writing circuit; 6, connection circuit; 7, reset circuit. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0023] First, the background of this application will be further explained. During the operation of a display panel, if residual charge on the nodes of the light-emitting path cannot be completely removed, it will directly lead to problems such as brightness deviation, grayscale distortion, image ghosting, and crosstalk between adjacent pixels in the next frame image. In the dual-mode of privacy mode and non-privacy mode, the difficulty of reset is further increased. Privacy mode and non-privacy mode drive two light-emitting elements respectively, that is, there are two light-emitting paths. The two light-emitting paths have a distinction between common nodes and independent nodes. Resetting the common node will affect both privacy mode and non-privacy mode simultaneously, while resetting the independent node needs to be controlled separately.

[0024] Currently, the common approach is to set up independent reset circuits for each node of each light-emitting path to adapt to the different reset requirements of privacy and non-privacy modes. Besides increasing circuit redundancy and manufacturing costs, multiple reset transistors may introduce additional leakage current paths, leading to faster node potential decay and a significant decrease in display brightness as the emission time increases. In particular, the current of a common node needs to drive two light-emitting elements simultaneously; if a leakage current path occurs, the leakage effect will be more pronounced compared to an architecture with only one light-emitting element. Furthermore, more transistors may exacerbate electromagnetic interference within the pixel driving unit, making it difficult to guarantee brightness consistency when switching between privacy and non-privacy modes. Therefore, simplifying the circuit structure of the pixel driving unit supporting privacy functionality while achieving reset adaptability for dual-mode characteristics is a pressing technical problem. Based on this, the embodiments of this application are proposed.

[0025] See Figure 1According to a first aspect of this application, this disclosure provides a display panel, including a gate driver, a pixel driving unit 10 connected to the gate driver, and a first light-emitting element D1 and a second light-emitting element D2 connected to the pixel driving unit 10. The pixel driving unit 10 includes a driving transistor Tr, a first light-emitting control circuit 1, a second light-emitting control circuit 2, a third light-emitting control circuit 3, and a reset circuit 4. The first electrode of the driving transistor Tr is connected to the first light-emitting control circuit 1 and the reset circuit 4 at a first node A, and the second electrode is connected to the second light-emitting control circuit 2 at a second node B. The second light-emitting control circuit 2 and the third light-emitting control circuit 3 are connected to a third node C. The first light-emitting element D1 is connected between the third node C and a first power line, and the second light-emitting element D2 is connected between the third light-emitting control circuit 3 and the first power line.

[0026] The first light-emitting control circuit 1 and the second light-emitting control circuit 2 are driven by different gate driving signals. During the light-emitting path reset stage of the pixel driving unit 10, the reset circuit 4 is turned on and drives the first light-emitting control circuit 1 to turn off and the second light-emitting control circuit 2 to turn on through the gate driving signal, so that the reset circuit 4 synchronously resets the first node A, the second node B and the third node C.

[0027] As an example, the anode of the first light-emitting element D1 is connected to the third node C, and the cathode is connected to the first power line; the anode of the second light-emitting element D2 is connected to the third light-emitting control circuit 3, and the cathode is connected to the first power line. The first light-emitting element D1 can be configured as a privacy-protecting light-emitting element, and the second light-emitting element D2 can be configured as a non-privacy-protecting light-emitting element.

[0028] As an example, the first light-emitting control circuit 1 is also connected to a second power supply line for providing drive current, and the voltage on the second power supply line is greater than the voltage on the first power supply line. When the first light-emitting control circuit 1, the driving transistor Tr, and the second light-emitting control circuit 2 are all in the ON state, the drive current provided by the second power supply line flows sequentially through the light-emitting path formed by the first light-emitting control circuit 1, the driving transistor Tr, and the second light-emitting control circuit 2 and is applied to the anode of the first light-emitting element D1, causing the first light-emitting element D1 to start emitting light. Based on the same principle, when the first light-emitting control circuit, the driving transistor Tr, the second light-emitting control circuit 2, and the third light-emitting control circuit 3 are all in the ON state, the first light-emitting element D1 and the second light-emitting element D2 can be driven to emit light synchronously, thereby realizing both privacy-protected and non-privacy-protected light-emitting modes.

[0029] In the above embodiment, during the light-emitting path reset stage, the reset circuit 4 can be driven to reset the first node A first, and then the second node B can be reset via the driving transistor Tr. Since the first light-emitting control circuit 1 and the second light-emitting control circuit 2 are driven by different gate drive signals, the first light-emitting control circuit 1 can be driven to disconnect, thus disconnecting the line between the first node A and the second power supply line used to provide drive current. Therefore, no drive current flows to the light-emitting element during the light-emitting path reset stage. The second light-emitting control circuit 2 can be driven to conduct, connecting the line between the second node B and the third node C, so that the potential of the second node B can be used to continue resetting the third node C. Furthermore, the third light-emitting control circuit 3 can control the anode of the second light-emitting element D2 to be reset using the potential of the third node C or not, to adapt to the reset requirements of the privacy display. In this way, synchronous reset of the first node A, the second node B, and the third node C can be achieved without needing to set up reset circuits for each node.

[0030] Reference Figure 1 As an example, the gate driver includes a first driving unit connected to a first light-emitting control circuit 1, a second driving unit connected to a second light-emitting control circuit 2, a third driving unit connected to a third light-emitting control circuit 3, and a fourth driving unit connected to a reset circuit 4.

[0031] As an example, the first light-emitting control circuit 1 includes a first transistor T1. The first transistor T1 includes a first electrode connected to the second power line, a second electrode connected to the first node A, and a control electrode connected to the first driving unit to receive the first driving signal EM1. The first transistor T1 controls the current path between the second power line and the first node A. When the first transistor T1 is turned on, the voltage of the second power line is applied to the first node A, providing driving current for the driving transistor Tr; when the first transistor T1 is turned off, the connection between the second power line and the first node A is cut off, preventing the driving current from flowing into the light-emitting path.

[0032] As an example, the second light-emitting control circuit 2 includes a second transistor T2. The second transistor T2 includes a first electrode connected to the second node B, a second electrode connected to the third node C, and a control electrode connected to the second driving unit to receive the second driving signal EM2. The second transistor T2 controls the current path between the second node B and the third node C. When the second transistor T2 is turned on, the driving transistor Tr can transmit the driving current to the third node C; when the second transistor T2 is turned off, it cuts off the driving current of the light-emitting path, causing both the first light-emitting element D1 and the second light-emitting element D2 to turn off.

[0033] As an example, the third light-emitting control circuit 3 includes a third transistor T3. The third transistor T3 includes a first electrode connected to the third node C, a second electrode connected to the second light-emitting element D2, and a control electrode connected to the third driving unit to receive the third driving signal EM3. When the third transistor T3 is turned off, the current path between the third node C and the second light-emitting element D2 is cut off, and only the first light-emitting element D1 emits light. When the third transistor T3 is turned on, the driving current transmitted to the third node C can flow to both the first light-emitting element D1 and the second light-emitting element D2 simultaneously, and both the first light-emitting element D1 and the second light-emitting element D2 emit light at the same time.

[0034] As an example, the reset circuit 4 includes a fourth transistor T4. The fourth transistor T4 includes a first electrode for receiving the reset voltage, a second electrode connected to the first node A, and a control electrode connected to the fourth driving unit to receive the reset drive signal Pscan2. The fourth transistor T4 controls the path between the reset voltage and the first node A. When the fourth transistor T4 is turned on, the reset voltage is applied to the first node A, pulling the potential of the first node A down to its initial state and eliminating residual charge accumulated during the previous frame display.

[0035] Among them, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can be P-type transistors.

[0036] See Figure 2 In some embodiments, the display cycle of the pixel driving unit 10 includes a data writing phase and a light-emitting path reset phase following the data writing phase. During the light-emitting path reset phase, the first driving unit outputs a first driving signal EM1 to control the first transistor T1 to turn off, the fourth driving unit outputs a reset driving signal Pscan2 to control the fourth transistor T4 to turn on, and the second driving unit outputs a second driving signal EM2 to control the second transistor T2 to turn on, thereby transmitting a reset voltage sequentially to the first node A, the second node B, and the third node C to reset the first node A, the second node B, and the third node C.

[0037] The display cycle refers to the time required for the display panel to refresh one frame of image. The light-emitting path refers to the path through which current flows from the second power line to the first light-emitting element D1, which includes the first transistor T1, the first node A, the driving transistor Tr, the second node B, the second transistor T2, the third node C, and the first light-emitting element D1, or includes the third node C, the third transistor T3, and the second light-emitting element D2. During the light-emitting process, nodes on the light-emitting path accumulate charge. If this charge is not reset in time, the residual charge will affect the display effect of the next frame.

[0038] Reference Figure 2During the light-emitting path reset phase, the first transistor T1 is turned off, disconnecting the connection between the second power line and the first node A to prevent the reset voltage from being shunted by the second power line, thus ensuring the effectiveness of the reset. The fourth transistor T4 is turned on, transmitting the reset voltage to the first node A. The second transistor T2 is turned on, allowing the reset voltage to be transmitted from the first node A through the driving transistor Tr to the second node B, and then through the second transistor T2 to the third node C, so that the anode of the first light-emitting element D1 connected to the third node C is reset. Thus, the synchronous reset of the first node A, the second node B, the third node C, and the anode of the first light-emitting element D1 is achieved through series transmission of the reset voltage.

[0039] Continue to refer to Figure 2 As an example, during the light-emitting path reset phase, the third transistor T3 can also be controlled to turn on, so as to use the potential of the third node C to reset the anode of the second light-emitting element D2, so as to realize the synchronous reset of the first node A, the second node B, the third node C, the anode of the first light-emitting element D1 and the anode of the second light-emitting element D2.

[0040] The reset voltage can be a low-level voltage, and its potential can be close to the potential of the first power line, so as to pull the potential of each node down to the initial state close to the potential of the first power line, and will not drive the first light-emitting element D1 and the second light-emitting element D2 to emit light.

[0041] In the above embodiments, the residual charge accumulated at each node on the light-emitting path can be eliminated during the light-emitting path reset stage, avoiding problems such as image ghosting, crosstalk, or uneven brightness when the next frame is displayed, thus improving display quality. Secondly, by using a series transmission reset voltage method for reset, only one fourth transistor T4 for transmitting the reset voltage is needed to simultaneously reset each node on the light-emitting path, eliminating the need for multiple transistors for reset and simplifying the circuit structure.

[0042] Reference Figure 3 In some embodiments, the gate driver further includes a fifth driving unit and a sixth driving unit. The pixel driving unit 10 also includes a write circuit 5 connected to the first node A and a connection circuit 6 for controlling the connection and disconnection between the control electrode of the second node B and the driving transistor Tr. The write circuit 5 includes a fifth transistor T5, which includes a first electrode connected to a data line, a second electrode connected to the first node A, and a control electrode connected to the fifth driving unit to access the write control signal Pscan. The connection circuit 6 includes a sixth transistor T6, which includes a first electrode connected to the second node B, a second electrode connected to the driving transistor Tr at the fourth node Q, and a control electrode connected to the sixth driving unit to access the connection control signal Nscan1.

[0043] As an example, the driving transistor Tr is used to convert the data voltage into a current that drives the first light-emitting element D1 and the second light-emitting element D2 to emit light. When the potential of the fourth node Q is higher than the threshold voltage of the driving transistor Tr, the driving transistor Tr is turned on, and the current flows from the first node A through the driving transistor Tr to the second node B. The magnitude of the on-state current of the driving transistor Tr is determined by its gate-source voltage, which is the difference between the potential of the fourth node Q and the potential of the first node A. The larger the gate-source voltage, the larger the on-state current, and the higher the brightness of the first light-emitting element D1 and the second light-emitting element D2.

[0044] As an example, the writing circuit 5 writes the data voltage transmitted on the data line to the control electrode of the driving transistor Tr to control the conduction level of the driving transistor Tr, thereby adjusting the brightness of the first light-emitting element D1 and / or the second light-emitting element D2. The fifth transistor T5 controls the current path between the data line and the first node A; when the fifth transistor T5 is on, the data voltage on the data line can be transmitted to the first node A. The sixth transistor T6 controls the connection between the control electrode of the driving transistor Tr and the second node B, achieving threshold voltage compensation for the driving transistor Tr. When the sixth transistor T6 is on, the fourth node Q is connected to the second node B; when the sixth transistor T6 is off, the fourth node Q is isolated from the second node B, and the potential of the fourth node Q remains stable. By shorting the control electrode of the driving transistor Tr to the second electrode through the sixth transistor T6, the gate-source voltage of the driving transistor Tr can automatically compensate for changes in the threshold voltage, ensuring consistency between the brightness of different first light-emitting elements D1 and different second light-emitting elements D2.

[0045] Reference Figure 3 In some embodiments, during the data writing stage, the fifth driving unit outputs a write control signal Pscan to control the fifth transistor T5 to turn on, and the sixth driving unit outputs a connection control signal Nscan1 to control the sixth transistor T6 to turn on, so that the data voltage transmitted on the data line is transmitted to the fourth node Q through the fifth transistor T5 and the sixth transistor T6.

[0046] As an example, during the data writing phase, the first transistor T1 remains off, disconnecting the connection between the second power line and the first node A. The fifth transistor T5 turns on, transmitting the data voltage on the data line to the first node A. The sixth transistor T6 turns on, shorting the control electrode of the driving transistor Tr to its second electrode. At this time, the gate-source voltage Vgs of the driving transistor Tr is 0, and the driving transistor Tr turns on. The potential of the first node A is transmitted to the second node B via the driving transistor Tr, and then to the fourth node Q via the sixth transistor T6.

[0047] When the potential of the fourth node Q is equal to the potential of the first node A, the gate-source voltage Vgs of the driving transistor Tr is 0, the driving transistor Tr is turned off, and the data writing process is completed. At this time, the potential of the fourth node Q is locked to the sum of the data voltage and the threshold voltage of the driving transistor Tr, i.e., Vdata + Vth, where Vdata is the data voltage and Vth is the threshold voltage of the driving transistor Tr.

[0048] Thus, in the subsequent light-emitting stage, when the first transistor T1 is turned on and the voltage VDD of the second power line is applied to the first node A, the gate-source voltage of the driving transistor Tr can be expressed as Vgs=(Vdata+Vth)-VDD, which is independent of the threshold voltage Vth of the driving transistor Tr. Therefore, the on-current of the driving transistor Tr is determined only by the data voltage Vdata and is not affected by the threshold voltage drift, thereby achieving threshold voltage compensation for the driving transistor Tr.

[0049] In some embodiments, the display cycle of the pixel driving unit 10 further includes a privacy light emission phase, which follows the light emission path reset phase. During the privacy light emission phase, the first driving signal EM1 output by the first driving unit controls the first transistor T1 to turn on, the second driving unit outputs the second driving signal EM2 to control the second transistor T2 to turn on, the driving transistor Tr turns on according to the data voltage written to the fourth node Q, causing the first light-emitting element D1 to emit light based on the data voltage, and the third driving unit outputs the third driving signal EM3 to control the third transistor T3 to turn off, causing the second light-emitting element D2 to not emit light.

[0050] The privacy-protected light-emitting stage is the light-emitting stage in which the pixel driving unit 10 operates in privacy mode. In privacy mode, the display area of ​​the display panel only displays images within a small viewing angle from the front, and the image brightness is reduced from the side viewing angle. The first light-emitting element D1 can be a narrow-view OLED (Organic Light Emitting Diode) as the privacy-protected light-emitting element. Its light-emitting angle is small and it can only be clearly seen from the front viewing angle. Thus, by controlling only the first light-emitting element D1 to emit light, the privacy function can be achieved.

[0051] Reference Figure 4 During the privacy-protected illumination phase, the first transistor T1 is turned on, and the voltage VDD of the second power line is applied to the first node A. The second transistor T2 is turned on, causing the driving current to flow from the first node A through the driving transistor Tr and the second transistor T2 to the third node C. The third transistor T3 is turned off, thus breaking the current path between the third node C and the second light-emitting element D2, so the second light-emitting element D2 does not emit light. The driving current flows only from the third node C to the first light-emitting element D1, causing the first light-emitting element D1 to emit light.

[0052] In some embodiments, the display cycle of the pixel driving unit 10 further includes a shared light-emitting phase, which follows the light-emitting path reset phase. During the shared light-emitting phase, the first driving unit outputs a first driving signal EM1 to control the first transistor T1 to turn on, the second driving unit outputs a second driving signal EM2 to control the second transistor T2 to turn on, the driving transistor Tr turns on according to the data voltage written to the fourth node Q, and the third driving unit outputs a third driving signal EM3 to control the third transistor T3 to turn on, causing the first light-emitting element D1 and the second light-emitting element D2 to emit light according to the data voltage, respectively.

[0053] The shared light-emitting stage is the light-emitting stage in which the pixel driving unit 10 operates in non-peeping mode. In non-peeping mode, the display area of ​​the display panel can display relatively clear images within a wide viewing angle range, which is suitable for scenarios where multiple people share display content. The second light-emitting element D2 can be a wide-viewing-angle OLED (Organic Light Emitting Diode) as a non-peeping-angle light-emitting element. Its large light-emitting angle can increase the viewing angle of the display panel. Thus, by controlling the first light-emitting element D1 and the second light-emitting element D2 to emit light simultaneously, the shared function of wide-viewing-angle display can be achieved.

[0054] Reference Figure 5 During the shared light-emitting phase, the first transistor T1 and the second transistor T2 remain on, and the driving current flows from the first node A through the driving transistor Tr and the second transistor T2 to the third node C. The third transistor T3 is turned on, causing the current at the third node C to split into two paths: one flowing to the first light-emitting element D1, and the other flowing through the third transistor T3 to the second light-emitting element D2. This allows both the first and second light-emitting elements D1 and D2 to emit light simultaneously. Compared to the privacy mode, the non-privacy mode displays a brighter display with a wider viewing angle. Furthermore, since the first and second light-emitting elements D1 and D2 are connected in parallel and driven by the same driving transistor Tr, their brightness is the same, determined by the data voltage written to the fourth node Q.

[0055] As an example, switching between privacy mode and non-privacy mode during the light-emitting stage can be achieved simply by changing the level of the third drive signal EM3 output by the third drive unit. The switching speed is fast and can be completed within one frame without affecting the display effect.

[0056] In some embodiments, the pixel driving unit 10 further includes a reset circuit 7. The gate driver further includes a seventh driving unit. The reset circuit 7 includes a seventh transistor T7, which includes a first electrode connected to a reset voltage, a second electrode connected to the fourth node Q, and a control electrode connected to the seventh driving unit to receive a reset driving signal Nscan2. The display cycle of the pixel driving unit 10 also includes an initial phase before the data writing phase. In the initial phase, the seventh driving unit outputs a reset driving signal Nscan2 to control the seventh transistor T7 to turn on, so that the reset voltage is output to the fourth node Q to reset the fourth node Q.

[0057] As an example, reset circuit 7 is used to pre-reset the control electrode of drive transistor Tr at the beginning of each display cycle, eliminating residual charge accumulated in the fourth node Q during the previous frame display. The seventh transistor T7 controls the path between the reset voltage and the fourth node Q, and the reset voltage can be a low-level voltage. At the initial stage of the display cycle, only the seventh transistor T7 is turned on, directly applying the reset voltage to the fourth node Q, thereby pulling the potential of the fourth node Q down to its initial state.

[0058] In some embodiments, the display cycle of the pixel driving unit 10 further includes a transistor reset phase between the data writing phase and the initialization phase. During the transistor reset phase, the seventh driving unit outputs a reset driving signal Nscan2 to control the seventh transistor T7 to turn on, and the sixth driving unit outputs a connection control signal Nscan1 to control the sixth transistor T6 to turn on. The driving transistor Tr turns on according to the reset voltage, causing the reset voltage to be transmitted via the seventh transistor T7 to the fourth node Q, then via the sixth transistor T6 to the second node B, and finally via the driving transistor Tr to the first node A, thereby resetting the first node A, the second node B, and the fourth node Q.

[0059] Reference Figure 6 As an example, the transistor reset phase is a reset operation performed after the initialization phase and before the data writing phase to eliminate residual charges on the first node A, the second node B, and the fourth node Q, ensuring that each node is in its initial state before data writing. During the transistor reset phase, the seventh transistor T7 remains on, and the reset voltage continues to be applied to the fourth node Q. The sixth transistor T6 is turned on, connecting the fourth node Q to the second node B. At this time, since the control electrode of the driving transistor Tr was reset to the reset voltage during the initialization phase, the second electrode of the driving transistor Tr is also set to the reset voltage, and the gate-source voltage Vgs of the driving transistor Tr is 0, causing the driving transistor Tr to turn on. Therefore, the reset voltage is transmitted from the fourth node Q through the sixth transistor T6 to the second node B, and then through the driving transistor Tr to the first node A.

[0060] Thus, only the seventh transistor T7 and the sixth transistor T6 need to be turned on to simultaneously reset the first node A, the second node B, and the fourth node Q.

[0061] In some embodiments, the pixel driving unit 10 further includes a first storage capacitor Cboost and a second storage capacitor Cst.

[0062] The second storage capacitor Cst is connected between the fourth node Q and the first power line to store the potential of the fourth node Q. After the data writing phase is completed, the fifth transistor T5 and the sixth transistor T6 are disconnected, isolating the fourth node Q from other nodes. The second storage capacitor Cst keeps the potential of the fourth node Q stable throughout the light-emitting phase, preventing changes in the driving current of the driving transistor Tr caused by charge leakage, thereby avoiding a decrease in the brightness of the first light-emitting element D1 and the second light-emitting element D2 over time.

[0063] The first storage capacitor Cboost is connected between the control electrode of the fifth transistor T5 and the fourth node Q. When the write control signal Pscan changes, it helps to improve the potential establishment speed of the fourth node Q through capacitive coupling effect, thus shortening the data writing time. During the light emission stage, the fifth transistor T5 is turned off, and the first storage capacitor Cboost and the second storage capacitor Cst form a parallel energy storage structure to jointly maintain the potential stability of the fourth node Q.

[0064] Reference Figure 7 In some embodiments, the pixel driving unit 10 may further include an anode reset unit 8 connected to the third node C. The anode reset unit 8 includes an eighth transistor T8, which includes a first electrode connected to the anode reset voltage, a second electrode connected to the third node C, and a control electrode connected to the fourth driving unit. When the pixel driving unit 10 includes the anode reset unit 8 connected to the third node C, the first driving unit and the second driving unit may use the same driving unit. During the light emission path reset stage, the reset driving signal Pscan2 output by the fourth driving unit drives the eighth transistor T8 to conduct, so as to reset the third node C separately through the anode reset voltage, without using the second driving unit to drive the second transistor T2 to conduct in order to use the reset circuit 4 for reset.

[0065] Reference Figure 1 and Figure 8 This disclosure exemplarily describes the operation of a display panel, in which the display panel sequentially passes through an initial stage T1, a transistor reset stage T2, a data writing stage T3, a light emission path reset stage T4, and a privacy light emission stage T5 during one display cycle in privacy mode.

[0066] In the initial stage T1, the seventh drive unit outputs a reset drive signal Nscan2 to control the seventh transistor T7 to turn on, while the other transistors remain off. The reset voltage is directly applied to the fourth node Q to complete the pre-reset of the fourth node Q.

[0067] During the transistor reset phase T2, the seventh transistor T7 remains on, and the sixth drive unit outputs a connection control signal Nscan1 to control the sixth transistor T6 to turn on, causing the control electrode and the second electrode of the drive transistor Tr to be shorted and turned on. The reset voltage is transmitted sequentially through the fourth node Q and the second node B to the first node A, and the reset of the first node A, the second node B and the fourth node Q are completed synchronously.

[0068] During the data writing phase T3, the seventh transistor T7 is turned off, and the fifth drive unit outputs the write control signal Pscan to control the fifth transistor T5 to turn on. The sixth transistor T6 remains on, and the first transistor T1 remains off. The data voltage on the data line is transmitted to the first node A via the fifth transistor T5, and then to the fourth node Q via the on-state drive transistor Tr and the sixth transistor T6. When the potential of the fourth node Q is equal to the potential of the first node A, the drive transistor Tr is turned off, the data writing is completed, and the threshold voltage compensation of the drive transistor Tr is automatically realized.

[0069] During the light-emitting path reset phase T4, the fifth transistor T5 and the sixth transistor T6 are disconnected. The fourth driving unit outputs a reset driving signal Pscan2 to control the fourth transistor T4 to turn on. The second driving unit outputs a second driving signal EM2 to control the second transistor T2 to turn on. The first transistor T1 remains disconnected. The reset voltage is transmitted sequentially through the first node A, the driving transistor Tr, the second node B, and the second transistor T2 to the third node C, simultaneously completing the reset of the first node A, the second node B, the third node C, and the anode of the first light-emitting element D1.

[0070] During the privacy-protected light-emitting stage T5, the fourth transistor T4 is turned off, the first driving unit outputs the first driving signal EM1 to control the first transistor T1 to turn on, the second transistor T2 remains on, and the third driving unit outputs the third driving signal EM3 to control the third transistor T3 to turn off. The driving current provided by the second power line flows sequentially through the first transistor T1, the driving transistor Tr, and the second transistor T2 to the third node C, and finally flows only into the first light-emitting element D1, causing the first light-emitting element D1 to emit light based on the written data voltage, thus realizing the privacy-protected display.

[0071] Reference Figure 9 In a display cycle in non-peeping mode, the display panel sequentially goes through the initial stage T1, transistor reset stage T2, data writing stage T3, light emission path reset stage T4, and shared light emission stage T6.

[0072] In non-spy mode, the operation of the initial stage T1, transistor reset stage T2, and data writing stage T3 is the same as in spy mode, and will not be described again here.

[0073] In the light-emitting path reset stage T4, compared to the privacy mode, the third driving unit needs to output the third driving signal EM3 to control the third transistor T3 to turn on, so that the anode of the second light-emitting element D2 is reset according to the potential of the third node C.

[0074] During the shared light-emitting stage T6, the fourth transistor T4 is turned off. The first driving unit outputs the first driving signal EM1 to control the first transistor T1 to turn on, while the second transistor T2 remains on. The third driving unit outputs the third driving signal EM3 to control the third transistor T3 to turn on. The driving current provided by the second power line flows sequentially through the first transistor T1, the driving transistor Tr, and the second transistor T2 to the third node C, where it is divided into two paths. One path flows into the first light-emitting element D1, and the other path flows into the second light-emitting element D2 through the third transistor T3. This allows the first light-emitting element D1 and the second light-emitting element D2 to emit light simultaneously based on the written data voltage, achieving a wide-viewing-angle shared display.

[0075] Reference Figure 10 , Figure 10 This is a schematic diagram of the architecture of the display device used in the display panel in the embodiments of this application. The display device also includes a timing controller 30 and a source driver 40.

[0076] The display device includes a display area AA, which may include multiple scan lines G1 to Gn, multiple data lines intersecting the scan lines G1 to Gn, and multiple pixel driving units 10 respectively disposed in multiple areas defined by the intersections of the scan lines G1 to Gn and the data lines. Each pixel driving unit 10 is a dual-emitting element pixel driving unit 10, including a first emitting element D1 and a second emitting element D2, which can realize the switching between two display modes: privacy protection and sharing.

[0077] The timing controller 30 receives externally input image data and control signals, and performs preprocessing on the image data, such as format conversion and data sorting, to obtain data signals. Simultaneously, the timing controller 30 generates seven independent gate control signals and clock signals, as well as source control signals. The seven independent gate control signals are: first drive signal EM1, second drive signal EM2, third drive signal EM3, reset drive signal Pscan2, write control signal Pscan, connection control signal Nscan1, and reset drive signal Nscan2. Then, the data signals and source control signals are sent to the source driver 40, and the aforementioned gate control signals and clock signals are sent to the gate driver 20.

[0078] The gate driver 20 integrates a first driving unit, a second driving unit, a third driving unit, a fourth driving unit, a fifth driving unit, a sixth driving unit, and a seventh driving unit. Each driving unit receives corresponding control signals and clock signals from the timing controller 30, generates a gate scan signal that is scanned line by line, and transmits it sequentially to the pixel driving unit 10 of the corresponding row through scan lines G1 to Gn, independently controlling the on / off timing of each transistor in the pixel driving unit 10. After receiving the data signal and control signal from the timing controller 30, the source driver 40 stores the data signal in its internal register and outputs it synchronously according to the scan signal of the gate driver 20. The data voltage is written into the pixel driving unit 10 of the corresponding column through data lines D1 to Dm, ultimately realizing the display of the image.

[0079] According to a second aspect of this application, a pixel driving circuit is provided, including a driving transistor Tr, a reset circuit 4, a first light-emitting control circuit 1, a second light-emitting control circuit 2, and a third light-emitting control circuit 3.

[0080] The first electrode of the driving transistor Tr is connected to the first light-emitting control circuit 1 and the reset circuit 4 at the first node A, and the second electrode is connected to the second light-emitting control circuit 2 at the second node B.

[0081] The second light-emitting control circuit 2 and the third light-emitting control circuit 3 are connected to the third node C. The first light-emitting element D1 is connected between the third node C and the first power line, and the second light-emitting element D2 is connected between the third light-emitting control circuit 3 and the first power line.

[0082] The first light-emitting control circuit 1 and the second light-emitting control circuit 2 are driven by different gate drive signals. During the light-emitting path reset stage, the reset circuit 4 is turned on and drives the first light-emitting control circuit 1 to turn off and the second light-emitting control circuit 2 to turn on through the gate drive signals, so that the reset circuit 4 synchronously resets the first node A, the second node B and the third node C.

[0083] The proprietary pixel driving circuit possesses all the beneficial effects of the aforementioned display panel, which will not be elaborated upon here.

[0084] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0086] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0087] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes a gate driver, a pixel driving unit connected to the gate driver, and a first light-emitting element and a second light-emitting element connected to the pixel driving unit; The pixel driving unit includes a driving transistor, a first light-emitting control circuit, a second light-emitting control circuit, a third light-emitting control circuit, and a reset circuit. The first electrode of the driving transistor is connected to the first light-emitting control circuit and the reset circuit at a first node, and the second electrode is connected to the second light-emitting control circuit at a second node; The second light-emitting control circuit and the third light-emitting control circuit are connected to the third node, the first light-emitting element is connected between the third node and the first power line, and the second light-emitting element is connected between the third light-emitting control circuit and the first power line. The first light-emitting control circuit and the second light-emitting control circuit are driven by different gate driving signals. During the light-emitting path reset phase of the pixel driving unit, the reset circuit is turned on and drives the first light-emitting control circuit to turn off and the second light-emitting control circuit to turn on through the gate driving signals, so that the reset circuit can synchronously reset the first node, the second node and the third node.

2. The display panel according to claim 1, characterized in that, The gate driver includes a first driving unit connected to the first light-emitting control circuit, a second driving unit connected to the second light-emitting control circuit, a third driving unit connected to the third light-emitting control circuit, and a fourth driving unit connected to the reset circuit. The first light-emitting control circuit includes a first transistor, the second light-emitting control circuit includes a second transistor, the third light-emitting control circuit includes a third transistor, and the reset circuit includes a fourth transistor; The first transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a control electrode connected to the first driving unit to receive a first driving signal; The second transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a control electrode connected to the second driving unit to receive a second driving signal; The third transistor includes a first electrode connected to the third node, a second electrode connected to the second light-emitting element, and a control electrode connected to the third driving unit to receive a third driving signal; The fourth transistor includes a first electrode for receiving a reset voltage, a second electrode connected to the first node, and a control electrode connected to the fourth driving unit for receiving a reset driving signal.

3. The display panel according to claim 2, characterized in that, During the light-emitting path reset phase, the first driving unit outputs the first driving signal to control the first transistor to turn off, the fourth driving unit outputs the reset driving signal to control the fourth transistor to turn on, and the second driving unit outputs the second driving signal to control the second transistor to turn on, so that the reset voltage is sequentially transmitted to the first node, the second node and the third node to reset the first node, the second node and the third node.

4. The display panel according to claim 3, characterized in that, The gate driver further includes a fifth driving unit and a sixth driving unit; the pixel driving unit further includes a write circuit connected to the first node and a connection circuit for controlling the on / off connection between the second node and the control electrode of the driving transistor. The write circuit includes a fifth transistor, which includes a first electrode connected to the data line, a second electrode connected to the first node, and a control electrode connected to the fifth driving unit to access the write control signal. The connection circuit includes a sixth transistor, which includes a first electrode connected to the second node, a second electrode connected to the driving transistor at the fourth node, and a control electrode connected to the sixth driving unit to receive a connection control signal.

5. The display panel according to claim 4, characterized in that: The display cycle of the pixel driving unit also includes a data writing phase; during the data writing phase, the fifth driving unit outputs the write control signal to control the fifth transistor to turn on, and the sixth driving unit outputs the connection control signal to control the sixth transistor to turn on, so that the data voltage transmitted on the data line is transmitted to the fourth node through the fifth transistor and the sixth transistor.

6. The display panel according to claim 5, characterized in that, The display cycle of the pixel driving unit also includes a privacy light emission phase, which is after the light emission path reset phase; During the privacy-protected light-emitting phase, the first driving unit outputs a first driving signal to control the first transistor to turn on, the second driving unit outputs a second driving signal to control the second transistor to turn on, the driving transistor turns on according to the data voltage written by the fourth node, causing the first light-emitting element to emit light based on the data voltage, and the third driving unit outputs a third driving signal to control the third transistor to turn off, causing the second light-emitting element to not emit light.

7. The display panel according to claim 5, characterized in that, The display cycle of the pixel driving unit also includes a shared light emission phase, which is after the light emission path reset phase; During the shared light-emitting phase, the first driving unit outputs a first driving signal to control the first transistor to turn on, the second driving unit outputs a second driving signal to control the second transistor to turn on, the driving transistor turns on according to the data voltage written by the fourth node, and the third driving unit outputs a third driving signal to control the third transistor to turn on, so that the first light-emitting element and the second light-emitting element emit light according to the data voltage.

8. The display panel according to claim 5, characterized in that, The pixel driving unit further includes a reset circuit; the gate driver further includes a seventh driving unit. The reset circuit includes a seventh transistor, which includes a first electrode that receives a reset voltage, a second electrode that is connected to the fourth node, and a control electrode that is connected to the seventh driving unit to receive a reset driving signal. The display cycle of the pixel driving unit also includes an initial phase prior to the data writing phase; In the initial stage, the seventh driving unit outputs a reset driving signal to control the seventh transistor to turn on, so that the reset voltage is output to the fourth node to reset the fourth node.

9. The display panel according to claim 8, characterized in that, The display cycle of the pixel driving unit also includes a transistor reset phase between the data writing phase and the initial phase; During the transistor reset phase, the seventh driving unit outputs a reset driving signal to control the seventh transistor to turn on, and the sixth driving unit outputs the connection control signal to control the sixth transistor to turn on. The driving transistor turns on according to the reset voltage, so that the reset voltage is transmitted to the fourth node via the seventh transistor, then to the second node via the sixth transistor, and finally to the first node via the driving transistor, so as to reset the first node, the second node, and the fourth node.

10. A pixel driving circuit, characterized in that, It includes a driving transistor, a reset circuit, a first light-emitting control circuit, a second light-emitting control circuit, and a third light-emitting control circuit; The first electrode of the driving transistor is connected to the first light-emitting control circuit and the reset circuit at a first node, and the second electrode is connected to the second light-emitting control circuit at a second node; The second light-emitting control circuit and the third light-emitting control circuit are connected to the third node, the first light-emitting element is connected between the third node and the first power line, and the second light-emitting element is connected between the third light-emitting control circuit and the first power line. The first light-emitting control circuit and the second light-emitting control circuit are driven by different gate drive signals. During the light-emitting path reset phase, the reset circuit is turned on and drives the first light-emitting control circuit to turn off and the second light-emitting control circuit to turn on through the gate drive signals, so that the reset circuit can synchronously reset the first node, the second node and the third node.

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