Shift register, gate drive circuit, and display panel

Abstract

Embodiments of the present application disclose a shift register, a gate drive circuit and a display panel. The shift register comprises an input module, a first inverting unit, a first output module, a control module and a second output module. The input module controls transmission of an input signal to an output end of the input module based on at least a first clock signal. An input end of the first inverting unit is connected with the output end of the input module. A control end of the first output module is connected with an output end of the first inverting unit. The first output module controls transmission of a second clock signal to an output end of the shift register based on a potential of the control end of the first output module. The control module is connected with at least one of the input module, the first inverting unit and the first output module. A control end of the second output module is connected with the control module. The second output module controls transmission of a first potential signal to the output end of the shift register based on a potential of the control end of the second output module. Embodiments of the present application can realize a narrow frame.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a shift register, a gate driving circuit, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above background, this application provides a shift register, a gate driving circuit and a display panel, which are intended to improve the performance of the display panel.

[0005] This application provides a shift register, including:

[0006] The input module has an input terminal that receives an input signal, and the input module controls the transmission of the input signal to the output terminal based on at least a first clock signal. The first inverting unit has its input terminal connected to the output terminal of the input module. The first output module has its control terminal connected to the output terminal of the first inverting unit; the first output module controls the transmission of the second clock signal to the output terminal of the shift register based on the potential of its control terminal. A control module, which is connected to at least one of the input module, the first inverting unit, and the first output module; The second output module has its control terminal connected to the control module. The second output module controls the transmission of the first potential signal to the output terminal of the shift register based on the potential of the control terminal of the second output module.

[0007] This application also provides a shift register, including: The input module has an input terminal that receives an input signal, and the input module controls the transmission of the input signal to the output terminal based on at least a first clock signal. The first output module has its control terminal connected to the output terminal of the input module, and / or the control terminal of the first output module has the same potential as the output terminal of the input module; the first output module controls the transmission of the second clock signal to the output terminal of the shift register based on the potential of its control terminal. A control module, which is connected to at least one of the input module and the first output module; The second output module has its control terminal connected to the control module. The second output module transmits the first potential signal to the output terminal of the shift register based on the potential of its control terminal. The effective level pulse of the input signal is a low level pulse, and the effective level pulse output by the output terminal of the shift register is a high level pulse.

[0008] This application also provides a gate driving circuit, including a plurality of cascaded shift registers provided in any embodiment of this application.

[0009] This application also provides a display panel, including the gate driving circuit provided in any embodiment of this application.

[0010] In this embodiment, the shift register includes an input module, a first inverting unit, a first output module, a control module, and a second output module. The input module receives an input signal and controls the transmission of the input signal to its output based on at least a first clock signal. The input of the first inverting unit is connected to the output of the input module. The control of the first output module is connected to the output of the first inverting unit. The first output module controls the transmission of a second clock signal to the output of the shift register based on the potential of its control terminal. The control module is connected to at least one of the input module, the first inverting unit, and the first output module. The control of the second output module is connected to the control module. The second output module controls the transmission of a first potential signal to the output of the shift register based on the potential of its control terminal. This configuration helps reduce the bezel width of the display panel, promoting narrower bezels and increasing the screen-to-body ratio. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application.

[0013] Figure 2 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0014] Figure 3 The timing waveform diagram of a shift register provided in an embodiment of this application is shown.

[0015] Figure 4 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0016] Figure 5 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0017] Figure 6 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0018] Figure 7 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0019] Figure 8 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0020] Figure 9a This is a schematic diagram of another shift register provided in an embodiment of this application.

[0021] Figure 9b The timing waveform diagram of another shift register provided in the embodiments of this application.

[0022] Figure 10 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0023] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0024] Figure 12 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0025] Figure 13 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0026] Figure 14 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0027] Figure 15 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0028] Figure 16 The timing waveform diagram of another shift register provided in the embodiments of this application.

[0029] Figure 17 This is a schematic diagram of another shift register provided in an embodiment of this application.

[0030] Figure 18 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0031] Figure 19 The timing waveform diagram is provided for a gate driving circuit according to an embodiment of this application.

[0032] Figure 20 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application.

[0033] Figure 21 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application.

[0034] Figure 22 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application.

[0035] Figure 23 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application.

[0036] Figure 24 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0037] Figure 25 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0038] Figure 26 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0042] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0043] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. The connection may include a direct connection or an indirect connection. The connection may be an electrical connection. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor conducts when its gate is connected to a high level and turns off when its gate is connected to a low level. One of the first and second terminals of the same transistor can be the source, and the other can be the drain. P-type transistors can include polysilicon transistors. N-type transistors can include metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors. For example, all transistors in a shift register or gate drive circuit have the same channel type, and the active layer material of each (or all) transistor in the shift register or gate drive circuit is the same, thus simplifying the manufacturing process.

[0044] This application provides a shift register. Figure 1 This is a schematic diagram of a shift register provided in an embodiment of this application. See also... Figure 1 The shift register 401 includes: an input module 10, a first inverting unit 40, a first output module 20, a control module 11, and a second output module 30.

[0045] The input terminal of the input module 10 is connected to the input signal SIN, and the input module 10 controls the transmission of the input signal SIN to the output terminal of the input module 10 based at least on the first clock signal SCK1.

[0046] The input terminal I1 of the first inverting unit 40 is connected to the output terminal of the input module 10.

[0047] The control terminal of the first output module 20 is connected to the output terminal O1 of the first inverting unit 40. The first output module 20 controls the transmission of the second clock signal SCK2 to the output terminal Sout of the shift register 401 based on the potential of the control terminal of the first output module 20.

[0048] The control module 11 is connected to at least one of the input module 10, the first inverting unit 40, and the first output module 20.

[0049] The control terminal of the second output module 30 is connected to the control module 11. Based on the potential of the control terminal of the second output module 30, the first potential signal V1 is transmitted to the output terminal Sout of the shift register 401.

[0050] For example, when the potential of the first clock signal SCK1 is at the on level, the input module 10 is turned on, and the input signal SIN can be transmitted to the output terminal of the input module 10.

[0051] For example, when the input terminal I1 of the first inverting unit 40 is low, the output terminal O1 of the first inverting unit 40 outputs a high level; when the input terminal I1 of the first inverting unit 40 is high, the output terminal O1 of the first inverting unit 40 outputs a low level. For example, the potentials of the input terminal I1 and the output terminal O1 of the first inverting unit 40 are opposite.

[0052] For example, when the potential at the control terminal of the first output module 20 is at the on level, the first output module 20 is turned on, and the second clock signal SCK2 can be transmitted to the output terminal Sout of the shift register, so that the output terminal Sout of the shift register 401 outputs a valid level pulse P1.

[0053] For example, when the output terminal of input module 10 is at a high level, the control terminal of the first output module 20 is at a low level. Conversely, when the output terminal of input module 10 is at a low level, the control terminal of the first output module 20 is at a high level.

[0054] For example, the input terminal of the first inverting unit 40 and the output terminal of the input module 10 have the same potential, for example, both are at a high level and both are at a low level.

[0055] For example, the output terminal of the first inverting unit 40 and the control terminal of the first output module 20 have the same potential, for example, both are at a high level and both are at a low level. Or, for example, the potential of the output terminal of the first inverting unit 40 and the potential of the control terminal of the first output module 20 can synchronously jump to a high level and synchronously jump to a low level.

[0056] The output terminal of the input module 10 is connected to the control terminal of the first output module 20 via the first inverting unit 40, which facilitates setting the transistors in the first output module 20 as P-type transistors and setting the effective level pulse P1 output by the output terminal Sout of the shift register 401 as a high-level pulse. While maintaining the same output power, setting the transistors in the first output module 20 as P-type transistors, compared to setting them as N-type transistors, reduces the size of the transistors in the first output module 20 and the space they occupy, thereby helping to reduce the bezel width of the display panel and achieve a narrow bezel.

[0057] For example, control module 11 can output control signals to the control terminal of second output module 30.

[0058] For example, when the potential at the control terminal of the second output module 30 is at the on level, the second output module 30 is turned on, and the first potential signal V1 can be transmitted to the output terminal Sout of the shift register.

[0059] For example, the effective level of the valid pulse P1 output by the output terminal Sout of the shift register 401 may be different from the first potential signal V1. For example, one of the valid pulse P1 output by the output terminal Sout of the shift register 401 and the first potential signal V1 may be low, and the other may be high. For example, the valid pulse P1 output by the output terminal Sout of the shift register 401 may be high, and the first potential signal V1 may be low (VGL).

[0060] For example, the first output module 20 and the second output module 30 can be turned on in a time-division manner, such as alternating between the two.

[0061] For example, when the output of shift register 401, Sout, outputs a valid level pulse P1, the second output module 30 is turned off.

[0062] For example, the switching states of the first output module 20 and the second output module 30 are opposite. For instance, when the first output module 20 is turned on, the second output module 30 is turned off; when the second output module 30 is turned on, the first output module 20 is turned off.

[0063] For example, the signal output from the output terminal Sout of shift register 401 can be used as a scanning signal or a light control signal.

[0064] For example, the output Sout of shift register 401 can provide a gate signal for the gate of the N-type transistor in the pixel circuit.

[0065] The shift register 401 in this embodiment has a simple structure, which helps to reduce the bezel width of the display panel and achieve a narrow bezel.

[0066] In this embodiment, the shift register 401 includes an input module 10, a first inverting unit 40, a first output module 20, a control module 11, and a second output module 30. The input terminal of the input module 10 is connected to an input signal SIN. The input module 10 controls the transmission of the input signal SIN to its output terminal based on at least a first clock signal SCK1. The input terminal of the first inverting unit 40 is connected to the output terminal of the input module 10. The control terminal of the first output module 20 is connected to the output terminal of the first inverting unit 40. The first output module 20 controls the transmission of a second clock signal SCK2 to the output terminal Sout of the shift register 401 based on the potential of its control terminal. The control module 11 is connected to at least one of the input module 10, the first inverting unit 40, and the first output module 20. The control terminal of the second output module 30 is connected to the control module 11. The second output module 30 controls the transmission of a first potential signal V1 to the output terminal Sout of the shift register 401 based on the potential of its control terminal. This configuration helps to reduce the bezel width of the display panel, achieving a narrow bezel.

[0067] Figure 2 This is a schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 2 The first output module 20 includes a first transistor M1. The first terminal of the first transistor M1 is connected to the second clock signal SCK2, the second terminal of the first transistor M1 is connected to the output terminal Sout of the shift register 401, and the gate of the first transistor M1 serves as the control terminal of the first output module 20.

[0068] For example, the first transistor M1 includes a P-type transistor, and / or the first transistor M1 includes a polysilicon transistor. To achieve the same output power, using P-type transistors in the first output module 20, compared to using N-type transistors, reduces the size of the transistors in the first output module 20, thereby facilitating a reduction in the bezel width of the display panel and achieving a narrow bezel. For example, the P-type transistor can be a polysilicon transistor.

[0069] P-type transistors or polysilicon transistors are smaller in size, which reduces space occupation. Furthermore, P-type transistors or polysilicon transistors are less prone to characteristic shift, making them more stable and reliable, which helps improve the reliability and stability of shift registers or gate drive circuits.

[0070] For example, see Figure 2 The first output module 20 or shift register 401 also includes a capacitor C1, which is connected between the second terminal and the gate of the first transistor M1.

[0071] Figure 3 This is a timing waveform diagram of a shift register provided in an embodiment of this application. For example, the effective level pulse P3 of the input signal SIN is a high-level pulse, and the effective level pulse P1 output by the output terminal Sout of the shift register 401 is a high-level pulse.

[0072] For example, the effective level pulse P3 of the input signal SIN overlaps with the effective level pulse P4 of the first clock signal SCK1.

[0073] For example, the effective level pulse P4 of the first clock signal SCK1 does not overlap with the effective level pulse P2 of the second clock signal SCK2. That is, the time period of the effective level pulse P4 of the first clock signal SCK1 and the time period of the effective level pulse P2 of the second clock signal SCK2 are different time periods, for example, they are staggered time periods.

[0074] For example, the effective level pulse P4 of the first clock signal SCK1 is a low level pulse, and the effective level pulse P2 of the second clock signal SCK2 is a high level pulse.

[0075] For example, the first clock signal SCK1 and the second clock signal SCK2 have the same frequency, for example, the same period.

[0076] For example, the effective level pulse P2 of the second clock signal SCK2 overlaps with the effective level pulse P1 output by the output terminal Sout of the shift register 401, for example, for synchronization. For example, the overlap may include partial overlap or complete coincidence. For example, the effective level pulse P2 of the second clock signal SCK2 and the effective level pulse P1 output by the output terminal Sout of the shift register 401 have the same width, for example, the same start time and the same end time.

[0077] For example, see Figure 2 The control module 11 includes a second inverting unit 50. The input terminal I2 of the second inverting unit 50 is connected to the output terminal O1 of the first inverting unit 40 and / or the control terminal of the first output module 20. The control terminal of the second output module 30 is connected to the output terminal O2 of the second inverting unit 50.

[0078] For example, when the input terminal I2 of the second inverting unit 50 is low, the output terminal O2 of the second inverting unit 50 outputs a high level; when the input terminal I2 of the second inverting unit 50 is high, the output terminal O2 of the second inverting unit 50 outputs a low level. For example, the potentials of the input terminal I2 and the output terminal O2 of the second inverting unit 50 are opposite. This configuration ensures that the control terminals of the first output module 20 and the second output module 30 have opposite potentials, allowing the first output module 20 and the second output module 30 to be turned on in a time-division multiplexing manner, transmitting the second clock signal SCK2 and the first potential signal V1 to the output terminal Sout of the shift register 401 in a time-division multiplexing manner.

[0079] For example, see Figure 2 The second output module 30 includes a second transistor M2. The first terminal of the second transistor M2 is connected to the first potential signal V1, the second terminal of the second transistor M2 is connected to the output terminal Sout of the shift register 401, and the gate of the second transistor M2 serves as the control terminal of the second output module 30.

[0080] For example, the second transistor M2 may include a P-type transistor or a polysilicon transistor. To achieve the same output power, using P-type transistors in the second output module 30, rather than N-type transistors, reduces the size of the transistors in the second output module 30, thereby facilitating a reduction in the bezel width of the display panel and achieving a narrow bezel. For example, the P-type transistor may be a polysilicon transistor.

[0081] For example, the first potential signal V1 is a low level VGL.

[0082] For example, when the control terminal of the first output module 20 is at a high level, the control terminal of the second output module 30 is at a low level. Conversely, when the control terminal of the first output module 20 is at a low level, the control terminal of the second output module 30 is at a high level. In other words, the potentials of the control terminals of the first and second output modules 30 are opposite in magnitude.

[0083] For example, see Figure 2 The control module 11 further includes a transmission unit 60. The control terminal of the transmission unit 60 is connected to a first clock signal SCK1. The first terminal of the transmission unit 60 is connected to at least one of the input terminal I1 of the first inverting unit 40 and the output terminal of the input module 10. The second terminal of the transmission unit 60 is connected to at least one of the output terminal O2 of the second inverting unit 50 and the control terminal of the second output module 30.

[0084] For example, the transmission unit 60 is turned on based on the first clock signal SCK1, connecting the first and second terminals of the transmission unit 60.

[0085] For example, during the period when the output terminal Sout of shift register 401 outputs a valid level pulse P1, the transmission unit 60 is turned on and the input module 10 is turned off.

[0086] For example, the transmission unit 60 includes a third transistor M3. The first gate of the third transistor M3 serves as the control terminal of the transmission unit 60. The first terminal of the third transistor M3 is connected to at least one of the input terminal I1 of the first inverting unit 40 and the output terminal of the input module 10, and the second terminal of the third transistor M3 is connected to at least one of the output terminal O2 of the second inverting unit 50 and the control terminal of the second output module 30.

[0087] For example, the transistors in the input module 10 and the transistors in the transmission unit 60 have different channel types. For instance, the channel types may include N-type and P-type. One of the transistors in the input module 10 and the transmission unit 60 may be an N-type transistor, and the other may be a P-type transistor. This configuration allows the gates of the transistors in the input module 10 and the transmission unit 60 to be connected to the same clock signal.

[0088] For example, the switching state of the transmission unit 60 is opposite to that of the input module 10. For example, when the input module 10 is on, the transmission unit 60 is off, and when the transmission unit 60 is on, the input module 10 is off. The transmission unit 60 can be used to latch the effective level corresponding to the effective level pulse P3 of the input signal SIN input to the input module 10 when the input module 10 is off, which is equivalent to maintaining the effective level corresponding to the effective level pulse P3 of the input signal SIN at the output of the input module 10.

[0089] For example, the third transistor M3 includes an N-type transistor, and / or the third transistor M3 includes an oxide transistor. For example, the N-type transistor may be an oxide transistor.

[0090] For example, see Figure 2 The input module 10 includes a fourth transistor M4. The first terminal of the fourth transistor M4 serves as the input terminal of the input module 10, the second terminal of the fourth transistor M4 serves as the output terminal of the input module 10, and the gate of the fourth transistor M4 is connected to the first clock signal SCK1.

[0091] For example, the fourth transistor M4 includes a P-type transistor, and / or the fourth transistor M4 includes a polysilicon transistor.

[0092] For example, see Figure 2The first inverting unit 40 includes a seventh transistor M7 and an eighth transistor M8. The first terminal of the seventh transistor M7 is connected to a first potential signal V1 or a low level VGL, and the first terminal of the eighth transistor M8 is connected to a second potential signal V2 or a high level VGH. The first gate of the seventh transistor M7 and the gate of the eighth transistor M8 are connected to the input terminal I1 of the first inverting unit 40. The second terminals of the seventh transistor M7 and the eighth transistor M8 are connected to the output terminal O1 of the first inverting unit 40.

[0093] For example, one of the first potential signal V1 and the second potential signal V2 is at a high level, and the other is at a low level.

[0094] For example, the second potential signal is a high level VGH, and the first potential signal is a low level VGL.

[0095] For example, the seventh transistor M7 and the eighth transistor M8 have different channel types. For example, one of the seventh transistor M7 and the eighth transistor M8 is a P-type transistor, and the other is an N-type transistor.

[0096] For example, the seventh transistor M7 includes an N-type transistor, and / or the seventh transistor M7 includes a metal-oxide transistor.

[0097] For example, the eighth transistor M8 includes a P-type transistor, and / or the eighth transistor M8 includes a polysilicon transistor.

[0098] For example, when the input terminal I1 of the first inverting unit 40 is high, the seventh transistor M7 is turned on and the eighth transistor M8 is turned off. The first potential signal V1 or the low level VGL is transmitted to the output terminal O1 of the first inverting unit 40 via the seventh transistor M7. For example, when the input terminal I1 of the first inverting unit 40 is low, the eighth transistor M8 is turned on and the seventh transistor M7 is turned off. The second potential signal V2 or the high level VGH is transmitted to the output terminal O1 of the first inverting unit 40 via the eighth transistor M8.

[0099] For example, see Figure 2 The second inverting unit 50 includes a ninth transistor M9 and a tenth transistor M10. The first terminal of the ninth transistor M9 is connected to a first potential signal V1 or a low level VGL, and the first terminal of the tenth transistor M10 is connected to a second potential signal V2 or a high level VGH. The first gate of the ninth transistor M9 and the gate of the tenth transistor M10 are connected to the input terminal I2 of the second inverting unit 50. The second terminals of the ninth transistor M9 and the tenth transistor M10 are connected to the output terminal O2 of the second inverting unit 50.

[0100] For example, the ninth transistor M9 and the tenth transistor M10 have different channel types. For example, one of the ninth transistor M9 and the tenth transistor M10 is a P-type transistor, and the other is an N-type transistor.

[0101] For example, the ninth transistor M9 includes an N-type transistor, and / or the ninth transistor M9 includes a metal-oxide transistor.

[0102] For example, the tenth transistor M10 includes a P-type transistor, and or, the tenth transistor M10 includes a polysilicon transistor.

[0103] For example, when the input terminal I2 of the second inverting unit 50 is high, the ninth transistor M9 is turned on and the tenth transistor M10 is turned off. The first potential signal V1 or the low level VGL is transmitted to the output terminal O2 of the second inverting unit 50 through the ninth transistor M9. For example, when the input terminal I2 of the second inverting unit 50 is low, the tenth transistor M10 is turned on and the ninth transistor M9 is turned off. The second potential signal V2 or the high level VGH is transmitted to the output terminal O2 of the second inverting unit 50 through the tenth transistor M10.

[0104] The working principle of the second inverting unit 50 is similar to that of the first inverting unit 40, and will not be described again here.

[0105] For example, the input terminal I1 of the first inverting unit 40, the output terminal of the input module 10, and the first terminal of the transmission unit 60 are connected to the first node Q'. For example, the input terminal I2 of the second inverting unit 50, the output terminal O1 of the first inverting unit 40, and the control terminal of the first output module 20 are connected to the second node QB. For example, the output terminal O2 of the second inverting unit 50, the control terminal of the second output module 30, and the second terminal of the transmission unit 60 are connected to the third node Q.

[0106] For example, see Figure 2 The shift register also includes a protection module 70. The first terminal of the protection module 70 is connected to the control terminal of the first output module 20, and the second terminal of the protection module 70 is connected to the output terminal O1 of the first inverting unit 40 and / or the input terminal I2 of the second inverting unit 50. The control terminal of the protection module 70 is connected to the first potential signal V1 or the low level VGL or the on level.

[0107] The protection module 70 can isolate the control terminal of the first output module 20 and the input terminal I2 of the second inverting unit 50, and / or isolate the control terminal of the first output module 20 and the output terminal O1 of the first inverting unit 40, so as to prevent the transistor connected to the second terminal of the protection module 70 from being damaged or broken down because the voltage of the control terminal of the first output module 20 is pulled down by the capacitor C1 when the second clock signal SCK2 jumps to a low level.

[0108] For example, protection module 70 can be a normally open module, which is equivalent to protection module 70 being in a normally open state.

[0109] For example, the protection module 70 includes a fifth transistor M5. The first terminal of the fifth transistor M5 can serve as the first terminal of the protection module 70, for example, by connecting to the control terminal of the first output module 20. The second terminal of the fifth transistor M5 can serve as the second terminal of the protection module 70, for example, by connecting to the output terminal of the first inverting unit 40 and / or the input terminal I2 of the second inverting unit 50. The gate of the fifth transistor M5 is connected to a first potential signal V1 or a low level VGL or a conduction level.

[0110] For example, the fifth transistor M5 may be a P-type transistor or a polysilicon transistor.

[0111] For example, see Figure 2 The shift register 401 also includes a reset module 80. The reset module 80 is connected to at least one of the output terminal of the input module 10 and the input terminal I1 of the first inverting unit 40. The reset module 80 transmits the control bit voltage Vr to at least one of the output terminal of the input module 10 and the input terminal I1 of the first inverting unit 40 based on the reset control signal RST.

[0112] The reset module 80 controls the first potential signal V1 or the low level VGL or the reset voltage Vr to transmit to at least one of the output terminal of the input module 10 and the input terminal I1 of the first inverting unit 40 based on the reset control signal RST.

[0113] During the power-on phase, the reset control signal RST can be at the on level, turning on the reset module 80 and transmitting either the first potential signal V1, a low level VGL, or a reset voltage Vr to at least one of the output terminal of the input module 10 or the input terminal I1 of the first inverting unit 40, thereby initializing the potential of at least one of these terminals. After the power-on phase, the reset control signal RST can be at the off level, turning off the reset module 80 and allowing the input module 10 to input a valid level pulse P3 of the input signal SIN.

[0114] For example, the reset voltage Vr may differ from the effective level of the effective pulse P3 of the input signal SIN. For example, the reset voltage Vr may be high and the effective level of the effective pulse P3 of the input signal SIN may be low.

[0115] For example, the reset voltage Vr can be the first potential signal V1 or a low level VGL.

[0116] For example, the first potential signal V1, or the low level VGL, or the reset voltage Vr can differ from the effective level of the effective level pulse P3 of the input signal SIN. For example, when the effective level of the effective level pulse P3 of the input signal SIN is high, the first potential signal V1 or the reset voltage Vr is low. For example, when the effective level of the effective level pulse P3 of the input signal SIN is low, the first potential signal V1 or the reset voltage Vr is high.

[0117] For example, see Figure 2 The reset module 80 includes a sixth transistor M6. The first terminal of the sixth transistor M6 can serve as the first terminal of the reset module 80, for example, by connecting a first potential signal V1, a low level VGL, or a reset voltage Vr. The second terminal of the sixth transistor M6 can serve as the second terminal of the reset module 80, for example, by connecting at least one of the output terminal of the input module 10 or the input terminal I1 of the first inverting unit 40. The gate of the sixth transistor M6 is connected to a reset control signal RST.

[0118] For example, the sixth transistor M6 may include an N-type transistor, and / or the sixth transistor M6 may include a P-type transistor.

[0119] Figure 3 Draw the voltage waveforms of the second node QB and the third node Q as an example. The voltages of the first node Q' and the third node Q are the same or identical. Compared to the first node Q', the potential of the third node Q is more stable and has less ripple.

[0120] Figure 3 Applicable to Figure 2 The shift register. See also Figure 2 and Figure 3 This section introduces the working process of shift registers, including the first-stage shift register. The working principles of each stage of the shift register are similar. The working process of a shift register may include part or all of the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4.

[0121] In the first stage t1, the input signal SIN is high, the first clock signal SCK1 is low, and the second clock signal SCK2 is low. The reset control signal RST can be off, for example, high. The input module 10 (which can be the fourth transistor M4) is turned on, transmitting the high level of the input signal SIN to the output terminal of the input module 10, the first node Q', and the input terminal I1 of the first inverter unit 40. The first inverter unit 40 can invert the high level of the input and output it. The output terminal O1 of the first inverter unit 40 outputs a low level to the input terminal I2 of the second inverter unit 50 and the second node QB. The low level output by the output terminal O1 of the first inverter unit 40 is transmitted through the turned-on protection module 70 (which can be the fifth transistor M5) to the control terminal (which can be the gate of the first transistor M1) of the first output module 20. The first output module 20 (which can be the first transistor M1) is turned on, transmitting the low level of the second clock signal SCK2 to the output terminal Sout of the shift register 401. The second inverting unit 50 can invert the low-level input and output a high-level signal. The output terminal O2 of the second inverting unit 50 outputs a high-level signal to the control terminal of the second output module 30 and the third node Q, thus turning off the second output module 30 (which may be the second transistor M2). The transmission unit 60 (which may be the third transistor M3) and the reset module 80 (which may be the sixth transistor M6) are also turned off.

[0122] In the second stage t2, the input signal SIN is low, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. The reset control signal RST can be off. Input module 10 (which can be the fourth transistor M4) is off, transmission unit 60 (which can be the third transistor M3) is on, the first node Q' and the third node Q are connected, and the potentials of the first node Q', the second node QB, and the third node Q are the same as the potentials in the first stage t1. The first output module 20 (which can be the first transistor M1) is on, and can transmit the valid level pulse P2 of the second clock signal SCK2 to the output terminal Sout of the shift register 401, that is, the output terminal Sout of the shift register 401 outputs the valid level pulse P1. The second output module 30 (which can be the second transistor M2) and the reset module 80 (which can be the sixth transistor M6) are off.

[0123] In the third stage t3, the input signal SIN is low, the first clock signal SCK1 is low, and the second clock signal SCK2 is low. The input module 10 (which can be the fourth transistor M4) is turned on, transmitting the low level of the input signal SIN to the output terminal of the input module 10, the first node Q', and the input terminal I1 of the first inverting unit 40. The first inverting unit 40 inverts the low level of the input and outputs a high level to the input terminal I2 of the second inverting unit 50 and the second node QB. The high level output by the output terminal O1 of the first inverting unit 40 is transmitted to the control terminal (which can be the gate of the first transistor M1) of the first output module 20 via the turned-on protection module 70 (which can be the fifth transistor M5). The first output module 20 (which can be the first transistor M1) is then turned off. The second inverting unit 50 inverts the high-level input and outputs a low-level signal. The output terminal O2 of the second inverting unit 50 outputs a low-level signal to the control terminal of the second output module 30 and the third node Q. The second output module 30 (which can be the second transistor M2) is then turned on, transmitting the first potential signal V1 to the output terminal Sout of the shift register 401. The transmission unit 60 (which can be the third transistor M3) and the reset module 80 (which can be the sixth transistor M6) are then turned off.

[0124] In the fourth stage t4, the input signal SIN is low, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. Input module 10 (which can be the fourth transistor M4) is turned off, transmission unit 60 (which can be the third transistor M3) is turned on, the first node Q' and the third node Q are connected, and the potentials of the first node Q', the second node QB, and the third node Q are the same as the potentials in the third stage t3. The first output module 20 (which can be the first transistor M1) is turned off. The second output module 30 (which can be the second transistor M2) is turned on, which can transmit the first potential signal V1 to the output terminal Sout of the shift register 401. Reset module 80 (which can be the sixth transistor M6) is turned off.

[0125] After the fourth stage t4, the third stage t3 and the fourth stage t4 can be repeated cyclically until the input signal SIN becomes high again and enters the first stage t1 again.

[0126] Figure 4 This is a schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 4 The at least one N-type transistor or at least one metal-oxide transistor further includes a second gate, and the second gate of the N-type transistor or the metal-oxide transistor is connected to a third potential signal VGL2.

[0127] This setting allows for regulation of the threshold voltage of N-type transistors or metal-oxide transistors, preventing the threshold voltage from being too low or too negative. This allows the N-type transistors or metal-oxide transistors to be turned off more effectively, thereby reducing leakage current.

[0128] For example, in an N-type transistor or a metal-oxide-semiconductor transistor, one of the first gate and the second gate is the top gate, and the other is the bottom gate. The top gate and the bottom gate of the same transistor can be located on opposite sides of the active portion of the transistor along the thickness direction of the active portion. For example, the top gate of the transistor is located above the active portion of the transistor, and the bottom gate of the transistor is located below the active portion of the transistor.

[0129] For example, the second gate of an N-type transistor or a metal-oxide transistor is a bottom gate.

[0130] For example, see Figure 4 The second gate of the third transistor M3 is connected to the third potential signal VGL2.

[0131] For example, see Figure 4 The second gate of the seventh transistor M7 is connected to the third potential signal VGL2.

[0132] For example, see Figure 4 The second gate of the ninth transistor M9 is connected to the third potential signal VGL2.

[0133] For example, the third potential signal VGL2 can be less than or equal to the first potential signal VGL.

[0134] For example, a smaller third potential signal VGL2 can regulate the threshold voltage of an N-type transistor or a metal-oxide transistor (e.g., at least one of the third transistor M3, the seventh transistor M7, and the ninth transistor M9), preventing the threshold voltage of the N-type transistor or metal-oxide transistor from being too small or too negative. This allows the N-type transistor or metal-oxide transistor to be turned off more effectively, thereby reducing leakage current.

[0135] In some embodiments, at least a portion of the N-type transistor or metal-oxide transistor includes only a first gate and excludes a second gate.

[0136] Figure 5 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 6 The timing waveform diagram of another shift register provided in the embodiments of this application. Figure 6 Applicable to Figure 5 The shift register in the database. For example, see [link to example]. Figure 5 and Figure 6 The fourth transistor M4 includes an N-type transistor, and / or the fourth transistor M4 includes a metal-oxide-semiconductor transistor. See, for example, [link to relevant documentation]. Figure 5 and Figure 6 The third transistor M3 includes a P-type transistor, and / or the third transistor M3 includes a polysilicon transistor. The effective level pulse P4 of the first clock signal SCK1 can be a high-level pulse.

[0137] Figure 5 and Figure 6 Corresponding technical solutions and Figure 2 and Figure 3 The corresponding technical solutions operate on similar principles, and will not be elaborated upon here. The differences lie in the channel type of the fourth transistor M4, the channel type of the third transistor M3, and the effective level pulse P4 of the first clock signal SCK1. Compared to... Figure 2 and Figure 3 The corresponding technical solution, Figure 5 and Figure 6 The corresponding technical solution and gate drive circuit can reduce the number of clock lines.

[0138] Figure 7 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 8 The timing waveform diagram of another shift register provided in the embodiments of this application. Figure 8 Applicable to Figure 7 The shift register in the database. For example, see [link to example]. Figure 7 and Figure 8 The control terminal of the transmission unit 60 is connected to the inverted clock signal SCK1B of the first clock signal SCK1. For example, the inverted clock signal SCK1B of the first clock signal SCK1 has the opposite potential to the first clock signal SCK1. For example, the transistors in the input module 10 and the transistors in the transmission unit 60 have the same channel type, for example, both are P-type transistors (see [reference]). Figure 7 ) or N-type transistor.

[0139] For example, see Figure 7 and Figure 8 The fourth transistor M4 includes a P-type transistor, and / or the fourth transistor M4 includes a polysilicon transistor; the third transistor M3 includes a P-type transistor, and / or the third transistor M3 includes a polysilicon transistor. The effective level pulse P4 of the first clock signal SCK1 can be a low-level pulse. For example, the gate of the fourth transistor M4 is connected to the inverted clock signal SCK1B of the first clock signal SCK1.

[0140] Figure 7 and Figure 8 Corresponding technical solutions and Figure 2 and Figure 3 The corresponding technical solutions operate on similar principles, and will not be elaborated upon here. The difference lies in the channel type of the third transistor M3. Compared to Figure 2 and Figure 3 The corresponding technical solution, Figure 7 and Figure 8 The corresponding technical solutions can reduce the number of N-type transistors or metal-oxide transistors, reduce the space occupied by shift registers, and help reduce the bezel width of the display panel.

[0141] In some embodiments, the fourth transistor M4 includes an N-type transistor, and / or the fourth transistor M4 includes a metal-oxide-semiconductor transistor; the third transistor M3 includes an N-type transistor, and / or the third transistor M3 includes a metal-oxide-semiconductor transistor. For example, it can be... Figure 7 The fourth transistor M4 and the third transistor M3 are both replaced with N-type transistors or metal-oxide transistors, corresponding to the following: Figure 8 By swapping the high and low levels of the first clock signal SCK1, Figure 8 The high and low potentials of the inverted clock signal SCK1B of the first clock signal SCK1 are swapped.

[0142] Figure 9a This is a schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 9a The control terminal of the second output module 30 is connected to at least one of the output terminal of the input module 10, the first terminal of the transmission unit 60, and the input terminal I1 of the first inverting unit 40.

[0143] Figure 3 Applicable to Figure 9a The shift register in the middle. Figure 3 and Figure 9a Corresponding technical solutions and Figure 2 and Figure 3 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0144] Figure 9b A timing waveform diagram of another shift register provided in an embodiment of this application. For example, see... Figure 9b The effective level pulse P1 output by the output terminal Sout of shift register 401 can be a low level pulse. For example, the output terminal Sout of shift register 401 is connected to the gate of the P-type transistor in the pixel circuit. For example, the effective level pulse P1 output by the output terminal Sout of shift register 401 can be output to the P-type transistor in the pixel circuit.

[0145] Figure 9b Applicable to Figure 2 The shift register in the middle. Figure 2 and Figure 9b Corresponding technical solutions and Figure 2 and Figure 3The working principle of the corresponding technical solutions is similar, and will not be elaborated here. The difference lies in the fact that the potential of the second clock signal SCK2 is reversed, and the effective level pulse P1 output by the output terminal Sout of the shift register 401 is different.

[0146] The shift register 401 may include some or all of the following: input module 10, first output module 20, first inverting unit 40, second inverting unit 50, transmission unit 60, second output module 30, protection module 70, and reset module 80. The control module 11 may include some or all of the second inverting unit 50 and transmission unit 60, and its structure can be configured as needed. The connection relationships between the modules can be configured as needed.

[0147] Based on the same inventive concept, this application provides another shift register. Figure 10 This is a schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 10 The shift register 401 includes: an input module 10, a first output module 20, a control module 11, and a second output module 30.

[0148] The input terminal of the input module 10 is connected to the input signal SIN, and the input module 10 controls the transmission of the input signal SIN to the output terminal of the input module 10 based at least on the first clock signal SCK1.

[0149] The control terminal of the first output module 20 is connected to the output terminal of the input module 10, and / or the control terminal of the first output module 20 and the output terminal of the input module 10 have the same potential. The first output module 20 controls the transmission of the second clock signal SCK2 to the output terminal Sout of the shift register 401 based on the potential of the control terminal of the first output module 20.

[0150] The control module 11 is connected to at least one of the input module 10 and the first output module 20.

[0151] The control terminal of the second output module 30 is connected to the control module 11. Based on the potential of the control terminal of the second output module 30, the first potential signal V1 is transmitted to the output terminal Sout of the shift register 401.

[0152] One of the effective level pulse P3 of the input signal SIN and the effective level pulse P1 output by the output terminal Sout of the shift register 401 is a low level pulse, and the other is a high level pulse.

[0153] This configuration allows for the use of P-type transistors in the first output module 20, and the setting of the effective level pulse P1 output by the shift register 401's output terminal Sout as a high-level pulse. While maintaining the same output power, using P-type transistors in the first output module 20, compared to using N-type transistors, reduces the size and space occupied by the transistors, thus facilitating a reduction in the display panel's bezel width and achieving a narrow bezel design.

[0154] The shift register 401 in this embodiment has a simple structure, which helps to reduce the bezel width of the display panel and achieve a narrow bezel.

[0155] This embodiment can be combined with some or all of the technical features in the above embodiments, which will not be repeated here.

[0156] For example, the effective level pulse P3 of the input signal SIN is a low level pulse, and the effective level pulse P1 output by the output terminal Sout of the shift register 401 is a high level pulse.

[0157] For example, the effective level pulse P3 of the input signal SIN overlaps with the effective level pulse P4 of the first clock signal SCK1.

[0158] For example, the effective level pulse P4 of the first clock signal SCK1 does not overlap with the effective level pulse P2 of the second clock signal SCK2.

[0159] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 11 The first output module 20 includes a first transistor M1. The first terminal of the first transistor M1 is connected to the second clock signal SCK2, the second terminal of the first transistor M1 is connected to the output terminal Sout of the shift register 401, and the gate of the first transistor M1 serves as the control terminal of the first output module 20.

[0160] For example, the first transistor M1 includes a P-type transistor, and / or the first transistor M1 includes a polysilicon transistor.

[0161] For example, see Figure 11 The control module 11 includes a first inverting unit 40. The input terminal of the first inverting unit 40 is connected to the output terminal of the input module 10. The control terminal of the second output module 30 is connected to the output terminal of the first inverting unit 40.

[0162] For example, see Figure 11The control module 11 may further include a second inverting unit 50. The input terminal of the second inverting unit 50 is connected to the output terminal of the first inverting unit 40.

[0163] For example, see Figure 11 The control module 11 may further include a transmission unit 60. The control terminal of the transmission unit 60 is connected to the first clock signal SCK1, the first terminal of the transmission unit 60 is connected to at least one of the input terminal of the first inverting unit 40 and the output terminal of the input module 10, and the second terminal of the transmission unit 60 is connected to the output terminal of the second inverting unit 50.

[0164] For example, the transistors in input module 10 and the transistors in transmission unit 60 have different channel types. For example, input module 10 includes a fourth transistor M4. The first terminal of the fourth transistor M4 serves as the input terminal of input module 10, the second terminal of the fourth transistor M4 serves as the output terminal of input module 10, and the gate of the fourth transistor M4 is connected to the first clock signal SCK1.

[0165] For example, the shift register 401 further includes a reset module 80, which is connected to at least one of the output terminal of the input module 10, the input terminal of the first inverting unit 40, and the control terminal of the first output module 20. For example, the reset module 80 controls the reset voltage Vr to be transmitted to at least one of the output terminal of the input module 10, the input terminal of the first inverting unit 40, and the control terminal of the first output module 20 based on a reset control signal.

[0166] For example, the reset voltage Vr may differ from the effective level of the effective pulse P3 of the input signal SIN. For example, the reset voltage Vr may be high and the effective level of the effective pulse P3 of the input signal SIN may be low.

[0167] For example, the reset voltage Vr can be the second potential signal V2.

[0168] For example, the reset module 80 controls the second potential signal V2 or the high level VGH or the reset voltage Vr to be transmitted to at least one of the output terminal of the input module 10, the input terminal of the first inverting unit 40, and the control terminal of the first output module 20 based on the reset control signal.

[0169] During the power-on phase, the reset control signal RST can be at the on level, turning on the reset module 80 and transmitting the second potential signal V2, a high level VGH, or a reset voltage Vr to at least one of the output terminal of the input module 10 and the input terminal I1 of the first inverting unit 40 to initialize the potential of at least one of these terminals. After the power-on phase, the reset control signal RST can be at the off level, turning off the reset module 80 and allowing the input module 10 to input a valid level pulse P3 of the input signal SIN.

[0170] For example, the second potential signal V2, or the high level VGH, or the reset voltage Vr can differ from the effective level of the effective level pulse P3 of the input signal SIN. For example, when the effective level of the effective level pulse P3 of the input signal SIN is high, the second potential signal V2 or the reset voltage Vr is low. For example, when the effective level of the effective level pulse P3 of the input signal SIN is low, the second potential signal V2 or the reset voltage Vr is high.

[0171] For example, shift register 401 also includes a protection module 70. The first terminal of the protection module 70 is connected to the control terminal of the first output module 20, the second terminal of the protection module 70 is connected to the output terminal of the input module 10 and / or the input terminal of the first inverting unit 40, and the control terminal of the protection module 70 is connected to a first potential signal V1 or a low level VGL.

[0172] For example, the input terminal I1 of the first inverting unit 40, the output terminal of the input module 10, the first terminal of the transmission unit 60, and the control terminal of the first output module 20 are connected to the first node Q'. For example, the input terminal I2 of the second inverting unit 50, the output terminal O1 of the first inverting unit 40, and the control terminal of the second output module 30 are connected to the second node QB. For example, the output terminal O2 of the second inverting unit 50 and the second terminal of the transmission unit 60 are connected to the third node Q.

[0173] Figure 12 The timing waveform diagram of another shift register provided in the embodiments of this application. Figure 12 Applicable to Figure 11 The shift register in [the system]. See [the source]. Figure 11 and Figure 12 This section introduces the working process of shift registers, specifically the first-stage shift register, as the working principles of each stage are similar. The shift register's operation can be divided into four stages: stage t1, stage t2, stage t3, and stage t4.

[0174] In the first stage t1, the input signal SIN is low, the first clock signal SCK1 is low, and the second clock signal SCK2 is low. The reset control signal RST can be off, for example, high. The input module 10 (which can be the fourth transistor M4) is turned on, transmitting the low level of the input signal SIN to the output terminal of the input module 10, the first node Q', and the input terminal I1 of the first inverting unit 40. The low level of the input signal SIN is transmitted to the control terminal (which can be the gate of the first transistor M1) of the first output module 20 via the turned-on protection module 70 (which can be the fifth transistor M5). The first output module 20 (which can be the first transistor M1) is turned on, transmitting the low level of the second clock signal SCK2 to the output terminal Sout of the shift register 401. The first inverting unit 40 inverts the input low level and outputs a high level. Its output terminal O1 outputs a high level to the input terminal I2 of the second inverting unit 50, the control terminal of the second output module 30 (which can be the gate of the second transistor M2), and the second node QB. The second output module 30 (which can be the second transistor M2) is then turned off. The second inverting unit 50 inverts the input high level and outputs a low level to the third node Q. The transmission unit 60 (which can be the third transistor M3) and the reset module 80 (which can be the sixth transistor M6) are then turned off.

[0175] In the second stage t2, the input signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. The reset control signal RST can be off. Input module 10 (which can be the fourth transistor M4) is off, transmission unit 60 (which can be the third transistor M3) is on, the first node Q' and the third node Q are connected, and the potentials of the first node Q', the second node QB, and the third node Q are the same as the potentials in the first stage t1. The first output module 20 (which can be the first transistor M1) is on, and can transmit the valid level pulse P2 of the second clock signal SCK2 to the output terminal Sout of the shift register 401, that is, the output terminal Sout of the shift register 401 outputs the valid level pulse P1. The second output module 30 (which can be the second transistor M2) and the reset module 80 (which can be the sixth transistor M6) are off.

[0176] In the third stage t3, the input signal SIN is high, the first clock signal SCK1 is low, and the second clock signal SCK2 is low. Input module 10 (which can be the fourth transistor M4) is turned on, transmitting the high level of the input signal SIN to the output terminal of input module 10, the first node Q', and the input terminal I1 of the first inverting unit 40. The high level of the input signal SIN is transmitted via the turned-on protection module 70 (which can be the fifth transistor M5) to the control terminal (which can be the gate of the first transistor M1) of the first output module 20, and the first output module 20 (which can be the first transistor M1) is turned off. The first inverting unit 40 inverts the high level of the input and outputs a low level from its output terminal O1 to the input terminal I2 of the second inverting unit 50, the control terminal (which can be the gate of the second transistor M2), and the second node QB. The second output module 30 (which can be the second transistor M2) is turned on, transmitting the first potential signal V1 to the output terminal Sout of the shift register 401. The second inverting unit 50 can invert the low-level input and output a high-level signal to the third node Q. The transmission unit 60 (which can be the third transistor M3) and the reset module 80 (which can be the sixth transistor M6) are turned off.

[0177] In the fourth stage t4, the input signal SIN is high, the first clock signal SCK1 is high, and the second clock signal SCK2 is high. Input module 10 (which can be the fourth transistor M4) is off, transmission unit 60 (which can be the third transistor M3) is on, the first node Q' and the third node Q are connected, and the potentials of the first node Q', the second node QB, and the third node Q are the same as the potentials in the third stage t3. The first output module 20 (which can be the first transistor M1) is off. The second output module 30 (which can be the second transistor M2) is on, and can transmit the first potential signal V1 to the output terminal Sout of the shift register 401. Reset module 80 (which can be the sixth transistor M6) is off.

[0178] After the fourth stage t4, the third stage t3 and the fourth stage t4 can be repeated cyclically until the input signal SIN becomes high again and enters the first stage t1 again.

[0179] Figure 13 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 14 The timing waveform diagram of another shift register provided in the embodiments of this application. Figure 14 Applicable to Figure 13 The shift register in the database. For example, see [link to example]. Figure 13 and Figure 14The fourth transistor M4 includes an N-type transistor, and / or, the fourth transistor M4 includes a metal-oxide-semiconductor transistor; the third transistor M3 includes a P-type transistor, and / or, the third transistor M3 includes a polysilicon transistor. The effective level pulse P4 of the first clock signal SCK1 can be a high-level pulse.

[0180] Figure 13 and Figure 14 Corresponding technical solutions and Figure 11 and Figure 12 The corresponding technical solutions operate on similar principles, and will not be elaborated upon here. The differences lie in the channel type of the fourth transistor M4, the channel type of the third transistor M3, and the effective level pulse P4 of the first clock signal SCK1. Compared to... Figure 11 and Figure 12 The corresponding technical solution, Figure 13 and Figure 14 The corresponding technical solution and gate drive circuit can reduce the number of clock lines.

[0181] Figure 15 This is a schematic diagram of another shift register provided in an embodiment of this application. Figure 16 The timing waveform diagram of another shift register provided in the embodiments of this application. Figure 16 Applicable to Figure 15 The shift register in the database. For example, see [link to example]. Figure 15 and Figure 16 The transistors in input module 10 and transmission unit 60 have the same channel type, for example, both are P-type transistors (see [reference]). Figure 15 ( ) or N-type transistor. The control terminal of the transmission unit 60 is connected to the inverted clock signal SCK1B of the first clock signal SCK1. For example, the inverted clock signal SCK1B of the first clock signal SCK1 has the opposite potential to the first clock signal SCK1.

[0182] For example, see Figure 15 and Figure 16 The fourth transistor M4 includes a P-type transistor, and / or the fourth transistor M4 includes a polysilicon transistor; the third transistor M3 includes a P-type transistor, and / or the third transistor M3 includes a polysilicon transistor. The effective level pulse P4 of the first clock signal SCK1 can be a low level pulse.

[0183] Figure 15 and Figure 16 Corresponding technical solutions and Figure 11 and Figure 12 The corresponding technical solutions operate on similar principles, and will not be elaborated upon here. The difference lies in the channel type of the third transistor M3. Compared to Figure 11 and Figure 12 The corresponding technical solution, Figure 15 and Figure 16 The corresponding technical solutions can reduce the number of N-type transistors or metal-oxide transistors, reduce the space occupied by shift registers, and help reduce the bezel width of the display panel.

[0184] In some embodiments, the fourth transistor M4 includes an N-type transistor, and / or the fourth transistor M4 includes a metal-oxide-semiconductor transistor; the third transistor M3 includes an N-type transistor, and / or the third transistor M3 includes a metal-oxide-semiconductor transistor. For example, it can be... Figure 15 The fourth transistor M4 and the third transistor M3 are both replaced with N-type transistors or metal-oxide transistors, corresponding to the following: Figure 16 By swapping the high and low levels of the first clock signal SCK1, Figure 16 The high and low potentials of the inverted clock signal SCK1B of the first clock signal SCK1 are swapped.

[0185] Figure 17 This is a schematic diagram of another shift register provided in an embodiment of this application. For example, see... Figure 17 The control terminal of the first output module 20 is connected to at least one of the second terminal of the transmission unit 60 and the output terminal O2 of the second inverting unit 50. For example, the first terminal of the protection module 70 is connected to the control terminal of the first output module 20, and the second terminal of the protection module 70 is connected to at least one of the second terminal of the transmission unit 60 and the output terminal O2 of the second inverting unit 50.

[0186] Figure 12 Applicable to Figure 17 The shift register in the middle. Figure 12 and Figure 17 Corresponding technical solutions and Figure 11 and Figure 12 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0187] The shift register 401 may include some or all of the following components: input module 10, first output module 20, first inverting unit 40, second inverting unit 50, transmission unit 60, second output module 30, protection module 70, and reset module 80. The control module 11 may include some or all of the following components: first inverting unit 40, second inverting unit 50, and transmission unit 60. The structure of the control module 11 can be configured as needed. The connection relationships between the modules can be configured as needed.

[0188] This application provides a gate driving circuit. Figure 18 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. See also... Figure 18The gate drive circuit 400 includes a plurality of cascaded shift registers 401 provided in any embodiment of this application, and possesses the beneficial effects of the shift registers 401 in any embodiment of this application, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0189] For example, see Figure 2 and Figure 18 The input terminal of the input module 10 in the (n+1)th stage shift register is connected to the output terminal O2 of the second inverting unit 50 in the nth stage shift register (that is, the second terminal of the third node Q or the transmission unit 60), or the control terminal of the second output module 30 in the nth stage shift register, or the output terminal of the input module 10 (that is, the first node Q' or the first terminal of the transmission unit 60), or the output terminal of the nth stage shift register, where n is an integer greater than or equal to 1.

[0190] For example, the output terminal O2 of the second inverting unit 50 in the nth stage shift register (that is, the second terminal of the third node Q or the second terminal of the transmission unit 60), or the control terminal of the second output module 30 in the nth stage shift register, or the output terminal of the input module 10 (that is, the first node Q' or the first terminal of the transmission unit 60), or the output terminal of the nth stage shift register can provide the input signal SIN of the input terminal of the input module 10 in the (n+1)th stage shift register.

[0191] For example, see Figure 2 and Figure 18 The input terminal of the first clock signal SCK1 of the nth stage shift register is connected to the first clock line L1. For example, the first clock line L1 can provide the first clock signal SCK1 to the nth stage shift register. For example, the input terminal of the first clock signal SCK1_1 of the first stage shift register is connected to the first clock line L1. For example, the input terminal of the first clock signal SCK1_3 of the third stage shift register is connected to the first clock line L1. For example, the input terminal of the first clock signal SCK1 of the odd-numbered stage shift register is connected to the first clock line L1. For example, n is an odd number.

[0192] For example, see Figure 2 and Figure 18 The input terminal of the first clock signal SCK1 of the (n+1)th stage shift register is connected to the second clock line L2. For example, the second clock line L2 can provide the first clock signal SCK1 to the (n+1)th stage shift register. For example, the input terminal of the first clock signal SCK1_2 of the second stage shift register is connected to the first clock line L1. For example, the input terminal of the first clock signal SCK1_4 of the fourth stage shift register is connected to the first clock line L1. For example, the input terminal of the first clock signal SCK1 of the even-numbered stage shift register is connected to the second clock line L2.

[0193] For example, see Figure 2 and Figure 18 The input terminal of the second clock signal SCK2 of the nth stage shift register is connected to the third clock line L3. For example, the third clock line L3 can provide the second clock signal SCK2 to the nth stage shift register. For example, the input terminal of the second clock signal SCK2_1 of the first stage shift register is connected to the third clock line L3. For example, the input terminal of the second clock signal SCK2_3 of the third stage shift register is connected to the third clock line L3. For example, the input terminal of the second clock signal SCK2 of the odd-numbered stage shift register is connected to the third clock line L3.

[0194] For example, see Figure 2 and Figure 18 The input terminal of the second clock signal SCK2 of the (n+1)th stage shift register is connected to the fourth clock line L4. For example, the fourth clock line L4 can provide the second clock signal SCK2 to the (n+1)th stage shift register. For example, the input terminal of the second clock signal SCK2_2 of the second stage shift register is connected to the fourth clock line L4. For example, the input terminal of the second clock signal SCK2_4 of the fourth stage shift register is connected to the fourth clock line L4. For example, the input terminal of the second clock signal SCK2 of the even-numbered stage shift register is connected to the fourth clock line L4.

[0195] Figure 19 The timing waveform diagram is provided for a gate driving circuit according to an embodiment of this application. Figure 19 Applicable to Figure 18 The gate drive circuit. For example, see... Figure 2 , Figure 3 , Figure 18 , Figure 19 The clock signal of the first clock line L1 has the same frequency as the clock signal of the second clock line L2, but different phases.

[0196] For example, see Figure 2 , Figure 3 , Figure 18 , Figure 19 The clock signal of the third clock line L3 has the same frequency as the clock signal of the fourth clock line L4, but different phases.

[0197] For example, see Figure 2 , Figure 3 , Figure 18 , Figure 19 The effective level pulse of the clock signal on the first clock line L1 overlaps with the effective level pulse of the clock signal on the fourth clock line L4. The effective level pulse of the clock signal on the second clock line L2 overlaps with the effective level pulse of the clock signal on the third clock line L3.

[0198] For example, see Figure 2 , Figure 3 , Figure 18 , Figure 19 When the potential on the first clock line L1 is high, the potential on the fourth clock line L4 is low. Conversely, when the potential on the first clock line L1 is low, the potential on the fourth clock line L4 is high. For example, the potentials of the first clock line L1 and the fourth clock line L4 are opposite.

[0199] For example, see Figure 2 , Figure 3 , Figure 18 , Figure 19 When the potential on the second clock line L2 is high, the potential on the third clock line L3 is low. Conversely, when the potential on the second clock line L2 is low, the potential on the third clock line L3 is high. For example, the potentials of the second clock line L2 and the third clock line L3 are opposite.

[0200] Figure 20 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application. Figure 21 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application. For example, see... Figure 20 or Figure 21 The gate drive circuit 400 also includes a third inverting unit 402 and / or a fourth inverting unit 403.

[0201] The third inverting unit 402 is connected between the first clock line L1 and the fourth clock line L4. For example, the first clock line L1 is connected to the input terminal of the third inverting unit 402, and the output terminal of the third inverting unit 402 is connected to the fourth clock line L4. Alternatively, for example, the fourth clock line L4 is connected to the input terminal of the third inverting unit 402, and the output terminal of the third inverting unit 402 is connected to the first clock line L1.

[0202] The fourth inverting unit 403 is connected between the second clock line L2 and the third clock line L3. For example, the second clock line L2 is connected to the input terminal of the fourth inverting unit 403, and the output terminal of the fourth inverting unit 403 is connected to the third clock line L3. Alternatively, for example, the third clock line L3 is connected to the input terminal of the fourth inverting unit 403, and the output terminal of the fourth inverting unit 403 is connected to the second clock line L2.

[0203] For example, see Figure 20 or Figure 21 The third inverting unit 402 includes an eleventh transistor M11 and a twelfth transistor M12.

[0204] For example, see Figure 20 or Figure 21 The fourth inverting unit 403 includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0205] The third inverting unit 402 has the same or similar structure or principle as the first inverting unit 40, and will not be described in detail here.

[0206] The fourth inverting unit 403 has the same or similar structure or principle as the first inverting unit 40, and will not be described in detail here.

[0207] Figure 22 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application. For example, see... Figure 22 , Figure 5 , Figure 6 The input terminal of the first clock signal SCK1 of the nth stage shift register is connected to the first clock line L1. The input terminal of the first clock signal SCK1 of the (n+1)th stage shift register is connected to the second clock line L2. The input terminal of the second clock signal SCK2 of the nth stage shift register is connected to the second clock line L2. The input terminal of the second clock signal SCK2 of the (n+1)th stage shift register is connected to the first clock line L1. This configuration reduces the number of clock lines, lowers the bezel width of the display panel, and achieves a narrow bezel.

[0208] Figure 23 This is a schematic diagram of another gate drive circuit provided in an embodiment of this application. For example, see... Figure 23 , Figure 7 , Figure 8 The input terminal of the inverted clock signal SCK1B of the first clock signal SCK1 of the nth stage (e.g., the odd-numbered stage) shift register is connected to the fourth clock line L4. The input terminal of the inverted clock signal SCK1B of the first clock signal SCK1 of the (n+1)th stage (e.g., the even-numbered stage) shift register is connected to the third clock line L3. For example, the input terminal of the inverted clock signal SCK1B_1 of the first clock signal SCK1 of the first stage shift register is connected to the fourth clock line L4. For example, the input terminal of the inverted clock signal SCK1B_2 of the first clock signal SCK1 of the second stage shift register is connected to the third clock line L3. For example, the input terminal of the inverted clock signal SCK1B_3 of the first clock signal SCK1 of the third stage shift register is connected to the fourth clock line L4. For example, the input terminal of the inverted clock signal SCK1B_4 of the first clock signal SCK1 of the fourth stage shift register is connected to the third clock line L3. For example, the fourth clock line L4 can provide the inverted clock signal SCK1B of the first clock signal SCK1 to the nth stage shift register. For example, the third clock line L3 can provide the inverted clock signal SCK1B of the first clock signal SCK1 to the (n+1)th stage shift register.

[0209] For example, Figure 18 Applicable to Figure 11 , Figure 12The corresponding technical solution.

[0210] For example, Figure 22 Applicable to Figure 13 , Figure 14 The corresponding technical solution.

[0211] For example, Figure 23 Applicable to Figure 15 , Figure 16 The corresponding technical solution.

[0212] For example, Figure 18 Applicable to Figure 3 , Figure 9a The corresponding technical solution.

[0213] For example, Figure 22 Applicable to Figure 2 , Figure 9b The corresponding technical solution.

[0214] For example, Figure 18 Applicable to Figure 12 , Figure 17 The corresponding technical solution.

[0215] In some embodiments, n is an even number.

[0216] For example, see Figure 18 The start signal line L0 can be connected to the input terminal of the input module 10 of the first-stage shift register 401, and the start signal line L0 can transmit the input signal SIN_1 of the first-stage shift register 10.

[0217] This application provides a display panel. Figure 24 This is a schematic diagram of a display panel provided in an embodiment of this application. The display panel 300 includes the gate driving circuit 400 provided in any of the above embodiments, and possesses the beneficial effects of the gate driving circuit 400 in any of the embodiments of this application, which will not be repeated here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0218] For example, the display panel 300 may include a display area 301 and a non-display area 302. The gate driving circuit 400 may be located in the non-display area 302.

[0219] For example, the display panel 300 may include light-emitting elements, which may be located in the display area 301.

[0220] For example, the display panel includes a plurality of pixel circuits 200 arranged in an array. For example, each column of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along a second direction Y.

[0221] For example, the multiple rows of pixel circuits 200 are arranged along the second direction Y. For example, each row of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along the first direction X.

[0222] Optionally, the display panel 300 includes gate lines L5, and the pixel circuit 200 is connected to the gate lines. For example, the gate lines extend along a first direction X. For example, multiple gate lines are arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, perpendicularly. For example, multiple data lines Data may extend along the second direction Y and be arranged along the first direction X.

[0223] For example, pixel circuit 200 includes N-type transistors or metal-oxide transistors, and gate drive circuit 400 is connected to the gate of the N-type transistors or metal-oxide transistors in pixel circuit 200.

[0224] Figure 25 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. For example, see... Figure 25 The pixel circuit 200 may include a driving transistor T1, and may also include a first reset transistor T4 and / or a compensation transistor T3. The first reset transistor T4 is connected to the driving transistor T1, for example, the first reset transistor T4 is connected to the gate or the second terminal of the driving transistor T1. The compensation transistor T3 is connected between the gate and the second terminal of the driving transistor T1.

[0225] For example, the gate drive circuit 400 (e.g., a first gate drive circuit) is connected to the gate of the first reset transistor T4. And / or, the gate drive circuit 400 (e.g., a second gate drive circuit) is connected to the gate of the compensation transistor T3.

[0226] For example, the first reset transistor T4 can be an N-type transistor or a metal-oxide-semiconductor transistor.

[0227] For example, the compensation transistor T3 can be an N-type transistor or a metal-oxide-semiconductor transistor.

[0228] The pixel circuit 200 may include some or all of the following: a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst. The first terminal of the first light-emitting control transistor T5 is connected to the first power supply voltage and / or the first power supply line VDD. The second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T1. The second terminal of the driving transistor T1 is electrically connected to the first terminal of the second light-emitting control transistor T6. The second terminal of the second light-emitting control transistor T6 is electrically connected to the first terminal (e.g., anode) of the light-emitting element 100. The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both connected to the light-emitting control signal EM. The second terminal (e.g., cathode) of the light-emitting element 100 is connected to the second power supply voltage and / or the second power supply line VSS. The first terminal of the data writing transistor T2 is connected to the data voltage Vdata. The second terminal of the data writing transistor T2 is electrically connected to the first terminal of the driving transistor T1. The gate of the data writing transistor T2 is connected to the third gate signal SP1. The first terminal of the compensation transistor T3 is electrically connected to the gate of the driving transistor T1. The second terminal of the compensation transistor T3 is electrically connected to the second terminal of the driving transistor T1. The threshold compensation transistor T3... The gate of the first reset transistor T4 is connected to the first initialization voltage Vref1, the first terminal of the second reset transistor T7 is connected to the second initialization voltage Vref2, the first terminal of the third reset transistor T8 is connected to the third initialization voltage VrefP, the second terminal of the first reset transistor T4 is electrically connected to the gate of the driving transistor T1, the second terminal of the second reset transistor T7 is electrically connected to the first terminal (e.g., anode) of the light-emitting element 100, the second terminal of the third reset transistor T8 is electrically connected to the first terminal of the driving transistor T1, the gate of the first reset transistor T4 is connected to the second gate signal SN1, the gate of the second reset transistor T7 is connected to the fourth gate signal SP2, the gate of the third reset transistor T8 is connected to the fourth gate signal SP2, the first terminal of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, the second terminal of the storage capacitor Cst is connected to the first power supply voltage and / or connected to the first power supply line VDD, and the driving transistor T1 generates a driving current according to the voltage of its gate to drive the light-emitting element 100 to emit light.

[0229] Figure 26 This is a schematic diagram of a display device provided in an embodiment of this application. This application also provides a display device 1, including the display panel 300 provided in any embodiment of this application.

[0230] For example, the display device includes a photosensitive element and a display panel provided in any embodiment of this application. The photosensitive element is used to receive light transmitted through the light-transmitting area. The photosensitive element may include one or more of a camera, a fingerprint recognition module, an ambient light sensor, an infrared sensor, etc.

[0231] Display devices include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablets, e-books, televisions, access control systems, smart landlines, consoles, laptops, wearable devices, in-vehicle displays, virtual reality (VR) and augmented reality (AR) and other near-eye display devices with display functions.

[0232] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0233] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0234] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A shift register, characterized in that, The shift register includes: An input module, wherein an input signal is connected to the input terminal of the input module, and the input module controls the transmission of the input signal to the output terminal of the input module based at least on a first clock signal; The first inverting unit has its input terminal connected to the output terminal of the input module; A first output module, the control terminal of the first output module is connected to the output terminal of the first inverting unit; the first output module controls the transmission of a second clock signal to the output terminal of the shift register based on the potential of the control terminal of the first output module. A control module, wherein the control module is connected to at least one of the input module, the first inverting unit, and the first output module; The second output module has its control terminal connected to the control module. The second output module transmits a first potential signal to the output terminal of the shift register based on the potential of the control terminal of the second output module.

2. The shift register according to claim 1, characterized in that, The first output module includes a first transistor, the first terminal of the first transistor is connected to the second clock signal, the second terminal of the first transistor is connected to the output terminal of the shift register, and the gate of the first transistor serves as the control terminal of the first output module. Preferably, the first transistor comprises a P-type transistor, and / or the first transistor comprises a polysilicon transistor; Preferably, the first output module further includes a capacitor connected between the second terminal and the gate of the first transistor; Preferably, the effective level pulse of the input signal is a high level pulse, and the effective level pulse output by the output terminal of the shift register is a high level pulse; Preferably, the effective level pulse of the input signal overlaps with the effective level pulse of the first clock signal; Preferably, the effective level pulses of the first clock signal and the effective level pulses of the second clock signal do not overlap; Preferably, the effective level pulse of the first clock signal is a low level pulse, and the effective level pulse of the second clock signal is a high level pulse; Preferably, when the output terminal of the input module is at a high level, the control terminal of the first output module is at a low level; when the output terminal of the input module is at a low level, the control terminal of the first output module is at a high level. Preferably, the first clock signal and the second clock signal have the same frequency.

3. The shift register according to claim 1, characterized in that, The control module includes: The second inverter unit has its input terminal connected to the output terminal of the first inverter unit and / or the control terminal of the first output module; the control terminal of the second output module is connected to the output terminal of the second inverter unit. Preferably, the second output module includes a second transistor, the first terminal of the second transistor is connected to the first potential signal, the second terminal of the second transistor is connected to the output terminal of the shift register, and the gate of the second transistor serves as the control terminal of the second output module; Preferably, the second transistor comprises a P-type transistor, and / or the second transistor comprises a polysilicon transistor; Preferably, the first potential signal is at a low level; Preferably, when the potential of the control terminal of the first output module is high, the potential of the control terminal of the second output module is low; when the potential of the control terminal of the first output module is low, the potential of the control terminal of the second output module is high.

4. The shift register according to claim 3, characterized in that, The control module further includes a transmission unit, the control terminal of which is connected to the first clock signal or an inverted clock signal of the first clock signal. The first end of the transmission unit is connected to at least one of the input terminal of the first inverting unit and the output terminal of the input module, and the second end of the transmission unit is connected to at least one of the output terminal of the second inverting unit and the control terminal of the second output module. Preferably, during the period when the output terminal of the shift register outputs a valid level pulse, the transmission unit is turned on and the input module is turned off; Preferably, the transmission unit includes a third transistor, and the first gate of the third transistor serves as the control terminal of the transmission unit. The first terminal of the third transistor is connected to at least one of the input terminal of the first inverting unit and the output terminal of the input module, and the second terminal of the third transistor is connected to at least one of the output terminal of the second inverting unit and the control terminal of the second output module. Preferably, the switching state of the transmission unit is opposite to that of the input module; Preferably, the control terminal of the transmission unit is connected to the first clock signal, and the transistors in the input module and the transistors in the transmission unit have different channel types; or, the control terminal of the transmission unit is connected to the inverted clock signal of the first clock signal, and the transistors in the input module and the transistors in the transmission unit have the same channel type. Preferably, the third transistor comprises an N-type transistor, and / or the third transistor comprises a metal-oxide-semiconductor transistor; Preferably, the input module includes a fourth transistor, the first terminal of the fourth transistor serves as the input terminal of the input module, the second terminal of the fourth transistor serves as the output terminal of the input module, and the gate of the fourth transistor is connected to the first clock signal or an inverted clock signal of the first clock signal; Preferably, the fourth transistor includes a P-type transistor, and / or the fourth transistor includes a polysilicon transistor; Preferably, the first inverting unit includes a seventh transistor and an eighth transistor, the first terminal of the seventh transistor is connected to the first potential signal, the first terminal of the eighth transistor is connected to the second potential signal, the first gate of the seventh transistor and the gate of the eighth transistor are connected to the input terminal of the first inverting unit; the second terminals of the seventh transistor and the second terminals of the eighth transistor are connected to the output terminal of the first inverting unit. Preferably, the seventh transistor comprises an N-type transistor; the eighth transistor comprises a P-type transistor; Preferably, the second inverting unit includes a ninth transistor and a tenth transistor, the first terminal of the ninth transistor is connected to the first potential signal, the first terminal of the tenth transistor is connected to the second potential signal, the first gate of the ninth transistor and the gate of the tenth transistor are connected to the input terminal of the second inverting unit; the second terminals of the ninth transistor and the tenth transistor are connected to the output terminal of the second inverting unit. Preferably, the ninth transistor comprises an N-type transistor; the tenth transistor comprises a P-type transistor; Preferably, the shift register further includes: a protection module, the first end of which is connected to the control terminal of the first output module, the second end of which is connected to the output terminal of the first inverting unit and / or the input terminal of the second inverting unit, and the control terminal of the protection module is connected to the first potential signal; Preferably, the protection module includes a fifth transistor, the first terminal of the fifth transistor is connected to the control terminal of the first output module, the second terminal of the fifth transistor is connected to the output terminal of the first inverting unit and / or the input terminal of the second inverting unit, and the gate of the fifth transistor is connected to the first potential signal; Preferably, the fifth transistor comprises a P-type transistor, and / or the fifth transistor comprises a polysilicon transistor; Preferably, at least one of the N-type transistors or at least one of the metal-oxide transistors further includes a second gate, and the second gate of the N-type transistor or the metal-oxide transistor is connected to a third potential signal; Preferably, one of the first gate and the second gate of the N-type transistor or the metal-oxide transistor is a top gate and the other is a bottom gate; Preferably, the second gate of the N-type transistor or the metal-oxide transistor is a bottom gate; Preferably, the second potential signal is at a high level, and the first potential signal is at a low level.

5. The shift register according to claim 1, characterized in that, The shift register further includes a reset module, which is connected to at least one of the output terminal of the input module and the input terminal of the first inverting unit. The reset module controls the first potential signal to be transmitted to at least one of the output terminal of the input module and the input terminal of the first inverting unit based on the reset control signal. Preferably, the reset module includes a sixth transistor, the first terminal of the sixth transistor is connected to a first potential signal, the second terminal of the sixth transistor is connected to at least one of the output terminal of the input module and the input terminal of the first inverting unit, and the gate of the sixth transistor is connected to the reset control signal.

6. A shift register, characterized in that, The shift register includes: An input module, wherein an input signal is connected to the input terminal of the input module, and the input module controls the transmission of the input signal to the output terminal of the input module based at least on a first clock signal; A first output module, wherein the control terminal of the first output module is connected to the output terminal of the input module, and / or the control terminal of the first output module has the same potential as the output terminal of the input module; the first output module controls the transmission of a second clock signal to the output terminal of the shift register based on the potential of the control terminal of the first output module. A control module, wherein the control module is connected to at least one of the input module and the first output module; The second output module has its control terminal connected to the control module. The second output module transmits a first potential signal to the output terminal of the shift register based on the potential of its control terminal. The effective level pulse of the input signal is a low level pulse, and the effective level pulse output by the output terminal of the shift register is a high level pulse.

7. The shift register according to claim 6, characterized in that, The first output module includes a first transistor, the first terminal of the first transistor is connected to the second clock signal, the second terminal of the first transistor is connected to the output terminal of the shift register, and the gate of the first transistor serves as the control terminal of the first output module. Preferably, the first transistor comprises a P-type transistor, and / or the first transistor comprises a polysilicon transistor; Preferably, the control module includes: The first inverting unit has its input terminal connected to the output terminal of the input module; the control terminal of the second output module is connected to the output terminal of the first inverting unit. The second inverting unit has its input terminal connected to the output terminal of the first inverting unit; A transmission unit, wherein the control terminal of the transmission unit is connected to the first clock signal or the inverted clock signal of the first clock signal, the first terminal of the transmission unit is connected to at least one of the input terminal of the first inverting unit and the output terminal of the input module, and the second terminal of the transmission unit is connected to the output terminal of the second inverting unit. Preferably, the control terminal of the first output module is connected to the output terminal of the input module or the output terminal of the second inverting unit; Preferably, the effective level pulses of the first clock signal and the effective level pulses of the second clock signal do not overlap; Preferably, the effective level pulse of the input signal overlaps with the effective level pulse of the first clock signal; Preferably, the control terminal of the transmission unit is connected to the first clock signal, and the transistors in the input module and the transistors in the transmission unit have different channel types; or, the control terminal of the transmission unit is connected to the inverted clock signal of the first clock signal, and the transistors in the input module and the transistors in the transmission unit have the same channel type. Preferably, the input module includes a fourth transistor, the first terminal of the fourth transistor serves as the input terminal of the input module, the second terminal of the fourth transistor serves as the output terminal of the input module, and the gate of the fourth transistor is connected to the first clock signal or an inverted clock signal of the first clock signal; Preferably, the shift register further includes a reset module, which is connected to at least one of the output terminal of the input module, the input terminal of the first inverting unit, and the control terminal of the first output module. The reset module controls the reset voltage to be transmitted to at least one of the output terminal of the input module, the input terminal of the first inverting unit, and the control terminal of the first output module based on the reset control signal. Preferably, the reset voltage is different from the effective level of the effective level pulse of the input signal; Preferably, one of the reset voltage and the effective level of the effective level pulse of the input signal is high, and the other is low; Preferably, the reset voltage is a second potential signal; Preferably, the shift register further includes a protection module, the first end of which is connected to the control terminal of the first output module, the second end of which is connected to the output terminal of the input module and / or the input terminal of the first inverting unit, and the control terminal of the protection module is connected to a first potential signal.

8. A gate driving circuit, characterized in that, This includes multiple cascaded shift registers as described in any one of claims 1-7.

9. The gate driving circuit according to claim 8, characterized in that, The input terminal of the input module in the (n+1)th stage shift register is connected to the output terminal of the second inverting unit in the nth stage shift register, or the control terminal of the second output module in the nth stage shift register, or the output terminal of the input module, or the output terminal of the nth stage shift register, where n is an integer greater than or equal to 1; Preferably, the input terminal of the first clock signal of the nth stage shift register is connected to the first clock line; The input terminal of the first clock signal of the shift register of the (n+1)th stage is connected to the second clock line; The input terminal of the second clock signal of the nth stage shift register is connected to the third clock line; The input terminal of the second clock signal of the shift register of the (n+1)th stage is connected to the fourth clock line; The clock signals of the first clock line and the clock signals of the second clock line have the same frequency but different phases. The clock signal of the third clock line has the same frequency as the clock signal of the fourth clock line, but different phase. Preferably, the effective level pulse of the clock signal on the first clock line overlaps with the effective level pulse of the clock signal on the fourth clock line; the effective level pulse of the clock signal on the second clock line overlaps with the effective level pulse of the clock signal on the third clock line. Preferably, when the potential on the first clock line is high, the potential on the fourth clock line is low; when the potential on the first clock line is low, the potential on the fourth clock line is high. When the potential on the second clock line is high, the potential on the third clock line is low; when the potential on the second clock line is low, the potential on the third clock line is high. Preferably, the gate driving circuit further includes a third inverting unit and / or a fourth inverting unit. The third inverting unit is connected between the first clock line and the fourth clock line; The fourth inverting unit is connected between the second clock line and the third clock line; Preferably, n is an odd number.

10. A display panel, characterized in that, include: The gate drive circuit as described in claim 8 or 9.

Images