Display driving circuit and electronic device

Abstract

The application discloses a display driving circuit and electronic equipment, and relates to the technical field of display, which can realize the function of multiple clock generating circuits in the prior art and reduce the number of clock generating circuits. Furthermore, the output gating circuit does not need to undertake the function of gating output of the first power voltage terminal and the second power voltage terminal, so that the structure of the output gating circuit is more simple, the area of the display driving circuit occupied by the output gating circuit is relatively small, and therefore, adding the output gating circuit does not increase the size of the display driving circuit, and even reduces the number of clock generating circuits, thereby realizing the effect of reducing the size of the display driving circuit. Thus, the application not only creates favorable conditions for the optimization of other circuits in the display driving circuit, but also effectively reduces the cost and power consumption.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driving circuit and electronic device. Background Technology

[0002] Electronic devices with display functions typically include a display panel and a display driver integrated circuit (DDIC) to drive the display panel to display images. The display panel usually has a gate driver circuit formed using array substrate row driving (GOA) technology. When the gate driver circuit is working, it needs to scan and drive the display panel based on the clock signal provided by the display driver circuit so that the display panel can realize the display function.

[0003] Typically, display driver circuits include a clock generation circuit to generate a clock signal for the gate driver circuit. Currently, a single clock generation circuit can only output one clock signal, while a gate driver circuit requires at least two. Furthermore, as the number of gate driver circuits in a display panel increases, the number of clock signals output by the display driver circuit also increases, leading to an increase in the number of clock generation circuits in the display driver circuit. This, in turn, increases the size of the display driver circuit, limiting the optimization space for other circuits within the display driver circuit and increasing its cost and power consumption. Summary of the Invention

[0004] This application provides a display driver circuit and electronic device that can reduce the size of the display driver circuit while supporting more clock signal outputs. This not only creates favorable conditions for the optimization of other circuits in the display driver circuit, but also effectively reduces cost and power consumption.

[0005] In a first aspect, this application provides a display driving circuit, which includes a clock generating circuit. The clock generating circuit comprises a gating control circuit, a power gating circuit, and an output gating circuit. The gating control circuit is connected to the power gating circuit and controls the power gating circuit to switch the first power supply voltage terminal and the second power supply voltage terminal on and off with the output terminal of the power gating circuit, respectively. Furthermore, the input terminal of the output gating circuit is connected to the output terminal of the power gating circuit. The output gating circuit has multiple clock output terminals and controls the switching between the input terminal of the output gating circuit and at least two clock output terminals, so that at least two clock output terminals output clock signals respectively.

[0006] Based on this, the display driver circuit in this embodiment, by setting an output gating circuit, can enable a single clock generation circuit to output at least two clock signals. This allows one clock generation circuit in this embodiment to effectively perform the functions of multiple clock generation circuits in the prior art, thereby reducing the number of clock generation circuits while supporting a greater number of clock signal outputs. Furthermore, since the output gating circuit does not need to handle the gating output of the first and second power supply voltage terminals, its structure can be simpler, occupying a relatively smaller area in the display driver circuit. This is significantly smaller than the area occupied by a single clock generation circuit in the prior art. Therefore, adding an output gating circuit does not increase the size of the display driver circuit; in fact, reducing the number of clock generation circuits can further reduce the size of the display driver circuit. Based on this, the display driver circuit in this embodiment not only creates favorable conditions for optimizing other circuits in the display driver circuit but also effectively reduces cost and power consumption, improving the product competitiveness of the display driver circuit.

[0007] In one possible implementation, the plurality of clock output terminals include a first clock output terminal and a second clock output terminal. The output gating circuit includes a first output switch and a second output switch. The first output switch is connected between the output terminal of the power gating circuit and the first clock output terminal, and the second output switch is connected between the output terminal of the power gating circuit and the second clock output terminal. Thus, the function of the output gating circuit can be realized by controlling the on and off states of the first and second output switches. Furthermore, since the switching technology is relatively mature, the implementation of the output gating circuit is relatively simple, reducing design difficulty and production costs. In addition, since the first and second output switches do not need to perform the function of gating the outputs of the first and second power supply voltage terminals, their switch structure can be simpler, occupying a relatively small area of ​​the display driver circuit, and will not significantly increase the occupied area.

[0008] In one possible implementation, the first output switch and the second output switch are transistors of the same conductivity type, and the control terminals of the first output switch and the second output switch are independent of each other. This allows the control terminals of the first and second output switches to receive control signals independently, preventing a short circuit caused by the first clock signal terminal and the second clock signal terminal being connected.

[0009] For example, both the first output switch and the second output switch are N-type transistors or P-type transistors.

[0010] In one possible implementation, the first output switch and the second output switch are transistors of different conductivity types, and the control terminals of the first and second output switches are interconnected. This allows the signals from the control terminals of the first and second output switches to be input through the same port, simplifying wiring, reducing design complexity, and minimizing the footprint of the clock generation circuit, while avoiding short circuits caused by connecting the first and second clock signal terminals.

[0011] For example, the first output switch is an N-type transistor and the second output switch is a P-type transistor. Alternatively, the first output switch is a P-type transistor and the second output switch is an N-type transistor.

[0012] In one possible implementation, the plurality of clock output terminals further includes an nth clock output terminal, which is connected to the first clock output terminal, where n is an odd number greater than 2. Since the display panel includes multiple gate driving circuits, the different gate driving circuits control different functions of the display panel scanning drive, but these gate driving circuits require the same clock signal. Therefore, to avoid signal interference, different clock output terminals need to output the same clock signal. Thus, by connecting the nth clock output terminal to the first clock output terminal, a single clock generation circuit can support outputting clock signals to multiple gate driving circuits, further reducing the size of the display driving circuit.

[0013] In one possible implementation, the multiple clock output terminals further include an nth clock output terminal, and the output gating circuit further includes an nth output switch. The nth clock output terminal is connected to the first clock output terminal or the output terminal of the power gating circuit via the nth output switch, where n is an odd number greater than 2. Therefore, by controlling the on / off state of the nth output switch, the output of the nth clock terminal can be controlled to determine whether it outputs a clock signal. For example, when the display panel supports partial scan driving, such as when some areas of the display panel require scan driving while others do not, the corresponding nth output switch can be turned off to avoid inputting clock signals to the gate drive circuit of the areas that do not require scan driving, thereby reducing power consumption.

[0014] In one possible implementation, the clock signal at the nth clock output is the same as the clock signal at the first clock output. This allows a single clock generation circuit to output the same clock signal to multiple gate drive circuits, further reducing the size of the display drive circuit.

[0015] In one possible implementation, the plurality of clock output terminals further includes an m-th clock output terminal, which is connected to the second clock output terminal, where m is an even number greater than 2. Since the display panel includes multiple gate driving circuits, the different gate driving circuits control different functions of the display panel scanning drive, but these gate driving circuits require the same clock signal. Therefore, to avoid signal interference, different clock output terminals need to output the same clock signal. Thus, by connecting the m-th clock output terminal to the second clock output terminal, a single clock generation circuit can support outputting clock signals to multiple gate driving circuits, further reducing the size of the display driving circuit.

[0016] In one possible implementation, the multiple clock output terminals further include an m-th clock output terminal, and the output gating circuit further includes an m-th output switch. The m-th clock output terminal is connected to the second clock output terminal or the output terminal of the power gating circuit via the m-th output switch, where m is an even number greater than 2. Therefore, whether the m-th clock output terminal outputs a clock signal can be controlled by controlling the on / off state of the n-th output switch. For example, when the display panel supports partial scan driving, such as when some areas of the display panel require scan driving while others do not, the corresponding m-th output switch can be turned off to avoid inputting clock signals to the gate drive circuit of the areas that do not require scan driving, thereby reducing power consumption.

[0017] In one possible implementation, the clock signal at the m-th clock output is the same as the clock signal at the second clock output. This allows a single clock generation circuit to output the same clock signal to multiple gate drive circuits, further reducing the size of the display drive circuit.

[0018] In one possible implementation, the power selection circuit includes a first selection switch and a second selection switch. The control terminal of the first selection switch is connected to a selection control circuit. A first terminal of the first selection switch is connected to a first power supply voltage terminal, and a second terminal is connected to the input terminal of the output selection circuit. Similarly, the control terminal of the second selection switch is connected to the selection control circuit. A first terminal of the second selection switch is connected to a second power supply voltage terminal, and a second terminal is connected to the input terminal of the output selection circuit. Thus, the function of the power selection circuit can be achieved by controlling the on and off states of the first and second selection switches. Furthermore, since switch technology is relatively mature, the implementation of the power selection circuit is relatively simple, reducing design complexity and production costs.

[0019] In one possible implementation, the first and second selector switches are transistors of the same conductivity type, and the control terminals of the first and second selector switches are independent of each other. This allows the control terminals of the first and second selector switches to independently receive control signals, preventing a short circuit caused by the connection between the first and second power supply voltage terminals.

[0020] For example, both the first gating switch and the second gating switch are N-type transistors or P-type transistors.

[0021] In one possible implementation, the first and second gating switches are transistors of different conductivity types, and their control terminals are interconnected. This allows the signals from the control terminals of both switches to be input from the same port, simplifying wiring, reducing design complexity, and minimizing the footprint of the clock generation circuit, while avoiding short circuits caused by connecting the first and second power supply voltage terminals.

[0022] For example, the first gating switch is an N-type transistor and the second gating switch is a P-type transistor. Alternatively, the first gating switch is a P-type transistor and the second gating switch is an N-type transistor.

[0023] In one possible implementation, the clock signals output from at least two clock output terminals include at least a first clock signal and a second clock signal. The first clock signal and the second clock signal have the same period and the same duty cycle, but different phases. Therefore, the clock signal requirements of any gate drive circuit can be met using as few clock generation circuits as possible, further reducing the size of the display drive circuit.

[0024] In one possible implementation, the phase difference between the first clock signal and the second clock signal is 180 degrees, further satisfying the clock signal requirements of any gate drive circuit.

[0025] In one possible implementation, the gating control circuit includes a level shifter (LS) circuit and a logic control circuit, which are connected together. The logic control circuit is also connected to the power gating circuit. The level shifter circuit receives a digital voltage signal, performs a level shift on the received digital voltage signal, and outputs it to the logic control circuit. The logic control circuit then converts the received signal to control the operation of the power gating circuit.

[0026] In one possible implementation, the gating control circuit is also connected to the output gating circuit for controlling the operation of the output gating circuit.

[0027] Secondly, this application also provides an electronic device, which includes a display panel and a display driving circuit. The display panel includes a gate driving circuit, and the display driving circuit is connected to the gate driving circuit. The display driving circuit is used to output a clock signal to the gate driving circuit. The display driving circuit is the same as that in the first aspect or various embodiments of the first aspect. Because the display driving circuit in the embodiments of this application has better performance, the electronic device including this display driving circuit also has better performance.

[0028] In one possible implementation, the multiple clock output terminals include a first clock output terminal and a second clock output terminal, which are connected to the same gate drive circuit. This allows for the use of as few clock generation circuits as possible to meet the clock signal requirements of any gate drive circuit, further reducing the size of the display drive circuit.

[0029] In one possible implementation, the display panel includes multiple gate driving circuits, and the multiple clock output terminals also include an nth clock output terminal, where n is an odd number greater than 2. The nth clock output terminal is connected to a different gate driving circuit than the first clock output terminal. Therefore, the clock signal requirements of multiple gate driving circuits can be met using as few clock generation circuits as possible, further reducing the size of the display driving circuit.

[0030] In one possible implementation, the display panel includes multiple gate driving circuits, and the multiple clock output terminals also include an m-th clock output terminal, where m is an even number greater than 2. The m-th clock output terminal and the second clock output terminal are connected to different gate driving circuits. Therefore, the clock signal requirements of multiple gate driving circuits can be met using as few clock generation circuits as possible, further reducing the size of the display driving circuit. Attached Figure Description

[0031] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0032] Figure 2 A schematic diagram of the structure of a display device provided in an embodiment of this application;

[0033] Figure 3 This is another schematic diagram of the structure of the display device provided in the embodiments of this application;

[0034] Figure 4 This is a schematic diagram of a display driving circuit in an embodiment of this application;

[0035] Figure 5 This is a signal timing diagram in one embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a clock generation circuit in an embodiment of this application;

[0037] Figure 7 This is another schematic diagram of the clock generation circuit in the embodiments of this application;

[0038] Figure 8 This is another schematic diagram of the clock generation circuit in the embodiments of this application;

[0039] Figure 9 This is yet another signal timing diagram in the embodiments of this application;

[0040] Figure 10 This is another schematic diagram of the clock generation circuit in the embodiments of this application;

[0041] Figure 11 This is another schematic diagram of the clock generation circuit in the embodiments of this application;

[0042] Figure 12 This is another schematic diagram of the clock generation circuit in the embodiments of this application.

[0043] Figure label:

[0044] 1-Electronic device; 11-Housing; 12-Display device; 100-Display panel; 110-Gate driving circuit; 200-Display driving circuit; 210-Clock generating circuit; 211-Gating control circuit; 2111-Level conversion circuit; 2112-Logic control circuit; 212-Power supply gating circuit; 213-Output gating circuit; PCK1 / PCK2-Clock pin; VGH-First power supply voltage terminal; VGL-Second power supply voltage terminal; PVGH / PVGL-Power supply pin; S CK1 - First clock signal; S CK2 - Second clock signal; CK1 - First clock output; CK2 - Second clock output; CK3 - Third clock output; CK4 - Fourth clock output; St1 - First output switch; St2 - Second output switch; St3 - Third output switch; St4 - Fourth output switch; Se1 - First gating switch; Se2 - Second gating switch; MSt1 / MSt2 / MSe1 / MSe2 - Transistors; S St1 / S St2 / S Se1 / S Se2 - Control signals. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0046] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0047] The display driving circuit provided in this application embodiment can be applied to electronic devices with display functions. These electronic devices include, for example, consumer electronics, home electronics, automotive electronics, and financial terminal electronics. Consumer electronics include, for example, mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include, for example, smart door locks, televisions, remote controls, refrigerators, and small household appliances (e.g., soymilk makers, robot vacuum cleaners). Automotive electronics include, for example, in-vehicle displays. Financial terminal products include, for example, Automated Teller Machines (ATMs) and self-service terminals.

[0048] For ease of explanation, we will use a mobile phone as an example below.

[0049] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of this application, referring to... Figure 1The electronic device 1 may include a housing 11 and a display device 12, with the display device 12 connected to the housing 11. Exemplarily, the display device 12 is fixedly mounted on the housing 11, which has a receiving cavity. Components such as the circuit board, electronic components, camera module, processor, and battery in the display device 12 can be installed within this cavity. Exemplarily, the housing 11 may include a mid-frame and a back cover, which can be either separate or integrated structures; this embodiment does not impose specific limitations. Furthermore, the housing 11 may be made of materials such as metal (e.g., aluminum alloy, titanium alloy, and stainless steel), plastic (e.g., acrylonitrile-butadiene-styrene, polycarbonate, and polypropylene), or glass (e.g., anti-glare glass) to meet the requirements of wear resistance, impact resistance, corrosion resistance, and aesthetics for the appearance of the electronic device 1.

[0050] Figure 2 This is a schematic diagram of a display device provided in an embodiment of this application, with reference to... Figure 2 The display device 12 may include a display panel 100 for displaying images. Exemplarily, the display panel 100 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, a mini light-emitting diode (Mini LED) display panel, a light-emitting diode (LED) display panel, etc.

[0051] For example, the display panel 100 has a display area AA and a border area. The display area AA may include a plurality of pixel units arranged in an array. Each pixel unit includes a plurality of sub-pixels. The sub-pixels have pixel circuits and light-emitting elements. The pixel circuits are used to drive the light-emitting elements to emit light. The pixel circuits include, but are not limited to, devices such as switching transistors and capacitors. The light-emitting elements may be one or more of OLED, QLED, Micro LED, Mini LED, and LED.

[0052] To drive the switching transistors in the pixel circuit, refer to... Figure 2The display panel 100 may include a gate driving circuit 110 in its bezel area. The gate driving circuit 110 provides gate driving signals to the switching transistors in the pixel circuit to drive the scanning of sub-pixels in the display panel, enabling the display panel to perform its display function. The gate driving signal controls the switching transistors to turn on and off, allowing the pixel circuit to drive the light-emitting elements to emit light. For example, the gate driving circuit 110 can be integrated into the display panel 100 using GOA (Gateway-Oriented Array) technology to improve integration, reduce cost, and achieve a narrow bezel.

[0053] During operation, the gate drive circuit 110 needs to receive a clock signal to achieve the function of outputting a gate drive signal. Therefore, refer to... Figure 2 The display device 12 also includes a display driving circuit 200, which is connected to the gate driving circuit 110. The display driving circuit 200 is used to output a clock signal (e.g., S) to the gate driving circuit 110. CK1 S CK2 This enables the gate driving circuit 110 to perform scanning drive on the display panel. For example, the display driving circuit 200 may have multiple clock pins (e.g., PCK1, PCK2), which are connected to the gate driving circuit 110, thereby outputting a clock signal (e.g., S) to the gate driving circuit 110 through the clock pins (e.g., PCK1, PCK2). CK1 S CK2 ).

[0054] In one embodiment, one or more gate driving circuits 110 may be disposed in the border area. It is understood that, in order to clearly illustrate the connection relationship between the display driving circuit 200 and the gate driving circuit 110 in this embodiment, Figure 2 The illustration takes one gate driving circuit 110 in the display panel as an example. In other embodiments of this application, two, three, four or more gate driving circuits 110 may be provided in the display panel, and this application does not limit this.

[0055] In one embodiment, the display driving circuit 200 may also integrate a source integrated circuit (Source IC) to provide data signals to the pixel circuits in the sub-pixels through the display driving circuit 200.

[0056] In one embodiment, the display device may also include a timing controller (TCON), a system-on-chip (SOC), etc. The SOC is connected to the TCON, and the TCON is connected to the display driver circuit 200. The SOC drives the TCON to control the operation of the display driver circuit 200. For example, the SOC outputs display data to the TCON. After processing the display data, the TCON outputs a digital voltage signal to the display driver circuit 200. Based on the digital voltage signal, the display driver circuit 200 outputs a clock signal to the gate driver circuit 110 and provides data signals to the pixel circuit, causing the display panel to display an image. Exemplarily, the TCON and the display driver circuit 200 can be integrated into one chip, or the TCON and the display driver circuit 200 can be respectively disposed in two chips.

[0057] As an example, refer to Figure 2 The display driver circuit 200 can be directly integrated onto the display panel 100 using a bonding process, which saves space and reduces the complexity of the wiring. This method is applicable to display panels of any structure, and is especially suitable for high-resolution and miniaturized display panels.

[0058] As another example, the display device may also include a circuit board (e.g., a printed circuit board (PCB)) and a flexible printed circuit board (FPC), with the circuit board connected to the display panel via the FPC. The display driving circuit 200 can be mounted on the circuit board using a bonding process, and then connected to the display panel via the circuit board and the FPC to achieve signal transmission. Alternatively, the display driving circuit 200 can also be mounted on the FPC using a bonding process, and then connected to the display panel via the FPC to achieve signal transmission.

[0059] Existing display driver circuits typically employ multiple clock generation circuits, each capable of outputting only one clock signal. However, a gate driver circuit requires at least two clock signals. Furthermore, as the number of gate driver circuits in a display panel increases, the number of clock signals output by the display driver circuit also increases, leading to a greater number of clock generation circuits required in the display driver circuit. This, in turn, increases the size of the display driver circuit, limiting the optimization space for other circuits within it and increasing both cost and power consumption.

[0060] To address the aforementioned issues, this application provides a display driver circuit that can reduce the size of the display driver circuit while supporting a greater number of clock signal outputs. This not only creates favorable conditions for optimizing other circuits in the display driver circuit but also effectively reduces cost and power consumption.

[0061] The structure of the display driving circuit 200 in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0062] Figure 3 This is another schematic diagram of the display device provided in the embodiments of this application. Figure 4 This is a schematic diagram of a display driving circuit in an embodiment of this application, with reference to... Figure 3 and Figure 4 The display driving circuit 200 in this embodiment may include a clock generating circuit 210, which is connected to the gate driving circuit 110 in the display panel 100. The clock generating circuit 210 outputs a clock signal (e.g., S) to the gate driving circuit 110. CK1 S CK2 ).

[0063] For example, refer to Figure 4 The clock generation circuit 210 may include a gating control circuit 211, a power gating circuit 212, and an output gating circuit 213. The gating control circuit 211 is connected to the power gating circuit 212, and controls the power gating circuit 212 so that the power gating circuit 212 can control the connection and disconnection between the first power supply voltage terminal VGH and the second power supply voltage terminal VGL and their respective output terminals. That is, the power gating circuit 212 is connected not only to the gating control circuit 211 but also to the first power supply voltage terminal VGH and the second power supply voltage terminal VGL. The gating control circuit 211 can control the operation of the power gating circuit 212. When the power gating circuit 212 is operating, it can control the connection and disconnection between the first power supply voltage terminal VGH and its output terminal, and it can also control the connection and disconnection between the second power supply voltage terminal VGL and its output terminal.

[0064] Furthermore, the input terminal of the output gating circuit 213 is connected to the output terminal of the power gating circuit 212. The output gating circuit 213 also has multiple clock output terminals (e.g., CK1, CK2), and the output gating circuit 213 is used to control the conduction and disconnection between the input terminal of the output gating circuit 213 and at least two clock output terminals, so that at least two clock output terminals output clock signals respectively. Thus, by setting the output gating circuit 213, a clock generation circuit 210 can output at least two clock signals, so that one clock generation circuit 210 in this embodiment can effectively realize the function of multiple clock generation circuits in the prior art, thereby reducing the number of clock generation circuits while supporting more clock signal outputs. Furthermore, since the output gating circuit 213 does not need to perform the function of gating the first power supply voltage terminal VGH and the second power supply voltage terminal VGL, its structure can be simpler, occupying a relatively small area in the display driver circuit 200. This is significantly smaller than the area of ​​a single clock generation circuit in the prior art. Therefore, adding the output gating circuit 213 does not increase the size of the display driver circuit 200; in fact, reducing the number of clock generation circuits can further reduce the size of the display driver circuit 200. Based on this, the display driver circuit 200 in this embodiment not only creates favorable conditions for optimizing other circuits within the display driver circuit 200 but also effectively reduces cost and power consumption, thereby improving the product competitiveness of the display driver circuit 200.

[0065] For example, refer to Figure 3 and Figure 4 The clock output terminals (e.g., CK1, CK2) are connected one-to-one with the clock pins (e.g., PCK1, PCK2), so that the clock signal output from the clock output terminals (e.g., CK1, CK2) can be input to the gate drive circuit 110 through the clock pins (e.g., PCK1, PCK2). Alternatively, the clock output terminals (e.g., CK1, CK2) can be directly used as clock pins (e.g., PCK1, PCK2), and this application does not limit this.

[0066] For example, the voltage at the first power supply voltage terminal VGH is the first power supply voltage, and the voltage at the second power supply voltage terminal VGL is the second power supply voltage. The first power supply voltage is generally greater than 0V, and the second power supply voltage is generally 0V or less than 0V. Furthermore, the specific values ​​of the first and second power supply voltages can be flexibly designed according to the actual application scenario, and this application does not limit them.

[0067] For example, refer to Figure 4The display driver circuit 200 may have multiple power supply pins (e.g., PVGH, PVGL). The first power supply voltage terminal VGH is connected to the power supply pin PVGH, and the second power supply voltage terminal VGL is connected to the power supply pin PVGL. Alternatively, the first power supply voltage terminal VGH may be directly used as the power supply pin PVGH, and the second power supply voltage terminal VGL may be directly used as the power supply pin PVGL. This application does not limit this.

[0068] In one embodiment, the display device may also include a power management integrated circuit (PMIC), which is connected to the power supply pins (e.g., PVGH, PVGL) of the display driver circuit 200 to provide the required voltage to the power supply pins (e.g., PVGH, PVGL).

[0069] In one embodiment of this application, reference is made to... Figure 5 , Figure 5 As an embodiment of the present application, the clock signals output by the at least two clock output terminals may include at least the first clock signal S. CK1 Second clock signal S CK2 First clock signal S CK1 Second clock signal S CK2 The clock signals have the same period, the same duty cycle, and different phases. Since the clock signals input to any gate driving circuit 110 typically have the characteristics of the same period, the same duty cycle, and different phases, in this embodiment, by enabling the same clock generation circuit 210 to support the output of clock signals with the same period, the same duty cycle, and different phases, the clock generation circuits 210 can be minimized to meet the clock signal requirements of any gate driving circuit 110, thereby further reducing the size of the display driving circuit 200.

[0070] For example, refer to Figure 5 First clock signal S CK1 Second clock signal S CK2 The phase difference can be 180 degrees, further satisfying the clock signal requirements of any gate drive circuit 110. Furthermore, the first clock signal S... CK1 Second clock signal S CK2 The cycle and duty cycle can be flexibly designed according to the needs of the actual application scenario, and are not limited here.

[0071] For example, refer to Figure 4 and Figure 5 The multiple clock output terminals of the output gating circuit 213 may include a first clock output terminal CK1 and a second clock output terminal CK2. The clock signal of the first clock output terminal CK1 is the first clock signal S. CK1The clock signal at the second clock output terminal CK2 is the second clock signal S. CK2 Therefore, the output gating circuit 213 can output the first clock signal S. CK1 Second clock signal S CK2 This allows the same clock generation circuit 210 to support two clock signals with the same output period, the same duty cycle, and a phase difference of 180 degrees.

[0072] In one embodiment of this application, reference is made to... Figure 3 and Figure 4 The first clock output terminal CK1 and the second clock output terminal CK2 can be connected to the same gate driving circuit, so that the clock generating circuit in this embodiment can provide the required clock signal to at least one gate driving circuit. For example, the display panel 100 may include multiple gate driving circuits, and the display driving circuit may include multiple clock generating circuits, each clock generating circuit being connected one-to-one with each gate driving circuit, so that each clock generating circuit can output the required clock signal to the corresponding gate driving circuit. This allows the number of clock generating circuits in this embodiment to be reduced by half compared to clock generating circuits in the prior art, significantly reducing the size of the display driving circuit. Alternatively, when the display panel 100 includes multiple gate driving circuits, for example, when some gate driving circuits require the same clock signal, the same clock generating circuit can be connected to all of those gate driving circuits, so that the first clock output terminal CK1 and the second clock output terminal CK2 are connected to multiple different gate driving circuits, further reducing the number of clock generating circuits and further reducing the size of the display driving circuit.

[0073] Figure 6 This is a schematic diagram of a clock generation circuit in an embodiment of this application, with reference to... Figure 6 In one embodiment of this application, the output gating circuit 213 may include a first output switch St1 and a second output switch St2. The first output switch St1 is connected between the output terminal of the power gating circuit 212 and the first clock output terminal CK1, and the second output switch St2 is connected between the output terminal of the power gating circuit 212 and the second clock output terminal CK2. Thus, the function of the output gating circuit 213 can be realized by controlling the on and off states of the first output switch St1 and the second output switch St2. Furthermore, since the switching technology is relatively mature, the implementation of the output gating circuit 213 is relatively simple, reducing design difficulty and production costs. In addition, since the first output switch St1 and the second output switch St2 do not need to perform the function of gating the outputs of the first power supply voltage terminal VGH and the second power supply voltage terminal VGL, their switching structure can be simpler, occupying a relatively small area of ​​the display driver circuit 200, and will not significantly increase the occupied area.

[0074] In one embodiment, reference is made to... Figure 6 The first output switch St1 has a first terminal and a second terminal. The first terminal of the first output switch St1 is connected to the output terminal of the power selection circuit 212, and the second terminal of the first output switch St1 is connected to the first clock output terminal CK1. In addition, the first output switch St1 also has a control terminal, which is used to receive control signals to control the conduction and disconnection of the first output switch St1.

[0075] In one embodiment, reference is made to... Figure 6 The second output switch St2 has a first terminal and a second terminal. The first terminal of the second output switch St2 is connected to the output terminal of the power selection circuit 212, and the second terminal of the second output switch St2 is connected to the second clock output terminal CK2. Furthermore, the second output switch St2 also has a control terminal, which is used to receive control signals to control the on and off states of the second output switch St2.

[0076] In one embodiment, the first output switch St1 and the second output switch St2 can be complementary in conduction; that is, when the first output switch St1 is on, the second output switch St2 is off, and when the first output switch St1 is off, the second output switch St2 is on. This avoids connecting the first clock output terminal CK1 and the second clock output terminal CK2, and prevents a short circuit between the two clock output terminals.

[0077] In one embodiment, reference is made to... Figure 7 , Figure 7 This is another schematic diagram of the clock generation circuit in the embodiments of this application. The first output switch St1 is set as transistor MSt1, and the second output switch St2 is set as transistor MSt2. Since the architecture of transistors MSt1 and MSt2 is relatively mature, the first output switch St1 and the second output switch St2 can be implemented relatively simply, reducing the design difficulty and production cost.

[0078] For example, a transistor may have a gate, a source, and a drain, with the gate used to control whether the transistor is turned on or off. When the transistor is on, current can flow between the source and drain. When the transistor is off, no current can flow between the source and drain. Based on this, refer to... Figure 7The control terminal of the first output switch St1 is the gate of transistor MST1, the first terminal of the first output switch St1 is the source of transistor MST1, and the second terminal of the first output switch St1 is the drain of transistor MST1; alternatively, the first terminal of the first output switch St1 is the drain of transistor MST1, and the second terminal of the first output switch St1 is the source of transistor MST1. Similarly, the control terminal of the second output switch St2 is the gate of transistor MST2, the first terminal of the second output switch St2 is the source of transistor MST2, and the second terminal of the second output switch St2 is the drain of transistor MST2; alternatively, the first terminal of the second output switch St2 is the drain of transistor MST2, and the second terminal of the second output switch St2 is the source of transistor MST2.

[0079] Since transistors can be classified into N-type transistors and P-type transistors based on their conductivity type, in one embodiment of this application, the first output switch St1 and the second output switch St2 can be configured as transistors of the same conductivity type. Furthermore, to ensure that the first output switch St1 and the second output switch St2 can be complementaryly activated, the control terminals of the first output switch St1 and the second output switch St2 are independent of each other, allowing the control terminals of the first output switch St1 and the second output switch St2 to independently receive control signals, thus preventing the first clock signal terminal and the second clock signal terminal from being connected. For example, refer to... Figure 5 and Figure 7 The first output switch St1 is an N-type transistor MST1, and the second output switch St2 is an N-type transistor MST2. The gates of transistor MST1 and MST2 are independent, meaning that the gate of transistor MST1 can receive the control signal S. St1 The gate of transistor MSt2 can receive the control signal S. St2 And control signal S St1 and S St2 A clock signal with opposite phase is used to enable transistors MSt1 and MSt2 to conduct complementaryly. Based on this, transistor MSt1 is controlled by the clock signal S. St1 It is turned on when the signal is high, and it is activated by the control signal S. St1 It is disconnected when the signal is low. Transistor MSt2 is activated by the control signal S. St2 It is turned on when the signal is high, and it is activated by the control signal S. St2 When the signal is low, the switch is disconnected. In other embodiments of this application, the first output switch St1 and the second output switch St2 can also both be configured as P-type transistors. Based on this, the first output switch St1 and the second output switch St2 are respectively connected when the control signal S is low. St1 and S St2 It is turned on when the signal is low, and is activated by the control signal S. St2 and S St2 Disconnect when the level is high.

[0080] For example, refer to Figure 5 Control signal S St1 and S St2 The period can be related to the clock signal (e.g., the first clock signal S). CK1 Second clock signal S CK2 The periods are the same.

[0081] As an example, refer to Figure 7 The output gating circuit 213 can also be controlled by the gating control circuit 211. Therefore, the output gating circuit 213 can also be connected to the gating control circuit 211, allowing the gating control circuit 211 to also control the operation of the output gating circuit 213. Based on this, when the output gating circuit 213 includes a first output switch St1 and a second output switch St2, the gating control circuit 211 is connected to the control terminals of the first output switch St1 and the second output switch St2, so that the control signal S... St1 and S St2 It can be output by the gating control circuit 211.

[0082] As yet another example, control signal S St1 and S St2 Alternatively, the input can be from other circuits in the display driver circuit 200, in which case the control terminal of the first output switch St1 and the control terminal of the second output switch St2 can be connected to other circuits in the display driver circuit 200.

[0083] The transistors in the embodiments of this application can be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), silicon carbide (SiC) MOSFETs, and other devices with switching functions. Repeated descriptions will not be repeated.

[0084] In one embodiment of this application, reference is made to... Figure 6The power selection circuit 212 may include a first selection switch Se1 and a second selection switch Se2. The control terminal of the first selection switch Se1 is connected to the selection control circuit 211. The first terminal of the first selection switch Se1 is connected to the first power supply voltage terminal VGH, and the second terminal of the first selection switch Se1 is connected to the input terminal of the output selection circuit 213. Similarly, the control terminal of the second selection switch Se2 is connected to the selection control circuit 211. The first terminal of the second selection switch Se2 is connected to the second power supply voltage terminal VGL, and the second terminal of the second selection switch Se2 is connected to the input terminal of the output selection circuit 213. Thus, the function of the power selection circuit 212 can be realized by controlling the on and off states of the first selection switch Se1 and the second selection switch Se2. Furthermore, since switch technology is relatively mature, the implementation of the power selection circuit 212 is relatively simple, reducing design difficulty and production costs.

[0085] In one embodiment, reference is made to... Figure 6 The control terminals of the first selector switch Se1 and the second selector switch Se2 are used to receive control signals to control the on and off states of the first selector switch Se1 and the second selector switch Se2. For example, the first selector switch Se1 and the second selector switch Se2 can be complementary in their conduction; that is, when the first selector switch Se1 is on, the second selector switch Se2 is off, and when the first selector switch Se1 is off, the second selector switch Se2 is on. This prevents the first power supply voltage terminal VGH and the second power supply voltage terminal VGL from being connected, thus avoiding a short circuit between the two power supply voltage terminals.

[0086] For example, refer to Figure 7 The first gating switch Se1 is configured as transistor MSe1, and the second gating switch Se2 is configured as transistor MSe2. Due to the mature architecture of transistors, the implementation of both gating switches Se1 and Se2 is relatively simple, reducing design complexity and production costs. Furthermore, the control terminal of the first gating switch Se1 can be the gate of transistor MSe1, its first terminal can be the source of transistor MSe1, and its second terminal can be the drain of transistor MSe1; alternatively, the first terminal of the first gating switch Se1 can be the drain of transistor MSe1, and its second terminal can be the source of transistor MSe1. Similarly, the control terminal of the second gating switch Se2 can be the gate of transistor MSe2, its first terminal can be the source of transistor MSe2, and its second terminal can be the drain of transistor MSe2; alternatively, the first terminal of the second gating switch Se2 can be the drain of transistor MSe2, and its second terminal can be the source of transistor MSe2.

[0087] In one embodiment of this application, the first gating switch Se1 and the second gating switch Se2 can be configured as transistors of the same conductivity type. Furthermore, in order to control the first gating switch Se1 and the second gating switch Se2 to conduct complementaryly, the control terminals of the first gating switch Se1 and the second gating switch Se2 are independent of each other, so that the control terminals of the first gating switch Se1 and the second gating switch Se2 can independently receive control signals. For example, refer to... Figure 5 and Figure 7 The first selection switch Se1 is an N-type transistor MSe1, and the second selection switch Se2 is an N-type transistor MSe2. The gates of transistor MSe1 and MSe2 are independent of each other, meaning that the gate of transistor MSe1 can receive the control signal S. Se1 The gate of transistor MSe2 can receive the control signal S. Se2 And control signal S Se1 and S Se2 A clock signal with opposite phase is used so that the first gating switch Se1 and the second gating switch Se2 can be complementaryly turned on. Based on this, transistor MSe1 is controlled by the clock signal S. Se1 It is turned on when the signal is high, and it is activated by the control signal S. Se1 It is disconnected when the signal is low. Transistor MSe2 is activated by the control signal S. Se2 It is turned on when the signal is high, and it is activated by the control signal S. Se2 When the signal is low, the switch is disconnected. In other embodiments of this application, the first gating switch Se1 and the second gating switch Se2 can also both be configured as P-type transistors. Based on this, the first gating switch Se1 and the second gating switch Se2 are respectively connected when the control signal S is low. Se1 and S Se2 Disconnect when the signal is high, as indicated by the control signal S. Se1 and S Se2 It is turned on when the voltage level is low.

[0088] For example, refer to Figures 5 to 7 Control signal S Se1 and S Se2 It can be output by the gating control circuit 211. Furthermore, the control signal S... Se1 and S Se2 The period can be the control signal S St1 and S St2 The period is K times the period of the integer K, where K is an integer and K≥2. For example, K can be 2, 3, 4 or other values, which are not limited here.

[0089] For example, the first output switch St1, the second output switch St2, the first gating switch Se1, and the second gating switch Se2 can all be configured as transistors of the same conductivity type. For example, refer to Figure 7The first output switch St1, the second output switch St2, the first gating switch Se1, and the second gating switch Se2 are all configured as N-type transistors. Alternatively, the first output switch St1, the second output switch St2, the first gating switch Se1, and the second gating switch Se2 can all be configured as P-type transistors. This allows for more flexible layout design and optimizes both area and performance.

[0090] It is understandable that, since the power selection circuit 212 architecture in the prior art is already very mature and has been widely used in the display driver circuit 200, the power selection circuit 212 in this application embodiment can also be directly implemented using the architecture in the prior art, which can significantly reduce development difficulty and cost while ensuring performance.

[0091] Understandably, since the first output switch St1 and the second output switch St2 do not need to perform the function of selecting the first power supply voltage terminal VGH and the second power supply voltage terminal VGL, while the first gating switch Se1 and the second gating switch Se2 do need to perform the function of selecting the first power supply voltage terminal VGH and the second power supply voltage terminal VGL, the area occupied by the first output switch St1 and the second output switch St2 is smaller than that occupied by the first gating switch Se1 and the second gating switch Se2, which can further reduce the size of the display driver circuit 200.

[0092] In one embodiment of this application, reference is made to... Figure 7 The gating control circuit 211 can receive a digital voltage signal and control the power gating circuit 212 to operate according to the digital voltage signal. For example, when the gating control circuit 211 is connected to the output gating circuit 213, the gating control circuit 211 also controls the output gating circuit 213 to operate according to the digital voltage signal. As an example, the gating control circuit 211 is connected to the TCON to receive the digital voltage signal output by the TCON.

[0093] For example, Figure 7 The gating control circuit 211 may include a level shifter (LS) 2111 and a logic control circuit 2112. The level shifter 2111 and the logic control circuit 2112 are connected, and the logic control circuit 2112 is connected to the power gating circuit 212. The level shifter 2111 is connected to the TCON and is used to receive digital voltage signals, perform level shifting on the received digital voltage signals, and output them to the logic control circuit 2112. The logic control circuit 2112 is used to convert the received signals and output control signals (e.g., S signals) to the power gating circuit 212. Se1 S Se2For example, the logic control circuit 2112 is connected to the control terminal of the first gating switch Se1 and the control terminal of the second gating switch Se2, so as to output control signals S to the first gating switch Se1 and the second gating switch Se2 respectively. Se1 and S Se2 .

[0094] For example, in the control signal S St1 and S St2 When the input is also from the gating control circuit 211, the logic control circuit 2112 is also connected to the output gating circuit 213 (e.g., the control terminal of the first output switch St1 and the control terminal of the second output switch St2) to output the control signal S. St1 and S St2 Understandably, in the control signal S St1 and S St2 When the input is also from the gating control circuit 211, since the first output switch St1 and the second output switch St2 do not need to perform the function of gating the first power supply voltage terminal VGH and the second power supply voltage terminal VGL, the area of ​​the level conversion circuit 2111 and the logic control circuit 2112 will not increase significantly.

[0095] Understandably, since the architecture of the level conversion circuit 2111 in the prior art is already very mature and has been widely used in the display driver circuit 200, the level conversion circuit 2111 in this application embodiment can be directly implemented using the architecture in the prior art, which can significantly reduce development difficulty and cost while ensuring performance.

[0096] For example, the logic control circuit 2112 can be implemented based on some logic gates (e.g., AND gates, NOT gates, etc.). Furthermore, since the architecture of the logic control circuit 2112 in the prior art is already very mature and has been widely used in the display driver circuit 200, the logic control circuit 2112 in this embodiment can also be directly implemented using the architecture in the prior art, which can significantly reduce development difficulty and cost while ensuring performance.

[0097] The above are merely examples illustrating some specific structures of the gating control circuit 211, power gating circuit 212, and output gating circuit 213 provided in the embodiments of this application. In specific implementations, the specific structures of the gating control circuit 211, power gating circuit 212, and output gating circuit 213 are not limited to the structures provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art based on the inventive concept of this application, which are not limited here.

[0098] The following is combined with Figure 5 and Figure 7The operation of the clock generation circuit 210 in the embodiments of this application will be described in detail. Figure 7 In this context, So represents the signal at the input terminal of the output gating circuit 213.

[0099] The level conversion circuit 2111 receives a digital voltage signal and converts it to a higher level before outputting it to the logic control circuit 2112. The logic control circuit 2112 then converts the received signal and outputs a control signal S. Se1 S Se2 S St1 and S St2 The following example uses "1" to represent a high level and "0" to represent a low level.

[0100] Control signal S Se1 The value is 1, and the control signal S is... Se2 When the value is 0, the first selection switch Se1 is turned on, the second selection switch Se2 is turned off, and the first power supply voltage input / output selection circuit 213 is activated at the first power supply voltage terminal VGH. During the Ta time period, the control signal S... St1 The value is 1, and the control signal S is... St2 When the value is 0, the first output switch St1 is turned on, the second output switch St2 is turned off, the first power supply voltage is input to the first clock output terminal CK1, and the first clock output terminal CK1 outputs a high level. Therefore, the first clock signal S... CK1 It is high level. After Ta time, the control signal S St1 and S St2 Level switching, control signal S St1 The value is 0, and the control signal S St2 When the value is 1, the first output switch St1 is open, the second output switch St2 is open, the first power supply voltage is input to the second clock output terminal CK2, and the second clock output terminal CK2 outputs a high level. Therefore, the second clock signal S... CK2 It is a high level.

[0101] Then, control signal S Se1 and S Se2 Level switching, control signal S Se1 The value is 0, and the control signal S Se2 When the value is 1, the first gating switch Se1 is open, the second gating switch Se2 is open, and the second power supply voltage input / output gating circuit 213 at the second power supply voltage terminal VGL is activated. Furthermore, the control signal S... St1 The value is 0, and the control signal S St2 When the value is 1, the first output switch St1 is open, the second output switch St2 is open, the second power supply voltage is input to the second clock signal terminal CK2, and the second clock signal terminal CK2 outputs a low level. Therefore, the second clock signal S... CK2The level changes to low. Furthermore, the first clock signal terminal CK1 remains high, causing the first clock signal S... CK1 It is a high level.

[0102] Then, control signal S Se1 and S Se2 The level switches again, control signal S Se1 The value is 1, and the control signal S is... Se2 When the value is 0, the first gating switch Se1 is turned on, the second gating switch Se2 is turned off, and the first power supply voltage input / output gating circuit 213 at the first power supply voltage terminal VGH is activated. During time Tb, the control signal S... St1 The value is 0, and the control signal S St2 When the value is 1, the first output switch St1 is open, the second output switch St2 is open, the first power supply voltage is input to the second clock signal terminal CK2, and the second clock signal S... CK2 When the voltage level changes from low to high, the first clock signal terminal CK1 remains high, making the first clock signal S... CK1 It is high level. After time Tb, the control signal S... St1 and S St2 The level switches again, control signal S St1 The value is 1, and the control signal S is... St2 When the value is 0, the first output switch St1 is turned on, the second output switch St2 is turned off, the first power supply voltage is input to the first clock signal terminal CK1, and the first clock signal S... CK1 When the signal is high, the second clock signal terminal CK2 remains high, causing the second clock signal S to... CK2 It is a high level.

[0103] Then, control signal S Se1 and S Se2 The level switches again, control signal S Se1 The value is 0, and the control signal S Se2 When the value is 1, the first gating switch Se1 is open, the second gating switch Se2 is open, and the second power supply voltage input / output gating circuit 213 at the second power supply voltage terminal VGL is activated. Furthermore, the control signal S... St1 The value is 1, and the control signal S is... St2 When the value is 0, the first output switch St1 is turned on, the second output switch St2 is turned off, the second power supply voltage is input to the first clock signal terminal CK1, and the first clock signal terminal CK1 outputs a low level, then the first clock signal S CK1 The level of the second clock signal changes to a low level. Furthermore, the second clock signal terminal CK2 remains high, causing the second clock signal S... CK2 It is a high level.

[0104] Then, this process can be repeated to output the first clock signal S.CK1 Second clock signal S CK2 .

[0105] Understandably, due to the first clock signal S CK1 Second clock signal S CK2 The high-level state is maintained for a short time, and there is no current discharge path for the output load (i.e., leakage current is small). The first clock signal S CK1 Second clock signal S CK2 Maintaining a high level will not cause any change in the operating state of the relevant transistors in the display panel.

[0106] Figure 8 This is another schematic diagram of the clock generation circuit in the embodiments of this application, referring to... Figure 8 This embodiment is a modification of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0107] In yet another embodiment of this application, reference is made to... Figure 8 The first output switch St1 and the second output switch St2 can also be configured as transistors of different conductivity types. For example, the first output switch St1 can be an N-type transistor MST1, and the second output switch St2 can be a P-type transistor MST2. Alternatively, the first output switch St1 can be a P-type transistor MST1, and the second output switch St2 can be an N-type transistor MST2.

[0108] For example, in order to control the first output switch St1 and the second output switch St2 to be complementaryly activated, the control terminals of the first output switch St1 and the second output switch St2 can be input with the same control signal. For example, refer to... Figure 9 , Figure 9 As another signal timing diagram in this application embodiment, the control terminals of the first output switch St1 and the second output switch St2 can receive control signal S. St1 So that the first output switch St1 is in control signal S St1 It is turned on when the signal is high, and it is activated by the control signal S. St1 When the signal is low, the switch is disconnected, and the second output switch St2 is activated by the control signal S. St1 Disconnect when the signal is high, in control signal S St1 It is turned on when the voltage level is low.

[0109] For example, the control terminals of the first output switch St1 and the second output switch St2 are interconnected so that the signals of the control terminals of the first output switch St1 and the second output switch St2 can be input from the same port, which simplifies wiring, reduces design difficulty, and also reduces the area occupied by the clock generation circuit.

[0110] As an example, refer to Figure 8 When the output gating circuit 213 includes a first output switch St1 and a second output switch St2, the control terminals of the first output switch St1 and the second output switch St2 are interconnected and connected to the gating control circuit 211, so that the gating control circuit 211 simultaneously outputs control signal S to the control terminals of the first output switch St1 and the second output switch St2. St1 .

[0111] As yet another example, control signal S St1 When input is received from other circuits in the display driver circuit 200, the control terminals of the first output switch St1 and the second output switch St2 are interconnected and connected to other circuits in the display driver circuit 200, so that these other circuits simultaneously output control signals S to the control terminals of the first output switch St1 and the second output switch St2. St1 .

[0112] In yet another embodiment of this application, reference is made to... Figure 8 The first gating switch Se1 and the second gating switch Se2 can also be configured as transistors of different conductivity types. For example, the first gating switch Se1 can be an N-type transistor MSt1, and the second gating switch Se2 can be a P-type transistor MSt2. Alternatively, the first gating switch Se1 can be a P-type transistor MSt1, and the second gating switch Se2 can be an N-type transistor MSt2.

[0113] For example, in order to control the first gating switch Se1 and the second gating switch Se2 to be complementaryly activated, the control terminals of the first gating switch Se1 and the second gating switch Se2 can be input with the same control signal. For example, refer to Figure 9 The control terminals of the first selector switch Se1 and the second selector switch Se2 can receive the control signal S. Se1 So that the first gating switch Se1 is in control signal S Se1 It is turned on when the signal is high, and it is activated by the control signal S. Se1 When the signal is low, it is disconnected, and the second gating switch Se2 is activated by the control signal S. Se1 Disconnect when the signal is high, in control signal S Se1 It is turned on when the voltage level is low.

[0114] For example, the control terminals of the first gating switch Se1 and the second gating switch Se2 are interconnected so that the control signals of the control terminals of the first gating switch Se1 and the second gating switch Se2 can be input from the same port, simplifying wiring, reducing design complexity, and also reducing the area occupied by the clock generation circuit. For example, refer to Figure 8When the output gating circuit 213 includes a first gating switch Se1 and a second gating switch Se2, the control terminals of the first gating switch Se1 and the second gating switch Se2 are interconnected and connected to the gating control circuit 211, so that the gating control circuit 211 simultaneously outputs control signals S to the control terminals of the first gating switch Se1 and the second gating switch Se2. Se1 .

[0115] In one embodiment, Figure 8 The clock generation circuit shown is combined with Figure 9 The working process of the signal timing diagram shown can be referred to Figure 7 The clock generation circuit shown is combined with Figure 5 The working process of the signal timing diagram shown is not detailed here.

[0116] Figure 10 This is another schematic diagram of the clock generation circuit in the embodiments of this application, referring to... Figure 10 This embodiment is a modification of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0117] In one embodiment, when the display panel 100 includes multiple gate driving circuits, since the switching transistors controlled by different gate driving circuits have different functions, but these gate driving circuits require the same clock signal, in order to avoid signal interference, they need to output the same clock signal from different clock output terminals. Based on this, in another embodiment of this application, the multiple clock output terminals may further include an nth clock output terminal, and the nth clock output terminal is connected to the first clock output terminal, which allows a clock generating circuit to support outputting clock signals to multiple gate driving circuits, further reducing the size of the display driving circuit. Here, n is an odd number greater than 2. For example, n can be 3, 5, 7, 9, etc., and is not limited here. For example, taking n=3 as an example, refer to... Figure 10 The plurality of clock output terminals may also include a third clock output terminal CK3, and the third clock output terminal CK3 is connected to the first clock output terminal CK1, so the clock signal of the third clock output terminal CK3 is the same as the clock signal of the first clock output terminal CK1.

[0118] For example, the clock signal at the nth clock output terminal is the same as the clock signal at the first clock output terminal, so that the clock generation circuit outputs a clock signal identical to the first clock signal. This allows one clock generation circuit to support outputting the same clock signal to multiple gate driving circuits, further reducing the size of the display driving circuit. Furthermore, the nth clock output terminal is connected to different gate driving circuits than the first clock output terminal. For example, refer to... Figure 10The first clock output terminal CK1 is connected to a gate drive circuit, and the third clock output terminal CK3 is connected to another gate drive circuit.

[0119] It is understandable that, in order to clearly illustrate the connection relationship between the nth clock output terminal and the first clock output terminal in the embodiments of this application, Figure 10 The third clock output terminal is used as an example for illustration. In other embodiments of this application, the plurality of clock output terminals may also include a fifth clock output terminal, a seventh clock signal terminal, a ninth clock signal terminal, etc., which will not be listed one by one in this application.

[0120] In another embodiment of this application, the plurality of clock output terminals may further include an m-th clock output terminal, and the m-th clock output terminal is connected to the second clock output terminal. This allows a clock generation circuit to support outputting clock signals to multiple gate driving circuits, further reducing the size of the display driving circuit. Here, m is an even number greater than 2. For example, m can be 4, 6, 8, 10, etc., and is not specifically limited here. For example, taking m = 4 as an example, refer to... Figure 10 The plurality of clock output terminals may also include a fourth clock output terminal CK4, and the fourth clock output terminal CK4 is connected to the second clock output terminal CK2, so the clock signal of the fourth clock output terminal CK4 is the same as the clock signal of the second clock output terminal CK2.

[0121] For example, the clock signal at the m-th clock output terminal is the same as the clock signal at the second clock output terminal, so that the clock generation circuit outputs a clock signal identical to the second clock signal. This allows one clock generation circuit to support outputting the same clock signal to multiple gate driving circuits, further reducing the size of the display driving circuit. Furthermore, the m-th clock output terminal and the second clock output terminal are connected to different gate driving circuits. For example, refer to... Figure 10 The second clock output terminal CK2 is connected to a gate drive circuit, and the fourth clock output terminal CK4 is connected to another gate drive circuit.

[0122] Understandably, in order to clearly demonstrate the connection relationship between the m-th clock output terminal and the second clock output terminal in the embodiments of this application, Figure 10 The fourth clock output terminal is used as an example for illustration. In other embodiments of this application, the plurality of clock output terminals may also include a sixth clock output terminal, an eighth clock signal terminal, a tenth clock signal terminal, etc., which will not be listed one by one in this application.

[0123] In another embodiment of this application, the first clock output terminal CK1 and the second clock output terminal CK2 can be connected to a gate driving circuit, and the third clock output terminal CK3 and the fourth clock output terminal CK4 can be connected to another gate driving circuit. Based on this, when m = n+1, the nth clock output terminal and the mth clock output terminal can be connected to the same gate driving circuit, and the mth clock output terminal and the (n-1)th clock output terminal can be connected to different gate driving circuits. For example, when n = 5 and m = 6, the fifth clock output terminal and the sixth clock output terminal can be connected to the same gate driving circuit, and the fifth clock output terminal and the fourth clock output terminal can be connected to different gate driving circuits.

[0124] Figure 11 This is another schematic diagram of the clock generation circuit in the embodiments of this application, referring to... Figure 11 This embodiment is a modification of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0125] In another embodiment of this application, when the plurality of clock output terminals may further include an nth clock output terminal, the output gating circuit may further include an nth output switch, and the nth clock output terminal is connected to the first clock output terminal through the nth output switch. Thus, by controlling the on and off state of the nth output switch, the nth clock output terminal can output a clock signal. For example, if the gate driving circuit connected to the nth clock output terminal needs to perform scan driving on the display panel 100, the nth output switch can be controlled to be turned on to input the clock signal from the nth clock output terminal into the corresponding gate driving circuit. If the gate driving circuit connected to the nth clock output terminal does not need to perform scan driving on the display panel 100, the nth output switch can be controlled to be turned off to avoid inputting the clock signal into the corresponding gate driving circuit, thereby reducing power consumption. For example, when the display panel 100 supports partial scan driving, such as when some areas of the display panel need scan driving and some areas do not, the corresponding nth output switch can be controlled to be turned off to avoid inputting a clock signal into the gate driving circuit of the area that does not need scan driving, thereby reducing power consumption.

[0126] For example, taking n=3 as an example, refer to Figure 11The plurality of clock output terminals may further include a third clock output terminal CK3, and the output gating circuit may further include a third output switch St3, with the third clock output terminal CK3 connected to the first clock output terminal CK1 via the third output switch St3. Therefore, when the gate driving circuit connected to the third clock output terminal CK3 needs to scan and drive the display panel 100, the third output switch St3 can be turned on to input the clock signal from the third clock output terminal CK3 into the corresponding gate driving circuit. When the gate driving circuit connected to the third clock output terminal CK3 does not need to scan and drive the display panel 100, the third output switch St3 can be turned off to prevent the clock signal from being input into the corresponding gate driving circuit, thus reducing power consumption.

[0127] For example, the implementation of the structure of any nth output switch can refer to the implementation of the structure of the first output switch, and will not be described in detail here. Furthermore, the control terminal of any nth output switch and the control terminal of the first output switch are independent of each other, that is, the control terminal of any nth output switch and the control terminal of the first output switch independently receive control signals to independently control the working state of any nth output switch and the first output switch.

[0128] For example, the clock signal of any nth clock output is the same as that of the first clock output.

[0129] Understandably, in order to clearly illustrate the connection relationship between the nth clock output terminal, the nth output switch, and the first clock output terminal in the embodiments of this application, Figure 11 The third clock output terminal and the third output switch are used as examples for illustration. In other embodiments of this application, the plurality of clock output terminals may also include a fifth clock output terminal and the output gating circuit may also include a fifth output switch; the plurality of clock output terminals may also include a seventh clock output terminal and the output gating circuit may also include a seventh output switch; the plurality of clock output terminals may also include a ninth clock output terminal and the output gating circuit may also include a ninth output switch. These will not be listed one by one in this application.

[0130] In another embodiment of this application, when the plurality of clock output terminals further includes an m-th clock output terminal, the output gating circuit may further include an m-th output switch, and the m-th clock output terminal is connected to the second clock output terminal through the m-th output switch. Thus, by controlling the on and off state of the m-th output switch, the m-th clock output terminal can output a clock signal. For example, if the gate driving circuit connected to the m-th clock output terminal needs to perform scan driving on the display panel 100, the m-th output switch can be controlled to be turned on to input the clock signal from the m-th clock output terminal into the corresponding gate driving circuit. If the gate driving circuit connected to the m-th clock output terminal does not need to perform scan driving on the display panel 100, the m-th output switch can be controlled to be turned off to avoid inputting the clock signal into the corresponding gate driving circuit, thereby reducing power consumption. For example, when the display panel 100 supports partial scan driving, such as when some areas of the display panel need scan driving and some areas do not, the corresponding m-th output switch can be controlled to be turned off to avoid inputting a clock signal into the gate driving circuit of the area that does not need scan driving, thereby reducing power consumption.

[0131] For example, taking m=4 as an example, refer to Figure 11 The plurality of clock output terminals may further include a fourth clock output terminal CK4, and the output gating circuit may further include a fourth output switch St4, with the fourth clock output terminal CK4 connected to the second clock output terminal CK2 via the fourth output switch St4. Therefore, when the gate driving circuit connected to the fourth clock output terminal CK4 needs to scan and drive the display panel 100, the fourth output switch St4 can be turned on to input the clock signal from the fourth clock output terminal CK4 into the corresponding gate driving circuit. When the gate driving circuit connected to the fourth clock output terminal CK4 does not need to scan and drive the display panel 100, the fourth output switch St4 can be turned off to prevent the clock signal from being input into the corresponding gate driving circuit, thus reducing power consumption.

[0132] For example, the implementation of the structure of any m-th output switch can refer to the implementation of the structure of the second output switch, and will not be described in detail here. Furthermore, the control terminals of any m-th output switch and the second output switch are independent of each other, that is, the control terminals of any m-th output switch and the second output switch independently receive control signals.

[0133] For example, the clock signal of any m-th clock output terminal is the same as that of the second clock output terminal.

[0134] Understandably, in order to clearly illustrate the connection relationship between the m-th clock output terminal, the m-th output switch, and the second clock output terminal in the embodiments of this application, Figure 11The fourth clock output terminal and the fourth output switch are illustrated as an example. In other embodiments of this application, the plurality of clock output terminals may also include a sixth clock output terminal and the output gating circuit may also include a sixth output switch; the plurality of clock output terminals may also include an eighth clock output terminal and the output gating circuit may also include an eighth output switch; the plurality of clock output terminals may also include a tenth clock output terminal and the output gating circuit may also include a tenth output switch. These will not be listed one by one in this application.

[0135] Figure 12 This is another schematic diagram of the clock generation circuit in the embodiments of this application, referring to... Figure 12 This embodiment is a modification of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will only be described below; the similarities will not be repeated here.

[0136] In another embodiment of this application, the nth clock output terminal can also be connected to the output terminal of the power selection circuit via the nth output switch. Therefore, by controlling the on and off state of the nth output switch, the clock signal can be input to or not input to the corresponding gate drive circuit. For example, taking n=3 as an example, refer to... Figure 12 The plurality of clock output terminals may further include a third clock output terminal CK3, and the output gating circuit may further include a third output switch St3, with the third clock output terminal CK3 connected to the output terminal of the power gating circuit via the third output switch St3. Therefore, when the gate driving circuit connected to the third clock output terminal CK3 needs to scan and drive the display panel 100, the third output switch St3 can be controlled to alternately turn on and off to input the clock signal from the third clock output terminal CK3 into the corresponding gate driving circuit. When the gate driving circuit connected to the third clock output terminal CK3 does not need to scan and drive the display panel 100, the third output switch St3 can be controlled to turn off, preventing the clock signal from being input into the corresponding gate driving circuit and reducing power consumption.

[0137] For example, the control terminal of any nth output switch can be independent of the control terminal of the first output switch, meaning that the control terminals of the nth output switch and the first output switch independently receive control signals to independently control their operating states. Alternatively, the control terminal of any nth output switch can be connected to the control terminal of the first output switch, allowing for unified control of their operating states and reducing wiring complexity.

[0138] In another embodiment of this application, the m-th clock output terminal can also be connected to the output terminal of the power selection circuit via the m-th output switch. Therefore, by controlling the on and off state of the m-th output switch, the clock signal can be input to or not input to the corresponding gate drive circuit. For example, taking m=4 as an example, refer to... Figure 12 The plurality of clock output terminals may further include a fourth clock output terminal CK4, and the output gating circuit may further include a fourth output switch St4, with the fourth clock output terminal CK4 connected to the output terminal of the power gating circuit via the fourth output switch St4. Therefore, when the gate driving circuit connected to the fourth clock output terminal CK4 needs to scan and drive the display panel 100, the fourth output switch St4 can be controlled to alternately turn on and off to input the clock signal from the fourth clock output terminal CK4 into the corresponding gate driving circuit. When the gate driving circuit connected to the fourth clock output terminal CK4 does not need to scan and drive the display panel 100, the fourth output switch St4 can be controlled to turn off, preventing the clock signal from being input into the corresponding gate driving circuit and reducing power consumption.

[0139] For example, the control terminal of any m-th output switch can be independent of the control terminal of the second output switch, meaning that the control terminals of any m-th output switch and the second output switch independently receive control signals to independently control the operating state of any m-th output switch and the second output switch. Alternatively, the control terminal of any m-th output switch can be interconnected with the control terminal of the second output switch, allowing for unified control of the operating states of the m-th output switch and the second output switch, thus reducing wiring complexity.

[0140] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A display driving circuit, characterized in that, The clock generation circuit includes: a gating control circuit, a power gating circuit, and an output gating circuit. The gating control circuit is connected to the power gating circuit and is used to control the power gating circuit so that the power gating circuit controls the connection and disconnection between the first power voltage terminal and the second power voltage terminal and the output terminal of the power gating circuit, respectively. The input terminal of the output gating circuit is connected to the output terminal of the power gating circuit. The output gating circuit has multiple clock output terminals, which are used to control the conduction and disconnection between the input terminal of the output gating circuit and at least two of the clock output terminals, so that the at least two clock output terminals output clock signals respectively.

2. The display driving circuit according to claim 1, characterized in that, The plurality of clock output terminals include a first clock output terminal and a second clock output terminal, and the output gating circuit includes a first output switch and a second output switch. The first output switch is connected between the output terminal of the power selection circuit and the first clock output terminal, and the second output switch is connected between the output terminal of the power selection circuit and the second clock output terminal.

3. The display driving circuit according to claim 2, characterized in that, The first output switch and the second output switch are transistors of the same conductivity type, and the control terminals of the first output switch and the second output switch are independent of each other; or... The first output switch and the second output switch are transistors of different conductivity types, and the control terminals of the first output switch and the second output switch are connected to each other.

4. The display driving circuit according to claim 2 or 3, characterized in that, The plurality of clock output terminals also includes an nth clock output terminal, where n is an odd number greater than 2; Wherein, the nth clock output terminal is connected to the first clock output terminal; or, The output gating circuit further includes an nth output switch, and the nth clock output terminal is connected to the first clock output terminal or the output terminal of the power gating circuit through the nth output switch.

5. The display driving circuit according to claim 4, characterized in that, The clock signal at the nth clock output terminal is the same as the clock signal at the first clock output terminal.

6. The display driving circuit according to any one of claims 2-5, characterized in that, The plurality of clock output terminals also includes the m-th clock output terminal, where m is an even number greater than 2; The m-th clock output terminal is connected to the second clock output terminal; or, The output gating circuit further includes an m-th output switch, and the m-th clock output terminal is connected to the second clock output terminal or the output terminal of the power gating circuit through the m-th output switch.

7. The display driving circuit according to claim 6, characterized in that, The clock signal at the m-th clock output terminal is the same as the clock signal at the second clock output terminal.

8. The display driving circuit according to any one of claims 1-7, characterized in that, The power selection circuit includes a first selection switch and a second selection switch; The control terminal of the first gating switch is connected to the gating control circuit, the first terminal of the first gating switch is used to connect to the first power supply voltage terminal, and the second terminal of the first gating switch is connected to the input terminal of the output gating circuit. The control terminal of the second gating switch is connected to the gating control circuit. The first terminal of the second gating switch is used to connect to the second power supply voltage terminal, and the second terminal of the second gating switch is connected to the input terminal of the output gating circuit.

9. The display driving circuit according to claim 8, characterized in that, The first and second selection switches are transistors of the same conductivity type, and the control terminals of the first and second selection switches are independent of each other; or... The first gating switch and the second gating switch are transistors of different conductivity types, and the control terminals of the first gating switch and the second gating switch are connected to each other.

10. The display driving circuit according to any one of claims 1-9, characterized in that, The clock signals output by the at least two clock output terminals include at least a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same period, the same duty cycle, and different phases.

11. The display driving circuit according to claim 10, characterized in that, The phase difference between the first clock signal and the second clock signal is 180 degrees.

12. An electronic device, characterized in that, Includes a display panel and a display driving circuit as described in any one of claims 1-11; The display panel includes a gate driving circuit, and the display driving circuit is connected to the gate driving circuit. The display driving circuit is used to output a clock signal to the gate driving circuit.

13. The electronic device according to claim 12, characterized in that, The plurality of clock output terminals include a first clock output terminal and a second clock output terminal, and the first clock output terminal and the second clock output terminal are connected to the same gate driving circuit.

14. The electronic device according to claim 13, characterized in that, The display panel includes multiple gate driving circuits; The plurality of clock output terminals also includes an nth clock output terminal, where n is an odd number greater than 2, and the nth clock output terminal is connected to a different gate driving circuit than the first clock output terminal. or, The plurality of clock output terminals also includes an m-th clock output terminal, where m is an even number greater than 2, and the m-th clock output terminal is connected to a different gate drive circuit than the second clock output terminal.

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