Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. The display device includes a display panel in which a plurality of data lines, a plurality of gate lines, a plurality of power lines, at least one selection line, and a plurality of pixels are disposed, a data driver electrically connected to the data lines, a gate driver electrically connected to the gate lines, and a selector configured to supply a selection signal to the selection line. A display area of the display panel is divided into a plurality of pixel areas which are driven at different frequencies according to a voltage of the selection signal.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0055968, filed on April 29, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a display device that supports variable refresh rate (VRR) and a driving method thereof. Background Technology

[0003] Various flat panel displays, such as liquid crystal displays (LCDs) and electroluminescent displays (OLEDs), are known. OLEDs can emit light themselves without backlighting using light-emitting elements provided in each pixel and can display input images. The light-emitting elements of OLEDs can be classified as organic or inorganic based on the material of the light-emitting layer. Active-matrix OLEDs offer advantages such as high response speed, high light emission efficiency, high brightness, and wide viewing angle because organic light-emitting diodes (OLEDs) are provided in each pixel, and because black can be represented as true black, OLEDs excel in contrast and color reproduction.

[0004] Recently, display devices have supported variable refresh rate (VRR). While variable refresh rate technology can reduce power consumption, it does not allow for free control of the refresh rate within the screen. Summary of the Invention

[0005] The embodiments disclosed herein address the aforementioned disadvantages and / or problems.

[0006] The problems addressed by this disclosure are not limited to those described above, and other problems not described will be clearly understood by those skilled in the art based on the following description.

[0007] A display device according to one embodiment includes: a display panel, wherein a plurality of data lines, a plurality of gate lines, a plurality of power lines, at least one select line, and a plurality of pixels are disposed thereon; a data driver electrically connected to the data lines; a gate driver electrically connected to the gate lines; and a selector configured to supply a select signal to the select line. The display area of ​​the display panel is divided into a plurality of pixel regions in a first direction, and these pixel regions are driven at different frequencies according to the voltage of the select signal.

[0008] The gate driver can supply multiple gate signals with different waveforms in the corresponding pixels to the gate lines. The display area of ​​the display panel can be divided into multiple pixel regions in a second direction, and these pixel regions are driven at different frequencies according to the voltage of at least one of the gate signals. The second direction may intersect with the first direction.

[0009] Each pixel may include multiple sub-pixels. Each sub-pixel may include: a light-emitting element; a driving element configured to drive the light-emitting element; a capacitor connected to the driving element; and at least one switching element connected to or electrically disconnected from the capacitor in response to a selection signal.

[0010] Each subpixel may include: a light-emitting element; a driving element configured to drive the light-emitting element; a capacitor connected to the driving element; a first-first switching element controlled according to the voltage of a selection signal; and a first-second switching element connected in series with the first-first switching element and controlled according to the voltage of at least one of the gate signals.

[0011] Each sub-pixel may include: a driving transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a capacitor connected between a first power line and the first node; a light-emitting element comprising an anode electrode connected to a fourth node and a cathode electrode connected to a second power line; a first-first switching transistor connected between the first node and the third node, which is turned on in response to a gate on voltage of a selection signal and turned off in response to a gate off voltage of a selection signal; and a first-second switching transistor connected between the first-first switching transistor and the third node. The three nodes are connected together, and the first switching transistor is turned on in response to the gate on voltage of the first gate signal and turned off in response to the gate off voltage of the first gate signal; the second-first switching transistor is connected between the first node and the fifth power supply line to which an initialization voltage is applied, and is turned on in response to the gate on voltage of the selection signal and turned off in response to the gate off voltage of the selection signal; and the second-second switching transistor is connected between the second-first switching transistor and the fifth power supply line, and is turned on in response to the gate on voltage of the first gate signal and turned off in response to the gate off voltage of the first gate signal.

[0012] Each sub-pixel may further include: a third switching transistor connected between the first power line and the second node, and turned on in response to a gate-on voltage of the fifth gate signal; a fourth switching transistor connected between the third node and the fourth node, and turned on in response to a gate-on voltage of the fifth gate signal; a fifth switching transistor connected between the second node and the third power line, and turned on in response to a gate-on voltage of the third gate signal; a sixth switching transistor connected between the fourth node and the fourth power line, and turned on in response to a gate-on voltage of the third gate signal; and a seventh switching transistor connected between the data line and the second node, and turned on in response to a gate-on voltage of the second gate signal.

[0013] Each sub-pixel may include: a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a capacitor connected between a first power line and the first node; a light-emitting element including an anode electrode connected to a fourth node and a cathode electrode connected to the second power line; a first-first switching transistor connected between the first node and the third node, which is turned on in response to a gate on voltage of a selection signal and turned off in response to a gate off voltage of a selection signal; a first-second switching transistor connected between the first-first switching transistor and the third node, which is turned on in response to a gate on voltage of a first gate signal and turned off in response to a gate off voltage of the first gate signal; and a second-first switching transistor connected between the first node and the node to which an initialization voltage is applied. The fifth power line is connected between the data line and the second node, and is turned on in response to the gate on voltage of the selection signal, and is turned off in response to the gate off voltage of the selection signal; the second switching transistor is connected between the data line and the second node, and is turned on in response to the gate on voltage of the second gate signal; the third switching transistor is connected between the first power line and the second node, and is turned on in response to the gate on voltage of the fourth gate signal; the fourth switching transistor is connected between the third node and the fourth node, and is turned on in response to the gate on voltage of the fourth gate signal; the fifth switching transistor is connected between the third node and the third power line, and is turned on in response to the gate on voltage of the third gate signal; and the sixth switching transistor is connected between the fourth node and the fourth power line, and is turned on in response to the gate on voltage of the third gate signal.

[0014] The non-display area of ​​the display panel may include dummy gate lines electrically connected to a gate driver. The gate driver may supply pulses of dummy gate signals to the dummy gate lines. A selector may be connected to two data lines and the dummy gate lines located in the non-display area of ​​the display panel and spaced apart by a predetermined distance.

[0015] The data driver may include: a first channel having an output having a first selection voltage selected according to the refresh rate of the pixel region and a data voltage corresponding to pixel data of the input image; and a second channel having an output having a second selection voltage selected according to the refresh rate of the pixel region and a data voltage corresponding to pixel data of the input image. The first data line of two spaced-apart data lines may be connected to the output terminal of the first channel. The second data line of two spaced-apart data lines may be connected to the output terminal of the second channel.

[0016] The selector may include: a first transistor including a gate electrode connected to a dummy gate line, a first electrode connected to a first data line, and a second electrode connected to a first gate node; a second transistor including a gate electrode connected to the first gate node, a first electrode for which a gate on voltage of a select signal is applied, and a second electrode connected to a select line; a first capacitor connected to the first gate node; a third transistor including a gate electrode connected to a dummy gate line, a first electrode connected to a second data line, and a second electrode connected to a second gate node; a fourth transistor including a gate electrode connected to the second gate node, a first electrode for which a gate off voltage of a select signal is applied, and a second electrode connected to a select line; and a second capacitor connected to the second gate node.

[0017] The channel characteristics of the second and fourth transistors can be different.

[0018] Each of the first and second selection voltages can be output from the data driver as either a high or low voltage. The high and low voltages can be selected within a voltage range between the maximum and minimum data voltages.

[0019] A display device according to another embodiment includes: a display panel having a plurality of data lines, a plurality of gate lines, a plurality of power lines, at least one select line, and a plurality of pixels; a data driver electrically connected to the data lines; a gate driver configured to supply a plurality of gate signals to the gate lines; and a selector configured to supply a select signal to the select line. The display area of ​​the display panel is divided into a plurality of pixel areas in a first direction, the plurality of pixel areas being driven at different frequencies according to the voltage of the select signal, and the display area of ​​the display panel is divided into a plurality of pixel areas in a second direction, the plurality of pixel areas being driven at different frequencies according to the voltage of at least one of the gate signals.

[0020] Each pixel may include multiple sub-pixels. Each sub-pixel may include: a light-emitting element; a driving transistor configured to drive the light-emitting element; a capacitor connected to the driving element; and a first-first switching transistor and a first-second switching transistor connected in series with the capacitor. The first-first switching transistor may be turned on in response to a selection signal. The first-second switching transistor may be turned on in response to at least one gate signal.

[0021] A method for driving a display device according to one embodiment includes: generating a selection signal, selecting a voltage of the selection signal according to a refresh rate of a pixel region divided in a first direction; generating a gate signal, selecting a voltage of the gate signal according to a refresh rate of a pixel region divided in a second direction intersecting the first direction; and controlling a driving frequency of the pixel region divided in the first and second directions by applying the selection signal and the gate signal to corresponding pixels.

[0022] According to embodiments of this disclosure, the refresh rate can be reduced to lower power consumption without causing a degradation in the image quality of the input image.

[0023] According to embodiments of this disclosure, the variable refresh rate within the screen of the display panel can be freely controlled by controlling the driving frequency of the pixels on the display panel to be different in two axial directions.

[0024] The effects of this disclosure are not limited to those described above, and those skilled in the art will understand other effects not described based on the following description and the appended claims. Attached Figure Description

[0025] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0027] Figure 2 This is a diagram showing an example of multiple pixel regions with different driving frequencies for pixels;

[0028] Figure 3 This is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure;

[0029] Figure 4 This shows the effect applied during the refresh frame and skip frame periods. Figure 3 The waveform diagram of the driving signal of the pixel circuit is shown.

[0030] Figure 5 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure;

[0031] Figure 6 This shows the effect applied during the refresh frame and skip frame periods. Figure 5 The waveform diagram of the driving signal of the pixel circuit is shown.

[0032] Figure 7 This is a diagram schematically illustrating a selector according to an embodiment of the present disclosure;

[0033] Figure 8 It is shown in detail Figure 7 The circuit diagram of an example selector is shown;

[0034] Figure 9 This is a schematic diagram illustrating a selector according to another embodiment of the present disclosure;

[0035] Figure 10 It is shown in detail Figure 9 The circuit diagram of an example selector is shown;

[0036] Figure 11 It specifically shows what can be applied to Figure 8 and Figure 10 A circuit diagram of another example of the selector shown;

[0037] Figure 12 This is a diagram illustrating an example of the selected voltage output from the data driver; and

[0038] Figure 13 and Figure 14 This diagram illustrates the structure of a device that divides pixel regions with different driving frequencies into a second direction of the display panel. Detailed Implementation

[0039] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and allow those skilled in the art to fully understand its scope.

[0040] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0041] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless otherwise expressly stated.

[0042] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0043] When using terms such as “top,” “above,” “below,” “side,” “connected or coupled with,” “cross,” or “intersect” to describe the position or interconnection between two components, one or more other components may be inserted between them unless “immediately” or “directly” is used.

[0044] When using terms such as “after,” “following,” “next,” or “before” to describe time-prior relationships, they may not be based on temporal continuity unless “immediately” or “directly” is used.

[0045] The terms “first”, “second”, etc., can be used to distinguish elements from each other, but the function or structure of a component is not limited by the ordinal number preceding the component or the component name.

[0046] The following embodiments may be combined or integrated with each other in part or in whole, and may be linked and operated in various technical ways. The embodiments may be performed independently of each other or in relation to each other.

[0047] The pixel circuit and gate drive circuit of the display device may include multiple transistors. The transistors may be implemented as thin-film transistors (TFTs). The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon TFTs (LTPS TFTs) including low-temperature polycrystalline silicon, etc.

[0048] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers initially flow out from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure does not limit the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0049] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The transistor is turned on in response to the gate on-voltage and turned off in response to the gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be the gate high voltage VGH, and the gate off-voltage can be the gate low voltage VGL. In the case of a p-channel transistor, the gate on-voltage can be the gate low voltage VGL, and the gate off-voltage can be the gate high voltage VGH.

[0050] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0052] refer to Figure 1 The display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data (or video data) to pixels 101 of the display panel 100, and a power supply 150 for generating power required to drive the pixels 101 and the display panel driving circuit.

[0053] The display panel 100 may be a rectangular panel having width (or length) in the X-axis direction, length in the Y-axis direction, and thickness in the Z-axis direction, but is not limited thereto. The X-axis direction, Y-axis direction, and Z-axis direction may be interpreted as a first direction, a second direction, and a third direction, respectively.

[0054] The screen of the display panel 100 may include a display area AA and a non-display area NA outside the display area AA. The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines commonly connected to two or more pixels. The power lines may be commonly connected to pixel circuitry to supply the power required to drive the pixels 101. The pixel array also includes one or more select signal lines (in... Figure 3 and Figure 5 In the middle, SL). The selection signal line SL supplies the selection signal to pixel 101 (in Figure 3 and Figure 5 In the first direction X, VSEL is used to select the driving frequency of a pixel based on the refresh rate of the pixel region.

[0055] Data line 102 is arranged as a long conductor along the Y-axis direction of display panel 100 and is electrically connected to the output terminal of data driver 110. Gate line 103 is arranged as a long conductor along the X-axis direction of display panel 100, intersects with data line 102, and is electrically connected to the output terminal of gate driver 120.

[0056] Each pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. Each pixel circuit is connected to data lines, gate lines, and power lines. The pixel circuitry can be implemented as follows: Figure 3 and Figure 5 The circuit shown is not limited to this.

[0057] The pixel array includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the X-axis in the pixel array of the display panel 100. Pixels arranged in a pixel line share a gate line 103. Subpixels arranged along the Y-axis in the data line direction share the same data line 102. A horizontal time period 1H can be obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0058] Display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. Transmissive display panels can be applied to transparent display devices, where an image is displayed on the screen and a real object in the background is visible. Display panel 100 can be manufactured as a flexible display panel.

[0059] Power supply 150 adjusts the level of the DC input voltage Vin applied from host system 200 and outputs the voltage required to drive the pixel array and display panel driving circuitry of display panel 100. Power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output gamma reference voltage, gate high voltage, gate low voltage, pixel drive voltage, pixel ground voltage, pixel compensation voltage, integrated circuit (IC) drive voltage, etc., through the DC-DC converter. The voltage output from power supply 150 can be a constant voltage (or DC voltage), but is not limited to this. The gamma reference voltage is supplied to data driver 110. The dynamic range of the data voltage output from data driver 110 is determined based on the voltage range of the gamma reference voltage. The dynamic range of the data voltage has a voltage range between the highest grayscale voltage and the lowest grayscale voltage. Gate high voltage and gate low voltage are supplied to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, pixel ground voltage, and pixel compensation voltage are supplied to pixel 101. The IC drive voltage is the drive voltage of the driver IC in which circuitry such as timing controller 130 and data driver 110 are embedded. The power supply 150 can be implemented as a power IC, such as a power management integrated circuit (PMIC) or an electronic integrated circuit (ELIC). The output voltage of the power supply 150 can be varied under the control of timing controller 130.

[0060] The display panel driving circuit, under the control of the timing controller 130, writes pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120. The display panel driving circuit may also include a demultiplexer (DEMUX) disposed between the data driver 110 and the data line 102, but embodiments of this disclosure are not limited thereto. When the demultiplexer is disposed between the output terminal of the data driver 110 and the data line 102, the number of channels (or output terminals) electrically connected to the data line 102 can be reduced.

[0061] The display panel driving circuit also includes a selector 111 for controlling pixel regions with different driving frequencies in the first direction X. The selector 111 may be located in the non-display area NA of the display panel 100, but embodiments of this disclosure are not limited thereto. For example, the selector 111 may be implemented as a driver IC together with the data driver 110. The selector 111 may output a selection signal VSEL in response to a voltage output from the data driver 110 and a dummy gate signal. The selection signal VSEL is applied to the sub-pixel via a selection signal line formed on the display panel 100 and selects pixel regions with different driving frequencies in the first direction X.

[0062] A touch sensor for sensing touch input can be disposed on the display panel 100. The touch sensor can be disposed on the display panel 100 as an on-cell type or an added type, or it can be implemented as an in-cell type touch sensor embedded in a pixel array.

[0063] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single driver IC.

[0064] Data driver 110 is electrically connected to data line 102 and supplies a data voltage corresponding to the pixel data of the input image to data line 102. Each channel of data driver 110 can use a digital-to-analog converter (hereinafter referred to as "DAC") to convert the pixel data of the input image received as a digital signal from timing controller 130 into a gamma compensation voltage, and can output a data voltage corresponding to the grayscale value of the pixel data. Data driver 110 can use a voltage distribution circuit (or voltage divider circuit) to divide the gamma reference voltage input from power supply 150 into gamma compensation voltages with different voltage levels according to grayscale. The gamma compensation voltage is supplied to the DAC of data driver 110. The data voltage can be output from each of the channels of data driver 110 via an output buffer and can be applied to data line 102.

[0065] When selection data, as a digital signal, is received from the timing controller 130, the data driver 110 uses a DAC to convert the selection data into a selection signal VSEL and outputs the selection signal VSEL. The DAC can convert the selection data into a gamma-compensated voltage and can output... Figures 7 to 10 The first selection voltage Von and the second selection voltage Voff are shown in the diagram. The DAC can convert the pixel data of the input image into a gamma-compensated voltage and can output... Figures 7 to 10 The data voltages DATA1 to DATA(n) are shown in the figure.

[0066] Gate driver 120 may be disposed in a non-display area NA on at least one of the right and left sides of the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA. Gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100, with the display area AA of the display panel inserted between them, and gate pulses may be supplied from both sides of gate line 103 via a dual-feed method. Gate driver 120 sequentially outputs gate signal pulses to gate line 103 under the control of timing controller 130. Gate driver 120 may use a shift register or edge-triggered flip-flop to shift the gate signal pulses to sequentially supply these signals to gate line 103. Gate driver 120 may include multiple gate drivers. Each of the multiple gate drivers may be implemented as a shift register or an edge-triggered flip-flop.

[0067] The gate driver 120 can supply a dummy gate signal to a dummy gate line located in a non-display area NA outside the display area AA. The dummy gate signal can be provided to the selector 111.

[0068] The timing controller 130 receives digital video data from the input image and timing signals synchronized with data from the host system 200. These timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal time period 1H. The data voltage of the pixel data can be simultaneously charged into the sub-pixels located in a pixel line within one horizontal time period 1H, and the pixel data can be written to the sub-pixels.

[0069] The timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110 and gate timing control signals for controlling the operation timing of the gate driver 120 based on timing signals (Vsync, Hsync, DE) received from the host system 200. The timing controller 130 controls the operation timing of the display panel driving circuit to synchronize the data driver 110 and the gate driver 120. The timing controller 130 can be implemented as an application-specific integrated circuit (ASIC).

[0070] The level shifter 140 can generate start signals, clock signals, masking signals, etc., based on the gate timing control signals received from the timing controller 130, convert the voltage of these signals into a swing width between a gate high voltage and a gate low voltage, and provide the converted signals to the gate driver 120 via the clock line 105. The gate driver 120 can output pulses of the gate signal in response to the start signals and clock signals input from the level shifter 140.

[0071] The display panel driving circuit can drive the pixels 101 at a variable refresh rate under the control of the timing controller 130. The timing controller 130 can reduce the refresh rate of the image displayed on the display panel 100 based on the frequency of the input image or based on the results of analyzing the input image, thereby reducing the power consumption of the display device and improving image quality. Using a variable refresh rate, the refresh driving frequency of the pixels can be varied to 1Hz, 30Hz, 60Hz, 120Hz, 144Hz, 165Hz, 240Hz, etc., but the embodiments of this disclosure are not limited to these.

[0072] Pixels are charged using a data voltage corresponding to the number of frames per second (FPS), which varies in real time according to the variable refresh rate. The unit of variable refresh rate is Hertz (Hz). When the refresh rate is 60Hz, pixel data is written to the pixel in each frame period of 60 frames per second, and when the refresh rate increases to 120Hz, pixel data is written to the pixel in each frame period of 120 frames per second. In display devices that support variable refresh rates, the refresh drive frequency at which pixel data is written to the pixel varies according to the variable refresh rate. The refresh drive frequency is the driving frequency of the pixel generated when pixel data is written in accordance with the number of frames per second (FPS), and it changes in accordance with the variable refresh rate.

[0073] The skip drive frequency is the drive frequency of pixels that have not been written with new pixel data and maintain the data voltage of the pixel data charged in the previous refresh frame. When a pixel is skipped from driving, initialization and data writing steps are not performed. Therefore, during skip drive, the power consumption in the display panel 100 and the display panel drive circuit is significantly lower compared to the refresh drive period.

[0074] The variable refresh rate does not maintain and changes the frame rate per second of the image reproduced on the screen of display panel 100 in real time. When displaying images such as games or animations on display panel 100, the display panel drive circuit can adjust the refresh drive frequency of pixels 101 in accordance with the frame rate per second (FPS) of the image under the control of timing controller 130, thereby reducing problems such as tearing or stuttering of the image reproduced on the screen of display panel 100.

[0075] The timing controller 130 can determine the refresh rate of the input image in real time by counting the input timing signals (Vsync, Hsync, DE) using a clock. The vertical synchronization signal Vsync defines a frame time period. One pulse period of the horizontal synchronization signal Hsync and the data enable signal DE is a horizontal time period 1H. The data enable signal DE defines the effective data interval where pixel data of the input image exists.

[0076] When a still image is input within a given time period under the control of the timing controller 130, the display panel driving circuit can reduce the refresh rate of pixel 101, thereby reducing the power consumption of the display device. Furthermore, it can increase the refresh drive frequency of the pixels according to the refresh rate of the input image, thereby achieving image quality optimized for the content of the input image. The refresh rate can be reduced when the display device operates in standby mode or in response to a user command. Additionally, the refresh rate can be reduced on an always-on display (AOD) screen. The AOD screen can be a partial pixel area of ​​the display area AA, in which preset information, such as brief information like remaining battery power and time, is displayed in standby mode.

[0077] The host system 200 can convert the resolution of the image signal from the video source to match the resolution of the display panel 100, and can transmit the image signal along with the timing signal to the timing controller 130.

[0078] Memory 132 can store timing information for drive settings of the display panel drive circuit, program code for compensation algorithms used to improve image quality, etc. Memory 132 may include non-volatile memory and volatile memory. Non-volatile memory may include one or more of readable and writable memory such as NAND flash memory, NOR flash memory, and electrically erasable programmable read-only memory (EEPROM). NAND flash memory may be of the single-cell (SLC) type. Volatile memory may include one or more of dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), and double data rate SDRAM (DDR SDRAM).

[0079] The display panel driving circuit can control pixels spatially divided within a screen at different driving frequencies, and can temporarily change the driving frequency of the pixels at a variable refresh rate under the control of the timing controller 130. Figure 2 As shown.

[0080] Figure 2 This is a diagram illustrating an example of multiple pixel regions with different driving frequencies. Figure 2 In this context, "FR(N) to FR(N+3)" indicates the time period from frame N (where N is a natural number) to frame (N+3). It should be noted that... Figure 2 The pixel areas A11 to A33 and refresh rates shown are for illustrative purposes only, and the pixel areas and refresh rates are not limited to these. Figure 2 Those shown. In Figure 2 In the middle, the thick line indicates the sampling period during which data is written at the refresh frame.

[0081] refer to Figure 2 The display area AA can be divided into two or more pixel regions A11 to A33 in at least one of the first direction X and the second direction Y, according to the driving frequency of the pixels. Each of the pixel regions A11 to A33 includes one or more pixels.

[0082] The timing controller 130 can control the data driver 110 and the gate driver 120 to independently control the driving frequency of pixels by dividing the screen into pixel regions. The timing controller 130 can increase the driving frequency of pixel regions that require data updates at high refresh rates, and can decrease the driving frequency of pixel regions where image quality degradation is not visible even when updating data at low refresh rates. The pixel driving frequency is proportional to the refresh rate. Pixels in pixel regions A11 to A33 can be driven at variable refresh rates such as 30Hz, 60Hz, and 120Hz, and pixels can be driven at different refresh rate frequencies according to pixel regions within a frame period.

[0083] exist Figure 2 In the example, A11, A12, and A13 are pixel regions divided along the first direction X, and can be driven such that the driving frequencies of the pixels are different. The position and size of each pixel region divided along the first direction X can be determined by a selection signal as described below (in... Figure 3 and Figure 5 In the middle, VSEL) control. A11, A21, and A31 are pixel regions divided along the second direction Y, and can be driven to make the driving frequency of the pixels different. The position and size of each pixel region divided along the second direction Y can be controlled by a capacitor (in Figure 3 and Figure 5 In the middle, Cst) the gate signal of the transistor (e.g., Figure 3 The timing controller 130 controls the driving frequency of the pixels according to the refresh rate of each of the pixel regions A11 to A33 by controlling the on and off of the transistors connected to capacitor Cst in each of the sub-pixels. Figures 3 to 6 As shown in the image.

[0084] Figure 3 This is a circuit diagram illustrating a pixel circuit according to an embodiment of the present disclosure. Figure 4 This shows the effect applied during the refresh frame and skip frame periods. Figure 3The waveform diagram of the driving signal for the pixel circuit is shown. Figure 4 In this configuration, the second scan signal SC2_O is a gate signal applied synchronously to the sub-pixels of odd-numbered pixel lines, along with the odd-numbered data voltage Vdata_O. The second scan signal SC2_E is a gate signal applied synchronously to the sub-pixels of even-numbered pixel lines, along with the even-numbered data voltage Vdata_E.

[0085] refer to Figure 3 and Figure 4 The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M11 to M7, and a capacitor Cst. Each of the first-first switching element M11, the first-second switching element M12, the second-first switching element M21, and the second-second switching element M22 can be implemented as an n-channel oxide TFT, but embodiments of the present disclosure are not limited thereto. Each of the driving element DT, the third switching element M3, the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 can be implemented as a p-channel LTPS TFT, but embodiments of the present disclosure are not limited thereto. For example, each of the first-first switching element M11, the first-second switching element M12, the second-first switching element M21, and the second-second switching element M22 can respond to... Figure 4 The gate high voltage VGH corresponding to the gate signal is turned on, and it can be turned off in response to the gate low voltage VGL. Each of the third switching element M3, the fourth switching element M4, the fifth switching element M5, the sixth switching element M6, and the seventh switching element M7 can be turned off in response to the gate high voltage VGH corresponding to the gate signal. Figure 4 It is turned on by the gate low voltage VGL corresponding to the gate signal, and can be turned off in response to the gate high voltage VGH.

[0086] The pixel circuit is connected to the data line DL, to which the pixel data voltage Vdata is applied, and to the gate lines GL1, GL2, GL3, SC4, and EM, to which gate signals SC1, SC2, SC3, SC4, and EM are applied. During the sampling period SAM of the refresh frame period RFR, the data voltage Vdata is applied to the data line DL. During the skip frame period SFR, a third compensation voltage (not shown) can be applied to the data line DL.

[0087] The pixel drive voltage ELVDD and pixel ground voltage ELVSS are set to voltages at which the driving element DT can operate in the saturation region. The pixel drive voltage ELVDD can be set to 2V to 3V, and the pixel ground voltage ELVSS can be set to -8V to -10V, but embodiments of this disclosure are not limited thereto. The gate high voltage VGH can be set higher than the pixel drive voltage ELVDD, and the gate low voltage VGL can be set lower than the pixel ground voltage ELVSS, but embodiments of this disclosure are not limited thereto.

[0088] The data voltage Vdata can have a dynamic range of 2V to 6V. Within this dynamic range, the voltage level of the data voltage Vdata is selected based on the grayscale value of the pixel data. The initialization voltage Vinit can be set below the lower limit voltage of the data voltage Vdata and above the pixel ground voltage ELVSS. For example, when the lower limit voltage of the data voltage Vdata is 2V and the pixel ground voltage ELVSS is -9V, the initialization voltage Vinit can be set to a voltage between -5V and -7V.

[0089] When pixel 101 is driven at a variable refresh rate, a pixel compensation voltage can be applied to the pixel circuit to reduce the brightness difference between the refresh frame period (RFR) and the skip frame period (SFR). The pixel compensation voltage may include a first compensation voltage (VOBS), a second compensation voltage (VAR), and a third compensation voltage (not shown).

[0090] The first compensation voltage VOBS is a conduction bias stress voltage (hereinafter referred to as "conduction bias voltage") applied to the drive element DT to reduce the difference in hysteresis characteristics between the on and off states of the drive element DT. The first compensation voltage VOBS can be set to a voltage range selected below the pixel drive voltage ELVDD and partially overlapping with the dynamic range of the data voltage Vdata. For example, when the dynamic range of the data voltage Vdata is 2V to 6V, the first compensation voltage VOBS can be set to a voltage of 4V to 8V under the control of the timing controller 130.

[0091] The second compensation voltage VAR initializes the anode voltage and parasitic capacitance Cel of the light-emitting element EL. The low grayscale brightness level of pixel 101 at low grayscale can be optimized by appropriately adjusting the initialization voltage to charge the parasitic capacitance Cel of the light-emitting element EL according to the second compensation voltage VAR. For example, when the dynamic range of the data voltage Vdata is 2V to 6V, the second compensation voltage VAR can be set to a voltage of -4V to -5V.

[0092] The third compensation voltage can be set to compensate for brightness changes in pixel 101 between refresh frame periods and skip frame periods, and can be applied to data line DL during skip frame periods. The third compensation voltage can be set within a voltage range smaller than the dynamic range of the data voltage Vdata. For example, when the dynamic range of the data voltage Vdata is 2V to 6V, the third compensation voltage can be set to a specific voltage of 4V to 6V, but embodiments of this disclosure are not limited thereto. The third compensation voltage can be output from power supply 150 and can be applied to data line DL via a separate switching element disposed on display panel 100 or a switching element of data driver 110.

[0093] Gate signals SC1, SC2, SC3, SC4 and EM consist of pulses that oscillate between gate high voltage VGH and gate low voltage VGL.

[0094] The timing controller 130 can control the driving frequency of the pixels during refresh drive or skip drive by controlling the switching elements M11, M12, M21 and M22 connected to capacitor Cst in the pixel circuits of each of the pixel regions A11 to A33.

[0095] The driving element DT includes a gate electrode connected to a first node n1, a first electrode connected to a second node n2, and a second electrode connected to a third node n3. A capacitor Cst is connected between a first power line PL1, to which the pixel driving voltage ELVDD is applied, and the first node n1. The light-emitting element EL includes an anode electrode connected to a fourth node n4 and a cathode electrode connected to a second power line PL2, to which the pixel ground voltage ELVSS is applied. The light-emitting element EL can be implemented as an OLED, but embodiments of this disclosure are not limited thereto. Due to the stacked structure, the OLED includes parasitic capacitance Cel.

[0096] The first-first switching element M11 and the first-second switching element M12 are connected in series between the first node n1 and the third node n3. The connection structure of the first-first switching element M11 and the first-second switching element M12 is not limited to... Figure 3 The connection structure is as follows. For example, the positions of the first-first switching element M11 and the first-second switching element M12 can be reversed. The positions of the first-first switching element M11 and the first-second switching element M12 can be reversed. When both the first-first switching element M11 and the first-second switching element M12 are turned on, the first node n1 is electrically connected to the third node n3. On the other hand, when at least one of the first-first switching element M11 and the first-second switching element M12 is turned off, the first node n1 is electrically disconnected from the third node n3.

[0097] The first-first switching element M11 is connected between the first node n1 and the first-second switching element M12, and is turned on in response to the gate high voltage VGH of the selection signal VSEL. When the first-first switching element M11 is turned on, the first-second switching element M12 can be electrically connected to the first node n1. The first-second switching element M12 is connected between the first-first switching element M11 and the third node n3, and is turned on in response to the gate high voltage VGH of the first scan signal SC1. When the first-second switching element M12 is turned on, the first-first switching element M11 can be electrically connected to the third node n3. The first-first switching element M11 includes a gate electrode connected to the selection signal line SL to which the selection signal VSEL is applied, a first electrode connected to the first node n1, and a second electrode connected to the first electrode of the first-second switching element M12. The first-second switching element M12 includes a gate electrode connected to the first gate line GL1 to which the first scan signal SC1 is applied, a first electrode connected to the second electrode of the first-first switching element M11, and a second electrode connected to the third node n3.

[0098] The second-first switching element M21 and the second-second switching element M22 are connected in series between the first node n1 and the fifth power supply line PL5 to which the initialization voltage Vinit is applied. The connection structure of the second-first switching element M21 and the second-second switching element M22 is not limited to... Figure 3 The connection structure is as follows. For example, the positions of the second-first switching element M21 and the second-second switching element M22 can be changed in opposite directions. The positions of the second-first switching element M21 and the second-second switching element M22 can be reversed. When both the second-first switching element M21 and the second-second switching element M22 are turned on, the initialization voltage Vinit can be applied to the first node n1. On the other hand, when at least one of the second-first switching element M21 and the second-second switching element M22 is turned off, the first node n1 is electrically disconnected from the fifth power line PL5 and is not initialized.

[0099] The second-first switching element M21 is connected between the first node n1 and the second-second switching element M22, and is turned on in response to the gate high voltage VGH of the selection signal VSEL. When the second-first switching element M21 is turned on, the first node n1 can be electrically connected to the second-second switching element M22. The second-second switching element M22 is connected between the second-first switching element M21 and the fifth power supply line PL5, and is turned on in response to the gate high voltage VGH of the fourth scan signal SC4. When the second-second switching element M22 is turned on, the second-second switching element M22 can be electrically connected to the fifth power supply line PL5 to which the initialization voltage Vinit is applied. The second-first switching element M21 includes a gate electrode connected to the selection signal line SL to which the selection signal VSEL is applied, a first electrode connected to the first node n1, and a second electrode connected to the first electrode of the second-second switching element M22. The second-second switching element M22 includes a gate electrode connected to the fourth gate line GL4 to which the fourth scan signal SC4 is applied, a first electrode connected to the second electrode of the second-first switching element M21, and a second electrode connected to the fifth power line PL5.

[0100] The third switching element M3 is connected between the first power line PL1 and the second node n2, and is turned on in response to the low gate voltage VGL of the EM signal EM. When the third switching element M3 is turned on, the pixel drive voltage ELVDD is applied to the second node n2. The fourth switching element M4 is connected between the third node n3 and the fourth node n4, and is turned on in response to the low gate voltage VGL of the EM signal EM. When the fourth switching element M4 is turned on, the third node n3 is electrically connected to the fourth node n4. The third switching element M3 includes a gate electrode connected to the fifth gate line GL5 to which the EM signal EM is applied, a first electrode connected to the first power line PL1, and a second electrode connected to the second node n2. The fourth switching element M4 includes a gate electrode connected to the fifth gate line GL5, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4. The EM signal can be interpreted as a transmit control signal or a fifth gate signal.

[0101] A fifth switching element M5 is connected between the second node n2 and the third power line PL3 to which a first compensation voltage VOBS is applied, and is turned on in response to a low gate voltage VGL of the third scan signal SC3. When the fifth switching element M5 is turned on, the first compensation voltage VOBS can be applied to the second node n2. A sixth switching element M6 is connected between the fourth node n4 and the fourth power line PL4 to which a second compensation voltage VAR is applied, and is turned on in response to a low gate voltage VGL of the third scan signal SC3. When the sixth switching element M6 is turned on, the second compensation voltage VAR can be applied to the anode electrode of the light-emitting element EL connected to the fourth node n4. The fifth switching element M5 includes a gate electrode connected to the third gate line GL3 to which the third scan signal SC3 is applied, a first electrode connected to the second node, and a second electrode connected to the third power line PL3. The sixth switching element M6 includes a gate electrode connected to the third gate line GL3, a first electrode connected to the fourth power line PL4, and a second electrode connected to the fourth node n4.

[0102] A seventh switching element M7 is connected between the data line DL and the second node n2, and is turned on in response to a low gate voltage VGL of the second scan signal SC2. When the seventh switching element M7 is turned on, the data line DL is electrically connected to the second node n2. The seventh switching element M7 includes a gate electrode connected to the second gate line GL2 to which the second scan signal SC2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the data line DL.

[0103] Assuming that the first-first switching element M11 and the second-first switching element M21 are in the on state, the refresh drive and skip drive of the pixel circuit will be described.

[0104] Pixel circuits can receive during the refresh frame period RFR. Figure 4 The refresh drive signal shown in the upper figure can be charged by the data voltage of the pixel data and can be driven at the refresh drive frequency. The refresh frame period RFR can be divided into a first conduction bias period OBS1, a first initialization period PRE, a second initialization period INI, a sampling period SAM, a second conduction bias period OBS2, and an emission period EMI. During the refresh frame period RFR, the light-emitting element EL is in the off state and does not emit light during the first conduction bias period OBS1, the first initialization period PRE, the second initialization period INI, the sampling period SAM, and the second conduction bias period OBS2. During the emission period EMI of the refresh frame period RFR, the light-emitting element EL can be driven by the current from the driving element DT and emit light.

[0105] The first floating period Tf1 can be set between the first conduction bias period OBS1 and the first initialization period PRE. The second floating period Tf2 can be set between the sampling period SAM and the second conduction bias period OBS2. The third floating period Tf3 can be set between the second conduction bias period OBS2 and the transmission period EMI. During the floating periods Tf1, Tf2, and Tf3, because all the first to seventh switching elements M1 to M7 are in the off state, the first to fourth nodes n1, n2, n3, and n4 are floated and maintained in their previous states.

[0106] During the first conduction bias period OBS1, the fifth switching element M5 and the sixth switching element M6 are turned on, the first compensation voltage VOBS is applied to the second node n2, and the second compensation voltage VAR is applied to the fourth node n4. During the first conduction bias period OBS1, the first-first switching element M11 and the first-second switching element M12 are turned on, and the first node n1 is electrically connected to the third node n3.

[0107] During the first initialization period PRE, the second-first switching element M21 and the second-second switching element M22 are turned on, and the initialization voltage Vinit is applied to the first node n1. During the second initialization period INI, the first-first switching element M11, the first-second switching element M12, the second-first switching element M21, and the second-second switching element M22 are turned on, and the initialization voltage Vinit is applied to the first node n1 and the third node n3. The initialization voltage Vinit is also applied to the second node n2 via the driving element DT.

[0108] During the sampling period SAM, the seventh switching element M7 is turned on in response to the low gate voltage VGL of the second scan signal SC2. In this case, the pixel data voltage Vdata is applied to the second node n2, and the data voltage Vdata is also applied to the first and third nodes n1 and n3 via the on-state driving element DT. During the second conduction bias period OBS2, the fifth switching element M5 and the sixth switching element M6 are turned on, the first compensation voltage VOBS is applied to the second node n2, and the second compensation voltage VAR is applied to the fourth node n4.

[0109] During the transmit-time EMI of the refresh frame period RFR, the third switching element M3 and the fourth switching element M4 are turned on in response to the low gate voltage VGL of the EM signal EM. During the transmit-time EMI, a current path can be formed between the pixel drive voltage ELVDD and the light-emitting element EL via the third switching element M3 and the fourth switching element M4, and the light-emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data.

[0110] Pixel circuits can receive during the skip frame period (SFR). Figure 4 The skip drive signal shown in the lower figure can be driven at a skip drive frequency lower than the refresh drive frequency. The skip frame period (SFR) can be divided into a third on-bias period (OBS3), a fourth on-bias period (OBS4), and an EMI transmission period. A floating period can exist between the third on-bias period (OBS3) and the fourth on-bias period (OBS4). A floating period can also exist between the fourth on-bias period (OBS4) and the EMI transmission period. During the skip frame period (SFR), the light-emitting element (EL) is off and does not emit light during the third on-bias period (OBS3) and the fourth on-bias period (OBS4). During the EMI transmission period of the skip frame period (SFR), the light-emitting element (EL) can be driven by current from the drive element (DT).

[0111] Data driver 110 does not output data voltage Vdata during the skip frame period (SFR). During the skip frame period (SFR), a third compensation voltage may be applied to data line DL, but embodiments of this disclosure are not limited thereto. During the skip frame period (SFR), the voltages of the first scan signal SC1 and the fourth scan signal SC4 are maintained at gate low voltage VGL, while the voltages of the second scan signals SC2_O and SC2_E are maintained at gate high voltage VGH. During the skip frame period (SFR), the first-first switching element M11, the first-second switching element M12, the second-first switching element M21, the second-second switching element M22, and the seventh switching element M7 remain off. Gate driver 120 may not output scan signals SC1, SC2_O, SC2_E, and SC4, excluding the third scan signal SC3, during the skip frame period (SFR). During the skip frame period (SFR), the pixel circuitry may be driven by the voltage of the capacitor Cst, which was charged with data voltage Vdata during the previous refresh frame period (RFR), and the light-emitting element EL may emit light.

[0112] During the third conduction bias period OBS3 and the fourth conduction bias period OBS4, the fifth switching element M5 and the sixth switching element M6 are turned on, the first compensation voltage VOBS is applied to the second node n2, and the second compensation voltage VAR is applied to the fourth node n4.

[0113] During the transmit-time EMI of the skip frame period (SFR), the third switching element M3 and the fourth switching element M4 are turned on in response to the low gate voltage VGL of the EM signal EM. During the transmit-time EMI, a current path can be formed between the pixel drive voltage ELVDD and the light-emitting element EL via the third switching element M3 and the fourth switching element M4, and the light-emitting element EL can emit light with a brightness corresponding to the grayscale value of the pixel data.

[0114] During the skip frame period (SFR), the pixel can emit light with a brightness corresponding to the grayscale of the previously written pixel data. During the skip frame period, the power consumption of the data driver 110 and the gate driver 120 is significantly reduced. The skip drive frequency of pixel 101 is significantly lower than the refresh drive frequency. Therefore, when pixel 101 is driven at a variable refresh rate, the power consumption of the display device can be reduced during the period when the input image is typically reproduced on the display panel 100, and the voltage consumption for charging the battery connected to the host system 200 can be reduced.

[0115] On the other hand, when the first-first switching element M11 and the second-first switching element M21 are turned off, the pixel circuit is skipped from driving because the capacitor Cst in the pixel circuit is not initialized. Even when Figure 4 When the refresh drive signal shown in the upper figure is input to the pixel circuit, the pixel circuit can also be skipped when the first-first switching element M11 and the second-first switching element M21 are turned off.

[0116] Figure 5 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 6 This shows the effect applied during the refresh frame period and the skip frame period. Figure 5 The waveform diagram of the driving signal of the pixel circuit is shown. In this embodiment, the description of the above embodiment will not be repeated.

[0117] refer to Figure 5 and Figure 6 The pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, multiple switching elements T11 to T6, and a capacitor Cst. The pixel circuit is connected to data lines DL, gate lines GL1, GL2, GL63, and GL64, and power lines PL1, PL2, PL63, and PL64. Each of the first-first switching element T11 and the first-second switching element T12 can be implemented as an n-channel oxide TFT, but embodiments of this disclosure are not limited thereto. Each of the driving element DT, the second switching element T2, the third switching element T3, the fourth switching element T4, the fifth switching element T5, and the sixth switching element T6 can be implemented as a p-channel LTPS TFT, but embodiments of this disclosure are not limited thereto.

[0118] The first-first switching element T11 and the first-second switching element T12 can be turned on in response to a high gate voltage VGH of the first scan signal SC1, and can be turned off in response to a low gate voltage VGL. Each of the second switching element T2, the third switching element T3, the fourth switching element T4, the fifth switching element T5, and the sixth switching element T6 can be turned on in response to a low gate voltage VGL of the corresponding gate signal (SC2, SC3, EM), and can be turned off in response to a high gate voltage VGH.

[0119] The first-first switching element T11 and the first-second switching element T12 are connected in series between the first node n1 and the third node n3. The connection structure of the first-first switching element T11 and the first-second switching element T12 is not limited to... Figure 5 The connection structure is as follows. For example, the positions of the first-first switching element T11 and the first-second switching element T12 can be changed in opposite directions. When both the first-first switching element T11 and the first-second switching element T12 are turned on, the first node n1 is electrically connected to the third node n3. On the other hand, when at least one of the first-first switching element T11 and the first-second switching element T12 is turned off, the first node n1 is electrically disconnected from the third node n3.

[0120] The first-first switching element T11 is connected between the first node n1 and the first-second switching element T12, and is turned on in response to the gate high voltage VGH of the selection signal VSEL. When the first-first switching element T11 is turned on, the first-second switching element T12 can be electrically connected to the first node n1. The first-second switching element T12 is connected between the first-first switching element T11 and the third node n3, and is turned on in response to the gate high voltage VGH of the first scan signal SC1 during the initialization period INI and sampling period SAM of the refresh frame period RFR. When the first-second switching element T12 is turned on, the first-first switching element T11 can be electrically connected to the third node n3. The first-first switching element T11 includes a gate electrode to which the selection signal VSEL is applied, a first electrode connected to the first node n1, and a second electrode connected to the first electrode of the first-second switching element T12. The first-second switching element T12 includes a gate electrode to which the first scan signal SC1 is applied, a first electrode connected to the second electrode of the first-first switching element T11, and a second electrode connected to the third node n3.

[0121] The second switching element T2 is connected between the data line DL and the second node n2, and is turned on during the sampling period SAM of the refresh frame period RFR in response to the low gate voltage VGL of the second scan signal SC2. When the second switching element T2 is turned on, the data line DL is electrically connected to the second node n2. The second switching element T2 includes a gate electrode to which the second scan signal SC2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the data line DL.

[0122] A third switching element T3 is connected between the first power line PL1 and the second node n2, and is turned on during the emission period EMI in response to a low gate voltage VGL of the EM signal EM. When the third switching element T3 is turned on, the pixel drive voltage ELVDD can be applied to the second node n2. A fourth switching element T4 is connected between the third node n3 and the fourth node n4, and is turned on during the emission period EMI in response to a low gate voltage VGL of the EM signal EM. When the fourth switching element T4 is turned on, the third node n3 can be electrically connected to the fourth node n4. The third switching element T3 includes a gate electrode connected to the fourth gate line GL64 to which the EM signal EM is applied, a first electrode connected to the first power line PL1, and a second electrode connected to the second node n2. The fourth switching element T4 includes a gate electrode connected to the fourth gate line GL64, a first electrode connected to the third node n3, and a second electrode connected to the fourth node n4.

[0123] The fifth switching element T5 is connected between the third node n3 and the third power supply line PL63, to which the first compensation voltage VOBIN is applied, and is turned on in response to the low gate voltage VGL of the third scan signal SC3. Figure 6 As shown, the first compensation voltage VOBIN is an AC voltage that oscillates between the on-bias voltage VOB and the initialization voltage VINI. The on-bias voltage VOB is a voltage higher than the initialization voltage VINI. The on-bias voltage VOB is applied to the third node n3 via the fifth switching element T5 during the on-bias periods OBS1 to OBS4. During the initialization period INI, the initialization voltage VINI is applied to the third node n3 via the fifth switching element T5. The on-bias voltage VOB corresponds to the first compensation voltage VOBS in the above embodiment, and the initialization voltage VINI corresponds to the initialization voltage Vinit in the above embodiment.

[0124] The sixth switching element T6 is connected between the fourth node n4 and the fourth power supply line PL64, and is turned on in response to the low gate voltage VGL of the third scan signal SC3. The second compensation voltage VAR is applied to the fourth node n4 via the sixth switching element T6 during the on-bias period OBS1 to OBS4.

[0125] On the other hand, when the first switching element T11 is turned off, the pixel circuit is skipped from driving because the capacitor Cst in the pixel circuit is not initialized. Even when Figure 6 When the refresh drive signal shown in the upper figure is input to the pixel circuit, the pixel circuit can also be skipped when the first-first switching element T11 is turned off.

[0126] Figure 7 This is a diagram schematically illustrating a selector according to an embodiment of the present disclosure. Figure 7 In the diagram, SP1 to SP3 are sub-pixels. Figure 8 It is shown Figure 7 The circuit diagram shown is an example of a selector.

[0127] refer to Figure 1 , Figure 7 and Figure 8 Selector 111 can be located in the upper non-display area NA of display panel 100. Selector 111 can be connected to data lines DL1 and DL3 spaced apart by a predetermined distance, as well as dummy gate lines. Dummy gate lines can be located in the non-display area NA outside the upper part of display area AA in display panel 100. Dummy gate signal SC2[0] can be applied to dummy gate lines. Dummy gate signal SC2[0] can be output from the gate driver that outputs the second scan signal SC2, but embodiments of this disclosure are not limited thereto. For example, dummy gate signals output from the gate drivers that output other gate signals SC1, SC3, SC4, and EM can be applied to selector 111.

[0128] like Figure 8 As shown, selector 111 may include first transistors TR1 to TR4, a first capacitor C1, and a second capacitor C2. Transistors TR1 to TR4 may be implemented as n-channel transistors, such as n-channel oxide TFTs, but embodiments of this disclosure are not limited thereto.

[0129] Each of the first transistor TR1 and the third transistor TR3 can be turned on in response to a pulse GP0 of a dummy gate signal applied via a dummy gate line. When the first transistor TR1 is turned on, the first data line DL1 can be electrically connected to the first gate node ng1. When the first selection voltage Von applied to the first gate node ng1 is a high voltage H, the second transistor TR2 is turned on and provides a gate high voltage VGH to the selection line SL, and when the first selection voltage Von is a low voltage L, the second transistor TR2 is turned off. The first transistor TR1 includes a gate electrode connected to the dummy gate line, a first electrode connected to the first data line DL1, and a second electrode connected to the first gate node ng1. The second transistor TR2 includes a gate electrode connected to the first gate node ng1, a first electrode to which a gate high voltage VGH is applied, and a second electrode connected to the selection line SL. The gate high voltage VGH can be interpreted as the gate turn-on voltage of the selection signal VSEL. The selection line SL can be arranged in the display area AA of the display panel 100 so as to be parallel to the data line DL and intersect with the gate lines GL1 to GL5, as shown below. Figure 7 As shown. In the display area AA, lines branching from the selection line SL connect to sub-pixels SP1, SP2, and SP3.

[0130] When the third transistor TR3 is turned on, the third data line DL3 can be electrically connected to the second gate node ng2. The data line connected to the third transistor TR3 is not limited to the third data line DL3. For example, when the second selection voltage Voff is applied to the second data line DL2, the third transistor TR3 can be connected to the second data line DL2. When the second selection voltage Voff applied to the second gate node ng2 is a high voltage H, the fourth transistor TR4 is turned on and supplies a gate low voltage VGL to the selection line SL; and when the second selection voltage Voff is a low voltage L, the fourth transistor TR4 is turned off. The third transistor TR3 includes a gate electrode connected to the dummy gate line, a first electrode connected to the third data line DL3, and a second electrode connected to the second gate node ng2. The fourth transistor TR4 includes a gate electrode connected to the second gate node ng2, a first electrode to which the gate low voltage VGL is applied, and a second electrode connected to the selection line SL. The gate low voltage VGL can be interpreted as the gate turn-off voltage of the selection signal VSEL.

[0131] When the first selection voltage Von is high (H) and the second selection voltage Voff is low (L), the voltage of the selection signal VSEL is the gate high voltage VGH. When the second selection voltage Voff is high (H) and the first selection voltage Von is low (L), the voltage of the selection signal VSEL is the gate low voltage VGL. When a refresh drive signal is applied, pixels for which the selection signal VSEL is applied with the gate high voltage VGH can be refreshed. Pixels for which the selection signal VSEL is applied with the gate low voltage VGL can be skipped because the voltage of capacitor Cst remains in its previous state even when a refresh drive signal is applied.

[0132] The first capacitor C1 can be charged with a first selection voltage Von applied to the first gate node ng1, and can maintain the gate voltage of the second transistor TR2 at the first selection voltage Von for one frame period. The first electrode of the first capacitor C1 can be connected to the first gate node ng1, and the second electrode of the first capacitor C1 can be connected to a power supply line to which a ground voltage or a reference voltage is applied. The second capacitor C2 can be charged with a second selection voltage Voff applied to the second gate node ng2, and can maintain the gate voltage of the fourth transistor TR4 at the second selection voltage Voff for one frame period. The first electrode of the second capacitor C2 can be connected to the second gate node ng2, and the second electrode of the second capacitor C2 can be connected to a power supply line to which a ground voltage or a reference voltage is applied. The capacitance of each of the first capacitor C1 and the second capacitor C2 can be substantially the same as the capacitance of the capacitor Cst of the pixel circuit.

[0133] The first channel of the data driver 110 can supply the first selection voltage Von corresponding to the selection data and the data voltages DATA1 to DATA(n) corresponding to the pixel data of the input image, received from the timing controller 130, to the first data line DL1. The second channel of the data driver 110 can supply the data voltages DATA1 to DATA(n) corresponding to the pixel data of the input image to the second data line DL2. The third channel of the data driver 110 can supply the second selection voltage Voff corresponding to the selection data and the data voltages DATA1 to DATA(n) corresponding to the pixel data of the input image, received from the timing controller 130, to the third data line DL3. The first selection voltage Von and the second selection voltage Voff can be output synchronously with the pulse GP0 of the dummy gate signal SC2[0] before the data voltages DATA1 to DATA(n), and can divide the pixel regions with different driving frequencies in the first direction of the display panel 100 during the current frame period. After the output of the dummy gate signal SC2[0] pulse GP0, the gate driver 120 can sequentially output the gate signals SC2[1] and SC2[2] applied to the pixel lines of the display area AA pulse GP1 and GP2.

[0134] The timing controller 130 can determine the logical value of the selected data based on the refresh rate of each pixel region divided in the first direction of the display panel 100. Therefore, the timing controller 130 can control the voltage of each of the selection voltages Von and Voff output from the data driver 110 according to the refresh rate of each pixel region.

[0135] Figure 9 This is a diagram schematically illustrating a selector according to another embodiment of the present disclosure. Figure 10 It is shown Figure 9 The circuit diagram of an example selector is shown. In this embodiment, the above will not be repeated. Figure 7 and Figure 8 The redundant description of the embodiments shown is as follows.

[0136] refer to Figure 9 and Figure 10 Selector 111 can be set in the lower non-display area NA of display panel 100.

[0137] In selector 111, each of the first transistor TR1 and the third transistor TR3 can be turned on in response to a pulse GP(n+1) of a dummy gate signal applied via the dummy gate line. When the first transistor TR1 is turned on, the first data line DL1 can be electrically connected to the first gate node ng1. When the first selection voltage Von applied to the first gate node ng1 is a high voltage H, the second transistor TR2 is turned on and supplies the gate high voltage VGH to the selection line SL, and when the first selection voltage Von is a low voltage L, the second transistor TR2 is turned off.

[0138] When the third transistor TR3 is turned on, the third data line DL3 can be electrically connected to the second gate node ng2. When the second selection voltage Voff applied to the second gate node ng2 is a high voltage H, the fourth transistor TR4 is turned on and supplies the gate low voltage VGL to the selection line SL, and when the second selection voltage Voff is a low voltage L, the fourth transistor TR4 is turned off. The first capacitor C1 changes with the first selection voltage Von applied to the first gate node ng1. The second capacitor C2 is charged using the second selection voltage Voff applied to the second gate node ng2. The first selection voltage Von and the second selection voltage Voff can be output synchronously with the pulse GP(n+1) of the dummy gate signal SC2[n+1] after the data voltages DATA1 to DATA(n), and can divide pixel regions with different driving frequencies in the first direction of the display panel 100 in the next frame period. The gate driver 120 can output a dummy gate signal SC2[n+1] pulse GP(n+1) after sequentially outputting pulses GP(n-1) and GP(n) of the gate signals SC2[n-1] and SC2[n] applied to the pixel lines of the display area AA.

[0139] Figure 11 It specifically shows what can be applied to Figure 8 and Figure 10 The circuit diagram shows another example of the selector. In this embodiment, the description of the above embodiments will not be repeated.

[0140] refer to Figure 11 The selector 111 may include first transistors TR1 through NTR4, a first capacitor C1, and a second capacitor C2. Each of the first transistor TR1, the third transistor TR3, and the fourth transistor NTR4 may be implemented as an n-channel transistor, such as an n-channel oxide TFT, but embodiments of this disclosure are not limited thereto. The second transistor PTR2 may be implemented as a p-channel transistor, such as a p-channel LTPS TFT, but embodiments of this disclosure are not limited thereto.

[0141] Each of the first and third transistors TR1 and TR3 can be turned on in response to a pulse of the dummy gate signal SC2[0] or SC2[n+1] applied via the dummy gate line. When the first transistor TR1 is turned on, the first data line DL1 can be electrically connected to the first gate node ng1. When the second transistor PTR2 is a p-channel transistor, the second transistor PTR2 is turned on and supplies the gate high voltage VGH to the select line SL when the first select voltage Von applied to the first gate node ng1 is a low voltage L, and the second transistor PTR2 is turned off when the first select voltage Von is a high voltage H.

[0142] When the third transistor TR3 is turned on, the third data line DL3 can be electrically connected to the second gate node ng2. When the second selection voltage Voff applied to the second gate node ng2 is a high voltage H, the fourth transistor NTR4 is turned on and supplies the low gate voltage VGL to the selection line SL. When the second selection voltage Voff is a low voltage L, the fourth transistor NTR4 is turned off.

[0143] When the second transistor PTR2 is a p-channel transistor and the fourth transistor NTR4 is an n-channel transistor, and when the voltages of the first selection voltage Von and the second selection voltage Voff are low (L), the voltage of the selection signal VSEL is the gate high voltage VGH. When the voltages of the first selection voltage Von and the second selection voltage Voff are high (H), the voltage of the selection signal VSEL is the gate low voltage VGL. When a refresh drive signal is applied, pixels for which the selection signal VSEL is applied with the gate high voltage VGH can be refresh driven. Pixels for which the selection signal VSEL is applied with the gate low voltage VGL can be skipped because the voltage of capacitor Cst remains in its previous state even when the refresh drive signal is applied.

[0144] Figure 12 This is a diagram illustrating an example of the selected voltage output from the data driver. Figure 12 In the text, "TCON" represents timing controller 130.

[0145] refer to Figure 12 The output voltage or dynamic voltage range of the data driver 110 is the voltage between the minimum voltage Vdmin and the maximum voltage Vdmax. The lowest grayscale voltage of the pixel data can be the minimum voltage Vdmin or a low grayscale voltage close to the minimum voltage Vdmin. The highest grayscale voltage of the pixel data can be the maximum voltage Vdmax or a high grayscale voltage close to the maximum voltage Vdmax.

[0146] The timing controller TCON transmits the pixel data DATA and selection data SEL of the input image as digital signal voltages to the data driver 110. Each channel of the data driver 110 can use the data voltage corresponding to the grayscale value of the pixel data output by the DAC as a gamma compensation voltage within the dynamic voltage range.

[0147] Data driver 110 can output a voltage corresponding to the logic value of the selected data SEL as a gamma compensation voltage within the dynamic voltage range. For example, when the first selected data SEL has a first logic value, the first channel of data driver 110 can use a high voltage H, selected by the DAC output as the maximum voltage Vdmax or a high grayscale voltage close to the maximum voltage Vdmax, as the first selected voltage Von. When the first selected data SEL has a second logic value, a low voltage L, selected as the minimum voltage or a low grayscale voltage close to the minimum voltage Vdmin, can be output from the first channel of data driver 110 as the first selected voltage Von. When the second selected data SEL has a first logic value, the third channel of data driver 110 can output a high voltage H, selected as the maximum voltage Vdmax or a high grayscale voltage close to the maximum voltage Vdmax, as the second selected voltage Voff. When the second selected data SEL has a second logic value, a low voltage L, selected as the minimum voltage Vdmin or a low grayscale voltage close to the minimum voltage Vdmin, can be output from the third channel of data driver 110 as the second selected voltage Voff. Here, the first logic value is "1" and the second logic value can be "0 (zero)", but the embodiments of this disclosure are not limited thereto.

[0148] Figure 13 and Figure 14 This diagram illustrates a device that divides pixel regions with different driving frequencies into a second direction of the display panel. Figure 13 and Figure 14 In this context, "SRO1 to SRO9" can be the gate signals of the switching elements connected to the capacitor in the pixel circuit, for example, Figure 3 and Figure 5 The first and fourth gate signals SC1 and SC4 are shown in the figure.

[0149] refer to Figure 13 and Figure 14 The timing controller TCON can determine the refresh-driven and skip-driven pixel regions based on the analysis of the input image. The timing controller TCON can output masking signals MSK with different logic values ​​in the refresh-driven and skip-driven pixel regions. The masking signals MSK can be provided to the gate driver 120 via a level shifter.

[0150] The interval ON for generating the masking signal MSK under a voltage V1 with a first logic value is controlled to be for pixel areas in the second direction Y of the display panel 100 where data is updated, i.e., pixel areas that are refreshed. The interval OFF for generating the masking signal MSK under a voltage V2 with a second logic value is controlled to be for pixel areas in the second direction Y of the display panel 100 where data is not updated, i.e., pixel areas that are skipped.

[0151] Gate driver 120 may include carry signal generator CB, gate signal generator OB, and masking processor MB.

[0152] The carry signal generator CB includes multiple signal transmission sections CST1 to CST9 connected in a cascaded manner via a clock line for the input clock signal CLK and a wire for the input carry signal CAR. The carry signal generator CB receives a start signal VST and a clock signal CLK, and sequentially outputs pulses of the carry signal CAR. The carry signal generator CB can be implemented as a shift register, but embodiments of this disclosure are not limited thereto. The start signal VST is input to the first signal transmission section CST1. Pulses of the carry signal sequentially output from signal transmission sections CST1 to CST9 are input to the gate signal generator OB and are transmitted as start signals to the next signal transmission section.

[0153] The gate signal generator OB includes multiple output sections OST1 to OST9, which are connected one-to-one to the signal transmission section of the carry signal generator CB. The gate signal generator OB can receive individual start and clock signals, but embodiments of this disclosure are not limited thereto. Output sections OST1 and OST9 can sequentially output pulses of the gate signal in response to a pulse of the carry signal CAR. The first output section OST1 outputs a pulse of the gate signal in response to the carry signal CAR received from the first signal transmission section CST1. Subsequently, the second output section OST2 outputs a pulse of the gate signal in response to the carry signal CAR received from the second signal transmission section CST2.

[0154] The masking processor MB includes multiple output control sections MST1 to MST9 connected one-to-one with the output sections OST1 to OST9 of the gate signal generator OB. A masking signal MSK can be input in series to the output control sections MST1 to MST9. Each of the output control sections MST1 to MST9 can, in response to the masking signal MSK, transmit a pulse of the gate signal to the corresponding gate line of the pixel line, or can block the output of the gate signal pulse and apply a gate turn-off voltage (e.g., gate low voltage VGL) to the corresponding gate line. For example, the first output control section MST1, in response to a first logic value of the masking signal MSK, transmits a pulse of the gate signal input from the first output section OST1 to the gate line of the sub-pixel connected to the first pixel line. The first output control section MST1 can, in response to a second logic value of the masking signal MSK, block the output of the gate signal pulse input from the first output section OST1 and apply a gate low voltage VGL to the gate line of the sub-pixel connected to the first pixel line to maintain the voltage of the gate line at the gate low voltage VGL for one frame period. The second output control section MST2, in response to the first logic value of the masking signal MSK, transmits the pulse of the gate signal input from the second output section OST2 to the gate line of the sub-pixel of the second pixel line. The second output control section MST2 can, in response to the second logic value of the masking signal MSK, block the output of the pulse of the gate signal input from the second output section OST2, and apply a gate low voltage VGL to the gate line of the sub-pixel connected to the second pixel line to maintain the voltage of the gate line at the gate low voltage VGL during a frame period.

[0155] According to one or more embodiments of this disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptop computers, monitors, cameras, camcorders, and home appliances, etc. Additionally, the display device according to one or more embodiments of this disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0156] The objectives to be achieved by this disclosure, the apparatus for achieving said objectives, and the effects of this disclosure do not specify the essential features of the claims; therefore, the scope of the claims is not limited to the content of this disclosure.

[0157] Although embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display device, comprising: The display panel includes multiple data lines, multiple gate lines, at least one select line, and multiple pixels. The data driver is electrically connected to the data line; as well as A selector, connected between the data driver and the plurality of pixels, is configured to supply a select signal to the select line based on a voltage from the data driver. The display area of ​​the display panel is divided into multiple pixel areas in a first direction, and the multiple pixel areas are driven at different frequencies according to the voltage of the selection signal.

2. The display device according to claim 1, further comprising a gate driver electrically connected to the gate line, wherein: The gate driver is configured to supply the gate line with a plurality of gate signals having different waveforms in the respective pixel. The display area of ​​the display panel is divided into a plurality of pixel areas in a second direction, and the plurality of pixel areas are driven at different frequencies according to the voltage of at least one of the gate signals. The second direction intersects with the first direction.

3. The display device according to claim 1, wherein, Each pixel in the pixel comprises multiple sub-pixels, and Each of the sub-pixels includes: Light-emitting elements; A driving element is configured to drive the light-emitting element; A capacitor is connected to the driving element; and At least one switching element is connected to or electrically disconnected from the capacitor in response to the selection signal.

4. The display device according to claim 2, wherein, Each pixel in the pixel comprises multiple sub-pixels, and Each of the sub-pixels includes: Light-emitting elements; A driving element is configured to drive the light-emitting element; A capacitor is connected to the driving element; First-first switching elements are controlled according to the voltage of the selection signal; and First and second switching elements are connected in series with the first and second switching elements and are controlled according to the voltage of at least one of the gate signals.

5. The display device according to claim 2, wherein, The display panel is provided with multiple power lines, and each pixel in the pixel array includes multiple sub-pixels. Each of the sub-pixels includes: The driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A capacitor is connected between the first power line and the first node in the plurality of power lines; The light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to the second power line of the plurality of power lines; A first-first switching transistor is connected between the first node and the third node, and is turned on in response to the gate on voltage of the selection signal, and turned off in response to the gate off voltage of the selection signal; The first and second switching transistors are connected between the first and second switching transistors and the third node, and are turned on in response to the gate turn-on voltage of the first gate signal in the gate signal, and are turned off in response to the gate turn-off voltage of the first gate signal; A second-first switching transistor is connected between the first node and a fifth power line among the plurality of power lines to which an initialization voltage is applied, and is turned on in response to a gate on-voltage of the selection signal, and turned off in response to a gate off-voltage of the selection signal; and The second-second switching transistor is connected between the second-first switching transistor and the fifth power supply line, and is turned on in response to the gate turn-on voltage of the first gate signal, and turned off in response to the gate turn-off voltage of the first gate signal.

6. The display device according to claim 5, wherein, Each of the sub-pixels also includes: A third switching transistor is connected between the first power line and the second node, and is turned on in response to the gate turn-on voltage of the fifth gate signal in the gate signal; A fourth switching transistor is connected between the third node and the fourth node, and is turned on in response to the gate turn-on voltage of the fifth gate signal; A fifth switching transistor is connected between the second node and the third power line, and is turned on in response to the gate on-voltage of the third gate signal in the gate signal; A sixth switching transistor is connected between the fourth node and the fourth power line of the plurality of power lines, and is turned on in response to the gate on-voltage of the third gate signal; and A seventh switching transistor is connected between the data line and the second node and is turned on in response to the gate on-voltage of the second gate signal in the gate signal.

7. The display device according to claim 2, wherein, The display panel is provided with multiple power lines, and each pixel in the pixel array includes multiple sub-pixels. Each of the sub-pixels includes: The driving transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A capacitor is connected between the first power line and the first node in the plurality of power lines; The light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode connected to the second power line of the plurality of power lines; A first-first switching transistor is connected between the first node and the third node, and is turned on in response to the gate on voltage of the selection signal, and turned off in response to the gate off voltage of the selection signal; The first and second switching transistors are connected between the first and second switching transistors and the third node, and are turned on in response to the gate turn-on voltage of the first gate signal in the gate signal, and are turned off in response to the gate turn-off voltage of the first gate signal; The second-first switching transistor is connected between the first node and the fifth power line among the plurality of power lines to which an initialization voltage is applied, and is turned on in response to the gate on voltage of the selection signal, and turned off in response to the gate off voltage of the selection signal. A second switching transistor is connected between the data line and the second node, and is turned on in response to the gate on-voltage of the second gate signal in the gate signal; A third switching transistor is connected between the first power line and the second node, and is turned on in response to the gate turn-on voltage of the fourth gate signal in the gate signal; A fourth switching transistor is connected between the third node and the fourth node, and is turned on in response to the gate on-voltage of the fourth gate signal; A fifth switching transistor is connected between the third node and the third power line of the plurality of power lines, and is turned on in response to the gate on-voltage of the third gate signal in the gate signals; and A sixth switching transistor is connected between the fourth node and the fourth power line of the plurality of power lines, and is turned on in response to the gate turn-on voltage of the third gate signal.

8. The display device according to claim 2, wherein: The non-display area of ​​the display panel includes dummy gate lines electrically connected to the gate driver. The gate driver is configured to supply pulses of the dummy gate signal to the dummy gate line, and The selector is connected to two data lines located in the non-display area of ​​the display panel and spaced apart by a predetermined distance, and is also connected to the dummy gate line.

9. The display device according to claim 8, wherein, The data driver includes: A first channel outputs a first selected voltage and a data voltage corresponding to pixel data of the input image, wherein the first selected voltage is selected based on the refresh rate of the pixel region; and The second channel outputs a second selection voltage and a data voltage corresponding to the pixel data of the input image, wherein the second selection voltage is selected based on the refresh rate of the pixel region. in: The first data line of the two spaced-out data lines is connected to the output terminal of the first channel, and The second data line of the two spaced-out data lines is connected to the output terminal of the second channel.

10. The display device according to claim 9, wherein, The selector includes: The first transistor includes a gate electrode connected to the dummy gate line, a first electrode connected to the first data line, and a second electrode connected to the first gate node. The second transistor includes a gate electrode connected to the first gate node, a first electrode to which the gate on-state voltage of the selection signal is applied, and a second electrode connected to the selection line. A first capacitor is connected to the first gate node; The third transistor includes a gate electrode connected to the dummy gate line, a first electrode connected to the second data line, and a second electrode connected to the second gate node; The fourth transistor includes a gate electrode connected to the second gate node, a first electrode to which a gate turn-off voltage of the selection signal is applied, and a second electrode connected to the selection line; and The second capacitor is connected to the second gate node.

11. The display device according to claim 10, wherein, The second transistor and the fourth transistor have different channel characteristics.

12. The display device according to claim 9, wherein: Each of the first selection voltage and the second selection voltage is output from the data driver as either a high voltage or a low voltage, and The high voltage and the low voltage are selected within a voltage range between the maximum and minimum voltage of the data voltage.

13. A display device, comprising: The display panel includes multiple data lines, multiple gate lines, at least one select line, and multiple pixels. The data driver is electrically connected to the data line; A gate driver is configured to supply a plurality of gate signals to the gate line; as well as A selector, connected between the data driver and the plurality of pixels, is configured to supply a select signal to the select line based on a voltage from the data driver. The display area of ​​the display panel is divided into multiple pixel areas in a first direction, which are driven at different frequencies according to the voltage of the selection signal, and in a second direction intersecting the first direction, it is divided into multiple pixel areas driven at different frequencies according to the voltage of at least one of the gate signals.

14. The display device according to claim 13, wherein, Each of the pixels comprises multiple sub-pixels, and Each of the sub-pixels includes: Light-emitting elements; A driving transistor is configured to drive the light-emitting element; A capacitor is connected to the driving element; and The first-first switching transistor and the first-second switching transistor are connected in series to the capacitor. in: The first-to-first switching transistor is turned on in response to the selection signal, and The first and second switching transistors are turned on in response to at least one of the gate signals.

15. A method for driving a display device, the method comprising: A selection signal is generated, and the voltage of the selection signal is selected according to the refresh rate of the pixel region divided in the first direction; A gate signal is generated, and the voltage of the gate signal is selected according to the refresh rate of the pixel region divided in a second direction intersecting the first direction; as well as The driving frequency of the pixel regions divided in the first and second directions is controlled by applying the selection signal and the gate signal to the pixels in the corresponding pixel regions.

Images