Display device and driving method thereof

Abstract

The application provides a display device and a driving method thereof. The display device comprises first to fourth sub-pixels, the light-emitting devices of the second and fourth sub-pixels are electrically connected with the same pixel driving circuit, the pixel driving circuit comprises a driving transistor, a first light-emitting control transistor and a second light-emitting control transistor, the drain of the driving transistor is electrically connected with the sources of the first and second light-emitting control transistors, and the drains of the first and second light-emitting control transistors are respectively electrically connected with the anodes of the light-emitting devices of the second and fourth sub-pixels. The light-emitting control signal generation circuit of the display panel comprises a first light-emitting control signal output end, a second light-emitting control signal output end and an inverter circuit, the input end of the inverter circuit is electrically connected with the first light-emitting control signal output end, and the output end is electrically connected with the second light-emitting control signal output end. The application reduces the frame width of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] Traditional Organic Light-Emitting Diode (OLED) display panels typically use red (R), green (G), and blue (B) subpixels for full-color display. In a conventional pixel arrangement, multiple subpixels are distributed in an array, with columns of different colors of subpixels alternating to form the display area. For example, in a typical pixel arrangement, the first column of subpixels consists of alternating red and blue subpixels in the column direction, the second column consists of green subpixels, the third column consists of alternating red and blue subpixels, and the fourth column consists of green subpixels. This arrangement forms the basic display unit.

[0003] To achieve the wide color gamut and privacy protection features required by display panels, a fourth sub-pixel needs to be introduced in addition to the traditional red, green, and blue sub-pixels. To control the emission of this fourth sub-pixel, a corresponding emission control signal needs to be provided to its pixel driving circuit. If a separate, complete emission control signal generation circuit is set up for the fourth sub-pixel, it will increase the wiring and circuit space in the non-display area, leading to an increase in the bezel width of the display panel. This is disadvantageous for display products aiming for narrow bezels.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a display device and its driving method, which aims to reduce the bezel width of the display panel.

[0006] This application provides a display device, which includes a display panel. The display panel includes a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels, and a plurality of fourth sub-pixels. The light-emitting devices of the second sub-pixels and the light-emitting devices of the fourth sub-pixels are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the light-emitting device of the second sub-pixel. The source of the second light-emitting control transistor... The other drain is electrically connected to the anode of the light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line. The display panel further includes at least one light-emitting control signal generation circuit, which includes a first light-emitting control signal output terminal, a second light-emitting control signal output terminal, and an inverting circuit. The first light-emitting control signal output terminal is electrically connected to the first light-emitting control signal line, and the second light-emitting control signal output terminal is electrically connected to the second light-emitting control signal line. The input terminal of the inverting circuit is electrically connected to the first light-emitting control signal output terminal, and the output terminal of the inverting circuit is electrically connected to the second light-emitting control signal output terminal.

[0007] This application also provides a driving method for a display device, the display device including a display panel, the display panel including a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels, a plurality of fourth sub-pixels, and at least one light-emitting control signal generating circuit, the light-emitting devices of the second sub-pixels and the light-emitting devices of the fourth sub-pixels being electrically connected to the same pixel driving circuit, the pixel driving circuit including a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor, one of the source and drain of the driving transistor being electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor, the other of the source and drain of the first light-emitting control transistor being electrically connected to the anode of the light-emitting device of the second sub-pixel, the other of the source and drain of the second light-emitting control transistor being electrically connected to the anode of the light-emitting device of the fourth sub-pixel, the gate of the first light-emitting control transistor being electrically connected to a first light-emitting control signal line, the gate of the second light-emitting control transistor being electrically connected to a second light-emitting control signal line, the light-emitting control signal generating circuit including a first light-emitting control signal output terminal, a second light-emitting control signal output terminal, and an inverting circuit, the first light-emitting control signal output terminal being electrically connected to the first light-emitting control signal generating circuit. The first light-emitting control signal output terminal is electrically connected to the first light-emitting control signal output terminal, and the second light-emitting control signal output terminal is electrically connected to the second light-emitting control signal output terminal. The driving cycle for the display device to display one frame includes an initialization phase and a light-emitting phase. The driving method includes: in the initialization phase and the light-emitting phase of the first display mode, the first light-emitting control signal output terminal outputs a first-level signal, the inverting circuit inverts the first-level signal to a second-level signal, the second light-emitting control signal output terminal outputs the second-level signal, the first light-emitting control transistor is turned on under the control of the first-level signal, and the second light-emitting control transistor is turned off under the control of the second-level signal; in the initialization phase and the light-emitting phase of the second display mode, the first light-emitting control signal output terminal outputs the second-level signal, the inverting circuit inverts the second-level signal to the first-level signal, the second light-emitting control signal output terminal outputs the first-level signal, the first light-emitting control transistor is turned off under the control of the second-level signal, and the second light-emitting control transistor is turned on under the control of the first-level signal.

[0008] The display device provided in the embodiments of this application introduces a fourth sub-pixel in the display panel. The light-emitting devices of the second and fourth sub-pixels are electrically connected to the same pixel driving circuit. This pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first and second light-emitting control transistors. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the light-emitting device of the second sub-pixel, and the other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device of the fourth sub-pixel. The first and second light-emitting control transistors control the light emission of the second and fourth sub-pixels, respectively. The light-emitting devices of the second and fourth sub-pixels share other circuits in the pixel driving circuit except for the first and second light-emitting control transistors, thereby reducing the complexity of the pixel driving circuit and reducing manufacturing costs.

[0009] The light emission control signal generation circuit includes a first light emission control signal output terminal, a second light emission control signal output terminal, and an inverting circuit. The input terminal of the inverting circuit is electrically connected to the first light emission control signal output terminal, and the output terminal of the inverting circuit is electrically connected to the second light emission control signal output terminal. The inverting circuit inverts the light emission control signal output from the first light emission control signal output terminal and outputs it to the second light emission control signal output terminal, ensuring that the levels of the light emission control signals output from the first and second light emission control signal output terminals are always opposite. When the first light emission control signal output terminal outputs a first-level signal, the second light emission control signal output terminal outputs a second-level signal. The first light emission control transistor is turned on, and the second light emission control transistor is turned off, allowing the driving current to flow to the anode of the light emission device of the second sub-pixel, causing the second sub-pixel to emit light. When the first light emission control signal output terminal outputs a second-level signal, the second light emission control signal output terminal outputs a first-level signal. The first light emission control transistor is turned off, and the second light emission control transistor is turned on, allowing the driving current to flow to the anode of the light emission device of the fourth sub-pixel, causing the fourth sub-pixel to emit light. The inverting circuit generates two light emission control signals with always opposite levels, achieving time-division driving of the second and fourth sub-pixels.

[0010] The technical solution of this application adds an inverting circuit to the first light-emitting control signal output terminal of the light-emitting control signal generation circuit. This inverting circuit generates a light-emitting control signal with an opposite level to the light-emitting control signal output from the first light-emitting control signal output terminal. This eliminates the need for a separate, complete light-emitting control signal generation circuit for the fourth sub-pixel, reducing the area occupied by the light-emitting control signal generation circuit in the non-display area and decreasing the bezel width of the display panel. Compared to a technical solution that requires a separate, complete light-emitting control signal generation circuit for the fourth sub-pixel, the technical solution of this application only needs to add an inverting circuit to achieve the output of two light-emitting control signals. The inverting circuit has a simple circuit structure and occupies a smaller area. Therefore, the technical solution of this application effectively reduces the wiring and circuit space in the non-display area, and decreases the bezel width of the display panel.

[0011] Furthermore, the technical solution of this application controls the light emission of the second sub-pixel and the fourth sub-pixel respectively through the first light emission control transistor and the second light emission control transistor. In different display modes, by controlling the level of the light emission control signal output by the first light emission control signal output terminal, the inverting circuit automatically inverts the light emission control signal and outputs it to the second light emission control signal output terminal, thereby realizing the time-division driving of the second sub-pixel and the fourth sub-pixel.

[0012] In the driving method of the display device provided in the embodiments of this application, during the initialization stage and the light-emitting stage of the first display mode, the first light-emitting control signal output terminal outputs a first level signal, the inverting circuit inverts the first level signal into a second level signal, the second light-emitting control signal output terminal outputs a second level signal, the first light-emitting control transistor is turned on under the control of the first level signal, the second light-emitting control transistor is turned off under the control of the second level signal, and the driving current flows to the anode of the light-emitting device of the second sub-pixel, causing the second sub-pixel to emit light. During the initialization stage and the light-emitting stage of the second display mode, the first light-emitting control signal output terminal outputs a second level signal, the inverting circuit inverts the second level signal into a first level signal, the second light-emitting control signal output terminal outputs a first level signal, the first light-emitting control transistor is turned off under the control of the second level signal, the second light-emitting control transistor is turned on under the control of the first level signal, and the driving current flows to the anode of the light-emitting device of the fourth sub-pixel, causing the fourth sub-pixel to emit light. By inverting the light-emitting control signal output from the first light-emitting control signal output terminal through an inverting circuit, the light-emitting control signal is output to the second light-emitting control signal output terminal, thereby realizing time-division driving of the second sub-pixel and the fourth sub-pixel. There is no need to set up a separate complete light-emitting control signal generation circuit for the fourth sub-pixel, which reduces the bezel width of the display panel. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0014] Figure 2 This is a schematic diagram of the pixel arrangement of the first embodiment of the display device provided in this application.

[0015] Figure 3 A schematic diagram of the pixel arrangement of a second embodiment of the display device provided in this application.

[0016] Figure 4 A circuit diagram of the pixel driving circuit of the first light-emitting unit and the third light-emitting unit of the display device provided in the embodiments of this application.

[0017] Figure 5 A circuit diagram of the pixel driving circuit of the second and fourth light-emitting units of the display device provided in the embodiments of this application.

[0018] Figure 6 A circuit diagram of the light emission control signal generation circuit for the display device provided in this application. Detailed Implementation

[0019] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0021] The technical solutions of different embodiments of this application can be combined with each other.

[0022] The display devices provided in the embodiments of this application may be, for example, organic light-emitting diode (OLED) display devices, mini light-emitting diode (Mini-LED) display devices, or micro light-emitting diode (Micro-LED) display devices. The embodiments of this application are described using organic light-emitting diode display devices as an example.

[0023] This application provides a display device and its driving method. The display device achieves multiple display functions by introducing a fourth sub-pixel SP4. By adding an inverting circuit to the output of the light-emitting control signal generation circuit, the light-emitting devices EL2 of the second sub-pixel SP2 and EL4 of the fourth sub-pixel SP4 share the same pixel driving circuit. The inverting circuit generates two light-emitting control signals with always opposite levels to control the light emission of EL2 of the second sub-pixel SP2 and EL4 of the fourth sub-pixel SP4 respectively. This eliminates the need for a separate complete light-emitting control signal generation circuit for EL4 of the fourth sub-pixel SP4, thereby reducing the area occupied by the non-display area and lowering the bezel width of the display device.

[0024] The display device provided in the embodiments of this application includes a display panel DP. The display panel DP includes a plurality of pixel units PX and at least one light emission control signal generation circuit. The plurality of pixel units PX includes a plurality of first sub-pixels SP1, a plurality of second sub-pixels SP2, a plurality of third sub-pixels SP3, and a plurality of fourth sub-pixels SP4. The plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, the plurality of third sub-pixels SP3, and the plurality of fourth sub-pixels SP4 are disposed in the display area of ​​the display panel DP, and the light emission control signal generation circuit is disposed in the non-display area of ​​the display panel DP.

[0025] The display device is an organic light-emitting diode (OLED) display device. For example... Figure 1 As shown, the display device includes a display panel (DP), a timing controller (TCON), and a source driver chip (SDIC). The timing controller (TCON) receives externally input image data and control signals. After processing the image data, the timing controller (TCON) transmits it to the source driver chip (SDIC). The timing controller (TCON) provides timing control signals to the source driver chip (SDIC) and the display panel (DP). The source driver chip (SDIC) converts the image data into data voltage according to the timing control signals, and outputs the data voltage to the data line (DL) of the display panel (DP).

[0026] The display panel DP includes a gate drive circuit GOA, multiple gate lines GL1 / GL2 / GL3 / GL4, multiple light emission control signal lines EM1 / EM2 / EM3, multiple data lines DL, a first power supply line VDD, a second power supply line VSS, multiple first sub-pixels SP1, multiple second sub-pixels SP2, multiple third sub-pixels SP3, and multiple fourth sub-pixels SP4. The gate drive circuit GOA is located in the non-display area of ​​the display panel DP and provides gate scan signals to the gate lines GL1 / GL2 / GL3 / GL4. The light emission control signal generation circuit is also located in the non-display area of ​​the display panel DP and provides light emission control signals to the light emission control signal lines EM1 / EM2 / EM3. Multiple first sub-pixels SP1, multiple second sub-pixels SP2, multiple third sub-pixels SP3, and multiple fourth sub-pixels SP4 are disposed within the display area of ​​the display panel DP. These sub-pixels are electrically connected to gate lines GL1 / GL2 / GL3 / GL4, light emission control signal lines EM1 / EM2 / EM3, data line DL, first power line VDD, and second power line VSS. The first power line VDD provides a high-level voltage, and the second power line VSS provides a low-level voltage.

[0027] like Figure 2 and Figure 3 As shown, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 emit light of different colors. In one embodiment of this application, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel. The fourth sub-pixel SP4 is a white sub-pixel, a yellow sub-pixel, a green sub-pixel, or a sub-pixel of other colors.

[0028] When some of the fourth sub-pixels SP4 are green sub-pixels and some of the fourth sub-pixels SP4 are white sub-pixels, the portion of the fourth sub-pixels SP4 that are white sub-pixels and the portion of the fourth sub-pixels SP4 that are green sub-pixels are staggered. That is, the portion of the fourth sub-pixels SP4 that are white sub-pixels and the portion of the fourth sub-pixels SP4 that are green sub-pixels are set alternately. White light includes light in the full spectrum wavelength range. In the second display mode, the white sub-pixels emit light together with the red, green and blue sub-pixels. After the white light is mixed with the red, green and blue light, it can expand the color gamut range of the display device, improve the brightness and color saturation of the display device, and thus realize wide color gamut display.

[0029] When some of the fourth sub-pixels SP4 are green sub-pixels and some are yellow sub-pixels, the portion of the fourth sub-pixels SP4 that are yellow sub-pixels and the portion of the fourth sub-pixels SP4 that are green sub-pixels are staggered. That is, the portion of the fourth sub-pixels SP4 that are yellow sub-pixels and the portion of the fourth sub-pixels SP4 that are green sub-pixels are set alternately. The wavelength range of yellow light is between that of red light and green light. In the second display mode, the yellow sub-pixels emit light together with the red, green and blue sub-pixels. After the yellow light is mixed with the red, green and blue light, it can expand the color gamut range of the display device in the yellow-green band and improve the color performance capability of the display device in this band, thereby realizing wide color gamut display.

[0030] When some of the fourth sub-pixels SP4 are green sub-pixels and some of the fourth sub-pixels SP4 are sub-pixels of other colors, the fourth sub-pixels SP4 of other colors and the fourth sub-pixels SP4 of green sub-pixels are staggered. That is, the fourth sub-pixels SP4 of other colors and the fourth sub-pixels SP4 of green sub-pixels are set alternately. When the light of this color is mixed with red light, green light and blue light, it can expand the color gamut range of the display device in the corresponding wavelength band, thereby realizing wide color gamut display.

[0031] Each sub-pixel includes a light-emitting device, which is an organic light-emitting diode (OLED). The light-emitting device includes an anode, an organic light-emitting layer, and a cathode. The anode is electrically connected to the pixel driving circuit, the cathode is electrically connected to the second power line VSS, and the organic light-emitting layer is disposed between the anode and the cathode.

[0032] In the first embodiment of this application, as Figure 2 As shown, multiple first sub-pixels SP1, multiple fourth sub-pixels SP4, multiple third sub-pixels SP3, and multiple fourth sub-pixels SP4 are arranged alternately along a first direction, while multiple second sub-pixels SP2 are arranged repeatedly along the first direction. Multiple first sub-pixels SP1 and multiple third sub-pixels SP3 are arranged alternately along a second direction, while multiple second sub-pixels SP2 are arranged repeatedly along the second direction, and multiple fourth sub-pixels SP4 are arranged repeatedly along the second direction. The second direction intersects with the first direction.

[0033] Along the second direction, the center line connecting multiple first sub-pixels SP1 is collinear with the center line connecting multiple third sub-pixels SP3. Along the second direction, the center line connecting multiple second sub-pixels SP2 is located between the center line connecting multiple first sub-pixels SP1 and the center line connecting multiple fourth sub-pixels SP4, and the center line connecting multiple fourth sub-pixels SP4 is located between the center line connecting multiple third sub-pixels SP3 and the center line connecting multiple second sub-pixels SP2.

[0034] Specifically, in the first embodiment, a first column of sub-pixels, a second column of sub-pixels, a third column of sub-pixels, and a fourth column of sub-pixels are arranged sequentially along a second direction. The first column of sub-pixels includes a first sub-pixel SP1, a fourth sub-pixel SP4, a third sub-pixel SP3, and a fourth sub-pixel SP4 arranged alternately along a first direction. Specifically, in the first column of sub-pixels, the first sub-pixel SP1, the fourth sub-pixel SP4, the third sub-pixel SP3, and the fourth sub-pixel SP4 are arranged sequentially and cyclically along the first direction. The second column of sub-pixels includes a plurality of second sub-pixels SP2 arranged along the first direction. The third column of sub-pixels includes a third sub-pixel SP3, a fourth sub-pixel SP4, a first sub-pixel SP1, and a fourth sub-pixel SP4 arranged alternately along the first direction. Specifically, in the third column of sub-pixels, the third sub-pixel SP3, the fourth sub-pixel SP4, the first sub-pixel SP1, and the fourth sub-pixel SP4 are arranged sequentially and cyclically along the first direction. The fourth column of sub-pixels includes a plurality of second sub-pixels SP2 arranged along the first direction.

[0035] In the first embodiment, the second sub-pixel SP2 in the second column of sub-pixels is located in the first direction between the first sub-pixel SP1 and the fourth sub-pixel SP4 in the adjacent first column of sub-pixels, or the second sub-pixel SP2 in the second column of sub-pixels is located in the first direction between the third sub-pixel SP3 and the fourth sub-pixel SP4 in the adjacent first column of sub-pixels. The first sub-pixel SP1 in the first column of sub-pixels and the third sub-pixel SP3 in the third column of sub-pixels are aligned or alternately staggered in the second direction, the fourth sub-pixel SP4 in the first column of sub-pixels and the fourth sub-pixel SP4 in the third column of sub-pixels are aligned or alternately staggered in the second direction, and the second sub-pixel SP2 in the second column of sub-pixels and the second sub-pixel SP2 in the fourth column of sub-pixels are aligned or alternately staggered in the second direction. The number of second sub-pixels SP2 in the second column of sub-pixels is half the total number of sub-pixels in the first column of sub-pixels, and the number of second sub-pixels SP2 in the fourth column of sub-pixels is half the total number of sub-pixels in the third column of sub-pixels.

[0036] In the second embodiment of this application, as Figure 3 As shown, multiple second sub-pixels SP2 and multiple first sub-pixels SP1 are arranged alternately along a first direction, as are multiple third sub-pixels SP3 and multiple fourth sub-pixels SP4 along the first direction. Along a second direction, the center line connecting the multiple third sub-pixels SP3 lies between the center line connecting the multiple second sub-pixels SP2 and the center line connecting the multiple first sub-pixels SP1, and the center line connecting the multiple fourth sub-pixels SP4 lies between the center line connecting the multiple first sub-pixels SP1 and the center line connecting the multiple second sub-pixels SP2. The second direction intersects the first direction.

[0037] Specifically, in the second embodiment, odd-numbered columns of sub-pixels and even-numbered columns of sub-pixels are alternately arranged along the second direction. The odd-numbered columns of sub-pixels include a second sub-pixel SP2 and a first sub-pixel SP1 alternately arranged along the first direction. Specifically, in the odd-numbered columns of sub-pixels, the second sub-pixel SP2 and the first sub-pixel SP1 are arranged sequentially and cyclically along the first direction. The even-numbered columns of sub-pixels include a third sub-pixel SP3 and a fourth sub-pixel SP4 alternately arranged along the second direction. Specifically, in the even-numbered columns of sub-pixels, the third sub-pixel SP3 and the fourth sub-pixel SP4 are arranged sequentially and cyclically along the first direction.

[0038] In the second embodiment, the third sub-pixel SP3 in the even-numbered sub-pixel column is located between the second sub-pixel SP2 and the first sub-pixel SP1 in the adjacent odd-numbered sub-pixel column in the first direction, and the fourth sub-pixel SP4 in the even-numbered sub-pixel column is located between the second sub-pixel SP2 and the first sub-pixel SP1 in the adjacent odd-numbered sub-pixel column in the first direction. The first sub-pixels SP1 in the adjacent odd-numbered sub-pixel column are aligned or alternately staggered in the first direction, the second sub-pixels SP2 in the adjacent odd-numbered sub-pixel column are aligned or alternately staggered in the first direction, the third sub-pixels SP3 in the adjacent even-numbered sub-pixel column are aligned or alternately staggered in the first direction, and the fourth sub-pixel SP4 in the adjacent even-numbered sub-pixel column are aligned or alternately staggered in the first direction.

[0039] like Figure 4 As shown, in the embodiments of this application, the light-emitting device EL1 of the first sub-pixel SP1 and the light-emitting device EL3 of the third sub-pixel SP3 are electrically connected to their respective pixel driving circuits, which are as follows: Figure 4 As shown. Figure 5 As shown in the embodiments of this application, the light-emitting device EL2 of the second sub-pixel SP2 and the light-emitting device EL4 of the fourth sub-pixel SP4 are electrically connected to the same pixel driving circuit, which is as follows: Figure 5As shown. The pixel driving circuit provides driving current to the light-emitting device EL2 of the second sub-pixel SP2 and the light-emitting device EL4 of the fourth sub-pixel SP4. The pixel driving circuit includes a driving transistor T1, a first light-emitting control transistor T6, and a second light-emitting control transistor T9. The driving transistor T1 generates the driving current. The first light-emitting control transistor T6 controls the flow of the driving current to the light-emitting device EL2 of the second sub-pixel SP2. The second light-emitting control transistor T9 controls the flow of the driving current to the light-emitting device EL4 of the fourth sub-pixel SP4. One of the source and drain of the driving transistor T1 (node ​​B) is electrically connected to one of the source and drain of the first light-emitting control transistor T6 and one of the source and drain of the second light-emitting control transistor T9. The other of the source and drain of the first light-emitting control transistor T6 is electrically connected to the anode of the light-emitting device EL2 of the second sub-pixel SP2. The other of the source and drain of the second light-emitting control transistor T9 is electrically connected to the anode of the light-emitting device EL4 of the fourth sub-pixel SP4. The gate of the first light-emitting control transistor T6 is electrically connected to the first light-emitting control signal line EM2. The gate of the second light-emitting control transistor T9 is electrically connected to the second light-emitting control signal line EM3.

[0040] In one embodiment of this application, the pixel driving circuit further includes a data writing transistor T2, a compensation transistor T3, a first initialization transistor T7, a second initialization transistor T4, a third light emission control transistor T5, a third initialization transistor T8, a storage capacitor Cst, and a boost capacitor Cboost.

[0041] The data write transistor T2 is used to control the writing of data voltage to the gate (node ​​Q) of the driving transistor T1. The gate of the data write transistor T2 is electrically connected to the first gate line GL1. One of the source and drain of the data write transistor T2 is electrically connected to the data line DL. The other of the source and drain of the data write transistor T2 is electrically connected to the other of the source and drain of the driving transistor T1 (node ​​A).

[0042] Compensation transistor T3 is used to compensate for the threshold voltage of driving transistor T1. The gate of compensation transistor T3 is electrically connected to the third gate line GL3. One of the source and drain of compensation transistor T3 is electrically connected to one of the source and drain of driving transistor T1 (node ​​B). The other of the source and drain of compensation transistor T3 is electrically connected to the gate of driving transistor T1.

[0043] The second initialization transistor T4 is used to initialize the gate of the driving transistor T1. The gate of the second initialization transistor T4 is electrically connected to the fourth gate line GL4. One of the source and drain of the second initialization transistor T4 is electrically connected to the second initialization voltage line VI2. The other of the source and drain of the second initialization transistor T4 is electrically connected to the gate of the driving transistor T1.

[0044] The third light-emitting control transistor T5 is used to control the writing of the voltage of the first power supply line VDD to the other of the source and drain of the driving transistor T1. The gate of the third light-emitting control transistor T5 is electrically connected to the third light-emitting control signal line EM1. One of the source and drain of the third light-emitting control transistor T5 is electrically connected to the first power supply line VDD. The other of the source and drain of the third light-emitting control transistor T5 is electrically connected to the other of the source and drain of the driving transistor T1.

[0045] The third initialization transistor T8 is used to initialize the other of the source and drain of the driving transistor T1. The gate of the third initialization transistor T8 is electrically connected to the second gate line GL2. One of the source and drain of the third initialization transistor T8 is electrically connected to the third initialization voltage line VI3. The other of the source and drain of the third initialization transistor T8 is electrically connected to the other of the source and drain of the driving transistor T1.

[0046] The first initialization transistor T7 is used to initialize the anode of the light-emitting device EL2 of the second sub-pixel SP2 and the anode of the light-emitting device EL4 of the fourth sub-pixel SP4. One of the source and drain of the first initialization transistor T7 is electrically connected to the first initialization voltage line VI1. The other of the source and drain of the first initialization transistor T7 is electrically connected to one of the source and drain of the first light-emitting control transistor T6 and one of the source and drain of the second light-emitting control transistor T9. The gate of the first initialization transistor T7 is electrically connected to the second gate line GL2. Since the first initialization transistor T7 is connected to the anode of the light-emitting device EL2 of the second sub-pixel SP2 or the anode of the light-emitting device EL4 of the fourth sub-pixel SP4 through the first light-emitting control transistor T6 or the second light-emitting control transistor T9, in order to initialize the anode of the light-emitting device EL2 of the second sub-pixel SP2 or the anode of the light-emitting device EL4 of the fourth sub-pixel SP4, it is necessary to control the first light-emitting control transistor T6 or the second light-emitting control transistor T9 to be turned on during the initialization phase. Specifically, since the signal of the second light-emitting control signal line EM3 is generated by inverting the signal of the first light-emitting control signal line EM2, the levels of the first light-emitting control signal line EM2 and the second light-emitting control signal line EM3 are always opposite. Therefore, during the initialization phase, only one of the first light-emitting control transistor T6 or the second light-emitting control transistor T9 is turned on, thereby initializing only the anode of the light-emitting device of the sub-pixel corresponding to the current light-emitting mode. For example, in the first display mode, only the anode of the light-emitting device EL2 of the second sub-pixel SP2 is initialized, and in the second display mode, only the anode of the light-emitting device EL4 of the fourth sub-pixel SP4 is initialized.

[0047] The storage capacitor Cst is used to store the gate voltage of the driving transistor T1. The first plate of the storage capacitor Cst is electrically connected to the first power supply line VDD. The second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1.

[0048] The boost capacitor Cboost is used to boost the gate voltage of the driving transistor T1. The first plate of the boost capacitor Cboost is electrically connected to the first gate line GL1. The second plate of the boost capacitor Cboost is electrically connected to the gate of the driving transistor T1.

[0049] In the embodiments of this application, the driving transistor T1, the data writing transistor T2, the first light-emitting control transistor T6, the second light-emitting control transistor T9, the first initialization transistor T7, the third light-emitting control transistor T5, and the third initialization transistor T8 are all P-type transistors. The compensation transistor T3 and the second initialization transistor T4 are both N-type transistors.

[0050] The light emission control signal generation circuit is used to provide light emission control signals to the first light emission control signal line EM2 and the second light emission control signal line EM3. For example... Figure 6 As shown, the light emission control signal generation circuit includes a first light emission control signal output terminal EM2, a second light emission control signal output terminal EM3, and an inverting circuit. The first light emission control signal output terminal EM2 is electrically connected to the first light emission control signal line EM2. The second light emission control signal output terminal EM3 is electrically connected to the second light emission control signal line EM3. The input terminal of the inverting circuit is electrically connected to the first light emission control signal output terminal EM2. The output terminal of the inverting circuit is electrically connected to the second light emission control signal output terminal EM3. The inverting circuit is used to invert the light emission control signal output from the first light emission control signal output terminal EM2 and output it to the second light emission control signal output terminal EM3.

[0051] like Figure 6 As shown, the inverting circuit includes a first transistor S14 and a second transistor S15. The gate of the first transistor S14 is electrically connected to the first light-emitting control signal output terminal EM2. One of the source and drain of the first transistor S14 is electrically connected to the first level signal line VGH. The other of the source and drain of the first transistor S14 is electrically connected to the second light-emitting control signal output terminal EM3. The gate of the second transistor S15 is electrically connected to the first light-emitting control signal output terminal EM2. One of the source and drain of the second transistor S15 is electrically connected to the second level signal line VGL. The other of the source and drain of the second transistor S15 is electrically connected to the second light-emitting control signal output terminal EM3.

[0052] In one embodiment of this application, the first transistor S14 is a P-type transistor, and the second transistor S15 is an N-type transistor. In this case, the first level signal line VGH is used to provide a high-level signal, and the second level signal line VGL is used to provide a low-level signal. When the first light-emitting control signal output terminal EM2 outputs a high-level signal, the first transistor S14 is turned off, the second transistor S15 is turned on, and the voltage of the second level signal line VGL is written to the second light-emitting control signal output terminal EM3 through the second transistor S15, causing the second light-emitting control signal output terminal EM3 to output a low-level signal. When the first light-emitting control signal output terminal EM2 outputs a low-level signal, the first transistor S14 is turned on, the second transistor S15 is turned off, and the voltage of the first level signal line VGH is written to the second light-emitting control signal output terminal EM3 through the first transistor S14, causing the second light-emitting control signal output terminal EM3 to output a high-level signal. The inverting circuit inverts the light-emitting control signal output from the first light-emitting control signal output terminal EM2 and outputs it to the second light-emitting control signal output terminal EM3, so that the levels of the light-emitting control signals output from the first light-emitting control signal output terminal EM2 and the second light-emitting control signal output terminal EM3 are always opposite.

[0053] In another embodiment of this application, the first transistor S14 is an N-type transistor, and the second transistor S15 is a P-type transistor. In this case, the first level signal line is used to provide a low-level signal, and the second level signal line is used to provide a high-level signal. When the first light-emitting control signal output terminal EM2 outputs a high-level signal, the first transistor S14 is turned on, the second transistor S15 is turned off, and the voltage of the first level signal line is written to the second light-emitting control signal output terminal EM3 through the first transistor S14, resulting in a low-level signal output from EM3. When the first light-emitting control signal output terminal EM2 outputs a low-level signal, the first transistor S14 is turned off, the second transistor S15 is turned on, and the voltage of the second level signal line is written to the second light-emitting control signal output terminal EM3 through the second transistor S15, resulting in a high-level signal output from EM3. The inverting circuit inverts the light-emitting control signal output from the first light-emitting control signal output terminal EM2 and outputs it to the second light-emitting control signal output terminal EM3.

[0054] like Figure 6 As shown, in one embodiment of this application, the light emission control signal generation circuit further includes a third transistor S10 and a fourth transistor S16. The third transistor S10 is used to control the writing of the voltage of the first level signal line VGH to the first light emission control signal output terminal EM2. The gate of the third transistor S10 is electrically connected to node N4. One of the source and drain of the third transistor S10 is electrically connected to the first level signal line VGH. The other of the source and drain of the third transistor S10 is electrically connected to the first light emission control signal output terminal EM2. The fourth transistor S16 is used to reset node N4. The gate of the fourth transistor S16 is electrically connected to the reset control signal line RST. One of the source and drain of the fourth transistor S16 is electrically connected to the second level signal line VGL. The other of the source and drain of the fourth transistor S16 is electrically connected to node N4.

[0055] In one specific embodiment of this application, such as Figure 6As shown, the light emission control signal generation circuit adopts a 16T3C architecture. The light emission control signal generation circuit includes transistors S1 to S16 and capacitors C1 to C3. The gate of transistor S4 is electrically connected to the clock signal line XCK, one of its source and drain is electrically connected to the second-level signal line VGL, and the other of its source and drain is electrically connected to node N2. The gate of transistor S5 is electrically connected to node N3, one of its source and drain is electrically connected to the clock signal line XCK, and the other of its source and drain is electrically connected to node N2. The gate of transistor S3 is electrically connected to the clock signal line XCK, one of its source and drain is electrically connected to the stage signal input line or the start signal input line STV, and the other of its source and drain is electrically connected to node N3. The gate of transistor S13 is electrically connected to the control signal line Control, one of its source and drain is electrically connected to the first-level signal line VGH, and the other of its source and drain is electrically connected to node N3. The gate of transistor S11 is electrically connected to the second-level signal line VGL, one of its source and drain is electrically connected to node N2, and the other of its source and drain is electrically connected to node N1. The gate of transistor S1 is electrically connected to node N2, one of its source and drain is electrically connected to the first-level signal line VGH, and the other of its source and drain is electrically connected to the other of its source and drain in transistor S2.

[0056] The first plate of capacitor C1 is electrically connected to node N5, and the second plate is electrically connected to the other of the source and drain terminals of transistor S1. The gate of transistor S2 is electrically connected to node N5, and one of its source and drain terminals is electrically connected to the clock signal line CK. The gate of transistor S6 is electrically connected to node N1, and one of its source and drain terminals is electrically connected to the clock signal line CK. The other of its source and drain terminals is electrically connected to the other of the source and drain terminals of transistor S7. The first plate of capacitor C2 is electrically connected to node N1, and the second plate is electrically connected to the other of the source and drain terminals of transistor S6. The gate of transistor S7 is electrically connected to the clock signal line CK, and the other of its source and drain terminals is electrically connected to node N4. The gate of transistor S8 is electrically connected to node N3, and one of its source and drain terminals is electrically connected to the first level signal line VGH. The other of its source and drain terminals is electrically connected to node N4. The first plate of capacitor C3 is electrically connected to the first-level signal line VGH, and the second plate is electrically connected to node N4. The gate of transistor S12 is electrically connected to the second-level signal line VGL, one of its source and drain is electrically connected to node N3, and the other of its source and drain is electrically connected to node N5. The gate of transistor S10 (the third transistor S10) is electrically connected to node N4, one of its source and drain is electrically connected to the first-level signal line VGH, and the other of its source and drain is electrically connected to the first light-emitting control signal output terminal EM2. The gate of transistor S9 is electrically connected to node N5, one of its source and drain is electrically connected to the second-level signal line VGL, and the other of its source and drain is electrically connected to the first light-emitting control signal output terminal EM2.

[0057] The inverter circuit includes transistor S14 (first transistor S14) and transistor S15 (second transistor S15). The gate of transistor S14 is electrically connected to the first light-emitting control signal output terminal EM2, one of its source and drain is electrically connected to the first level signal line VGH, and the other of its source and drain is electrically connected to the second light-emitting control signal output terminal EM3. Similarly, the gate of transistor S15 is electrically connected to the first light-emitting control signal output terminal EM2, one of its source and drain is electrically connected to the second level signal line VGL, and the other of its source and drain is electrically connected to the second light-emitting control signal output terminal EM3.

[0058] The gate of transistor S16 (fourth transistor S16) is electrically connected to the reset control signal line RST, one of its source and drain is electrically connected to the second level signal line VGL, and the other of its source and drain is electrically connected to node N4.

[0059] In one embodiment of this application, transistors S1 to S14 are all P-type transistors, and transistors S15 and S16 are N-type transistors. In another embodiment of this application, transistors S1 to S14 are all N-type transistors, and transistors S15 and S16 are P-type transistors. When transistors S1 to S9 and S11 to S14 are P-type transistors, transistor S10 can also be an N-type transistor, in which case one of the source and drain of transistor S16 is electrically connected to the first level signal line VGH. When transistors S1 to S9 and S11 to S14 are N-type transistors, transistor S10 can also be a P-type transistor, in which case one of the source and drain of transistor S16 is electrically connected to the second level signal line VGL.

[0060] In the first display mode, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 emit light, while the fourth sub-pixel SP4 does not emit light. In the second display mode, the first sub-pixel SP1, the third sub-pixel SP3, and the fourth sub-pixel SP4 emit light, while the second sub-pixel SP2 does not emit light. The display device switches between the first and second display modes by time-division driving the light-emitting devices EL2 of the second sub-pixel SP2 and EL4 of the fourth sub-pixel SP4.

[0061] When the second display mode is the privacy display mode, the light emission color of the fourth sub-pixel SP4 is the same as that of the second sub-pixel SP2. In the first display mode, the display device displays normally according to the three primary colors of red, green, and blue, and the light emitted by the light-emitting devices EL1, EL2, and EL3 of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 is emitted directly outward. In the second display mode, the fourth sub-pixel SP4 emits light together with the first sub-pixel SP1 and the third sub-pixel SP3, while the second sub-pixel SP2 does not emit light.

[0062] In one embodiment of this application, the display device employs a wide-viewing-angle privacy mode. The cross-sectional structure of the display panel DP, from bottom to top, includes a substrate, a thin-film transistor layer, an anode layer, a pixel defining layer, a light-emitting layer located within an opening in the pixel defining layer, a cathode layer, a thin-film encapsulation layer, a first inorganic layer, a first touch metal layer, a second inorganic layer, a second touch metal layer, a third inorganic layer, a multilayer planarization layer, a light-blocking layer, and a passivation layer. The first and second touch metal layers serve as two touch electrodes for the touch device. The multilayer planarization layer is used to insulate and planarize the touch metal layers, and the passivation layer is made of an organic material. In the fourth sub-pixel SP4, the light-blocking layer is disposed between the planarization layer and the passivation layer, and is located above the light-emitting layer of the light-emitting device EL4 of the fourth sub-pixel SP4. From a top-view perspective of the display panel DP, the light-blocking layer overlaps with the light-emitting layer of the light-emitting device EL4 of the fourth sub-pixel SP4. The light-blocking layer is used to block the light emitted by the light-emitting device EL4 of the fourth sub-pixel SP4 in the narrow viewing angle direction. In the fourth sub-pixel SP4, the light emitted from the light-emitting layer of the light-emitting device EL4 shines upwards towards the light-blocking layer and is blocked or reflected. The light emitted from the side edge of the light-blocking layer shines obliquely, thus creating an interfering image at a wide viewing angle and achieving the privacy function. In the second sub-pixel SP2, no light-blocking layer is placed directly above the light-emitting layer of the light-emitting device EL2. The light emitted from the light-emitting layer of the second sub-pixel SP2 passes directly through the thin-film encapsulation layer, multiple planarization layers, and passivation layers before escaping outwards. The light-blocking layer is an opaque material layer, and the material of the light-blocking layer includes, but is not limited to, metal materials and black resin materials. In the first sub-pixel SP1, no light-blocking layer is placed directly above the light-emitting device EL1. The light emitted from the light-emitting device EL1 of the first sub-pixel SP1 sequentially passes through the cathode layer, thin-film encapsulation layer, the opening of the touch device, the planarization layer, and the passivation layer, escaping in both the narrow and wide viewing angle directions. No light-blocking layer is set directly above the third sub-pixel SP3. The light emitted by the light-emitting device EL3 of the third sub-pixel SP3 passes through the cathode layer, thin film encapsulation layer, opening of the touch device, planarization layer and passivation layer in sequence, and is emitted in the direction of small viewing angle and large viewing angle.

[0063] In another embodiment of this application, the display device employs a narrow-view privacy mode. The cross-sectional structure of the display panel DP, from bottom to top, includes a substrate, a thin-film transistor layer, an anode layer, a pixel defining layer and an opening within which a light-emitting layer, a cathode layer, a thin-film encapsulation layer, a first inorganic layer, a first touch metal layer, a second inorganic layer, a second touch metal layer, a third inorganic layer, a first planarization layer, a first light-blocking layer, a second planarization layer, a third planarization layer, a second light-blocking layer, and a passivation layer. In the fourth sub-pixel SP4, the first light-blocking layer is disposed between the first planarization layer and the second planarization layer, and the second light-blocking layer is disposed between the third planarization layer and the passivation layer. Wide-viewing-angle light emitted from the light-emitting layer of the light-emitting device EL4 of the fourth sub-pixel SP4 is directed upwards towards and blocked by the first and second light-blocking layers, while narrow-viewing-angle light bypasses the first and second light-blocking layers and is emitted outwards. In the second sub-pixel SP2, no first or second light-blocking layer is disposed directly above the light-emitting layer of the light-emitting device EL2 of the second sub-pixel SP2. The light emitted from the light-emitting layer of the light-emitting device EL2 of the second sub-pixel SP2 passes directly through the thin film encapsulation layer, each planarization layer, and the passivation layer and is emitted outward. From a top-view perspective of the display panel DP, the first and second light-blocking layers are disposed at the outer edge of the light-emitting layer of the light-emitting device EL4 of the fourth sub-pixel SP4, surrounding the light-emitting layer of the light-emitting device EL4 of the fourth sub-pixel SP4. No first or second light-blocking layers are disposed directly above the first sub-pixel SP1 and the third sub-pixel SP3.

[0064] When the emitted color of the fourth sub-pixel SP4 is different from the emitted colors of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the second display mode is a wide color gamut display mode. In the second display mode, the fourth sub-pixel SP4 emits light together with the first sub-pixel SP1 and the third sub-pixel SP3, while the second sub-pixel SP2 does not emit light. The fourth sub-pixel SP4 emits light of a different color than the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. This light, when mixed with the red light emitted by the first sub-pixel SP1 and the blue light emitted by the third sub-pixel SP3, expands the color gamut range of the display device, achieving wide color gamut display.

[0065] Embodiments of this application also provide a driving method for a display device. The driving cycle for displaying one frame of an image includes an initialization phase, a data voltage writing phase, and a light emission phase. In the initialization phase, the gate of the driving transistor T1 and the anode of the light-emitting device EL2 of the second sub-pixel SP2 or the anode of the light-emitting device EL4 of the fourth sub-pixel SP4 are initialized. In the data voltage writing phase, a data voltage is written to the gate of the driving transistor T1. In the light emission phase, the driving transistor T1 generates a driving current, which flows to the light-emitting device EL2 of the second sub-pixel SP2 or the light-emitting device EL4 of the fourth sub-pixel SP4, causing the second sub-pixel SP2 or the fourth sub-pixel SP4 to emit light.

[0066] In the first display mode (normal display mode), during the initialization phase of the drive cycle for displaying one frame, the first light-emitting control signal output terminal EM2 outputs a first-level signal. The inverting circuit inverts the first-level signal to a second-level signal, and the second light-emitting control signal output terminal EM3 outputs the second-level signal. The first light-emitting control transistor T6 is turned on under the control of the first-level signal, and the second light-emitting control transistor T9 is turned off under the control of the second-level signal. The second gate line GL2 provides a first-level signal to the gate of the first initialization transistor T7, turning on the first initialization transistor T7. The voltage of the first initialization voltage line VI1 is written to the anode of the light-emitting device EL2 of the second sub-pixel SP2 via the first initialization transistor T7 and the first light-emitting control transistor T6, thus initializing the anode of the light-emitting device EL2 of the second sub-pixel SP2. During the light-emitting phase of the first display mode, the first light-emitting control signal output terminal EM2 outputs a first-level signal. The inverting circuit inverts the first-level signal to a second-level signal, and the second light-emitting control signal output terminal EM3 outputs the second-level signal. The first light-emitting control transistor T6 is turned on under the control of the first-level signal, and the second light-emitting control transistor T9 is turned off under the control of the second-level signal. The third light-emitting control signal line EM1 provides a first-level signal to the gate of the third light-emitting control transistor T5, turning on the third light-emitting control transistor T5. The driving current flows into the anode of the light-emitting device EL2 of the second sub-pixel SP2 through the third light-emitting control transistor T5, the driving transistor T1, and the first light-emitting control transistor T6, causing the second sub-pixel SP2 to emit light.

[0067] In the second display mode (privacy mode or wide color gamut mode), during the initialization phase of the drive cycle for displaying one frame, the first light-emitting control signal output terminal EM2 outputs a second-level signal. The inverting circuit inverts the second-level signal to a first-level signal, and the second light-emitting control signal output terminal EM3 outputs the first-level signal. The first light-emitting control transistor T6 is turned off under the control of the second-level signal, and the second light-emitting control transistor T9 is turned on under the control of the first-level signal. The second gate line GL2 provides a first-level signal to the gate of the first initialization transistor T7, turning on the first initialization transistor T7. The voltage of the first initialization voltage line VI1 is written to the anode of the light-emitting device EL4 of the fourth sub-pixel SP4 via the first initialization transistor T7 and the second light-emitting control transistor T9, thus initializing the anode of the light-emitting device EL4 of the fourth sub-pixel SP4. During the light-emitting phase of the second display mode, the first light-emitting control signal output terminal EM2 outputs a second-level signal, the inverting circuit inverts the second-level signal to a first-level signal, and the second light-emitting control signal output terminal EM3 outputs the first-level signal. The first light-emitting control transistor T6 is turned off under the control of the second level signal, and the second light-emitting control transistor T9 is turned on under the control of the first level signal. The third light-emitting control signal line EM1 provides the first level signal to the gate of the third light-emitting control transistor T5, and the third light-emitting control transistor T5 is turned on. The driving current flows into the anode of the light-emitting device EL4 of the fourth sub-pixel SP4 through the third light-emitting control transistor T5, the driving transistor T1, and the second light-emitting control transistor T9, and the fourth sub-pixel SP4 emits light.

[0068] During the initialization phase of the second display mode, to enable the first light-emitting control signal output terminal EM2 to output a second-level signal, the reset control signal line RST provides a third-level signal to the gate of the fourth transistor S16. The fourth transistor S16 is turned on, and the potential of node N4 becomes the potential of the second-level signal line VGL. The third transistor S10 is then turned on under the control of the potential of the second-level signal line VGL. The first light-emitting control signal output terminal EM2 outputs the potential of the first-level signal line VGH. The inverting circuit inverts the potential of the first-level signal line VGH to the potential of the second-level signal line VGL. The second light-emitting control signal output terminal EM3 outputs the potential of the second-level signal line VGL. During the initialization phase of the first display mode and all light-emitting phases, the reset control signal line RST provides a fourth-level signal to the gate of the fourth transistor S16, and the fourth transistor S16 is turned off.

[0069] In the embodiments of this application, the first level signal is a low level signal, the second level signal is a high level signal, the third level signal is a high level signal, and the fourth level signal is a low level signal. The P-type transistor is turned on under the control of the low level signal and turned off under the control of the high level signal. The N-type transistor is turned on under the control of the high level signal and turned off under the control of the low level signal.

[0070] In the first display mode, during the driving cycle of displaying one frame, the third light-emitting control signal line EM1 first provides a second-level signal (high-level signal) to the gate of the third light-emitting control transistor T5, and the third light-emitting control transistor T5 is turned off. During the period when the third light-emitting control transistor T5 is turned off, the second gate line GL2 generates a first-level pulse (first-low-level pulse), the first initialization transistor T7 is turned on, and the anode of the light-emitting device EL2 of the second sub-pixel SP2 is initialized. Subsequently, the third gate line GL3 provides a second-level signal (high-level signal) to the gate of the compensation transistor T3, and the compensation transistor T3 is turned on. During the period when the compensation transistor T3 is turned on, the fourth gate line GL4 generates a second-level pulse (a high-level pulse), the second initialization transistor T4 is turned on, and the gate of the driving transistor T1 is initialized. After the second-level pulse of the fourth gate line GL4 ends, the first gate line GL1 generates a first-level pulse (a low-level pulse), the data writing transistor T2 and the third initialization transistor T8 are turned on, and the data voltage is written to the gate of the driving transistor T1 through the data writing transistor T2. After the first level pulse of the first gate line GL1 ends, the third gate line GL3 provides a first level signal (low level signal) to the gate of the compensation transistor T3, and the compensation transistor T3 is turned off. After the compensation transistor T3 is turned off, the second gate line GL2 generates a second first level pulse (second low level pulse), the first initialization transistor T7 is turned on, and the anode of the light-emitting device EL2 of the second sub-pixel SP2 is re-initialized. After the second first level pulse of the second gate line GL2 ends, the third light-emitting control signal line EM1 provides a first level signal (low level signal) to the gate of the third light-emitting control transistor T5, the third light-emitting control transistor T5 is turned on, the driving current flows to the light-emitting device EL2 of the second sub-pixel SP2, and the second sub-pixel SP2 emits light.

[0071] In the second display mode, during the driving cycle of displaying one frame, the timing of the third gate line GL3, the fourth gate line GL4, the first gate line GL1, the second gate line GL2, and the third light-emitting control signal line EM1 is the same as in the first display mode. During the driving cycle of the second display mode, since the first light-emitting control signal output terminal EM2 outputs a second-level signal (high-level signal), the inverting circuit inverts the second-level signal into a first-level signal (low-level signal), and the second light-emitting control signal output terminal EM3 outputs a first-level signal (low-level signal). The first light-emitting control transistor T6 is turned off under the control of the second-level signal, and the second light-emitting control transistor T9 is turned on under the control of the first-level signal. The voltage of the first initialization voltage line VI1 is written to the anode of the light-emitting device EL4 of the fourth sub-pixel SP4 via the first initialization transistor T7 and the second light-emitting control transistor T9. The driving current flows to the light-emitting device EL4 of the fourth sub-pixel SP4, and the fourth sub-pixel SP4 emits light.

[0072] Through the aforementioned timing control, the single-pixel driving circuit achieves time-division independent reset and driving of the light-emitting devices EL2 of the second sub-pixel SP2 and the fourth sub-pixel SP4. In the first display mode, the second sub-pixel SP2 emits light, while the fourth sub-pixel SP4 does not. In the second display mode, the fourth sub-pixel SP4 emits light, while the second sub-pixel SP2 does not. The display device switches between the first and second display modes as needed, thereby achieving switching between normal display mode, privacy display mode, or wide color gamut display mode.

[0073] The technical solution of this application adds an inverting circuit to the first light-emitting control signal output terminal EM2 of the light-emitting control signal generation circuit. This inverting circuit inverts the light-emitting control signal output from the first light-emitting control signal output terminal EM2 and outputs it to the second light-emitting control signal output terminal EM3. This ensures that the levels of the light-emitting control signals output from the first light-emitting control signal output terminal EM2 and the second light-emitting control signal output terminal EM3 are always opposite, thereby achieving time-division driving of the light-emitting device EL2 of the second sub-pixel SP2 and the light-emitting device EL4 of the fourth sub-pixel SP4. This technical solution eliminates the need for a separate complete light-emitting control signal generation circuit for the light-emitting device EL4 of the fourth sub-pixel SP4; only the inverting circuit is needed to achieve the output of two light-emitting control signals. The inverting circuit has a simple circuit structure, occupies a small area, reduces wiring and circuit space in non-display areas, and lowers the bezel width of the display panel DP. Furthermore, the inverting circuit allows the light-emitting devices EL2 of the second sub-pixel SP2 and EL4 of the fourth sub-pixel SP4 to share a pixel driving circuit, avoiding the problem of significantly widening the bezel caused by adding a complete light-emitting control signal generation circuit.

[0074] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, which includes a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels, and a plurality of fourth sub-pixels. The light-emitting devices of the second sub-pixels and the light-emitting devices of the fourth sub-pixels are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the light-emitting device of the second sub-pixel. The other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line. The display panel further includes at least one light emission control signal generation circuit. The light emission control signal generation circuit includes a first light emission control signal output terminal, a second light emission control signal output terminal, and an inverting circuit. The first light emission control signal output terminal is electrically connected to the first light emission control signal line, the second light emission control signal output terminal is electrically connected to the second light emission control signal line, the input terminal of the inverting circuit is electrically connected to the first light emission control signal output terminal, and the output terminal of the inverting circuit is electrically connected to the second light emission control signal output terminal.

2. The display device according to claim 1, characterized in that, The inverting circuit includes a first transistor and a second transistor. The gate of the first transistor is electrically connected to the first light-emitting control signal output terminal. One of the source and drain of the first transistor is electrically connected to a first level signal line. The other of the source and drain of the first transistor is electrically connected to the second light-emitting control signal output terminal. The gate of the second transistor is electrically connected to the first light-emitting control signal output terminal. One of the source and drain of the second transistor is electrically connected to a second level signal line. The other of the source and drain of the second transistor is electrically connected to the second light-emitting control signal output terminal.

3. The display device according to claim 2, characterized in that, The first transistor is either a P-type transistor or an N-type transistor, and the second transistor is either a P-type transistor or an N-type transistor.

4. The display device according to claim 2, characterized in that, The light emission control signal generation circuit includes a third transistor and a fourth transistor. The gate of the third transistor is electrically connected to the first node. One of the source and drain of the third transistor is electrically connected to the first level signal line. The other of the source and drain of the third transistor is electrically connected to the first light emission control signal output terminal. The gate of the fourth transistor is electrically connected to the reset control signal line. One of the source and drain of the fourth transistor is electrically connected to the second level signal line. The other of the source and drain of the fourth transistor is electrically connected to the first node.

5. The display device according to claim 1, characterized in that, The pixel driving circuit includes a first initialization transistor, one of the source and drain of the first initialization transistor is electrically connected to a first initialization voltage line, the other of the source and drain of the first initialization transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor, and the gate of the first initialization transistor is electrically connected to a second gate line.

6. The display device according to claim 5, characterized in that, The pixel driving circuit includes a data writing transistor, a compensation transistor, a second initialization transistor, a third light-emitting control transistor, a storage capacitor, and a boost capacitor. The gate of the data writing transistor is electrically connected to a first gate line. One of the source and drain of the data writing transistor is electrically connected to a data line, and the other of the source and drain of the data writing transistor is electrically connected to the other of the source and drain of the driving transistor. The gate of the compensation transistor is electrically connected to a third gate line. One of the source and drain of the compensation transistor is electrically connected to one of the source and drain of the driving transistor, and the other of the source and drain of the compensation transistor is electrically connected to the gate of the driving transistor. The gate of the second initialization transistor is electrically connected to a fourth gate line. One of the source and drain of the second initialization transistor is electrically connected to a second initialization voltage line, and the other of the source and drain of the second initialization transistor... The gate of the third light-emitting control transistor is electrically connected to the gate of the driving transistor; the gate of the third light-emitting control transistor is electrically connected to the third light-emitting control signal line; one of the source and drain of the third light-emitting control transistor is electrically connected to the first power supply line; the other of the source and drain of the third light-emitting control transistor is electrically connected to the other of the source and drain of the driving transistor; the gate of the third initialization transistor is electrically connected to the first gate line; one of the source and drain of the third initialization transistor is electrically connected to the third initialization voltage line; the other of the source and drain of the third initialization transistor is electrically connected to the other of the source and drain of the driving transistor; the first plate of the storage capacitor is electrically connected to the first power supply line; the second plate of the storage capacitor is electrically connected to the gate of the driving transistor; the first plate of the boost capacitor is electrically connected to the first gate line; and the second plate of the boost capacitor is electrically connected to the gate of the driving transistor.

7. The display device according to claim 1, characterized in that, A plurality of second sub-pixels and a plurality of first sub-pixels are arranged alternately along a first direction, and a plurality of third sub-pixels and a plurality of fourth sub-pixels are arranged alternately along the first direction; Along the second direction, the center line connecting the plurality of third sub-pixels is located between the center line connecting the plurality of second sub-pixels and the center line connecting the plurality of first sub-pixels, and the center line connecting the plurality of fourth sub-pixels is located between the center line connecting the plurality of first sub-pixels and the center line connecting the plurality of second sub-pixels, and the second direction intersects the first direction.

8. The display device according to claim 1, characterized in that, Multiple first sub-pixels, multiple fourth sub-pixels, and multiple third sub-pixels are arranged alternately along a first direction, and multiple second sub-pixels are arranged repeatedly along the first direction; Multiple first sub-pixels and multiple third sub-pixels are arranged alternately along the second direction, multiple second sub-pixels are arranged repeatedly along the second direction, and multiple fourth sub-pixels are arranged repeatedly along the second direction; Along the second direction, the center line connecting the plurality of first sub-pixels is collinear with the center line connecting the plurality of third sub-pixels; Along the second direction, the center line connecting the plurality of second sub-pixels is located between the center line connecting the plurality of first sub-pixels and the center line connecting the plurality of fourth sub-pixels, and the center line connecting the plurality of fourth sub-pixels is located between the center line connecting the plurality of third sub-pixels and the center line connecting the plurality of second sub-pixels, and the second direction intersects the first direction.

9. The display device according to claim 1, characterized in that, In the first display mode, the first sub-pixel, the second sub-pixel, and the third sub-pixel emit light, while the fourth sub-pixel does not emit light. In the second display mode, the first sub-pixel, the third sub-pixel, and the fourth sub-pixel emit light, while the second sub-pixel does not emit light.

10. The display device according to claim 9, characterized in that, The emission color of the fourth sub-pixel is the same as the emission color of the second sub-pixel, and the second display mode is a privacy display mode.

11. The display device according to claim 9, characterized in that, The emission color of the fourth sub-pixel is different from the emission colors of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

12. A driving method for a display device, characterized in that, The display device includes a display panel, which includes a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels, a plurality of fourth sub-pixels, and at least one light-emitting control signal generation circuit. The light-emitting devices of the second sub-pixels and the fourth sub-pixels are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the light-emitting device of the second sub-pixel. The source or drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line. The light-emitting control signal generation circuit includes a first light-emitting control signal output terminal, a second light-emitting control signal output terminal, and an inverting circuit. The first light-emitting control signal output terminal is electrically connected to the first light-emitting control signal line, and the second light-emitting control signal output terminal is electrically connected to the second light-emitting control signal line. The input terminal of the inverting circuit is electrically connected to the first light-emitting control signal output terminal, and the output terminal of the inverting circuit is electrically connected to the second light-emitting control signal output terminal. The driving cycle for displaying one frame of an image by the display device includes an initialization phase and a light emission phase, and the driving method includes: In the initialization phase and the light emission phase of the first display mode, the first light emission control signal output terminal outputs a first level signal, the inverting circuit inverts the first level signal into a second level signal, the second light emission control signal output terminal outputs the second level signal, the first light emission control transistor is turned on under the control of the first level signal, and the second light emission control transistor is turned off under the control of the second level signal. During the initialization phase and the light emission phase of the second display mode, the first light emission control signal output terminal outputs the second level signal, the inverting circuit inverts the second level signal to the first level signal, the second light emission control signal output terminal outputs the first level signal, the first light emission control transistor is turned off under the control of the second level signal, and the second light emission control transistor is turned on under the control of the first level signal.

13. The driving method for the display device according to claim 12, characterized in that, The pixel driving circuit includes a first initialization transistor, one of the source and drain of the first initialization transistor is electrically connected to a first initialization voltage line, the other of the source and drain of the first initialization transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor, and the gate of the first initialization transistor is electrically connected to a second gate line. During the initialization phase of the first display mode, the driving method includes: The first level signal is provided to the second gate line, causing the first initialization transistor to be turned on, and the voltage of the first initialization voltage line is written into the anode of the light-emitting device of the second sub-pixel via the first initialization transistor and the first light-emitting control transistor. During the initialization phase of the second display mode, the driving method includes: The first level signal is provided to the second gate line, causing the first initialization transistor to turn on, and the voltage of the first initialization voltage line is written into the anode of the light-emitting device of the fourth sub-pixel via the first initialization transistor and the second light-emitting control transistor.

14. The driving method for the display device according to claim 12, characterized in that, The light emission control signal generation circuit includes a third transistor and a fourth transistor. The gate of the third transistor is electrically connected to the first node. One of the source and drain of the third transistor is electrically connected to a first-level signal line. The other of the source and drain of the third transistor is electrically connected to the first light emission control signal output terminal. The gate of the fourth transistor is electrically connected to a reset control signal line. One of the source and drain of the fourth transistor is electrically connected to a second-level signal line. The other of the source and drain of the fourth transistor is electrically connected to the first node. During the initialization phase of the second display mode, the driving method includes: A third-level signal is provided to the reset control signal line, causing the fourth transistor to turn on. The potential of the first node becomes the potential of the second-level signal line. The third transistor turns on under the control of the potential of the second-level signal line. The first light-emitting control signal output terminal outputs the potential of the first-level signal line. The inverting circuit inverts the potential of the first-level signal line to the potential of the second-level signal line. The second light-emitting control signal output terminal outputs the potential of the second-level signal line.

15. The driving method for the display device according to claim 12, characterized in that, The pixel driving circuit includes a third light-emitting control transistor, the gate of which is electrically connected to a third light-emitting control signal line, one of the source and drain of which is electrically connected to a first power supply line, and the other of the source and drain of which is electrically connected to the other of the source and drain of the driving transistor. During the light-emitting phase of the first display mode, the driving method includes: The first level signal is provided to the third light emission control signal line, so that the third light emission control transistor is turned on, and the driving current flows into the anode of the light emission device of the second sub-pixel through the third light emission control transistor, the driving transistor and the first light emission control transistor; During the light-emitting phase of the second display mode, the driving method includes: The first level signal is provided to the third light emission control signal line, so that the third light emission control transistor is turned on, and the driving current flows into the anode of the light emission device of the fourth sub-pixel through the third light emission control transistor, the driving transistor and the second light emission control transistor.

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