Display device and driving method thereof

Abstract

The application provides a display device driving method and a display device. The display device comprises a plurality of pixels arranged in an array. The pixels comprise a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel. The color of light emitted by the fourth sub-pixel is the same as the color of light emitted by the second sub-pixel. In a first display mode, the first sub-pixel, the second sub-pixel and the third sub-pixel in the pixel located in the i-th row and the j-th column are controlled to emit light, and the fourth sub-pixel in the pixel located in the i-th row and the j-th column does not emit light. In a second display mode, the first sub-pixel and the fourth sub-pixel in the pixel located in the i-th row and the j-th column and the third sub-pixel in the pixel located in the i+1-th row and the j-th column are controlled to emit light, and the second sub-pixel in the pixel located in the i-th row and the j-th column does not emit light. The application realizes switching between a normal display mode and a privacy display mode without reducing the pixel density.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] Existing display panels typically consist of multiple pixel units, each including red, green, and blue sub-pixels. These sub-pixels are driven by pixel driving circuits to achieve full-color display. However, when adding privacy protection features to traditional display panels, it is often difficult to strike a balance between maintaining display quality and controlling implementation costs. Specifically, adding privacy protection features to traditional display panels often leads to a reduction in pixel density, thus affecting image quality. Furthermore, traditional display panels have poor flexibility in switching between normal display mode and privacy display mode, making it difficult to meet users' display needs in different usage scenarios.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0004] The purpose of this application is to provide a display device and its driving method, which aims to achieve switching between normal display mode and privacy display mode without reducing pixel density.

[0005] This application provides a driving method for a display device, the display device including a display panel, the display panel including a plurality of pixels arranged in an array, the pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the color of the light emitted by the fourth sub-pixel being the same as the color of the light emitted by the second sub-pixel; the driving method includes: in a first display mode, controlling the first sub-pixel, the second sub-pixel and the third sub-pixel located in the i-th row and j-th column of the pixels to emit light, and controlling the fourth sub-pixel located in the i-th row and j-th column of the pixels to not emit light, i being a positive integer and j being a positive integer; in a second display mode, controlling the first sub-pixel and the fourth sub-pixel located in the i-th row and j-th column of the pixels and the third sub-pixel located in the (i+1)-th row and j-th column of the pixels to emit light, and controlling the second sub-pixel located in the i-th row and j-th column of the pixels to not emit light.

[0006] In the driving method of the above-described display device, the anode of the second light-emitting device of the second sub-pixel and the anode of the fourth light-emitting device of the fourth sub-pixel are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the second light-emitting device of the second sub-pixel. The other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the fourth light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line.

[0007] In the above-described driving method for the display device, the driving method further includes: in the second display mode, providing a first level signal to the first light-emitting control signal line and providing a second level signal to the second light-emitting control signal line, so that the first light-emitting control transistor is turned off and the second light-emitting control transistor is turned on.

[0008] In the above-described driving method for the display device, the driving method further includes: in the first display mode, providing the second level signal to the first light-emitting control signal line and providing the first level signal to the second light-emitting control signal line, so that the first light-emitting control transistor is turned on and the second light-emitting control transistor is turned off.

[0009] In the driving method of the above-described display device, the pixel driving circuit includes an initialization transistor. One of the source and drain of the initialization transistor is electrically connected to an initialization voltage line. The other of the source and drain of the initialization transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The gate of the initialization transistor is electrically connected to an initialization control signal line. The driving cycle of the display device displaying one frame includes an initialization phase. In the initialization phase, the driving method further includes: providing a first level signal to the initialization control signal line to turn on the initialization transistor; providing a second level signal to the first light-emitting control signal line to turn on the first light-emitting control transistor, and writing the voltage of the initialization voltage line into the anode of the second light-emitting device of the second sub-pixel; and providing the second level signal to the second light-emitting control signal line to turn on the second light-emitting control transistor, and writing the voltage of the initialization voltage line into the anode of the fourth light-emitting device of the fourth sub-pixel.

[0010] In the driving method of the above-mentioned display device, the driving method further includes: in the second display mode, controlling the sub-pixels of the first p rows of the display panel to not emit light, and controlling the sub-pixels of the last q rows of the display panel to not emit light, where p and q are both positive integers.

[0011] This application provides a display device, the display device including a display panel, the display panel including a plurality of pixels arranged in an array, the pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the color of the light emitted by the fourth sub-pixel is the same as the color of the light emitted by the second sub-pixel; in a first display mode, the first sub-pixel, the second sub-pixel and the third sub-pixel in the pixels located in the i-th row and the j-th column are configured to emit light, and the fourth sub-pixel in the pixels located in the i-th row and the j-th column is configured not to emit light; in a second display mode, the first sub-pixel and the fourth sub-pixel in the pixels located in the i-th row and the j-th column, and the third sub-pixel in the pixels located in the (i+1)-th row and the j-th column are configured to emit light, and the second sub-pixel in the pixels located in the i-th row and the j-th column is configured not to emit light, where i is a positive integer and j is a positive integer.

[0012] In the above-described display device, a plurality of first sub-pixels and a plurality of third sub-pixels are arranged alternately along a first direction, and a plurality of second sub-pixels and a plurality of fourth sub-pixels are arranged alternately along the first direction.

[0013] In the above-described display device, the center line connecting the plurality of second sub-pixels arranged along the second direction is located between the center line connecting the plurality of third sub-pixels arranged along the second direction and the center line connecting the plurality of first sub-pixels arranged along the second direction, and the center line connecting the plurality of fourth sub-pixels arranged along the second direction is located between the center line connecting the plurality of first sub-pixels arranged along the second direction and the center line connecting the plurality of third sub-pixels arranged along the second direction, wherein the second direction intersects the first direction.

[0014] In the above-described display device, the centers of a plurality of third sub-pixels arranged along the second direction are aligned, the centers of a plurality of first sub-pixels arranged along the second direction are aligned, the centers of a plurality of second sub-pixels arranged along the second direction are aligned, the centers of a plurality of fourth sub-pixels arranged along the second direction are aligned, and the second direction intersects the first direction.

[0015] In the above-described display device, the anode of the second light-emitting device of the second sub-pixel and the anode of the fourth light-emitting device of the fourth sub-pixel are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the light-emitting device of the second sub-pixel. The other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line. In the above-described display device, the pixel driving circuit includes an initialization transistor, one of the source and drain of the initialization transistor is electrically connected to an initialization voltage line, the other of the source and drain of the initialization transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor, and the gate of the initialization transistor is electrically connected to an initialization control signal line.

[0016] In the above-described display device, the display panel includes a pixel definition layer and a light-blocking layer. The pixel definition layer includes an opening, and the light-blocking layer is disposed on the light-emitting side of the fourth sub-pixel. From a top-view perspective of the display panel, the light-blocking layer surrounds the opening of the pixel definition layer located at the fourth sub-pixel.

[0017] In the above-described display device, the display panel includes a first planarization layer and a second planarization layer, the second planarization layer being located on the side of the first planarization layer away from the fourth sub-pixel, and the light-blocking layer including a first light-blocking layer and a second light-blocking layer, the first light-blocking layer being located within the first planarization layer or on the side of the first planarization layer close to the fourth sub-pixel or on the side of the first planarization layer away from the fourth sub-pixel, and the second light-blocking layer being located within the second planarization layer or on the side of the second planarization layer close to the fourth sub-pixel or on the side of the second planarization layer away from the fourth sub-pixel.

[0018] The technical solution of this application achieves switching between a first display mode (normal display mode) and a second display mode (privacy display mode) by controlling the light emission state of sub-pixels under different display modes. In the first display mode, the first, second, and third sub-pixels located in the i-th row and j-th column are controlled to emit light, while the fourth sub-pixel located in the i-th row and j-th column remains silent, thus achieving normal wide-viewing-angle full-color display. In the second display mode, the first and fourth sub-pixels located in the i-th row and j-th column, as well as the third sub-pixel located in the (i+1)-th row and j-th column, are controlled to emit light, while the second sub-pixel located in the i-th row and j-th column remains silent. In the second display mode, the fourth sub-pixel combines with the first and third sub-pixels of the adjacent row to emit light, achieving full-color display in privacy mode through this borrowed light emission method. Since the fourth sub-pixel emits the same color light as the second sub-pixel, pixel reuse is achieved by controlling the selective emission of the second and fourth sub-pixels in different display modes. This avoids the problem of reduced pixel density caused by adding extra pixels, thus maintaining the pixel density of the display panel while achieving the privacy function, and avoiding the impact of reduced pixel density on display quality.

[0019] Furthermore, the technical solution of this application connects the anode of the second light-emitting device of the second sub-pixel and the anode of the fourth light-emitting device of the fourth sub-pixel to the same pixel driving circuit. This pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the second light-emitting device of the second sub-pixel. The other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the fourth light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to the first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to the second light-emitting control signal line. The second and fourth sub-pixels share the same driving transistor in the same pixel driving circuit. Selective driving of the second and fourth sub-pixels is achieved simply by adding a first light-emitting control transistor and a second light-emitting control transistor, and controlling the first and second light-emitting control transistors respectively through the first and second light-emitting control signal lines. Without adding additional driving transistors or other transistors, by providing different level signals to the first light-emitting control signal line and the second light-emitting control signal line, the first light-emitting control transistor or the second light-emitting control transistor is selectively turned on, thereby controlling the driving current output by the driving transistor to flow to the second light-emitting device of the second sub-pixel or the fourth light-emitting device of the fourth sub-pixel. This achieves rapid switching between normal display mode and privacy display mode, meeting the user's needs for display effect in different usage scenarios.

[0020] In addition, the technical solution of this application controls the sub-pixels of the first p rows of the display panel to not emit light and controls the sub-pixels of the last q rows of the display panel to not emit light in the second display mode, thereby avoiding abnormal display in the edge area caused by borrowed light emission and improving the display quality in the privacy mode. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the display state of the display device provided in the embodiments of this application in a first display mode.

[0023] Figure 3 This is a schematic diagram of the display state of the display device provided in the second display mode according to an embodiment of the present application.

[0024] Figure 4A cross-sectional view of the portion of the display device provided in the embodiments of this application containing the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit.

[0025] Figure 5 A cross-sectional view of the display device provided in an embodiment of this application, in the portion where the fourth light-emitting unit is located.

[0026] Figure 6 A circuit diagram of the pixel driving circuit of the first light-emitting unit and the third light-emitting unit of the display device provided in the embodiments of this application.

[0027] Figure 7 A circuit diagram of the pixel driving circuit of the second and fourth light-emitting units of the display device provided in the embodiments of this application.

[0028] Figure 8 A timing diagram of a first driving timing of the pixel driving circuits of the second and fourth light-emitting units of the display device provided in the embodiments of this application.

[0029] Figure 9 A timing diagram of a second driving timing for the pixel driving circuits of the second and fourth light-emitting units of the display device provided in the embodiments of this application.

[0030] Figure 10 A timing diagram of a third driving timing for the pixel driving circuits of the second and fourth light-emitting units of the display device provided in the embodiments of this application.

[0031] Figure 11 A timing diagram of a fourth driving timing for the pixel driving circuits of the second and fourth light-emitting units of the display device provided in the embodiments of this application. Detailed Implementation

[0032] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0033] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0034] The technical solutions of different embodiments of this application can be combined with each other.

[0035] The display devices provided in the embodiments of this application may be, for example, organic light-emitting diode (OLED) display devices, mini light-emitting diode (Mini-LED) display devices, or micro light-emitting diode (Micro-LED) display devices. The embodiments of this application are described using organic light-emitting diode display devices as an example.

[0036] like Figure 1 As shown, an embodiment of this application provides a display device, which is an organic light-emitting diode (OLED) display device. The display device includes a display panel (DP), a timing controller (TCON), and a source driver chip (SDIC). The timing controller (TCON) is electrically connected to the source driver chip (SDIC) and the display panel (DP), and the source driver chip (SDIC) is also electrically connected to the display panel (DP). The timing controller (TCON) receives externally input image data and control signals, processes the image data and generates timing control signals, transmits the processed image data to the source driver chip (SDIC), and transmits the timing control signals to both the source driver chip (SDIC) and the display panel (DP). The source driver chip (SDIC) generates a data voltage based on the image data and timing control signals transmitted by the timing controller (TCON) and outputs the data voltage to the data line (DL) of the display panel (DP).

[0037] The display panel (DP) includes a gate driver circuit (GOA), multiple gate lines GL1 / GL2 / GL3 / GL4, multiple light emission control signal lines EM1 / EM2 / EM3, multiple data lines DL, multiple first power lines VDD, multiple second power lines VSS, and multiple pixels (PX). The gate driver circuit (GOA) is electrically connected to the gate lines GL1 / GL2 / GL3 / GL4. Based on the timing control signals provided by the timing controller (TCON), the GOA generates gate scan signals and light emission control signals. The GOA outputs the gate scan signals to the corresponding gate lines GL1 / GL2 / GL3 / GL4 and the light emission control signals to the corresponding light emission control signal lines EM1 / EM2 / EM3. The data lines DL are electrically connected to the source driver chip (SDIC) and receive the data voltage output by the SDIC. The first power line VDD provides a high-level voltage, and the second power line VSS provides a low-level voltage.

[0038] like Figure 2 and Figure 3As shown, the display panel DP includes multiple pixels PX arranged in an array within the display area of ​​the display panel DP. Each pixel PX includes a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. The first sub-pixel SP1 emits red light, the second sub-pixel SP2 emits green light, the third sub-pixel SP3 emits blue light, and the fourth sub-pixel SP4 emits green light or other colors of light. The color of the light emitted by the fourth sub-pixel SP4 is the same as the color of the light emitted by the second sub-pixel SP2. The first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 each include a first light-emitting device EL1, a second light-emitting device EL2, a third light-emitting device EL3, and a fourth light-emitting device EL4, respectively. These light-emitting devices are organic light-emitting diodes (OLEDs).

[0039] Multiple first sub-pixels SP1 and multiple third sub-pixels SP3 are arranged alternately along a first direction, as are multiple second sub-pixels SP2 and multiple fourth sub-pixels SP4 along the first direction. The first direction is a column direction. The second direction is a row direction, and the second direction intersects with the first direction.

[0040] Specifically, along the first direction, the j-th third sub-pixel SP3, the j-th first sub-pixel SP1, the (j+1)-th third sub-pixel SP3, the (j+1)-th first sub-pixel SP1, the (j+2)-th third sub-pixel SP3, and the (j+2)-th first sub-pixel SP1 are arranged sequentially, where j is a positive integer. Along the first direction, the j-th second sub-pixel SP2, the j-th fourth sub-pixel SP4, the (j+1)-th second sub-pixel SP2, the (j+1)-th fourth sub-pixel SP4, the (j+2)-th second sub-pixel SP2, and the (j+2)-th fourth sub-pixel SP4 are arranged sequentially.

[0041] The center line connecting the multiple second sub-pixels SP2 arranged along the second direction is located between the center line connecting the multiple third sub-pixels SP3 arranged along the second direction and the center line connecting the multiple first sub-pixels SP1 arranged along the second direction. The center line connecting the multiple fourth sub-pixels SP4 arranged along the second direction is located between the center line connecting the multiple first sub-pixels SP1 arranged along the second direction and the center line connecting the multiple third sub-pixels SP3 arranged along the second direction.

[0042] Specifically, along the first direction, the center of the j-th second sub-pixel SP2 is located between the center of the j-th third sub-pixel SP3 and the center of the j-th first sub-pixel SP1, and the center of the j-th fourth sub-pixel SP4 is located between the center of the j-th first sub-pixel SP1 and the center of the (j+1)-th third sub-pixel SP3.

[0043] The centers of multiple third sub-pixels SP3 arranged along the second direction are aligned, the centers of multiple first sub-pixels SP1 arranged along the second direction are aligned, the centers of multiple second sub-pixels SP2 arranged along the second direction are aligned, and the centers of multiple fourth sub-pixels SP4 arranged along the second direction are aligned.

[0044] In the embodiments of this application, the first sub-pixel SP1 and the third sub-pixel SP3 are electrically connected to their respective pixel driving circuits, such as... Figure 6 As shown, the anode of the second light-emitting device EL2 of the second sub-pixel SP2 and the anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4 are electrically connected to the same pixel driving circuit, which is as follows: Figure 7 As shown. The pixel driving circuit shared by the second sub-pixel SP2 and the fourth sub-pixel SP4 includes a driving transistor T1, a first light-emitting control transistor T6, and a second light-emitting control transistor T9. One of the source and drain of the driving transistor T1 is electrically connected to one of the source and drain of the first light-emitting control transistor T6, and one of the source and drain of the driving transistor T1 is simultaneously electrically connected to one of the source and drain of the second light-emitting control transistor T9. The other of the source and drain of the first light-emitting control transistor T6 is electrically connected to the anode of the second light-emitting device EL2 of the second sub-pixel SP2, and the other of the source and drain of the second light-emitting control transistor T9 is electrically connected to the anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4. The gate of the first light-emitting control transistor T6 is electrically connected to the first light-emitting control signal line EM2, and the gate of the second light-emitting control transistor T9 is electrically connected to the second light-emitting control signal line EM3.

[0045] Specifically, the gate of driving transistor T1 is electrically connected to node Q, one of the source and drain of driving transistor T1 is electrically connected to node B, and the other of the source and drain of driving transistor T1 is electrically connected to node A. One of the source and drain of the first light-emitting control transistor T6 is electrically connected to node B, and the other of the source and drain of the first light-emitting control transistor T6 is electrically connected to the anode of the second light-emitting device EL2 of the second sub-pixel SP2. One of the source and drain of the second light-emitting control transistor T9 is electrically connected to node B, and the other of the source and drain of the second light-emitting control transistor T9 is electrically connected to the anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4.

[0046] The pixel driving circuit also includes a data writing transistor T2. The gate of the data writing transistor T2 is electrically connected to the first gate line GL1, one of the source and drain of the data writing transistor T2 is electrically connected to the data line DL, and the other of the source and drain of the data writing transistor T2 is electrically connected to node A. The pixel driving circuit also includes a threshold compensation transistor T3. The gate of the threshold compensation transistor T3 is electrically connected to the third gate line GL3, one of the source and drain of the threshold compensation transistor T3 is electrically connected to node B, and the other of the source and drain of the threshold compensation transistor T3 is electrically connected to node Q.

[0047] The pixel driving circuit also includes a first initialization transistor T4, a second initialization transistor T7, and a third initialization transistor T8. The second initialization transistor T7 is an initialization transistor. The gate of the first initialization transistor T4 is electrically connected to a fourth gate line GL4. One of the source and drain of the first initialization transistor T4 is electrically connected to a second initialization voltage line VI2, and the other of the source and drain of the first initialization transistor T4 is electrically connected to node Q. The gate of the second initialization transistor T7 is electrically connected to a second gate line GL2. One of the source and drain of the second initialization transistor T7 is electrically connected to a first initialization voltage line VI1, which is an initialization voltage line. The other of the source and drain of the second initialization transistor T7 is electrically connected to node B. The other of the source and drain of the second initialization transistor T7 is electrically connected to one of the source and drain of the first light-emitting control transistor T6, and the other of the source and drain of the second initialization transistor T7 is simultaneously electrically connected to one of the source and drain of the second light-emitting control transistor T9. The gate of the third initialization transistor T8 is electrically connected to the second gate line GL2. One of the source and drain of the third initialization transistor T8 is electrically connected to the third initialization voltage line VI3, and the other of the source and drain of the third initialization transistor T8 is electrically connected to node A. The second gate line GL2 is an initialization control signal line.

[0048] The pixel driving circuit also includes a first power control transistor T5. The gate of the first power control transistor T5 is electrically connected to the third light emission control signal line EM1, one of the source and drain of the first power control transistor T5 is electrically connected to the first power line VDD, and the other of the source and drain of the first power control transistor T5 is electrically connected to node A.

[0049] The pixel driving circuit also includes a storage capacitor Cst and a boost capacitor Cboost. The first plate of the storage capacitor Cst is electrically connected to the first power supply line VDD, and the second plate of the storage capacitor Cst is electrically connected to node Q. The first plate of the boost capacitor Cboost is electrically connected to the first gate line GL1, and the second plate of the boost capacitor Cboost is electrically connected to node Q. The anode of the second light-emitting device EL2 of the second sub-pixel SP2 is electrically connected to the other of the source and drain of the first light-emitting control transistor T6, and the cathode of the second light-emitting device EL2 of the second sub-pixel SP2 is electrically connected to the second power supply line VSS. The anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4 is electrically connected to the other of the source and drain of the second light-emitting control transistor T9, and the cathode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4 is electrically connected to the second power supply line VSS.

[0050] In the embodiments of this application, the driving transistor T1, data writing transistor T2, first power control transistor T5, first light-emitting control transistor T6, second initialization transistor T7, third initialization transistor T8, and second light-emitting control transistor T9 are P-type transistors. The threshold compensation transistor T3 and the first initialization transistor T4 are N-type transistors. The driving transistor T1 is made of low-temperature polycrystalline oxide semiconductor material, and the other transistors are made of low-temperature polycrystalline silicon semiconductor material.

[0051] In the embodiments of this application, the first sub-pixel SP1 and the third sub-pixel SP3 are electrically connected to their respective pixel driving circuits. The circuit types of these pixel driving circuits include, but are not limited to, 7T1C, 8T2C, 9T2C, 10T2C, and 11T2C circuits. The pixel driving circuit shared by the second sub-pixel SP2 and the fourth sub-pixel SP4 is based on the circuit architecture of the pixel driving circuits of the first sub-pixel SP1 and the third sub-pixel SP3, with the addition of a transistor, such as... Figure 6 and Figure 7 As shown, the pixel driving circuit corresponding to the first sub-pixel SP1 only drives the first light-emitting device EL1 of the first sub-pixel SP1, and the pixel driving circuit corresponding to the third sub-pixel SP3 only drives the third light-emitting device EL3 of the third sub-pixel SP3.

[0052] In embodiments of this application, the display panel DP includes a light-blocking layer. The light-blocking layer is disposed on the light-emitting side of the fourth sub-pixel SP4, such as... Figure 5 As shown, no light-blocking layer is set on the light-emitting side of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, as... Figure 4As shown. The display panel DP includes a pixel definition layer, which includes an opening. From a top-view perspective, a light-blocking layer surrounds the opening in the pixel definition layer located at the fourth sub-pixel SP4. The light-blocking layer blocks large-angle light rays emanating from the fourth sub-pixel SP4, allowing only small-angle light rays emanating from the fourth sub-pixel SP4 to pass through, thus achieving a privacy screen effect.

[0053] like Figure 4 and Figure 5 As shown, the display panel DP includes a substrate SUB, a driving circuit layer DC, a light-emitting device layer EL, a packaging layer TFE, an interlayer insulating layer IL, a third planarization layer OC3, a lens layer MLP, a first planarization layer OC1, a second planarization layer OC2, and a passivation layer PAS. The substrate SUB carries the driving circuit layer DC. The driving circuit layer DC is located on the substrate SUB and includes the transistors in the aforementioned pixel driving circuit. The light-emitting device layer EL includes an anode layer, a pixel definition layer, a light-emitting layer, and a cathode layer, and is located on the driving circuit layer DC. The pixel definition layer includes an opening that defines the light-emitting areas of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4. The packaging layer TFE is located on the cathode layer and encapsulates the first light-emitting devices EL1, EL2, EL3, and EL4 of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4. The interlayer insulating layer IL is located on the packaging layer TFE. The third planarization layer OC3 is located on the interlayer insulating layer IL. The lens layer MLP is located on the third planarization layer OC3. The first planarization layer OC1 is located on the lens layer MLP. The second planarization layer OC2 is located on the first planarization layer OC1. The passivation layer PAS is located on the second planarization layer OC2.

[0054] like Figure 5As shown, the light-blocking layer includes a first light-blocking layer BM1 and a second light-blocking layer BM2. The second planarization layer OC2 is located on the side of the first planarization layer OC1 away from the fourth sub-pixel SP4. The first light-blocking layer BM1 is located within the first planarization layer OC1, or on the side of the first planarization layer OC1 close to the fourth sub-pixel SP4, or on the side of the first planarization layer OC1 away from the fourth sub-pixel SP4. The second light-blocking layer BM2 is located within the second planarization layer OC2, or on the side of the second planarization layer OC2 close to the fourth sub-pixel SP4, or on the side of the second planarization layer OC2 away from the fourth sub-pixel SP4. In one embodiment, the first light-blocking layer BM1 is embedded within the first planarization layer OC1. In another embodiment, the first light-blocking layer BM1 is located between the first planarization layer OC1 and the lens layer MLP, or between the first planarization layer OC1 and the second planarization layer OC2. In one embodiment, the second light-blocking layer BM2 is embedded within the second planarization layer OC2. In another embodiment, the second light-blocking layer BM2 is located between the first planarization layer OC1 and the second planarization layer OC2 or between the second planarization layer OC2 and the passivation layer PAS.

[0055] A first light-blocking layer BM1 and a second light-blocking layer BM2 form a light-blocking member around the light-emitting area of ​​the fourth sub-pixel SP4. This light-blocking member restricts the emission angle of light, ensuring that only small-angle light rays exit from the fourth sub-pixel SP4 and pass through the light-blocking layer, while large-angle light rays are blocked. Of the light rays emitted from the fourth sub-pixel SP4, those with an angle less than a preset angle to the normal direction of the light-emitting surface of the fourth sub-pixel SP4 pass through the light-transmitting area between the first light-blocking layer BM1 and the second light-blocking layer BM2, while those with an angle greater than or equal to the preset angle are blocked by either the first light-blocking layer BM1 or the second light-blocking layer BM2. The preset angle ranges from 30 degrees to 60 degrees. In one embodiment, the preset angle is 45 degrees.

[0056] The first light-blocking layer BM1 and the second light-blocking layer BM2 comprise a metallic material or a black resin material. In one embodiment, the first light-blocking layer BM1 and the second light-blocking layer BM2 comprise chromium or molybdenum. In another embodiment, the first light-blocking layer BM1 and the second light-blocking layer BM2 comprise a black photoresist material. The thickness of the first light-blocking layer BM1 ranges from 0.1 micrometers to 1 micrometer, and the thickness of the second light-blocking layer BM2 ranges from 0.1 micrometers to 1 micrometer. The distance between the first light-blocking layer BM1 and the second light-blocking layer BM2 ranges from 5 micrometers to 20 micrometers.

[0057] The technical solution of this application achieves the switching between a first display mode and a second display mode by controlling the light emission state of sub-pixels under different display modes. The first display mode is a normal display mode, and the second display mode is a privacy screen display mode. In the first display mode, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 in the pixels located in the i-th row and j-th column are configured to emit light, while the fourth sub-pixel SP4 in the pixels located in the i-th row and j-th column is configured not to emit light, where i is a positive integer and j is a positive integer, thus achieving normal wide-viewing-angle full-color display. In the second display mode, the first sub-pixel SP1 and the fourth sub-pixel SP4 in the pixels located in the i-th row and j-th column, as well as the third sub-pixel SP3 in the pixels located in the (i+1)-th row and j-th column, are configured to emit light, while the second sub-pixel SP2 in the pixels located in the i-th row and j-th column is configured not to emit light. In the second display mode, the fourth sub-pixel SP4 combines with the first sub-pixel SP1 and the third sub-pixel SP3 in the adjacent row to emit light, achieving full-color display in privacy screen mode through this borrowed light emission method. Since the fourth sub-pixel SP4 emits the same color light as the second sub-pixel SP2, the selective emission of the second sub-pixel SP2 and the fourth sub-pixel SP4 is controlled in different display modes to achieve pixel reuse. This avoids the problem of reduced pixel density caused by adding extra pixels, thus maintaining the pixel density of the display panel DP while achieving the privacy function, and avoiding the impact of reduced pixel density on display quality.

[0058] The second sub-pixel SP2 and the fourth sub-pixel SP4 share the same driving transistor T1 in the same pixel driving circuit. By adding a first light-emitting control transistor T6 and a second light-emitting control transistor T9, and controlling them respectively through the first light-emitting control signal line EM2 and the second light-emitting control signal line EM3, selective driving of the second sub-pixel SP2 and the fourth sub-pixel SP4 is achieved. Without adding additional driving transistors or other transistors, by providing different level signals to the first light-emitting control signal line EM2 and the second light-emitting control signal line EM3, the first light-emitting control transistor T6 or the second light-emitting control transistor T9 is selectively turned on. This controls the driving current output by the driving transistor T1 to flow to the second light-emitting device EL2 of the second sub-pixel SP2 or the fourth light-emitting device EL4 of the fourth sub-pixel SP4, enabling rapid switching between normal display mode and privacy display mode, meeting the user's display effect needs in different usage scenarios.

[0059] Embodiments of this application also provide a driving method for a display device. This driving method is used to drive the aforementioned display device. The driving method includes a driving process in a first display mode and a driving process in a second display mode.

[0060] like Figure 2 As shown, in the first display mode, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 located in the i-th row and j-th column are controlled to emit light, while the fourth sub-pixel SP4 located in the i-th row and j-th column remains off. Specifically, the j-th third sub-pixel SP3, the j-th first sub-pixel SP1, and the j-th second sub-pixel SP2 emit light simultaneously to achieve full-color display. The j-th fourth sub-pixel SP4 is in the off state and does not emit light. The display panel DP performs normal wide-viewing angle display in the first display mode.

[0061] like Figure 7 As shown, in the first display mode, a second-level signal is provided to the first light-emitting control signal line EM2, and a first-level signal is provided to the second light-emitting control signal line EM3, causing the first light-emitting control transistor T6 to be turned on and the second light-emitting control transistor T9 to be turned off. The first-level signal is a low-level signal, and the second-level signal is a high-level signal. When the first light-emitting control transistor T6 is turned on and the second light-emitting control transistor T9 is turned off, the driving current output by the driving transistor T1 flows through the first light-emitting control transistor T6 to the second light-emitting device EL2 of the second sub-pixel SP2, causing the second sub-pixel SP2 to emit light, while the fourth sub-pixel SP4 does not emit light.

[0062] like Figure 3 As shown, in the second display mode, the first sub-pixel SP1 and the fourth sub-pixel SP4 in the i-th row and j-th column, and the third sub-pixel SP3 in the (i+1)-th row and j-th column, are controlled to emit light, while the second sub-pixel SP2 in the i-th row and j-th column remains off. The fourth sub-pixel SP4, together with the adjacent first sub-pixel SP1 and the third sub-pixel SP3 in the adjacent row, form a pixel unit. Specifically, the j-th fourth sub-pixel SP4, the j-th first sub-pixel SP1, and the (j+1)-th third sub-pixel SP3 emit light simultaneously, achieving full-color display. The j-th second sub-pixel SP2 is in the off state and does not emit light. In the second display mode, the combination of the fourth sub-pixel SP4 with the adjacent first sub-pixel SP1 and the third sub-pixel SP3 in the adjacent row achieves borrowed emission of sub-pixels, maintaining the resolution and color balance of the display panel DP.

[0063] like Figure 7As shown, in the second display mode, a first-level signal is provided to the first light-emitting control signal line EM2, and a second-level signal is provided to the second light-emitting control signal line EM3, causing the first light-emitting control transistor T6 to be turned off and the second light-emitting control transistor T9 to be turned on. When the first light-emitting control transistor T6 is turned off and the second light-emitting control transistor T9 is turned on, the driving current output by the driving transistor T1 flows through the second light-emitting control transistor T9 to the fourth light-emitting device EL4 of the fourth sub-pixel SP4, causing the fourth sub-pixel SP4 to emit light, while the second sub-pixel SP2 does not emit light.

[0064] In the second display mode, only the fourth sub-pixel SP4 has a light-blocking layer. When an observer views the display panel DP from a wide viewing angle, the green light emitted from the fourth sub-pixel SP4 is blocked by the light-blocking layer, but the red light emitted from the first sub-pixel SP1 and the blue light emitted from the third sub-pixel SP3 still propagate to the observer from the wide viewing angle. Since green light accounts for approximately 60% to 70% of the brightness perceived by the human eye, when green light is blocked at a wide viewing angle, the perceived display brightness is reduced by 60% to 70%. Under normal ambient light conditions, the technical solution of this application significantly reduces the display brightness, resulting in a significant decrease in contrast at wide viewing angles, making it difficult for observers at wide viewing angles to clearly identify the displayed content, thus achieving a privacy protection effect. Although red and blue light still propagate to the observer at wide viewing angles, the significant reduction in overall brightness and contrast significantly reduces the readability of the displayed content, thereby achieving the privacy protection function.

[0065] In the second display mode, the sub-pixels in the first p rows of the control display panel DP are kept off-light, and the sub-pixels in the last q rows of the control display panel DP are kept off-light, where p and q are both positive integers. This avoids abnormal display in the edge area caused by borrowed light emission, improving the display quality in the privacy mode. In one embodiment, both p and q are 1. In this case, the third sub-pixel SP3 in the first row of the control display panel DP is kept off-light, and the first sub-pixel SP1 and the fourth sub-pixel SP4 in the last row of the control display panel DP are kept off-light. The third sub-pixel SP3 in the first row cannot combine with the fourth sub-pixel SP4 and the first sub-pixel SP1 in the previous row to emit light because there is no previous row. Similarly, the fourth sub-pixel SP4 and the first sub-pixel SP1 in the last row cannot combine with the third sub-pixel SP3 in the next row to emit light because there is no next row. By controlling these sub-pixels that cannot properly borrow light emission, bright colored lines are avoided.

[0066] The driving cycle for a display device to display one frame of an image includes an initialization phase, a data writing phase, and a light emission phase.

[0067] During the initialization phase, the driving method includes providing a first-level signal to the second gate line GL2, causing the second initialization transistor T7 and the third initialization transistor T8 to turn on. The voltage of the first initialization voltage line VI1 is written to node B via the second initialization transistor T7, and the voltage of node B is initialized. The voltage of the third initialization voltage line VI3 is written to node A via the third initialization transistor T8, and the voltage of node A is initialized. The second gate line GL2 is an initialization control signal line.

[0068] During the initialization phase, a second-level signal is provided to the first light-emitting control signal line EM2, causing the first light-emitting control transistor T6 to conduct. The voltage of the first initialization voltage line VI1 is written to the anode of the second light-emitting device EL2 of the second sub-pixel SP2 via the second initialization transistor T7 and the first light-emitting control transistor T6, thus initializing the voltage of the anode of the second light-emitting device EL2 of the second sub-pixel SP2. A second-level signal is provided to the second light-emitting control signal line EM3, causing the second light-emitting control transistor T9 to conduct. The voltage of the first initialization voltage line VI1 is written to the anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4 via the second initialization transistor T7 and the second light-emitting control transistor T9, thus initializing the voltage of the anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4. The first initialization voltage line VI1 is the initialization voltage line.

[0069] During the data writing phase, a first-level signal is provided to the third light-emitting control signal line EM1, turning on the first power control transistor T5. A high-level signal is provided to the third gate line GL3, turning on the threshold compensation transistor T3. A high-level signal is provided to the fourth gate line GL4, turning on the first initialization transistor T4. The voltage of the second initialization voltage line VI2 is written to node Q via the first initialization transistor T4, initializing the voltage of node Q. Subsequently, a first-level signal is provided to the first gate line GL1, turning on the data writing transistor T2. The voltage of the data line DL is written to node A via the data writing transistor T2. Because the threshold compensation transistor T3 is turned on, one of the gate, source, and drain of the driving transistor T1 is turned on, and the threshold voltage of the driving transistor T1 is compensated to node Q. The boost capacitor Cboost boosts the voltage of node Q during the data writing phase, improving the driving capability of the driving transistor T1.

[0070] During the light-emitting phase, a first-level signal is provided to the third light-emitting control signal line EM1, causing the first power control transistor T5 to turn on. In the first display mode, a second-level signal is provided to the first light-emitting control signal line EM2, causing the first light-emitting control transistor T6 to turn on, and a first-level signal is provided to the second light-emitting control signal line EM3, causing the second light-emitting control transistor T9 to turn off. The voltage of the first power line VDD is applied to the anode of the second light-emitting device EL2 of the second sub-pixel SP2 via the first power control transistor T5, the driving transistor T1, and the first light-emitting control transistor T6, driving the second sub-pixel SP2 to emit light. In the second display mode, a first-level signal is provided to the first light-emitting control signal line EM2, causing the first light-emitting control transistor T6 to turn off, and a second-level signal is provided to the second light-emitting control signal line EM3, causing the second light-emitting control transistor T9 to turn on. The voltage of the first power line VDD is applied to the anode of the fourth light-emitting device EL4 of the fourth sub-pixel SP4 via the first power control transistor T5, the driving transistor T1, and the second light-emitting control transistor T9, driving the fourth sub-pixel SP4 to emit light.

[0071] The embodiments of this application provide four timing control methods.

[0072] like Figure 8As shown, in the first timing control method, within the driving cycle of one frame in the first display mode, the signal of the third light-emitting control signal line EM1 first changes from low to high and remains high. During the period when the signal of the third light-emitting control signal line EM1 remains high, the signal of the second gate line GL2 generates a first low-level pulse. Subsequently, the signal of the third gate line GL3 changes from low to high and remains high. During the period when the signal of the third gate line GL3 remains high, the signal of the fourth gate line GL4 generates a high-level pulse, and after the high-level pulse of the fourth gate line GL4 ends, the signal of the first gate line GL1 generates a low-level pulse. After the low-level pulse of the first gate line GL1 ends, the signal of the third gate line GL3 changes from high to low. After the signal of the third gate line GL3 changes to low, the signal of the second gate line GL2 generates a second low-level pulse. After the second low-level pulse of the second gate line GL2 ends, the signal of the third light-emitting control signal line EM1 changes from high to low. The signal of the first light-emitting control signal line EM2 synchronously transitions to a high level when the signal of the third light-emitting control signal line EM1 transitions to a high level. It also synchronously generates a first low-level pulse when the signal of the second gate line GL2 generates its first low-level pulse, and a second low-level pulse when the signal of the second gate line GL2 generates its second low-level pulse. Furthermore, it synchronously transitions to a low level when the signal of the third light-emitting control signal line EM1 transitions to a low level. During the light-emitting phase of one frame's drive cycle in the first display mode, the signal of the second light-emitting control signal line EM3 is in a high-level state. Additionally, during the initialization phase, i.e., when the signal of the second gate line GL2 is low, the signal of the second light-emitting control signal line EM3 is in a low-level state.

[0073] like Figure 8As shown, in the first timing control method, within the driving cycle of one frame in the second display mode, the signal of the third light-emitting control signal line EM1 first changes from low to high and remains high. During the period when the signal of the third light-emitting control signal line EM1 remains high, the signal of the second gate line GL2 generates a first low-level pulse. Subsequently, the signal of the third gate line GL3 changes from low to high and remains high. During the period when the signal of the third gate line GL3 remains high, the signal of the fourth gate line GL4 generates a high-level pulse, and after the high-level pulse of the fourth gate line GL4 ends, the signal of the first gate line GL1 generates a low-level pulse. After the low-level pulse of the first gate line GL1 ends, the signal of the third gate line GL3 changes from high to low. After the signal of the third gate line GL3 changes to low, the signal of the second gate line GL2 generates a second low-level pulse. After the second low-level pulse of the second gate line GL2 ends, the signal of the third light-emitting control signal line EM1 changes from high to low. The signal of the second light-emitting control signal line EM3 synchronously transitions to a high level when the signal of the third light-emitting control signal line EM1 transitions to a high level. It also synchronously generates a first low-level pulse when the signal of the second gate line GL2 generates its first low-level pulse, and a second low-level pulse when the signal of the second gate line GL2 generates its second low-level pulse. Furthermore, it synchronously transitions to a low level when the signal of the third light-emitting control signal line EM1 transitions to a low level. During the light-emitting phase of a frame's drive cycle in the second display mode, the signal of the first light-emitting control signal line EM2 is in a high-level state. Additionally, during the initialization phase, i.e., when the signal of the second gate line GL2 is low, the signal of the first light-emitting control signal line EM2 is in a low-level state.

[0074] like Figure 9As shown, in the second timing control method, the timing relationship of the signals of the fourth gate line GL4, the third gate line GL3, the first gate line GL1, the second gate line GL2, and the third light-emitting control signal line EM1 is consistent with that of the first timing control method. During the driving cycle of one frame in the first display mode, the signal of the first light-emitting control signal line EM2 synchronously transitions to a high level when the signal of the third light-emitting control signal line EM1 transitions from a low level to a high level. When the signal of the second gate line GL2 generates the first low-level pulse, the signal of the first light-emitting control signal line EM2 synchronously generates a low-level pulse. When the signal of the second gate line GL2 generates the second low-level pulse, the signal of the first light-emitting control signal line EM2 switches to a low level and remains in a low-level state. When the signal of the third light-emitting control signal line EM1 transitions from a high level to a low level, the signal of the first light-emitting control signal line EM2 remains in a low-level state. During the light-emitting phase of one frame in the driving cycle of the first display mode, the signal of the second light-emitting control signal line EM3 is in a high-level state. In addition, during the initialization phase, i.e. when the signal of the second gate line GL2 is at a low level, the signal of the second light emission control signal line EM3 is also at a low level.

[0075] like Figure 9 As shown, in the second timing control method, within the driving cycle of one frame in the second display mode, the signal of the second light-emitting control signal line EM3 synchronously transitions to a high level when the signal of the third light-emitting control signal line EM1 transitions from a low level to a high level. When the signal of the second gate line GL2 generates the first low-level pulse, the signal of the second light-emitting control signal line EM3 synchronously generates a low-level pulse. When the signal of the second gate line GL2 generates the second low-level pulse, the signal of the second light-emitting control signal line EM3 switches to a low level and remains in a low-level state. When the signal of the third light-emitting control signal line EM1 transitions from a high level to a low level, the signal of the second light-emitting control signal line EM3 remains in a low-level state. During the light-emitting phase within the driving cycle of one frame in the second display mode, the signal of the first light-emitting control signal line EM2 is in a high-level state. Furthermore, during the initialization phase, i.e., when the signal of the second gate line GL2 is low, the signal of the first light-emitting control signal line EM2 is in a low-level state.

[0076] like Figure 10As shown, in the third timing control method, the timing relationship of the signals of the fourth gate line GL4, the third gate line GL3, the first gate line GL1, the second gate line GL2, and the third light-emitting control signal line EM1 is consistent with that of the first timing control method. During the driving cycle of one frame in the first display mode, the signal of the first light-emitting control signal line EM2 synchronously changes to a high level when the signal of the third light-emitting control signal line EM1 changes from low to high. When the signal of the second gate line GL2 generates the first low-level pulse, the signal of the first light-emitting control signal line EM2 remains at a high level. When the signal of the second gate line GL2 generates the second low-level pulse, the signal of the first light-emitting control signal line EM2 synchronously generates a low-level pulse. When the signal of the third light-emitting control signal line EM1 changes from high to low, the signal of the first light-emitting control signal line EM2 synchronously changes to a low level. During the light-emitting phase of one frame in the driving cycle of the first display mode, the signal of the second light-emitting control signal line EM3 is at a high level. In addition, during the initialization phase, i.e. when the signal of the second gate line GL2 is at a low level, the signal of the second light emission control signal line EM3 is also at a low level.

[0077] like Figure 10 As shown, in the third timing control method, within the driving cycle of one frame in the second display mode, the signal of the second light-emitting control signal line EM3 synchronously transitions to a high level when the signal of the third light-emitting control signal line EM1 transitions from a low level to a high level. When the signal of the second gate line GL2 generates the first low-level pulse, the signal of the second light-emitting control signal line EM3 remains at a high level. When the signal of the second gate line GL2 generates the second low-level pulse, the signal of the second light-emitting control signal line EM3 synchronously generates a low-level pulse. When the signal of the third light-emitting control signal line EM1 transitions from a high level to a low level, the signal of the second light-emitting control signal line EM3 synchronously transitions to a low level. During the light-emitting phase within the driving cycle of one frame in the second display mode, the signal of the first light-emitting control signal line EM2 is at a high level. Furthermore, during the initialization phase, i.e., when the signal of the second gate line GL2 is at a low level, the signal of the first light-emitting control signal line EM2 is at a low level.

[0078] like Figure 11As shown, in the fourth timing control method, the timing relationship of the signals of the fourth gate line GL4, the third gate line GL3, the first gate line GL1, the second gate line GL2, and the third light-emitting control signal line EM1 is consistent with that of the first timing control method. During the driving cycle of one frame in the first display mode, the signal of the first light-emitting control signal line EM2 synchronously changes to a high level when the signal of the third light-emitting control signal line EM1 changes from low to high. During the period when the signal of the second gate line GL2 generates the first low-level pulse, the signal of the first light-emitting control signal line EM2 remains at a high level. During the period when the signal of the second gate line GL2 generates the second low-level pulse, the signal of the first light-emitting control signal line EM2 switches to a low level and remains at a low level. When the signal of the third light-emitting control signal line EM1 changes from high to low, the signal of the first light-emitting control signal line EM2 remains at a low level. During the light-emitting phase of one frame in the driving cycle of the first display mode, the signal of the second light-emitting control signal line EM3 is at a high level. In addition, during the initialization phase, i.e. when the signal of the second gate line GL2 is at a low level, the signal of the second light emission control signal line EM3 is also at a low level.

[0079] like Figure 11 As shown, in the fourth timing control method, during the driving cycle of one frame in the second display mode, the signal of the second light-emitting control signal line EM3 synchronously transitions to a high level when the signal of the third light-emitting control signal line EM1 transitions from a low level to a high level. During the period when the signal of the second gate line GL2 generates the first low-level pulse, the signal of the second light-emitting control signal line EM3 remains at a high level. During the period when the signal of the second gate line GL2 generates the second low-level pulse, the signal of the second light-emitting control signal line EM3 switches to a low level and remains at a low level. When the signal of the third light-emitting control signal line EM1 transitions from a high level to a low level, the signal of the second light-emitting control signal line EM3 remains at a low level. During the light-emitting phase of one frame in the driving cycle of the second display mode, the signal of the first light-emitting control signal line EM2 is at a high level. Furthermore, during the initialization phase, i.e., when the signal of the second gate line GL2 is at a low level, the signal of the first light-emitting control signal line EM2 is at a low level.

[0080] Through the above four timing control methods, the anodes of the second light-emitting device EL2 of the second sub-pixel SP2 and the fourth light-emitting device EL4 of the fourth sub-pixel SP4 are initialized during the initialization phase, and selective driving of the second sub-pixel SP2 and the fourth sub-pixel SP4 is achieved during the emission phase. The first and second timing control methods initialize the anodes of the second light-emitting device EL2 of the second sub-pixel SP2 and the fourth light-emitting device EL4 of the fourth sub-pixel SP4 simultaneously during the initialization phase. The third and fourth timing control methods initialize only the anodes of the light-emitting devices of the sub-pixels that need to emit light in the current display mode during the initialization phase.

[0081] In the embodiments of this application, through algorithms and gamma settings, in the first display mode, the first light-emitting control signal line EM2 controls the first light-emitting control transistor T6 to be turned on, and the second light-emitting control signal line EM3 controls the second light-emitting control transistor T9 to be turned off. The second sub-pixel SP2 emits light, the fourth sub-pixel SP4 does not emit light, and the first sub-pixel SP1 and the third sub-pixel SP3 adjacent to the second sub-pixel SP2 emit light, achieving normal three-color display. In the second display mode, the first light-emitting control signal line EM2 controls the first light-emitting control transistor T6 to be turned off, and the second light-emitting control signal line EM3 controls the second light-emitting control transistor T9 to be turned on. The second sub-pixel SP2 does not emit light, and the fourth sub-pixel SP4 emits light. Through an algorithm, the first sub-pixel SP1 adjacent to the fourth sub-pixel SP4 and the third sub-pixel SP3 in the adjacent row emit light, achieving three-color display by row. In the second display mode, the sub-pixels in the first p rows of the display panel DP are controlled not to emit light, and the sub-pixels in the last q rows of the display panel DP are controlled not to emit light, avoiding bright colored lines.

[0082] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A driving method for a display device, characterized in that, The display device includes a display panel, the display panel includes a plurality of pixels arranged in an array, the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the color of the light emitted by the fourth sub-pixel is the same as the color of the light emitted by the second sub-pixel; The driving method includes: In the first display mode, the first sub-pixel, the second sub-pixel, and the third sub-pixel located in the i-th row and the j-th column are controlled to emit light, while the fourth sub-pixel located in the i-th row and the j-th column is not emitted light, where i is a positive integer and j is a positive integer; In the second display mode, the first sub-pixel and the fourth sub-pixel in the pixel located in the i-th row and j-th column, as well as the third sub-pixel in the pixel located in the (i+1)-th row and j-th column, are controlled to emit light, while the second sub-pixel in the pixel located in the i-th row and j-th column is not emitting light.

2. The driving method for the display device according to claim 1, characterized in that, The anode of the second light-emitting device of the second sub-pixel and the anode of the fourth light-emitting device of the fourth sub-pixel are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the second light-emitting device of the second sub-pixel. The other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the fourth light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line.

3. The driving method for the display device according to claim 2, characterized in that, The driving method further includes: In the second display mode, a first level signal is provided to the first light-emitting control signal line and a second level signal is provided to the second light-emitting control signal line, so that the first light-emitting control transistor is turned off and the second light-emitting control transistor is turned on.

4. The driving method for the display device according to claim 3, characterized in that, The driving method further includes: In the first display mode, the second level signal is provided to the first light-emitting control signal line, and the first level signal is provided to the second light-emitting control signal line, so that the first light-emitting control transistor is turned on and the second light-emitting control transistor is turned off.

5. The driving method for the display device according to claim 2, characterized in that, The pixel driving circuit includes an initialization transistor, one of the source and drain of the initialization transistor is electrically connected to an initialization voltage line, the other of the source and drain of the initialization transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor, and the gate of the initialization transistor is electrically connected to an initialization control signal line. The driving cycle for the display device to display one frame of an image includes an initialization phase, and in the initialization phase, the driving method further includes: A first-level signal is provided to the initialization control signal line, causing the initialization transistor to turn on; A second-level signal is provided to the first light-emitting control signal line, causing the first light-emitting control transistor to turn on, and the voltage of the initialization voltage line is written into the anode of the second light-emitting device of the second sub-pixel; and The second level signal is provided to the second light emission control signal line, causing the second light emission control transistor to be turned on, and the voltage of the initialization voltage line is written into the anode of the fourth light emission device of the fourth sub-pixel.

6. The driving method for the display device according to claim 1, characterized in that, The driving method further includes: In the second display mode, the sub-pixels in the first p rows of the display panel are controlled not to emit light, and the sub-pixels in the last q rows of the display panel are controlled not to emit light, where p and q are both positive integers.

7. A display device, characterized in that, The display device includes a display panel, the display panel includes a plurality of pixels arranged in an array, the pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the color of the light emitted by the fourth sub-pixel is the same as the color of the light emitted by the second sub-pixel; In the first display mode, the first sub-pixel, the second sub-pixel, and the third sub-pixel in the pixel located in the i-th row and j-th column are configured to emit light, and the fourth sub-pixel in the pixel located in the i-th row and j-th column is configured to not emit light. In the second display mode, the first sub-pixel and the fourth sub-pixel in the pixel located in the i-th row and j-th column, as well as the third sub-pixel in the pixel located in the (i+1)-th row and j-th column, are configured to emit light, and the second sub-pixel in the pixel located in the i-th row and j-th column is configured to not emit light, where i is a positive integer and j is a positive integer.

8. The display device according to claim 7, characterized in that, A plurality of first sub-pixels and a plurality of third sub-pixels are arranged alternately along a first direction, and a plurality of second sub-pixels and a plurality of fourth sub-pixels are arranged alternately along the first direction.

9. The display device according to claim 8, characterized in that, The center line connecting the plurality of second sub-pixels arranged along the second direction is located between the center line connecting the plurality of third sub-pixels arranged along the second direction and the center line connecting the plurality of first sub-pixels arranged along the second direction. The center line connecting the plurality of fourth sub-pixels arranged along the second direction is located between the center line connecting the plurality of first sub-pixels arranged along the second direction and the center line connecting the plurality of third sub-pixels arranged along the second direction. The second direction intersects the first direction.

10. The display device according to claim 8, characterized in that, The centers of the plurality of third sub-pixels arranged along the second direction are aligned, the centers of the plurality of first sub-pixels arranged along the second direction are aligned, the centers of the plurality of second sub-pixels arranged along the second direction are aligned, and the centers of the plurality of fourth sub-pixels arranged along the second direction are aligned, wherein the second direction intersects the first direction.

11. The display device according to claim 7, characterized in that, The anode of the second light-emitting device of the second sub-pixel and the anode of the fourth light-emitting device of the fourth sub-pixel are electrically connected to the same pixel driving circuit. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor. One of the source and drain of the driving transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor. The other of the source and drain of the first light-emitting control transistor is electrically connected to the anode of the light-emitting device of the second sub-pixel. The other of the source and drain of the second light-emitting control transistor is electrically connected to the anode of the light-emitting device of the fourth sub-pixel. The gate of the first light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the second light-emitting control transistor is electrically connected to a second light-emitting control signal line.

12. The display device according to claim 11, characterized in that, The pixel driving circuit includes an initialization transistor, one of the source and drain of the initialization transistor is electrically connected to an initialization voltage line, the other of the source and drain of the initialization transistor is electrically connected to one of the source and drain of the first light-emitting control transistor and one of the source and drain of the second light-emitting control transistor, and the gate of the initialization transistor is electrically connected to an initialization control signal line.

13. The display device according to claim 7, characterized in that, The display panel includes a pixel definition layer and a light-blocking layer. The pixel definition layer includes an opening, and the light-blocking layer is disposed on the light-emitting side of the fourth sub-pixel. From a top-view perspective of the display panel, the light-blocking layer surrounds the opening of the pixel definition layer located at the fourth sub-pixel.

14. The display device according to claim 13, characterized in that, The display panel includes a first planarization layer and a second planarization layer. The second planarization layer is located on the side of the first planarization layer away from the fourth sub-pixel. The light-blocking layer includes a first light-blocking layer and a second light-blocking layer. The first light-blocking layer is located within the first planarization layer, or on the side of the first planarization layer close to the fourth sub-pixel, or on the side of the first planarization layer away from the fourth sub-pixel. The second light-blocking layer is located within the second planarization layer, or on the side of the second planarization layer close to the fourth sub-pixel, or on the side of the second planarization layer away from the fourth sub-pixel.

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