Display panel, driving method thereof, and display device

Abstract

Embodiments of the present disclosure provide a display panel and a driving method thereof, and a display device, which relate to the technical field of display, and are used for reducing the energy consumption and cost of the display panel, improving the integration of the display panel, and improving the calculation efficiency of the neural network. The display panel has a display area and a peripheral area surrounding the display area. The display panel includes a plurality of sub-pixels, a neural network, and a control circuit. The plurality of sub-pixels are arranged in the display area, and the plurality of sub-pixels are arranged in an array. The neural network is arranged in the display area, and includes a plurality of neurons arranged in an array. The neurons are configured to store weights, perform weighted calculation, and output a calculation current. The control circuit is arranged in the peripheral area and is electrically connected to the neural network. The control circuit is configured to transmit an input signal to the neural network and perform summation operation on the calculation current. The display panel is used for displaying an image.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the development of display technology, display devices with intelligent sensing capabilities have seen significant advancements. Intelligent sensing refers to the ability of a display device to perform actions including, but not limited to, environmental sensing, content sensing, and user eye / posture sensing, and to adjust its display status based on this information. For example, a display device can sense the intensity of ambient light and adjust its brightness accordingly. Improving the integration of intelligent sensing capabilities in display devices is a pressing technical challenge that needs to be addressed. Summary of the Invention

[0003] The purpose of the embodiments of this disclosure is to provide a display panel and display device for reducing the energy consumption and cost of the display panel, improving the integration of the display panel, and improving the computational efficiency of the neural network.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: On one hand, a display panel is provided. The display panel has a display area and a peripheral area surrounding the display area. The display panel includes a plurality of sub-pixels, a neural network, and a control circuit. The plurality of sub-pixels are disposed in the display area and arranged in an array. The neural network is disposed in the display area and includes a plurality of neurons arranged in an array, the neurons being configured to perform weighted calculations and output a calculated current. The control circuit is disposed in the peripheral area and electrically connected to the neural network, the control circuit being configured to: transmit an input signal to the neural network and perform a summation operation on the calculated current.

[0005] The display panel provided in the embodiments of this disclosure includes a neural network and a control circuit. At least a portion of the neural network is disposed within the display area. The neural network may include multiple neurons arranged in an array. The neurons are configured to perform weighted calculations and output calculated currents. The control circuit is disposed in the peripheral area and can be electrically connected to both the neural network and a sensor. The control circuit is configured to transmit an input signal to the neural network based on parameter information detected by the sensor. The neurons of the neural network can store weights and use the input signal from the control circuit to calculate a current, which is then transmitted to the control circuit. The control circuit can sum the currents output by the multiple neurons and adjust the display state of the display panel based on the result of the summation. In the embodiments of this disclosure, a large number of neurons of the neural network are integrated within the display area of ​​the display panel. This eliminates the need for additional computing chips or reduces the computational power requirements of external chips, thereby reducing the energy consumption and cost of the display panel and improving its integration.

[0006] In some embodiments, the neuron includes a floating-gate transistor, a weight loading subcircuit, a first energy storage subcircuit, an input subcircuit, a second energy storage subcircuit, and a switching subcircuit. The control gate of the floating-gate transistor is electrically connected to a first node, the first terminal of the floating-gate transistor is electrically connected to a first voltage signal terminal, and the second terminal of the floating-gate transistor is electrically connected to a second node. The weight loading subcircuit is electrically connected to a first control signal terminal, a second voltage signal terminal, and the first node. The weight loading subcircuit is configured to transmit a second voltage signal from the second voltage signal terminal to the first node under the control of a control signal from the first control signal terminal. The first energy storage subcircuit is electrically connected to a first reference voltage signal terminal and the first node and is configured to maintain the voltage of the first node. The input subcircuit is electrically connected to the first control signal terminal, an input signal terminal, and a third node. The input subcircuit is configured to transmit an input signal from the input signal terminal to the third node under the control of the control signal. The second energy storage subcircuit is electrically connected to a second reference voltage signal terminal and the third node and is configured to maintain the voltage of the third node. The switching sub-circuit is electrically connected to the second node, the third node, and the output signal terminal, and is configured to electrically connect the second node to the output signal terminal under the control of the third node.

[0007] In some embodiments, the floating gate of the floating gate transistor is configured to store a weight W, wherein the weight W may satisfy: (1) (2) Where k is the normalized weighting coefficient, μ is the channel carrier mobility of the floating gate transistor, and Cox is the gate oxide capacitance per unit area. Vw is the ratio of channel width to length; Vth1 is the voltage of the control gate of the floating gate transistor; ΔVth is the threshold voltage when the floating gate of the floating gate transistor does not store charge; ΔVth is the threshold voltage offset corresponding to the charge stored in the floating gate of the floating gate transistor; Qfg is the charge stored in the floating gate of the floating gate transistor; and Cfg is the equivalent total capacitance of the floating gate of the floating gate transistor.

[0008] In some embodiments, the weighting subcircuit includes a first transistor. The control electrode of the first transistor is electrically connected to a first control signal terminal, a first terminal of the first transistor is electrically connected to a second voltage signal terminal, and a second terminal of the first transistor is electrically connected to the first node. The first energy storage subcircuit includes a first capacitor, one plate of the first capacitor is electrically connected to the first node, and the other plate is electrically connected to the first reference voltage signal terminal. The input subcircuit includes a second transistor, the control electrode of the second transistor is electrically connected to the first control signal terminal, a first terminal of the second transistor is electrically connected to the input signal terminal, and a second terminal of the second transistor is electrically connected to a third node. The second energy storage subcircuit includes a second capacitor, one plate of the second capacitor is electrically connected to the third node, and the other plate is electrically connected to a second reference voltage signal terminal. The switching subcircuit includes a third transistor, the control electrode of the third transistor is electrically connected to the third node, a first terminal of the third transistor is electrically connected to the second node, and a second terminal of the third transistor is electrically connected to the output terminal.

[0009] In some embodiments, the neural network further includes multiple bit lines, multiple word lines, and multiple input signal lines. The multiple bit lines are arranged along the row direction and extend along the column direction. One bit line is electrically connected to the output terminal of a column of neurons, and the bit line is electrically connected to the control circuit. The control circuit is further configured to sum the currents on the bit lines. The multiple word lines are arranged along the column direction and extend along the row direction. One word line is electrically connected to a row of neurons, and the word line is configured as the first control signal terminal. The multiple input signal lines are arranged along the row direction and extend along the column direction. One bit line is electrically connected to the input signal terminal of a column of neurons. The row direction is the row direction of the multiple sub-pixels, the column direction is the column direction of the multiple sub-pixels, and the row direction intersects the column direction.

[0010] In some embodiments, the sub-pixel includes a pixel circuit and a light-emitting device. The pixel circuit includes a fourth transistor, a fifth transistor, and a third capacitor. The control electrode of the fourth transistor is electrically connected to a scan signal line, the first electrode of the fourth transistor is electrically connected to a data signal line, and the second electrode of the fourth transistor is electrically connected to a fourth node. The control electrode of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to a third voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the anode of the light-emitting device. One plate of the third capacitor is electrically connected to the first node, and the other plate is electrically connected to a third reference voltage signal terminal.

[0011] In some embodiments, along the row direction, at least one sub-pixel is included between two adjacent neurons.

[0012] On the other hand, a driving method for a display panel is provided, used to drive the display panel described in any of the above embodiments. A frame includes a display phase and a blanking phase. The driving method includes: in the display phase, multiple sub-pixels display a pattern; in the blanking phase, a control circuit drives a neural network to perform calculations.

[0013] In some embodiments, the blanking phase includes a loading phase, a writing phase, and a computation phase, and the neuron includes a floating-gate transistor, a weight loading sub-circuit, an input sub-circuit, and a switching sub-circuit. The driving method further includes: in the loading phase, a first control signal terminal controls the weight loading sub-circuit to transmit a second voltage signal from a second voltage signal terminal to a first node; in the writing phase, the first control signal terminal controls the input sub-circuit to transmit an input signal from an input signal terminal to a third node; in the computation phase, the switching sub-circuit, under the control of the third node and the second node, generates a computation current and transmits the computation current to an output signal terminal; the control circuit performs calculations on the computation current output by a series of neurons.

[0014] In another aspect, a display device is provided, comprising a display panel and a sensor as described in any of the above embodiments. The sensor is electrically connected to a control circuit of the display panel, and the sensor is configured to sense predetermined parameters and transmit sensing signals to the control circuit.

[0015] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0017] Figure 1 This is a structural diagram of a display device according to some embodiments; Figure 2 This is a structural diagram of a display panel according to some embodiments; Figure 3 This is an equivalent circuit diagram of a pixel circuit according to some embodiments; Figure 4 This is another structural diagram of a display panel according to some embodiments; Figure 5 This is a structural diagram of a floating gate transistor according to some embodiments; Figure 6 Here is a block diagram of the circuit structure of a neuron according to some embodiments; Figure 7 Here is an equivalent circuit diagram of a neuron according to some embodiments; Figure 8 This is a control timing diagram of a display panel according to some embodiments. Detailed Implementation

[0018] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0019] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplarily," or "for example" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0020] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0021] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0022] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0023] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0024] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0025] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0026] In the embodiments of this disclosure, the transistor used may be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. In the embodiments of this disclosure, the transistor is described as a thin film transistor.

[0027] In the embodiments of this disclosure, the control electrode of each thin-film transistor is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally indistinguishable. That is, the first electrode and the second electrode of the thin-film transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source. The circuits provided in the embodiments of this disclosure will be described below using P-type transistors as an example.

[0028] In embodiments of this disclosure, the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes. Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.

[0029] In the embodiments of this disclosure, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0030] In embodiments of this disclosure, "operating voltage" refers to the voltage that enables a transistor to conduct; correspondingly, "non-operating voltage" refers to the voltage that prevents a transistor from conducting. In embodiments of this disclosure, where all transistors are P-type transistors, "low voltage" refers to the voltage that enables a P-type transistor to conduct; correspondingly, "high voltage" refers to the voltage that prevents a P-type transistor from conducting. In other words, operating voltage can be understood as low voltage, and non-operating voltage can be understood as high voltage.

[0031] See Figure 1 Some embodiments of this disclosure provide a display device 1000, which can be any device that displays text or images, whether in motion (e.g., video) or still (e.g., image).

[0032] For example, the aforementioned display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), clock, global positioning system (GPS) receiver / navigator, vehicle display, flight display, wearable device, virtual reality (VR) device, augmented reality (AR) device, sight, rangefinder, sign, electronic billboard, and shopping mall display.

[0033] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device, etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The following uses a rectangular and flat OLED display device as an example to illustrate some embodiments of this disclosure; however, the embodiments of this disclosure are not limited to this, and any other display device can be considered, as long as the same technical concept is applied.

[0034] In some embodiments, see Figure 2 and Figure 3 The display device 1000 may include a display panel 100, which may include a display area AA and a peripheral area BB disposed on at least one side of the display area AA. For example, the peripheral area BB may be disposed around the display area AA. Here, the display area AA refers to the area in the display panel 100 used for displaying images, and the peripheral area BB may also be called a non-display area, which refers to the area in the display panel 100 outside the display area AA.

[0035] The display panel 100 may include a plurality of sub-pixels P arranged in an array, and the plurality of sub-pixels P are disposed within the display area AA. Sub-pixel P refers to the smallest light-emitting unit in the display panel 100. Sub-pixel P includes a pixel circuit 10 and a light-emitting device EL. The pixel circuit 10 is electrically connected to the light-emitting device EL and is configured to transmit a driving current to the light-emitting device EL to drive the light-emitting device EL to emit light.

[0036] Multiple sub-pixels P, comprising multiple pixel circuits 10, can be arranged in multiple rows and columns. Each row of pixel circuits 10 includes multiple pixel circuits 10 arranged along the row direction X, and the multiple rows of pixel circuits 10 are arranged along the column direction Y. Each column of pixel circuits 10 includes multiple pixel circuits 10 arranged along the column direction Y, and the multiple columns of pixel circuits 10 are arranged along the row direction X. The row direction X and the column direction Y intersect; for example, the row direction X and the column direction Y are perpendicular to each other.

[0037] The display panel 100 also includes a gate driver on array (GOA) 21 and a source driver chip 22 disposed in the peripheral area BB, as well as multiple scan signal lines GL and multiple data signal lines DL located simultaneously in the display area AA and the peripheral area BB. A row of pixel circuits 10 can be electrically connected to the gate driver circuit 21 through at least one scan signal line GL, and a column of pixel circuits 10 can be electrically connected to the source driver chip 22 through one data signal line DL. Of course, the structure of the display panel is not limited to this, and the embodiments disclosed herein will not be listed one by one.

[0038] Pixel circuit 10 may include multiple thin-film transistors (TFTs) and at least one capacitor Cst. Exemplarily, pixel circuit 10 may be a "2T1C" circuit, a "3T1C" circuit, a "5T1C" circuit, a "7T1C" circuit, or an "8T2C" circuit, etc., where "T" refers to a TFT, and the number before "T" indicates the number of TFTs; "C" refers to a capacitor Cst, and the number before "C" indicates the number of capacitors Cst. The embodiments of this disclosure do not specifically limit the specific structure of pixel circuit 10. Below, only a "2T1C" circuit is used as an example to exemplify the embodiments of this disclosure.

[0039] like Figure 3 As shown, when the pixel circuit 10 is a "2T1C" circuit, the pixel circuit 10 may include a fourth transistor T4, a fifth transistor T5, and a third capacitor C3. The control electrode of the fourth transistor T4 is electrically connected to the scan signal line GL, the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4. The control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the third voltage signal terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the anode of the light-emitting device EL. One plate of the third capacitor C3 is electrically connected to the fourth node N4, and the other plate is electrically connected to the third reference voltage signal terminal Vref3.

[0040] The display panel may also include multiple third reference voltage signal lines and multiple third voltage signal lines. The third reference voltage signal lines are electrically connected to the pixel circuit and are configured as third reference voltage signal terminals electrically connected to the pixel circuit.

[0041] Multiple third reference voltage signal lines can extend along the row direction and be spaced apart along the column direction; alternatively, multiple third reference voltage signal lines can extend along the column direction and be spaced apart along the row direction; alternatively, a portion of the third reference voltage signal lines extend along the row direction and are spaced apart along the column direction, while another portion extends along the column direction and is spaced apart along the row direction. The third reference voltage signal lines extending along the row direction and the third reference voltage signal lines extending along the column direction are located in different film layers and are electrically connected to each other, so that the multiple third reference voltage signal lines are electrically connected to form a mesh structure, thereby reducing the overall resistance of the third reference voltage signal lines.

[0042] Multiple third voltage signal lines can extend along the row direction and be spaced apart along the column direction; alternatively, multiple third voltage signal lines can extend along the column direction and be spaced apart along the row direction; or, a portion of the third voltage signal lines extend along the row direction and are spaced apart along the column direction, while another portion extends along the column direction and is spaced apart along the row direction. The third voltage signal lines extending along the row direction and those extending along the column direction are located in different film layers and are electrically connected to each other. In this way, the multiple third voltage signal lines are electrically connected to form a mesh structure, which can reduce the overall resistance of the third voltage signal lines.

[0043] For example, a display frame cycle of the display panel 100 may include a display phase and a blanking phase. The display phase may include a data writing phase and a light-emitting phase. During the data writing phase, the scan signal line GL can transmit an operating voltage (low level), and the fourth transistor T4 is turned on under the control of the scan signal line GL. The fourth transistor T4 transmits the data signal transmitted on the data signal line DL to the fourth node N4. During the light-emitting phase, the scan signal line GL transmits a non-operating voltage, and the fourth transistor T4 is turned off under the control of the scan signal line GL. At this time, the third capacitor Cst can maintain the voltage of the fourth node N4, and the fifth transistor T5 can generate a driving current under the control of the voltage difference between the fourth node N4 and the third voltage signal line VDD to drive the light-emitting device EL to emit light. When the pixel circuit 10 adopts a 2T1C circuit, it helps to reduce the overall area occupied by the pixel circuit 10, which is beneficial to improving the pixel density of the display panel and also facilitates the integration of the neural network into the display area of ​​the display panel (see below).

[0044] In some embodiments, the display device 1000 may be a display device with intelligent sensing capabilities. In this case, the display device 1000 may further include sensors capable of detecting / sensing predetermined parameter information. Exemplarily, the sensors may include, but are not limited to, environmental adaptive sensors, viewer eye state sensing sensors, gesture and posture sensing sensors, biometric identification sensors, and display panel self-state monitoring sensors. Environmental adaptive sensors include, but are not limited to, ambient light brightness sensors (which can be used to sense the brightness of ambient light) and infrared proximity sensors (which can be used to sense the distance between the measured object and the screen). Viewer eye state perception sensors include, but are not limited to, near-infrared IR cameras (which can be used for gaze tracking and perception) and near-infrared eye-tracking cameras (which can be used to sense the degree of eye fatigue). Gesture and posture perception sensors can include, but are not limited to, infrared image sensors (which can be used for spatial gesture recognition) and six-axis inertial measurement units (IMUs) (which can be used for sensing the posture and tilt angle of the display panel). Biometric identification sensors include, but are not limited to, infrared cameras (which can be used for face recognition and perception) and optical fingerprint sensors / ultrasonic fingerprint sensors (which can be used for fingerprint recognition and perception). Display panel self-state monitoring sensors include, but are not limited to, on-chip temperature sensors built into the driver IC (which can be used for screen temperature sensing), thin-film strain sensors (which can be used for flexible screen bending deformation sensing), and built-in photoelectric detection sensors (which can be used for panel local defect sensing).

[0045] In related technologies, display devices with intelligent sensing capabilities, in addition to the aforementioned sensors, may also include a storage chip and a computing chip. The storage chip is configured to store parameters and weights required for intelligent computing, while the computing chip can be used to set up a neural network and perform calculations on the data sensed by the sensors. During intelligent sensing, the computing chip can retrieve the parameters and weights stored in the storage chip, then perform calculations and analysis on the information detected by the sensors, and adjust the display state of the display panel based on the calculation and analysis results. Using external storage and computing chips requires significant data migration (such as weight retrieval), leads to higher power consumption and cost for the display device, and hinders the improvement of the display device's integration level.

[0046] See Figure 4To address at least one of the aforementioned technical problems, the display panel provided in the embodiments of this disclosure further includes a neural network 30 and a control circuit 40. At least a portion of the neural network 30 is disposed within the display area AA. The neural network 30 may include multiple neurons 31 arranged in an array. The neurons 31 are configured to store weights, perform weighted calculations, and output calculated current. The control circuit 40 is disposed in the peripheral area BB. The control circuit 40 can be electrically connected to the neural network 30 and a sensor (not shown in the figure), respectively. The control circuit 40 is configured to transmit an input signal to the neural network based on parameter information detected by the sensor. The weights stored in the neurons 31 of the neural network 30 and the input signal input to the control circuit 40 are used to calculate the current, which is then transmitted to the control circuit 40. The control circuit 40 can sum the currents output by the multiple neurons 31 and adjust the display state of the display panel based on the result of the summation operation. In the embodiments of this disclosure, a large number of neurons 31 of the neural network 30 are integrated in the display area AA of the display panel 100. This eliminates the need for additional computing chips, or reduces the computational power requirements of external chips, thereby reducing the energy consumption and cost of the display panel 100 and improving its integration level. The neurons 31 of the neural network 30 can be used to store weights, thereby reducing the use of external storage chips, further reducing the energy consumption and cost of the display panel 100, and improving its integration level. Furthermore, storing weights directly in the neurons 31 reduces data movement, decreases the number of data migrations, and improves the computational efficiency of the neural network 30.

[0047] For example, the arrangement density of neurons 31 in the display area can be the same as the arrangement density of pixel circuits, that is, one neuron 31 is set for each pixel circuit. For example, along the row direction X, there is one neuron 31 between two adjacent pixel circuits. This helps to increase the total number of neurons 31.

[0048] For example, the arrangement density of neurons 31 in the display area may not be equal to the arrangement density of pixel circuits. For instance, one neuron 31 may be set for each multiple pixel circuits, and multiple pixel circuits may be set between each two neurons 31 along the row direction X. This is beneficial to increase the arrangement density of pixel circuits, thereby increasing the pixel density of the display panel.

[0049] Exemplarily, the control circuit 40 may include, but is not limited to, at least one of an input signal circuit, an output signal circuit, an array switching circuit, a preprocessing circuit, a post-processing circuit, and a timing and control circuit. The input signal circuit may include, for example, at least one of a digital-to-analog converter circuit, an input buffer (voltage follower), a word line driver circuit, a signal modulation circuit, and a sample-and-hold circuit. The output signal circuit is electrically connected to the neural network and is configured to receive the signal output by the neural network. Exemplarily, the output signal circuit includes, but is not limited to, at least one of a transimpedance amplifier (current-to-voltage conversion circuit), an analog-to-digital converter, a column readout buffer amplifier, a sampling circuit / readout sample-and-hold circuit, and a current mirroring circuit. The array switching circuit may include, but is not limited to, bit line switching transistors and row gating switch arrays. The preprocessing circuit may include the circuit structure between the sensor signal and the neural network input. The post-processing circuit may include, but is not limited to, circuits for further processing after the neural network output. The timing and control circuit may include, but is not limited to, a clock control circuit and a bias voltage generation circuit. In embodiments of this disclosure, the specific structure and function of the control circuit 40 are not listed one by one. See also... Figures 5-7 In some embodiments, neuron 31 may include floating-gate transistor 32, the floating gate Fg of which is configured to store weight W, the weight W satisfying: (1) (2) In equation (1) above, k is the normalized weighting coefficient, μ is the channel carrier mobility of the floating gate transistor, and Cox is the gate oxide capacitance per unit area. Vw is the ratio of the channel width to the length of the floating-gate transistor; Vth1 is the threshold voltage of the floating-gate transistor when the floating gate does not store charge; ΔVth is the threshold voltage offset corresponding to the charge stored in the floating gate of the floating-gate transistor; Qfg is the amount of charge stored in the floating gate of the floating-gate transistor; and Cfg is the equivalent total capacitance of the floating gate of the floating-gate transistor. Therefore, the weight of charge stored in different floating-gate transistors 32 can be adjusted by controlling the amount of charge Qfg stored in the floating gate of the floating-gate transistor 32.

[0050] For example, in the at least two neurons 31 included in the neural network 30, at least one of the above parameters may not be equal, or, in the at least two neurons 31 included in the neural network 30, all the above parameters except for the amount of charge Qfg stored in the floating gate and the voltage Vw of the control gate are equal.

[0051] For example, such as Figure 5As shown, the floating gate transistor 32 may include a semiconductor layer 34, a tunneling oxide layer 35, a floating gate Fg, a control oxide layer 36, and a control gate Cg sequentially disposed along a direction away from the substrate 33. Furthermore, the floating gate transistor 32 may also include a first electrode 37 and a second electrode 38 electrically connected to the semiconductor layer 34. The floating gate transistor 32 can form a non-volatile memory structure, ensuring that the charge written to the floating gate Fg can be retained for a long time (e.g., more than 10 years), reducing the loading and refreshing of weights and lowering the power consumption of the neural network.

[0052] When the floating gate transistor 32 operates in the saturation region, the current Ic of the floating gate transistor 32 satisfies: (3) (4) Assuming the threshold voltage offset corresponding to the floating gate charge Qfg of the floating gate transistor 32 is ΔVth, the transconductance gm of the floating gate transistor 32 can satisfy: (5) The weight W of the floating gate transistor 32 is k×gm (6). Substituting the above equation (5) into equation (6) yields the above equation (1).

[0053] Furthermore, based on equations (1) and (2), the weight W value stored in the floating gate transistor 32 can be adjusted by adjusting ΔVth, that is, the weight W value stored in the floating gate transistor 32 can be adjusted by adjusting the floating gate charge Qfg of the floating gate transistor 32.

[0054] In other words, in the embodiments of this disclosure, by setting the floating gate transistor 32, the neuron 31 can achieve the purpose of storing weight W, and by adjusting the floating gate charge Qfg of the floating gate transistor 32, the purpose of storing different weight values ​​in different neurons 31 can be achieved.

[0055] For example, such as Figure 5 As shown, the floating gate transistor 32 may include a semiconductor layer 34, a tunneling oxide layer 35, a floating gate Fg, a control oxide layer 36, and a control gate Cg sequentially disposed along a direction away from the substrate 33. Furthermore, the floating gate transistor 32 may also include a first electrode 37 and a second electrode 38 electrically connected to the semiconductor layer 34. The floating gate transistor 32 can form a non-volatile memory structure, ensuring that the charge written to the floating gate Fg can be retained for a long time (e.g., more than 10 years).

[0056] See Figure 6 and Figure 7In some embodiments, the control gate Cg of the floating gate transistor 32 is electrically connected to the first node N1, the first terminal (e.g., the source) of the floating gate transistor 32 is electrically connected to the first voltage signal terminal Vss, and the second terminal (e.g., the drain) of the floating gate transistor 32 is electrically connected to the second node N2.

[0057] Optionally, neuron 31 may also include a weight loading sub-circuit 41, a first energy storage sub-circuit 42, an input sub-circuit 43, a second energy storage sub-circuit 44, and a switching sub-circuit 45.

[0058] The weight loading sub-circuit 41 is electrically connected to the first control signal terminal EN, the second voltage signal terminal Vw, and the first node N1. The weight loading sub-circuit 41 is configured to transmit the second voltage signal from the second voltage signal terminal Vw to the first node N1 under the control of the control signal from the first control signal terminal EN. The first voltage signal terminal Vss can be configured to transmit a constant low voltage signal, or the first voltage signal terminal Vss can also be a ground wire.

[0059] The weight loading sub-circuit 41 may include a first transistor T1. The control terminal of the first transistor T1 is electrically connected to the first control signal terminal EN, the first terminal of the first transistor T1 is electrically connected to the second voltage signal terminal Vw, and the second terminal of the first transistor T1 is electrically connected to the first node N1. For example, when a control signal is transmitted at the first control signal terminal EN, the first transistor T1 is turned on, and the second voltage at the second voltage signal terminal Vw is transmitted to the first node N1 through the first transistor T1.

[0060] The first energy storage sub-circuit 42 is electrically connected to the first reference voltage signal terminal Vref1 and the first node N1, and the first energy storage sub-circuit 42 is configured to maintain the voltage of the first node N1.

[0061] The aforementioned first energy storage sub-circuit 42 may include a first capacitor C1, one plate of which is electrically connected to the first node N1, and the other plate is electrically connected to the first reference voltage signal terminal Vref1. For example, when the first transistor T1 is in the off state, the first capacitor C1 can maintain the voltage of the first node N1 to maintain the conduction state of the floating gate transistor 32.

[0062] The input sub-circuit 43 is electrically connected to the first control signal terminal EN, the input signal terminal V-in, and the third node N3. The input sub-circuit 43 is configured to transmit the input signal Vin from the input signal terminal V-in to the third node N3 under the control of the control signal EN.

[0063] The input sub-circuit 43 may include a second transistor T2. The control electrode of the second transistor T2 is electrically connected to the first control signal terminal EN, the first electrode of the second transistor T2 is electrically connected to the input signal terminal V-in, and the second electrode of the second transistor T2 is electrically connected to the third node N3. For example, when a control signal is transmitted at the first control signal terminal EN, the second transistor T2 is turned on, and the input signal Vin at the input signal terminal V-in is transmitted to the third node N3 through the second transistor T2.

[0064] The second energy storage sub-circuit 44 is electrically connected to the second reference voltage signal terminal Vref2 and the third node N3, and the second energy storage sub-circuit 44 is configured to maintain the voltage of the third node N3.

[0065] The aforementioned second energy storage sub-circuit 44 may include a second capacitor C2, one plate of which is electrically connected to the third node N3, and the other plate is electrically connected to the second reference voltage signal terminal Vref2. For example, when the second transistor T2 is in the off state, the second capacitor C2 can maintain the voltage of the third node N3.

[0066] The switching sub-circuit 45 is electrically connected to the second node N2, the third node N3 and the output signal terminal Out. The switching sub-circuit 45 is configured to electrically connect the second node N2 and the output signal terminal Out under the control of the third node N3.

[0067] The switching sub-circuit 45 includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the output signal terminal Out. For example, when the input sub-circuit 43 transmits an input signal Vin to the third node N3, the third transistor T3, under the control of the voltage difference between the third node N3 and the second node N2, generates a calculated current and transmits the calculated current to the output signal terminal Out.

[0068] When the third transistor T3 operates in the linear region, the current Ic2 of the third transistor T3 satisfies: (7) In the above equation (7), μ is the channel carrier mobility of the third transistor T3, Cox is the gate oxide capacitance per unit area of ​​the third transistor T3, W / L is the ratio of the channel width to the length of the third transistor T3, Vgs is the voltage difference between the control electrode (third node N3) and the first electrode (second node N2) of the third transistor T3, Vth2 is the threshold voltage of the third transistor T3, and Vds is the voltage difference between the second electrode (bit line BL) and the first electrode (second node N2) of the third transistor T3. Since Vds is extremely small, the above "0.5×Vds" 2"It can be ignored, and the above equation (7) can be approximately simplified to: (8) In equation (8) above, gm is the transconductance of the floating gate transistor 32. When the floating gate transistor 32 is operating in the saturation region, the voltage of the second node N2 can control the stable transconductance gm of the floating gate transistor 32, and the transconductance gm of the floating gate transistor 32 can determine the voltage stability of N2. Vin is the gate voltage written to the third transistor T3.

[0069] See Figure 4 In some embodiments, the neural network 30 further includes multiple bit lines BL, multiple word lines WL, and multiple input signal lines IN. The multiple bit lines BL are arranged along the row direction X and extend along the column direction Y. One bit line BL is electrically connected to the output terminal Out of a column of neurons 31, and the bit line BL is electrically connected to the control circuit 40, which is also configured to sum the currents on the bit lines BL. The multiple word lines WL are arranged along the column direction Y and extend along the row direction X. One word line WL is electrically connected to a row of neurons 31, and the word line WL is configured as a first control signal terminal EN. The multiple input signal lines IN are arranged along the row direction X and extend along the column direction Y. One input signal line IN is electrically connected to the input signal terminal V-in of a column of neurons 31.

[0070] The display panel may further include multiple first reference voltage signal lines, multiple second reference voltage signal lines, multiple first voltage signal lines, and multiple second voltage signal lines; the first reference voltage signal lines are electrically connected to neurons of the neural network and are configured as first reference voltage signal terminals electrically connected to neurons. The second reference voltage signal lines are electrically connected to neurons of the neural network and are configured as second reference voltage signal terminals electrically connected to neurons.

[0071] For example, at least one of the plurality of first reference voltage signal lines, the plurality of second reference voltage signal lines, and the plurality of first voltage signal lines may extend along the row direction and be spaced apart along the column direction. Alternatively, at least one of the plurality of first reference voltage signal lines, the plurality of second reference voltage signal lines, and the plurality of first voltage signal lines may extend along the column direction and be spaced apart along the row direction. Alternatively, at least one of the plurality of first reference voltage signal lines, the plurality of second reference voltage signal lines, and the plurality of first voltage signal lines may include a plurality of first sub-lines and a plurality of second sub-lines, wherein the plurality of first sub-lines extend along the row direction and are spaced apart along the column direction, and the plurality of second sub-lines extend along the column direction and are spaced apart along the row direction, wherein the plurality of first sub-lines and the plurality of second sub-lines are located in different film layers, and the plurality of first sub-lines and the plurality of second sub-lines are electrically connected to each other, and the plurality of first sub-lines and the plurality of second sub-lines form an interwoven mesh structure to reduce the overall resistance. For example, multiple second voltage signal lines can extend along the column direction and be spaced apart along the row direction. One second voltage signal line is electrically connected to a column of neurons to provide differentiated second voltage signals to different neurons.

[0072] For example, at least one signal line transmitting a constant voltage that is electrically connected to the pixel circuit (such as the third voltage signal line and the third reference voltage signal line) can be reused as at least one signal line transmitting a constant voltage that is electrically connected to the neuron (such as the first reference voltage signal line, the second reference voltage signal line, the first voltage signal line and the second voltage signal line) to reduce the overall number of signal lines in the display panel, which helps to increase the arrangement space of the pixel circuit and the neuron and increase the arrangement density of the pixel circuit and the neuron.

[0073] For example, any signal line electrically connected to the pixel circuit can also be electrically insulated from any signal line electrically connected to the neuron. That is, the display panel has separate signal lines for the neural network and the pixel circuit.

[0074] See Figure 8 Some embodiments of this disclosure also provide a driving method for a display panel, which can be used to drive the display panel described in any of the above embodiments. A frame period may include a display phase D1 and a blanking phase D2. The driving method includes displaying a pattern by multiple sub-pixels in the display phase D1. And in the blanking phase D2, the control circuit 40 drives the neural network 30 to perform calculations. That is to say, the driving method for the display panel provided by the embodiments of this disclosure can utilize the blanking phase to realize the calculation function of the neural network, which can reduce signal interference between the neural network and the pixel circuit, and ensure that the display function of the sub-pixels and the calculation function of the neural network do not interfere with each other.

[0075] See Figure 7 and Figure 8In some embodiments, the blanking phase D2 includes a loading phase D21, a writing phase D22, and a computation phase D23. When the neuron 31 includes a floating-gate transistor 32, a weight loading sub-circuit 41, an input sub-circuit 43, and a switching sub-circuit 45, the driving method for the display panel may include: During the loading phase D21, the first control signal terminal EN controls the weight loading sub-circuit 41 to transmit the second voltage signal from the second voltage signal terminal Vw to the first node N1.

[0076] For example, during the loading phase D21, the control circuit 40 controls the first control signal terminal EN to transmit the operating voltage (low voltage). The first control signal terminal EN drives the first transistor T1 and the second transistor T2 to turn on, respectively. The second voltage Vw at the second voltage signal terminal Vw is transmitted to the first node N1 through the first transistor T1, that is, to the control gate Cg of the floating gate transistor 32. The floating gate transistor 32 can then conduct and transmit a stable voltage to the second node N2. During the loading phase D21, there is no input signal transmitted at the input signal terminal V-in, and the voltage of the third node N3 remains unchanged.

[0077] During the writing phase D22, the first control signal terminal EN controls the input sub-circuit 43 to transmit the input signal Vin from the input signal terminal V-in to the third node N3.

[0078] For example, during the write phase D22, the first control signal terminal EN continues to transmit the operating voltage (low voltage). The first control signal terminal EN drives the first transistor T1 and the second transistor T2 to remain on. The second voltage signal terminal Vw can stop transmitting the second voltage signal, and the first capacitor C1 can keep the voltage of the first node N1 unchanged. The input signal terminal V-in begins to transmit the input signal Vin, and the input signal Vin is transmitted to the third node N3 through the second transistor T2.

[0079] In the embodiments of this disclosure, the time for writing the second voltage to the control gate of the floating gate transistor 32 is spaced apart from the time for writing the input signal Vin to the gate of the third transistor T3. This helps to avoid uncontrollable critical data and prevents the floating gate transistor 32 from starting to operate uncontrollably. Exemplarily, multiple word lines WL (first control signal terminal EN) can transmit the operating voltage sequentially, or multiple word lines WL can transmit the operating voltage together. The embodiments of this disclosure will not elaborate further on this.

[0080] For example, multiple word lines WL (first control signal terminal EN) can transmit the operating voltage sequentially, or multiple word lines WL can transmit the operating voltage together, as will not be elaborated further in the embodiments of this disclosure.

[0081] During the calculation phase D23, the switching sub-circuit 45, under the control of the third node N3 and the second node N2, generates a calculation current and transmits the calculation current to the output signal terminal.

[0082] For example, during computation phase D23, the first control signal terminal EN transmits a non-operating voltage (high voltage), and the first transistor T1 and the second transistor T2 are turned off. The voltage of the first node N1 is maintained by the first capacitor C1, that is, the voltage of the control gate Cg of the floating gate transistor 32 remains unchanged. The voltage of the third node N3 is maintained by the second capacitor C2, and the gate voltage of the third transistor T3 remains unchanged. Under the action of the second node N2 and the third node N3, the third transistor T3 generates a computation current, which is transmitted through the bit line BL. The computation current satisfies the following conditions: (9) In the above equation (9), gm is the transconductance of the floating gate transistor 32, Vin is the voltage written to the third node N3, and Vth2 is the threshold voltage of the third transistor T3.

[0083] Furthermore, during the calculation phase D23, the control circuit 40 can perform calculations on the current of a column of neurons 31 (multiple neurons 31 electrically connected to the same bit line BL).

[0084] For example, during the annulmentation stage, in addition to performing the aforementioned current calculation functions, the control circuit and neural network can also maintain the weights stored in the neural network and detect the threshold voltage of the floating-gate transistors in the neurons. Display phase D1 may include a data writing phase and a light emission phase.

[0085] During the data writing phase, the gate drive circuit drives the scan signal line GL to transmit the working voltage (low level). The fourth transistor T4 is turned on under the control of the scan signal line GL, and the fourth transistor T4 transmits the data signal transmitted on the data signal line DL to the fourth node N4.

[0086] During the light-emitting stage, the scan signal line GL transmits a non-operating voltage. The fourth transistor T4 is turned off under the control of the scan signal line GL. At this time, the third capacitor Cst can maintain the voltage of the fourth node N4, and the fifth transistor T5 can generate a drive current under the control of the voltage difference between the fourth node N4 and the third voltage signal line VDD.

[0087] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a peripheral area surrounding the display area. Multiple sub-pixels are disposed in the display area, and the multiple sub-pixels are arranged in an array; A neural network, at least partially disposed in the display area, includes a plurality of neurons arranged in an array, the neurons being configured to perform weighted calculations and output computational currents; A control circuit, located in the peripheral area and electrically connected to the neural network, is configured to: transmit an input signal to the neural network and perform a summation operation on the calculated current.

2. The display panel according to claim 1, characterized in that, The neurons include: A floating-gate transistor, wherein the floating gate of the floating-gate transistor is configured to store weights, the control gate of the floating-gate transistor is electrically connected to a first node, the first terminal of the floating-gate transistor is electrically connected to a first voltage signal terminal, and the second terminal of the floating-gate transistor is electrically connected to a second node; A weight loading sub-circuit is electrically connected to a first control signal terminal, a second voltage signal terminal, and the first node. The weight loading sub-circuit is configured to transmit a second voltage signal from the second voltage signal terminal to the first node under the control of a control signal from the first control signal terminal. The first energy storage sub-circuit, electrically connected to the first reference voltage signal terminal and the first node, is configured to maintain the voltage of the first node; An input sub-circuit is electrically connected to the first control signal terminal, the input signal terminal, and the third node. The input sub-circuit is configured to transmit the input signal from the input signal terminal to the third node under the control of the control signal. The second energy storage sub-circuit, electrically connected to the second reference voltage signal terminal and the third node, is configured to maintain the voltage of the third node; A switching sub-circuit, electrically connected to the second node, the third node, and the output signal terminal, is configured to electrically connect the second node to the output signal terminal under the control of the third node.

3. The display panel according to claim 2, characterized in that, The weight W of the floating gate storage of the floating gate transistor can satisfy: （1） （2） Where k is the normalized weighting coefficient, μ is the channel carrier mobility of the floating gate transistor, and Cox is the gate oxide capacitance per unit area. Vw is the ratio of channel width to length; Vth1 is the voltage of the control gate of the floating gate transistor; ΔVth is the threshold voltage when the floating gate of the floating gate transistor does not store charge; ΔVth is the threshold voltage offset corresponding to the charge stored in the floating gate of the floating gate transistor; Qfg is the charge stored in the floating gate of the floating gate transistor; and Cfg is the equivalent total capacitance of the floating gate of the floating gate transistor.

4. The display panel according to claim 2, characterized in that, The weight loading sub-circuit includes a first transistor, the control electrode of the first transistor is electrically connected to a first control signal terminal, the first electrode of the first transistor is electrically connected to a second voltage signal terminal, and the second electrode of the first transistor is electrically connected to the first node. The first energy storage sub-circuit includes a first capacitor, one plate of the first capacitor is electrically connected to the first node, and the other plate is electrically connected to the first reference voltage signal terminal; The input sub-circuit includes a second transistor, the control electrode of the second transistor is electrically connected to the first control signal terminal, the first electrode of the second transistor is electrically connected to the input signal terminal, and the second electrode of the second transistor is electrically connected to the third node. The second energy storage sub-circuit includes a second capacitor, one plate of which is electrically connected to the third node, and the other plate is electrically connected to the second reference voltage signal terminal. The switching sub-circuit includes a third transistor, the control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the output terminal.

5. The display panel according to any one of claims 2 to 4, characterized in that, The neural network also includes: Multiple bit lines are arranged along the row direction and extend along the column direction. Each bit line is electrically connected to the output terminal of a column of neurons and is also electrically connected to the control circuit, which is further configured to sum the currents on the bit lines. The row direction is the row direction of the arrangement of the multiple sub-pixels, and the column direction is the column direction of the arrangement of the multiple sub-pixels. The row direction and the column direction intersect. Multiple word lines are arranged along the column direction and extend along the row direction, one word line is electrically connected to one row of neurons, and the word line is configured as the first control signal terminal; Multiple input signal lines are arranged along the row direction and extend along the column direction, with each input signal line electrically connected to the input signal terminal of a column of neurons.

6. The display panel according to any one of claims 1 to 4, characterized in that, The sub-pixel includes a pixel circuit and a light-emitting device, the pixel circuit including: The fourth transistor has its control electrode electrically connected to the scan signal line, its first electrode electrically connected to the data signal line, and its second electrode electrically connected to the fourth node. The fifth transistor has its control electrode electrically connected to the fourth node, its first electrode electrically connected to the third voltage signal line, and its second electrode electrically connected to the anode of the light-emitting device. The third capacitor has one plate electrically connected to the fourth node and the other plate electrically connected to the third reference signal terminal.

7. The display panel according to claim 1, characterized in that, Along the row direction, at least one sub-pixel is included between two adjacent neurons.

8. A driving method for a display panel, used to drive the display panel as described in any one of claims 1 to 7, characterized in that, A frame cycle includes a display phase and a blanking phase; the driving method includes: During the display phase, multiple sub-pixels display a pattern; During the blanking phase, the control circuit drives the neural network to perform calculations.

9. The driving method according to claim 8, characterized in that, The blanking phase includes a loading phase, a writing phase, and a computation phase. The neuron includes a floating gate transistor, a weight loading sub-circuit, an input sub-circuit, and a switching sub-circuit. The driving method further includes: During the loading phase, the first control signal terminal controls the weight loading sub-circuit to transmit the second voltage signal from the second voltage signal terminal to the first node; During the writing phase, the first control signal terminal controls the input sub-circuit to transmit the input signal from the input signal terminal to the third node; During the calculation phase, the switching sub-circuit generates a calculation current under the control of the third node and the second node, and transmits the calculation current to the output signal terminal. The control circuit calculates the current output by a series of neurons.

10. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 7; The sensor, electrically connected to the control circuit of the display panel, is configured to sense predetermined parameters and transmit sensing signals to the control circuit.

Images