Driving method of pixel circuit and display device

Abstract

The application discloses a driving method of a pixel circuit and a display device, and belongs to the technical field of display. The method comprises the following steps: in each display frame, a light-emitting control signal is controlled to have a cutoff pulse for controlling a light-emitting control transistor to be turned off, and a first scanning signal is controlled to have three turn-on pulses for controlling a data writing transistor to be turned on, and the three turn-on pulses are all located in the cutoff pulse of the light-emitting control signal; the three turn-on pulses of the first scanning signal comprise a first pulse, a second pulse and a third pulse which appear in sequence; in a writing frame, a second scanning signal is controlled to have a turn-on pulse for controlling a threshold value compensation transistor to be turned on, and the turn-on pulse of the second scanning signal is time-overlapped with the second pulse and is not time-overlapped with the first pulse and the third pulse; in the same writing frame, the pulse width of at least one of the first pulse and the third pulse is greater than the pulse width of the second pulse. The embodiment of the application can improve the characteristic drift of a driving transistor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving method for pixel circuits and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays and flat panel displays based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display devices. However, current display devices suffer from the problem of uneven display. Summary of the Invention

[0003] This invention provides a driving method and display device for pixel circuits to improve the characteristic drift of driving transistors, enhance display uniformity, and improve display effect.

[0004] In a first aspect, embodiments of the present invention provide a driving method for a pixel circuit, the pixel circuit comprising: a driving transistor, a data writing transistor, a threshold compensation transistor, and a light-emitting control transistor; the data writing transistor is connected to a first electrode of the driving transistor and connected to a first scan signal; the threshold compensation transistor is connected between the gate and a second electrode of the driving transistor and connected to a second scan signal; the light-emitting control transistor is connected in series with the driving transistor and connected to a light-emitting control signal.

[0005] The driving method for the pixel circuit includes:

[0006] In each display frame, the control signal for the light emission has a cutoff pulse for controlling the light emission control transistor to turn off, and the control signal for the first scan signal has three turn-on pulses for controlling the data write transistor to turn on, and the three turn-on pulses of the first scan signal are all located within the cutoff pulse of the control signal; wherein, the three turn-on pulses of the first scan signal include a first pulse, a second pulse, and a third pulse that appear sequentially;

[0007] In the write frame, the control of the second scan signal has a turn-on pulse for controlling the threshold compensation transistor to turn on; wherein at least a portion of the display frame is the write frame; in the write frame, the turn-on pulse of the second scan signal overlaps with the second pulse in time, but does not overlap with the first pulse and the third pulse in time; in the same write frame, the pulse width of at least one of the first pulse and the third pulse is greater than the pulse width of the second pulse.

[0008] Optionally, in the same write frame, the pulse widths of the first pulse and the third pulse are both greater than the pulse width of the second pulse;

[0009] Preferably, in the same write frame, the pulse width of the first pulse is greater than the pulse width of the third pulse.

[0010] Optionally, some of the display frames are write frames, and the remaining display frames are hold frames;

[0011] The pulse width of each conduction pulse of the first scan signal in the hold frame is greater than or equal to the pulse width of the corresponding conduction pulse in the first scan signal in the write frame;

[0012] Preferably, the pulse width of at least one on pulse of the first scan signal in the hold frame is greater than the pulse width of the corresponding on pulse of the first scan signal in the write frame;

[0013] Preferably, the pulse width of each conduction pulse of the first scan signal in the hold frame is greater than the pulse width of the corresponding conduction pulse in the first scan signal in the write frame.

[0014] Optionally, some of the display frames are write frames, and the remaining display frames are hold frames, with multiple hold frames spaced apart between two adjacent write frames;

[0015] In the first hold frame, the pulse width of each conduction pulse of the first scan signal is less than or equal to the pulse width of the corresponding conduction pulse in the first scan signal in the second hold frame; wherein, the first hold frame and the second hold frame are two hold frames that appear sequentially between two adjacent write frames;

[0016] Preferably, the pulse width of at least one turn-on pulse of the first scan signal in the first hold frame is smaller than the pulse width of the corresponding turn-on pulse in the first scan signal in the second hold frame;

[0017] Preferably, the pulse width of each conduction pulse of the first scan signal in the first hold frame is smaller than the pulse width of the corresponding conduction pulse in the first scan signal in the second hold frame.

[0018] Optionally, within the same display frame, the first time interval between the end time of the third pulse and the end time of the cutoff pulse of the light emission control signal is less than the second time interval between the end time of the second pulse and the start time of the third pulse.

[0019] Preferably, the first time interval is less than or equal to the first time threshold;

[0020] Preferably, the first time threshold is less than or equal to 1 μs.

[0021] Optionally, the pixel circuit further includes: a first initialization transistor connected to the gate of the driving transistor and connected to a third scan signal; the driving method of the pixel circuit further includes:

[0022] In the write frame, the control third scan signal has a turn-on pulse for controlling the first initialization transistor to turn on; wherein, in the write frame, the turn-on pulse of the third scan signal is located within the cutoff pulse of the light emission control signal, and the turn-on pulse of the third scan signal ends before the start of the second pulse;

[0023] Preferably, the activation pulse of the third scan signal ends before the start of the first pulse;

[0024] Preferably, within the same write frame, the third time interval between the end time of the first pulse and the start time of the second pulse is less than the fourth time interval between the end time of the turn-on pulse of the third scan signal and the start time of the first pulse.

[0025] Preferably, the third time interval is less than or equal to the second time threshold;

[0026] Preferably, the second time threshold is less than or equal to 1 µs;

[0027] Preferably, some of the display frames are write frames, and the remaining display frames are hold frames; the driving method for the pixel circuit further includes:

[0028] In the hold frame, the control third scan signal is held at a potential used to control the first initialization transistor to turn off.

[0029] Optionally, some of the display frames are write frames, and the remaining display frames are hold frames;

[0030] The fifth time interval between the start time of the cutoff pulse of the light emission control signal in the hold frame and the start time of the first pulse is less than the sixth time interval between the start time of the cutoff pulse of the light emission control signal and the start time of the first pulse in the write frame.

[0031] Preferably, the fifth time interval is 0.

[0032] Optionally, the data writing transistor is also connected to a data line; some of the display frames are the writing frames, and the remaining display frames are holding frames; the driving method for the pixel circuit further includes:

[0033] In the write frame, during the period when the first scan signal outputs the second pulse, the data line is controlled to transmit a data voltage for controlling the magnitude of the drive current generated by the drive transistor;

[0034] During the hold frame, at least during the period when the first scan signal outputs the second pulse, the data line is controlled to transmit a reset voltage;

[0035] Preferably, in the hold frame, before the first scan signal starts outputting the first pulse, the data line is controlled to start transmitting the reset voltage, and the reset voltage is continuously transmitted until the third pulse ends;

[0036] Preferably, during the hold frame, the data line is controlled to continuously transmit the reset voltage;

[0037] Preferably, the light-emitting control transistor, the driving transistor, and the light-emitting device are connected in series between a first power line and a second power line, and the first power line transmits a first power signal; a plurality of hold frames are included between two adjacent write frames; the driving method of the pixel circuit further includes:

[0038] For any two hold frames between two adjacent write frames, the voltage difference between the reset voltage transmitted by the data line and the first power signal in the preceding hold frame is controlled to be less than or equal to the voltage difference between the reset voltage transmitted by the data line and the first power signal in the following hold frame.

[0039] Optionally, the pixel circuit further includes: a second initialization transistor connected to the anode of the light-emitting device and connected to a fourth scan signal; the driving method of the pixel circuit further includes:

[0040] In each of the display frames, the control of the fourth scan signal has at least one turn-on pulse for controlling the second initialization transistor to turn on, and each turn-on pulse of the fourth scan signal is located within the cutoff pulse of the light emission control signal;

[0041] Preferably, some of the display frames are write frames, and the remaining display frames are hold frames;

[0042] The driving method for the pixel circuit further includes: during the hold frame, controlling the second scan signal to maintain a potential for controlling the threshold compensation transistor to turn off.

[0043] Secondly, embodiments of the present invention also provide a display device, including: a display panel and a driving component; the display panel includes a plurality of pixel circuits, and the driving component is connected to the display panel; the driving component is used to drive each of the pixel circuits using the pixel circuit driving method provided in any embodiment of the present invention.

[0044] In the pixel circuit driving method provided in this embodiment of the invention, by setting the first scan signal to have three conduction pulses within the cutoff pulse of the light emission control signal in each display frame, the bias of the driving transistor can be improved before the light emission in each display frame, thereby improving the consistency of the display effect in each display frame. Specifically, in the write frame, the second pulse corresponds to the conduction pulse of the second scan signal, which is equivalent to providing a bias improvement stage before and after the data writing stage of the write frame, resetting the first electrode of the driving transistor. The first pulse resets the potential of the first electrode of the driving transistor before the data writing stage, effectively improving the characteristic drift of the driving transistor caused by bias during the period when the light emission control signal is held at the conduction potential of the light emission control transistor in the previous display frame, improving the characteristics of the driving transistor and enabling it to correctly perform data writing. The third pulse resets the potential of the first electrode of the driving transistor after the data writing stage, effectively improving the characteristic drift of the driving transistor caused by bias during the period between the data writing stage and the light emission stage, improving the characteristics of the driving transistor and enabling it to provide the expected driving current, avoiding brightness drift of the light-emitting device. Furthermore, by setting the pulse width of at least one of the first and third pulses in the write frame to be greater than the pulse width of the second pulse, the reset time of the first electrode of the driving transistor can be increased as much as possible, achieving a more thorough potential reset and improving the bias improvement effect on the driving transistor. Therefore, the embodiments of the present invention can improve the characteristic drift of the driving transistor, enhance display uniformity, and improve display effect.

[0045] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of the brightness change of a display device in related technologies;

[0050] Figure 4 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0051] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0052] Figure 6 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0053] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0054] Figure 8 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0055] Figure 9 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0056] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0058] As mentioned in the background section, display devices in related technologies suffer from uneven display. The main reason for this problem is that the driving transistors in the pixel circuit are in a biased state for a long time during the light-emitting stage, causing the driving transistors to drift and the threshold voltage to shift. This causes the driving current generated by the driving transistors to change under the same data voltage, affecting the brightness of the light-emitting device and resulting in uneven display.

[0059] To address the aforementioned problems, embodiments of the present invention provide a driving method for a pixel circuit. To facilitate explanation of this method, the structure of the pixel circuit will first be briefly described below. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1 The pixel circuit includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, and a light-emitting control transistor. The data writing transistor M2 is connected to the first terminal (e.g., the source) of the driving transistor M1 and is connected to a first scan signal S1. The threshold compensation transistor M3 is connected between the gate and the second terminal (e.g., the drain) of the driving transistor M1 and is connected to a second scan signal S2. The light-emitting control transistor is connected in series with the driving transistor M1 and is connected to a light-emitting control signal EM. Specifically, the gate of the data writing transistor M2 is connected to the first scan signal S1, the first terminal of the data writing transistor M2 is connected to the data line LS, and the second terminal of the data writing transistor M2 is connected to the first terminal of the driving transistor M1; the first terminal of the threshold compensation transistor M3 is connected to the second terminal of the driving transistor M1, the second terminal of the threshold compensation transistor M3 is connected to the gate of the driving transistor M1, and the gate of the threshold compensation transistor M3 is connected to the second scan signal S2. The pixel circuit may include two light-emitting control transistors, namely the first light-emitting control transistor M4 and the second light-emitting control transistor M5. The first light-emitting control transistor M4, the driving transistor M1, the second light-emitting control transistor M5, and the light-emitting device L are connected in series, for example, between the first power line and the second power line; the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are both connected to the light-emitting control signal EM; the first power line is used to transmit the first power signal VDD, and the second power line is used to transmit the second power signal VSS. The first power signal VDD has a high potential, for example, and the second power signal VSS has a low potential, for example.

[0060] When the first scan signal S1 controls the data writing transistor M2 to turn on, the signal transmitted on the data line LS can be transmitted to the first terminal of the driving transistor M1 through the second transistor M2; when the second scan signal S2 controls the threshold compensation transistor M3 to turn on, the driving transistor M1 is connected in the form of a diode, and the voltage-related signal of the first terminal of the driving transistor M1 can be transmitted to the gate of the driving transistor M1; when the light emission control signal EM controls the two light emission control transistors to turn on, the driving transistor M1 can generate a driving current according to the voltage of its gate and transmit it to the light emission device L to drive the light emission device L to emit light.

[0061] The driving method of the pixel circuit will be explained in detail below.

[0062] Figure 2 This is a schematic diagram of the driving timing of a pixel circuit according to an embodiment of the present invention. Combined with... Figure 1 and Figure 2 The specific driving methods for pixel circuits include:

[0063] In each display frame, the control signal EM for controlling the light emission control transistor to turn off has a cutoff pulse, and the control signal S1 for controlling the data writing transistor M2 to turn on has three conduction pulses, and the three conduction pulses of the first scan signal S1 are all located within the cutoff pulse of the control signal EM for controlling the light emission control transistor to turn off.

[0064] In the write frame, the control second scan signal S2 has a turn-on pulse for controlling the threshold compensation transistor M3 to turn on.

[0065] In each display frame, the three conduction pulses of the first scan signal S1 include a first pulse pulse1, a second pulse pulse2, and a third pulse pulse3 that occur sequentially. In the write frame, the conduction pulse of the second scan signal S2 is located within the cutoff pulse of the light emission control signal EM. The conduction pulse of the second scan signal S2 overlaps with the second pulse pulse2 in time, but does not overlap with the first pulse pulse1 or the third pulse pulse3 in time. In the same write frame, the pulse width of at least one of the first pulse pulse1 and the third pulse pulse3 is greater than the pulse width of the second pulse pulse2. At least a portion of the display frames are write frames.

[0066] It is understood that for any two pulses, pulse A being within pulse B can be interpreted as the duration of pulse B completely covering the duration of pulse A in time. A written frame can be understood as a display frame that writes a voltage related to the signal transmitted on the data line LS to the gate of the driving transistor M1, causing the gate voltage of the driving transistor M1 to refresh. For example, the data writing transistor M2 is a P-type transistor, therefore each conduction pulse of the first scan signal S1 has a low potential. Similarly, both light-emitting control transistors are P-type transistors, and the corresponding cutoff pulse of the light-emitting control signal EM has a high potential; the threshold compensation transistor M3 is an N-type transistor, and the corresponding conduction pulse of the second scan signal S2 has a high potential. However, the above transistor types are not intended to limit the invention. In other embodiments, the transistor types can be changed as needed, and the control signals connected to the transistor gates can be inverted accordingly. For example, if the data writing transistor M2 is replaced with an N-type transistor, the first scan signal S1 is inverted accordingly, and its conduction pulse is replaced with a high potential.

[0067] Figure 2 This can be viewed as a driver timing sequence written into a frame, combined with... Figure 1 and Figure 2 The driving process of this pixel circuit specifically includes a scanning phase and a light-emitting phase T4. The scanning phase corresponds to the duration of the cutoff pulse of the light-emitting control signal EM, and the light-emitting phase T4 corresponds to the period when the light-emitting control signal EM has the on-state potential of the light-emitting control transistor. The scanning phase may specifically include a first bias improvement phase T1, a data writing phase T2, and a second bias improvement phase T3. It is understood that in actual operation, the duration of the light-emitting phase T4 is much longer than the duration of the scanning phase. The duration ratios in the accompanying drawings of this embodiment are adjusted to clearly show the waveforms of each signal in the scanning phase, and only the timing relationship of each phase is shown, not the actual duration relationship of each phase. The specific working process of each phase is described below:

[0068] The first bias improvement stage T1 corresponds to the duration of the first pulse pulse1. In the first bias improvement stage T1, the data writing transistor M2 is turned on, providing the signal transmitted on the data line LS to the first terminal of the driving transistor M1, thereby resetting the first terminal of the driving transistor M1 and improving the bias of the driving transistor M1 during its prolonged illumination in the previous frame's illumination stage T4. It can be understood that the signal transmitted on the data line LS in this stage may have a first preset voltage value, which is within the data voltage range corresponding to all gray levels, for example, the data voltage corresponding to any gray level, to improve the characteristic drift caused by the first terminal of the driving transistor M1 receiving the first power supply signal VDD for a long time during the illumination stage T4 of the previous display frame. For example, the first preset voltage value may specifically be the data voltage value in the data writing stage T2 of the previous write frame (or the first write frame) so as to adjust the characteristics of the driving transistor M1 to be consistent with the previous write frame (or the first write frame), so that the driving transistor M1 can perform data writing under the same characteristics as the previous write frame (or the first write frame), ensuring that the subsequent data writing process is fully and correctly performed.

[0069] The data writing phase T2 corresponds to the overlapping period of the second pulse pulse2 and the conduction pulse of the second scan signal S2. For example, in the write frame, if the second pulse pulse2 is located within the conduction pulse of the second scan signal S2, then the data writing phase T2 corresponds to the duration of the second pulse pulse2. During the data writing phase T2, both the data writing transistor M2 and the threshold compensation transistor M3 are turned on. The signal transmitted on the data line LS is transmitted to the gate of the driving transistor M1 via the data writing phase T2 and the diode-type driving transistor M1, completing the gate potential write refresh of the driving transistor M1 in this write frame. It is understandable that the signal transmitted on the data line LS during this stage is the data voltage corresponding to the target gray level of the write frame, denoted as Vdata0. Then, after the data writing is completed and the data charging is finished, the voltages of the three terminals of the driving transistor M1 are as follows: the voltage of the first terminal is Vdata0, the gate voltage is Vdata0-|vth|, vth is the threshold voltage of the driving transistor M1, and the voltage of the second terminal is Vdata0-I*R(M1), where I is the current flowing through the driving transistor in the data writing stage T2, and R(M1) is the on-resistance of the driving transistor M1.

[0070] The second bias improvement stage T3 corresponds to the duration of the third pulse 3. In the second bias improvement stage T3, the data writing transistor M2 is turned on, providing the signal transmitted on the data line LS to the first terminal of the driving transistor M1, thus resetting the first terminal of the driving transistor M1 and improving the bias generated by the driving transistor M1 in the data writing stage T2. It can be understood that the signal transmitted on the data line LS in this stage can have a second preset voltage value, which is within the data voltage range corresponding to all gray levels. For example, it can be equal to the first preset voltage value, or it can be the data voltage corresponding to any gray level, such as the data voltage value in the data writing stage T2 of the previous writing frame (or the first writing frame), so that the characteristics of the driving transistor M1 are adjusted to be consistent with those in the previous writing frame (or the first writing frame), allowing the driving transistor M1 to emit light with characteristics consistent with the previous writing frame (or the first writing frame), ensuring that the driving current generated during subsequent light emission meets the display requirements of the target gray level.

[0071] During the light-emitting stage T4, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned on, and the driving transistor M1 generates a driving current based on the voltage difference between its gate and the first electrode, driving the light-emitting device L to emit light.

[0072] In this write frame, the second pulse (pulse2) corresponds to the charging process of the gate of the driving transistor M1, and its pulse width is determined by the refresh rate and resolution. The first pulse (pulse1) and the third pulse (pulse3) correspond to the reset process of the first electrode of the driving transistor M1, and do not involve the gate charging process. Therefore, the pulse widths of the first pulse (pulse1) and the third pulse (pulse3) can be adjusted as needed and do not need to be consistent with the pulse width of the second pulse (pulse2). To better improve the bias, this embodiment of the invention sets the pulse width of at least one of the first pulse (pulse1) and the third pulse (pulse3) in the write frame to be greater than the pulse width of the second pulse (pulse2). This effectively increases the reset time of the first electrode of the driving transistor M1, achieving a more thorough reset and thus improving the bias improvement effect on the driving transistor M1.

[0073] For example, the specific pulse widths of the first pulse (pulse1) and the third pulse (pulse3) can be determined through multiple experiments. Specifically, any grayscale level can be selected as the test grayscale level, and the display panel can be controlled to display the test grayscale level in full screen. The pulse widths of the first pulse (pulse1) and the third pulse (pulse3) are continuously adjusted, and the display effect of each display frame is recorded until the display uniformity meets the requirements, at which point the pulse width / pulse width range of the first pulse (pulse1) and the third pulse (pulse3) is determined. Furthermore, multiple test grayscale levels can be selected to better determine the pulse widths of the first pulse (pulse1) and the third pulse (pulse3). It is understood that the above pulse width determination process is only illustrative and is not intended to limit the invention.

[0074] In the pixel circuit driving method provided in this embodiment of the invention, by setting the first scan signal S1 within the cutoff pulse of the light emission control signal EM in each display frame to have three conduction pulses, the bias of the driving transistor M1 can be improved before light emission in each display frame, thereby improving the consistency of the display effect in each display frame. Specifically, in the write frame, the second pulse pulse2 is set to correspond to the conduction pulse of the second scan signal S2, which is equivalent to providing a bias improvement stage before and after the data writing stage T2 of the write frame, resetting the first electrode of the driving transistor M1. The invention provides a first pulse (pulse1) to reset the potential of the first electrode of the driving transistor M1 before the data writing phase T2. This effectively mitigates the characteristic drift of the driving transistor M1 caused by bias during the period when the light-emitting control signal EM is held at the on-state potential of the light-emitting control transistor in the previous display frame, thus improving the characteristics of the driving transistor M1 and enabling it to correctly perform data writing. A third pulse (pulse3) is provided after the data writing phase T2 to reset the potential of the first electrode of the driving transistor M1. This effectively mitigates the characteristic drift of the driving transistor M1 caused by bias during the period between the data writing phase T2 and the light-emitting phase T4, thus improving the characteristics of the driving transistor M1 and enabling it to provide the expected driving current, preventing brightness drift in the light-emitting device. Furthermore, by setting the pulse width of at least one of the first pulse (pulse1) and the third pulse (pulse3) in the writing frame to be greater than the pulse width of the second pulse (pulse2), the reset time of the first electrode of the driving transistor M1 can be maximized, achieving a more thorough potential reset and improving the bias improvement effect of the driving transistor M1. Therefore, this embodiment of the invention can improve the characteristic drift of the driving transistor M1, enhance display uniformity, and improve the display effect.

[0075] Based on the above embodiments, optionally, in the same write frame, the pulse widths of the first pulse pulse1 and the third pulse pulse3 can be set to be greater than the pulse width of the second pulse pulse2. In this way, the time for resetting the first electrode of the driving transistor M1 can be extended as much as possible, so that the characteristics of the driving transistor can be better improved before the data writing stage T2 and before the light emission stage T4, effectively improving the bias improvement effect of the driving transistor M1.

[0076] Based on the above embodiments, optionally, within the same write frame, the pulse width of the first pulse (pulse1) can be set to be greater than the pulse width of the third pulse (pulse3). This is equivalent to setting the duration of the first bias improvement stage T1 to be longer. Since a relatively long light-emitting stage T4 in the previous display frame has occurred before the start of the cutoff pulse of the light-emitting control signal EM, the first electrode of the driving transistor M1 continuously receives the first power supply signal VDD, which has a large difference from the gate voltage. Therefore, before the start of the first pulse (pulse1), the characteristic drift of the driving transistor M1 is more severe. Before the start of the third pulse (pulse3), the driving transistor M1 has completed the data writing to the gate, and the voltage of the first electrode of the driving transistor M1 is the data voltage corresponding to the target grayscale of the write frame, and the difference between it and the gate voltage has been reduced. Therefore, the characteristic drift of the driving transistor M1 before the start of the first pulse (pulse1) is more severe than the characteristic drift before the start of the third pulse (pulse3). By setting the pulse width of the first pulse (pulse1) to be larger, it is equivalent to providing more sufficient characteristic charging and recovery time for the more severe characteristic drift, which is beneficial to improving the bias improvement effect. It is understandable that the pulse width adjustments of the first pulse (pulse1) and the third pulse (pulse3) are both performed within the allowable range of the cutoff pulse width of the light emission control signal EM, and it is not necessary to change the cutoff pulse width of the light emission control signal EM in the written frame. At the same time, it should be noted that the pulse width adjustments of the first pulse (pulse1) and the third pulse (pulse3) should not affect the performance of other driving processes. For example, the pulse widths of the first pulse (pulse1) and the third pulse (pulse3) should not overlap with the turn-on pulse of the second scan signal S2 in time.

[0077] In one implementation, each display frame can be optionally configured as a write frame to achieve a high refresh rate display. By fully resetting the gate of the driving transistor M1 in each write frame, the uniformity of the display can be effectively improved.

[0078] In another implementation, optionally, some display frames can be set as write frames and the remaining display frames as hold frames to provide a low refresh rate display function. For example, a low refresh rate can be achieved by interpolating frames, i.e., setting at least one hold frame between every two adjacent write frames. It is understood that a hold frame refers to a display frame in which the voltage related to the signal transmitted on the data line LS is not written to the gate of the driving transistor M1, so that the gate of the driving transistor M1 maintains the voltage written in the previous write frame. Therefore, in each hold frame, the light emission control signal EM also has a cutoff pulse, and the first scan signal S1 also has three conduction pulses. This is equivalent to resetting the first terminal of the driving transistor M1 before the light emission phase of the hold frame begins, thereby improving the characteristics of the driving transistor M1, enhancing the consistency of the display effect between the hold frame and the write frame, and solving the low-frequency flicker problem.

[0079] The causes of low-frequency flickering are briefly explained below:

[0080] Currently, to save power in the overall system, there is an increasing demand for low-frequency displays. However, pixel circuits composed entirely of P-type LTPS transistors, due to the use of p-si materials, have high leakage current, resulting in continuous flickering in dark conditions. Based on the advantage of N-type IGZO transistors, which have very low leakage current, such as... Figure 1 The LTPO product, which combines the two types of transistors shown, represents the future trend; however, LTPO products are prone to flickering over time. See, for example... Figure 3 If a display device that supports a maximum refresh rate of 60Hz is used at a refresh rate of 10Hz, flickering will occur once every 100ms. This is because: the duration of each display frame on a display device that supports a maximum refresh rate of 60Hz is 1 / 60s. When displaying at a refresh rate of 10Hz, there are six display frames in one display cycle; each display cycle lasts 100ms, including one write frame and five hold frames, that is, there are five hold frames between every two adjacent write frames. Therefore, if... Figure 3 As shown, since the data writing transistor M2 is no longer turned on after the data is written in the write frame until the end of the display cycle, the first terminal of the driving transistor M1 is always biased by the first power supply signal VDD, causing the characteristics of the driving transistor M1 to deviate. Therefore, there is a brightness difference between the brightness of the holding frame in the previous display cycle and the brightness of the writing frame in the next display cycle when it is charged and lit. There is a trough every 100ms. This brightness difference is perceived by the human eye and manifests as periodic flickering according to the refresh time.

[0081] In this embodiment of the invention, by providing a new timing sequence, special timing design is performed in both the write frame and the hold frame. The first scan signal S1 outputs a special 3-pulse, and the first pole of the driving transistor M1 is reset before the light emission stage of the write frame and the light emission stage of the hold frame. In each display frame, the characteristic drift caused by the long-term bias of the driving transistor M1 during the light emission stage is improved, which can effectively solve the problem of low-frequency periodic screen flicker.

[0082] The pulse relationship between the signals in the maintenance frame and the display frame will be described in detail below, but this is not intended to limit the invention.

[0083] Based on the above embodiments, optionally, the pulse width of each conduction pulse of the first scan signal S1 in the hold frame can be set to be greater than or equal to the pulse width of the corresponding conduction pulse of the first scan signal S1 in the write frame. It is understood that the corresponding pulse refers to the pulse with the same sequence number in the write frame and the hold frame. Therefore, the pulse width of the first pulse pulse1 in the hold frame can be set to be greater than or equal to the pulse width of the first pulse pulse1 in the write frame, the pulse width of the second pulse pulse2 in the hold frame can be greater than or equal to the pulse width of the second pulse pulse2 in the write frame, and the pulse width of the third pulse pulse3 in the hold frame can be greater than or equal to the pulse width of the third pulse pulse3 in the write frame. For example, the waveform of each signal within each display cycle can change periodically.

[0084] The following provides an exemplary description of several possible waveform relationships for the first scan signal S1 in the write frame and the hold frame.

[0085] Figure 4 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 4 In one implementation, optionally, the waveform of the first scan signal S1 in the retention frame FI can be set to be the same as that in the write frame FA to reduce the risk of waveform errors.

[0086] Figure 5 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 5In another embodiment, optionally, the pulse width of at least one conduction pulse of the first scan signal S1 in the hold frame FI can be set to be greater than the pulse width of the corresponding conduction pulse of the first scan signal S1 in the write frame FA. Since no data is written to the gate of the driving transistor M1 during the cutoff pulse of the light emission control signal EM in the hold frame FI, if the improvement effect on the characteristics of the driving transistor M1 in a display frame is insufficient, the characteristic drift of the driving transistor M1 due to bias will accumulate to a certain extent during the subsequent continuous light emission process. Therefore, through the setting of this embodiment, the first electrode of the driving transistor M1 can be more fully reset in the hold frame, improving the characteristic consistency of the driving transistor in each display frame within the same display cycle.

[0087] For example, the pulse width of each conduction pulse of the first scan signal S1 in the hold frame FI can be set to be greater than the pulse width of the corresponding conduction pulse in the first scan signal S1 in the write frame FA, so as to maximize the duration of resetting the first pole of the drive transistor M1 in the hold frame.

[0088] Based on the above embodiments, optionally, when there are multiple hold frames between two adjacent write frames, that is, when a display cycle includes multiple hold frames, the pulse width of each conduction pulse of the first scan signal S1 in the first hold frame can be set to be less than or equal to the pulse width of the corresponding conduction pulse of the first scan signal S1 in the second hold frame. Here, the first hold frame and the second hold frame are two hold frames that appear sequentially between two adjacent write frames. In other words, for any two hold frames in the same display cycle, the preceding hold frame can be recorded as the first hold frame, and the following hold frame can be recorded as the second hold frame. In this embodiment, the pulse width of the first pulse pulse1 in the first holding frame is set to be less than or equal to the pulse width of the first pulse pulse1 in the second holding frame, the pulse width of the second pulse pulse2 in the first holding frame is less than or equal to the pulse width of the second pulse pulse2 in the second holding frame, and the pulse width of the third pulse pulse3 in the first holding frame is less than the pulse width of the third pulse pulse3 in the second holding frame. This ensures that the time for resetting the driving transistor M1 in the later holding frame in the same display cycle is at least the same as that in the earlier holding frame, thereby ensuring the consistency of the characteristics of the driving transistor M1 in the same display cycle.

[0089] In one implementation, see Figure 5 It can be set that the pulse width of pulses with the same sequence number in each hold frame is the same to reduce the risk of waveform errors.

[0090] Figure 6 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 6In another embodiment, optionally, the pulse width of at least one conduction pulse of the first scan signal S1 in the first hold frame can be set to be smaller than the pulse width of the corresponding conduction pulse of the first scan signal S1 in the second hold frame. This setting allows for a longer reset time for the first electrode of the drive transistor M1 in later hold frames, thus improving the consistency of the drive transistor's characteristics across display frames within the same display cycle, especially when the improvement in the characteristics of the drive transistor M1 is insufficient in a single display frame and the characteristic drift caused by bias accumulates to a certain extent during subsequent continuous light emission.

[0091] For example, the pulse width of each conduction pulse of the first scan signal S1 in the first holding frame can be set to be smaller than the pulse width of the corresponding conduction pulse of the first scan signal S1 in the second holding frame, so as to maximize the time for resetting the first pole of the driving transistor M1 in the subsequent holding frame.

[0092] It should be noted that the pulse width ratio of each conduction pulse in the first scan signal S1 in the hold frame can be the same as or different from the pulse width ratio of each conduction pulse in the first scan signal S1 in the write frame. The pulse width ratio of each conduction pulse in the first scan signal S1 in different hold frames can also be the same or different. The specific settings can be determined according to actual needs, and no limitation is made here.

[0093] Based on the above embodiments, optionally, by adjusting the signal transmitted on the data line LS, functions such as data writing and bias improvement can be achieved, which will be explained in detail below.

[0094] In one embodiment, the driving method for the pixel circuit may optionally further include:

[0095] 1) During the write frame, when the first scan signal S1 outputs the second pulse pulse2, the control data line LS transmits the data voltage used to control the magnitude of the drive current generated by the drive transistor M1 so that the correct data writing is completed in the data write phase T2.

[0096] 2) During the holding frame, at least during the period when the first scan signal S1 outputs the second pulse pulse2, the control data line transmits the reset voltage (which can be denoted as Vskip).

[0097] The reset voltage is used to reset the gate of the driving transistor M1 to improve the characteristic drift of the driving transistor M1. The reset voltage can be any gray level within the data voltage range corresponding to all gray levels. For example, the specific value of the reset voltage can be obtained through repeated testing and debugging. For instance, based on a standard flicker test method, the reset voltage value is adjusted multiple times, and the flickering is recorded after each adjustment until the flickering level is reduced to an imperceptible level, and the reset voltage value / selectable voltage range is saved.

[0098] Furthermore, in the hold frame, before the first scan signal S1 starts outputting the first pulse pulse1, the data line LS can be controlled to start transmitting the reset voltage and continue transmitting the reset voltage until the third pulse pulse3 ends. In this way, it can be ensured that the first terminal of the driving transistor M1 can be reset in each conduction pulse of the first scan signal S1 in the hold frame, thus ensuring the bias improvement effect.

[0099] Furthermore, during the hold frame, the data line LS can be controlled to consistently transmit a reset voltage to avoid the effects of voltage fluctuations on the data line LS. For example, data voltage and reset voltage can be provided to the data line LS separately through different terminals of the driver chip; alternatively, data voltage and reset voltage can be provided to the data line LS separately through different control chips.

[0100] In one embodiment, optionally, when there are multiple hold frames between two adjacent write frames, the voltage value of the reset voltage in each hold frame can be set to be consistent, and the bias improvement effect of each hold frame can be adjusted to be consistent by providing different pulse widths for the corresponding conduction pulses of the first scan signal S1 provided to different hold frames in the above embodiment.

[0101] Alternatively, in another implementation, when multiple hold frames are included between two adjacent write frames, the voltage value of the reset signal can be adjusted to achieve a consistent reset effect across all hold frames. Specifically, for any two hold frames between two adjacent write frames, the voltage difference between the reset voltage transmitted on the data line LS in the preceding hold frame and the first power signal VDD is controlled to be less than or equal to the voltage difference between the reset voltage transmitted on the data line LS in the following hold frame and the first power signal VDD. For example, if the reset voltage is lower than the voltage of the first power signal VDD, the voltage value of the reset voltage in the later hold frame within the same display cycle can be set to be lower. This is equivalent to providing a stronger reset effect to the following hold frames, so that the bias improvement effect of each hold frame tends to be consistent.

[0102] Understandably, in practical applications, in different hold frames, the bias can be improved by adjusting the reset voltage while ensuring that the pulse width of the corresponding conduction pulse of the first scan signal S1 is the same; alternatively, the pulse width adjustment of the conduction pulse of the first scan signal S1 and the voltage adjustment of the reset voltage can be combined to more effectively improve the bias effect.

[0103] Based on the above embodiments, optionally, except for transmitting the data voltage corresponding to the target gray level to the data line LS in the second pulse pulse2 of the written frame, the same reset potential can be provided to the data line LS in other conduction pulses of the first scan signal S1, so as to avoid the influence of reset voltage fluctuation on the bias improvement result.

[0104] See also Figure 4 Based on the above embodiments, optionally, within the same display frame, the first time interval Δt1 between the end time of the third pulse pulse3 and the end time of the cutoff pulse of the light emission control signal EM is less than the second time interval Δt2 between the end time of the second pulse pulse2 and the start time of the third pulse pulse3. That is, the third pulse pulse3 can be set closer to the light emission stage T4. Since the setting of the third pulse pulse3 is to prevent the characteristic drift of the driving transistor M1 due to bias during the time between the data writing stage T2 and the light emission stage T4, the first electrode potential of the driving transistor M1 is reset, thereby improving the characteristics of the driving transistor M1. Therefore, it is better to set the third pulse pulse3 as close as possible to the light emission stage T4 to ensure that the characteristics of the driving transistor M1 are corrected before light emission.

[0105] For example, a first time interval Δt1 can be set to be less than or equal to a first time threshold; the first time threshold is set to be less than or equal to 1µs for example.

[0106] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 7 Based on the above embodiments, optionally, the pixel circuit further includes a first initialization transistor M6; the first initialization transistor M6 is connected to the gate of the driving transistor M1 and is connected to the third scan signal S3 and the first initialization voltage Vref1.

[0107] Correspondingly, the driving methods for pixel circuits also include:

[0108] In the write frame, the control third scan signal S3 has a turn-on pulse for controlling the first initialization transistor M6 to turn on, so that the first initialization voltage Vref1 is transmitted through the first initialization transistor M6 to the gate of the driving transistor M1, thereby completing the reset of the gate of the driving transistor M1.

[0109] For details, please refer to Figure 8 The turn-on pulse of the third scan signal S3 corresponds to the initialization phase T0. In the write frame, the turn-on pulse of the third scan signal S3 is located within the cut-off pulse of the light emission control signal EM, and the turn-on pulse of the third scan signal S3 ends before the start of the second pulse pulse2. That is, the initialization phase T0 is completed before the data write phase T2 to ensure that the driving transistor M1 can be turned on at the start of the data write phase T2, thereby transmitting the data voltage-related voltage to the gate of the driving transistor M1. For example, the first initialization transistor M6 is an N-type transistor, and the turn-on pulse of the third scan signal S3 has a high potential.

[0110] Furthermore, the conduction pulse of the third scan signal S3 can be set to end before the start of the first pulse pulse1. That is, the initialization stage T0 is set before the first bias improvement stage T1. This is beneficial to improve flickering, and the specific analysis is as follows: In the light emission stage T4 of the previous holding frame before the start of the write frame, the voltages of the three poles of the driving transistor M1 are as follows: the first pole voltage is the first power supply signal VDD, the gate voltage is Vdata-|vth|, where Vdata is the data voltage on the write frame data line LS of the previous display cycle, and the second pole voltage is Vdata-I1*R(M1), where I1 is the current flowing through the driving transistor M1 in the write frame of the previous display cycle. During the initialization phase T0 of the write frame, the gate potential is replaced by the first initialization voltage Vref1. At this time, the gate potential of the driving transistor M1 is the first initialization voltage Vref1, and the first electrode voltage is the residual first power supply signal VDD. Since the first initialization voltage Vref1 is more negative than Vdata, the voltage difference between the gate and the first electrode of the driving transistor is more negative than in the previous hold frame. The driving transistor M1 is subjected to greater voltage stress. Setting the first pulse pulse1 after the initialization phase T0 is equivalent to pulling the characteristics of the driving transistor M1 back and immediately performing the data write operation. In this way, the characteristics of the driving transistor M1 can be kept closest to the first write frame. Therefore, the threshold voltage Vth of the driving transistor M1 is closest to that of the first write frame, ensuring the accuracy of the potential of the gate of the driving transistor M1 written in this write frame, thus avoiding the problem of periodic flickering.

[0111] Figure 9 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 9Based on the above embodiments, optionally, within the same write frame FA, a third time interval Δt3 between the end time of the first pulse pulse1 and the start time of the second pulse pulse2 can be set to be less than the fourth time interval Δt4 between the end time of the conduction pulse of the third scan signal S3 and the start time of the first pulse pulse1. That is, the first pulse pulse1 can be set to be closer to the data writing stage T2. Since the setting of the first pulse pulse1 is to prevent the characteristic drift of the driving transistor M1 caused by the bias in the light emission stage of the previous display frame, and to reset the first electrode potential of the driving transistor M1, the closer the first pulse pulse1 is to the data writing stage T2, the better, so as to ensure that data writing is performed immediately after the threshold voltage of the driving transistor M1 is improved to avoid data distortion.

[0112] For example, a third time interval Δt3 can be set to be less than or equal to a second time threshold, such as less than or equal to 1µs.

[0113] See also Figure 8 and Figure 9 Based on the above embodiments, optionally, the pixel circuit driving method further includes: in the holding frame, controlling the third scan signal S3 to maintain a potential for controlling the first initialization transistor M6 to turn off, so as to avoid mistakenly transmitting the first initialization voltage Vref1 to the gate of the driving transistor M1 in the holding frame. Also, in the holding frame, controlling the second scan signal S2 to maintain a potential for controlling the threshold compensation transistor M3 to turn off, so as to avoid changing the gate potential of the driving transistor M1 in the holding frame.

[0114] See also Figure 7 Based on the above embodiments, the pixel circuit may optionally include: a second initialization transistor M7; the second initialization transistor M7 is connected to the anode of the light-emitting device L and is connected to the fourth scan signal S4 and the second initialization voltage Vref2.

[0115] Correspondingly, the driving methods for pixel circuits also include:

[0116] In each display frame, the control fourth scan signal S4 has at least one turn-on pulse for controlling the second initialization transistor M7 to turn on, and each turn-on pulse of the fourth scan signal S4 is located within the cut-off pulse of the light emission control signal EM.

[0117] Among them, see Figure 8The fourth scan signal S4 may have a conduction pulse in each display frame (including the write frame FA and the hold frame FI). During the conduction pulse of the fourth scan signal S4, the second initialization transistor M7 is turned on, providing the second initialization voltage Vref2 to the anode of the light-emitting device L, thereby resetting the anode of the light-emitting device L. In the write frame FA, the conduction pulse of the fourth scan signal S4 may correspond to the anode initialization stage T5. For example, the second initialization transistor M7 is a P-type transistor, and the conduction pulse of the fourth scan signal S4 has a low potential.

[0118] For example, the turn-on pulse of the fourth scan signal S4 can be set to any time period within the cut-off pulse of the light emission control signal EM, for example... Figure 8 As shown, it is located between the first pulse (pulse1) and the second pulse (pulse2), or as... Figure 9 The display overlaps with other stages in time, for example, with the first pulse 1 / second pulse 2. It is understood that the start time of the activation pulse of the fourth scan signal S4 can be the same or different in each display frame, and can be set according to actual needs; no limitation is made here.

[0119] See also Figure 9 Based on the above embodiments, optionally, the fifth time interval Δt5 between the start time of the cutoff pulse of the light emission control signal EM in the holding frame F1 and the start time of the first pulse pulse1 can be set to be less than the sixth time interval Δt6 between the start time of the cutoff pulse of the light emission control signal EM in the writing frame FA and the start time of the first pulse pulse1. This setting allows the first pulse pulse1 to appear earlier in the holding frame FI than in the writing frame FA, enabling a faster reset of the first electrode of the driving transistor M1, thus achieving a more thorough bias improvement effect.

[0120] In this context, since the first terminal of the driving transistor M1 maintains the voltage of the first power supply signal VDD during the fifth time interval Δt5, it is essentially still in a biased state. Therefore, the shorter the fifth time interval Δt5, the better. For example, the fifth time interval Δt5 can be set to 0, so that after the light emission stage of the previous display frame ends, the first pulse pulse1 is immediately provided as soon as the light emission control signal EM goes high to improve the bias, shortening the bias time and achieving a better bias improvement effect. It can be understood that the bias improvement effect is due to the combined effect of the reset voltage's duration and voltage value. If the set reset voltage value can achieve a good bias improvement effect in a short time, then the pulse width selection range and the setting time selection range of each conduction pulse of the first scan signal S1 will be more flexible.

[0121] It should be noted that the cutoff pulse width of the luminous control signal EM in the write frame and hold frame can be set to be the same or different as required; here, the width is not limited and can be different.

[0122] It should also be noted that the time interval between adjacent conduction pulses in the first scan signal S1 of the hold frame can be the same as or different from the time interval between two corresponding adjacent conduction pulses in the first scan signal S1 of the write frame. The time intervals between adjacent conduction pulses in the first scan signal S1 of different hold frames can also be the same or different, and the aforementioned time intervals can also be the same or different in different display frames. The specific settings can be determined according to actual needs and are not limited here. Through the above flexible adjustment methods, the bias can be effectively improved.

[0123] See also Figure 7 Based on the above embodiments, optionally, the pixel circuit may further include: a storage capacitor Cst, which is connected between the gate of the driving transistor M1 and the first power supply line, and is used to store the gate potential of the driving transistor M1. Additionally, the pixel circuit may further include: a coupling capacitor C1, which is connected between the gate of the driving transistor M1 and the gate of the data writing transistor M2. When the data writing transistor M2 is turned off, the first scan signal S1 has a rising edge. The coupling capacitor C1 couples the voltage transition of the first scan signal S1 to the gate of the driving transistor M1 through coupling, thereby compensating for the potential drop caused by gate leakage of the driving transistor M1.

[0124] In summary, the embodiments of the present invention, by designing a new driving timing sequence for the pixel circuit and by performing special timing design simultaneously on the write frame and the hold frame, enable the first scan signal S1 to output a special 3-pulse in each display frame, and provide detailed timing relationships between these three conduction pulses and other control signals. This can effectively improve the characteristic drift of the driving transistor caused by bias, enhance display uniformity, and solve the problem of low-frequency flicker.

[0125] This invention also provides a display device, which can be driven by the pixel circuit driving method provided in any embodiment of this invention. The display device may include a display panel and a driving component. The display panel includes multiple sub-pixels, each sub-pixel including a pixel circuit and a light-emitting device. The driving component is connected to the display panel; the driving component is used to drive each pixel circuit using the pixel circuit driving method provided in any embodiment of this invention, so that each pixel circuit provides a driving current to the connected light-emitting device, driving the light-emitting device to emit light. For example, the driving component may include a driving chip. For example, the display device may be an OLED display device, specifically a computer, mobile phone, television, and wearable electronic products (such as smartwatches and smart bracelets).

[0126] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0127] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A driving method for a pixel circuit, characterized in that, The pixel circuit includes: a driving transistor, a data writing transistor, a threshold compensation transistor, and a light-emitting control transistor; the data writing transistor is connected to the first terminal of the driving transistor and is connected to a first scan signal; the threshold compensation transistor is connected between the gate and the second terminal of the driving transistor and is connected to a second scan signal; the light-emitting control transistor is connected in series with the driving transistor and is connected to a light-emitting control signal. The driving method for the pixel circuit includes: In each display frame, the control signal for the light emission has a cutoff pulse for controlling the light emission control transistor to turn off, and the control signal for the first scan signal has three turn-on pulses for controlling the data write transistor to turn on, and the three turn-on pulses of the first scan signal are all located within the cutoff pulse of the control signal; wherein, the three turn-on pulses of the first scan signal include a first pulse, a second pulse, and a third pulse that appear sequentially; In the write frame, the control of the second scan signal has a turn-on pulse for controlling the threshold compensation transistor to turn on; wherein at least a portion of the display frame is the write frame; in the write frame, the turn-on pulse of the second scan signal overlaps with the second pulse in time, but does not overlap with the first pulse and the third pulse in time; in the same write frame, the pulse width of at least one of the first pulse and the third pulse is greater than the pulse width of the second pulse.

2. The driving method for the pixel circuit according to claim 1, characterized in that, In the same write frame, the pulse widths of the first pulse and the third pulse are both greater than the pulse width of the second pulse; Preferably, in the same write frame, the pulse width of the first pulse is greater than the pulse width of the third pulse.

3. The driving method for the pixel circuit according to claim 1, characterized in that, Some of the display frames are write frames, and the rest are hold frames; The pulse width of each conduction pulse of the first scan signal in the hold frame is greater than or equal to the pulse width of the corresponding conduction pulse in the first scan signal in the write frame; Preferably, the pulse width of at least one on pulse of the first scan signal in the hold frame is greater than the pulse width of the corresponding on pulse of the first scan signal in the write frame; Preferably, the pulse width of each conduction pulse of the first scan signal in the hold frame is greater than the pulse width of the corresponding conduction pulse in the first scan signal in the write frame.

4. The driving method for the pixel circuit according to claim 1 or 3, characterized in that, Some of the display frames are write frames, and the rest of the display frames are hold frames, with multiple hold frames spaced between two adjacent write frames; In the first hold frame, the pulse width of each conduction pulse of the first scan signal is less than or equal to the pulse width of the corresponding conduction pulse in the first scan signal in the second hold frame; wherein, the first hold frame and the second hold frame are two hold frames that appear sequentially between two adjacent write frames; Preferably, the pulse width of at least one turn-on pulse of the first scan signal in the first hold frame is smaller than the pulse width of the corresponding turn-on pulse in the first scan signal in the second hold frame; Preferably, the pulse width of each conduction pulse of the first scan signal in the first hold frame is smaller than the pulse width of the corresponding conduction pulse in the first scan signal in the second hold frame.

5. The driving method for the pixel circuit according to claim 1, characterized in that, Within the same display frame, the first time interval between the end time of the third pulse and the end time of the cutoff pulse of the light emission control signal is less than the second time interval between the end time of the second pulse and the start time of the third pulse. Preferably, the first time interval is less than or equal to the first time threshold; Preferably, the first time threshold is less than or equal to 1 μs.

6. The driving method for the pixel circuit according to claim 1, characterized in that, The pixel circuit further includes: a first initialization transistor, connected to the gate of the driving transistor, and connected to a third scan signal; the driving method of the pixel circuit further includes: In the write frame, the control third scan signal has a turn-on pulse for controlling the first initialization transistor to turn on; wherein, in the write frame, the turn-on pulse of the third scan signal is located within the cutoff pulse of the light emission control signal, and the turn-on pulse of the third scan signal ends before the start of the second pulse; Preferably, the activation pulse of the third scan signal ends before the start of the first pulse; Preferably, within the same write frame, the third time interval between the end time of the first pulse and the start time of the second pulse is less than the fourth time interval between the end time of the conduction pulse of the third scan signal and the start time of the first pulse. Preferably, the third time interval is less than or equal to the second time threshold; Preferably, the second time threshold is less than or equal to 1 µs; Preferably, some of the display frames are write frames, and the remaining display frames are hold frames; the driving method for the pixel circuit further includes: In the hold frame, the control third scan signal is held at a potential used to control the first initialization transistor to turn off.

7. The driving method for the pixel circuit according to claim 1 or 6, characterized in that, Some of the display frames are write frames, and the rest are hold frames; The fifth time interval between the start time of the cutoff pulse of the light emission control signal in the hold frame and the start time of the first pulse is less than the sixth time interval between the start time of the cutoff pulse of the light emission control signal and the start time of the first pulse in the write frame. Preferably, the fifth time interval is 0.

8. The driving method for the pixel circuit according to claim 1, characterized in that, The data writing transistor is also connected to a data line; some of the display frames are the writing frames, and the rest of the display frames are holding frames. The driving method for the pixel circuit further includes: In the write frame, during the period when the first scan signal outputs the second pulse, the data line is controlled to transmit a data voltage for controlling the magnitude of the drive current generated by the drive transistor; During the hold frame, at least during the period when the first scan signal outputs the second pulse, the data line is controlled to transmit a reset voltage; Preferably, in the hold frame, before the first scan signal starts outputting the first pulse, the data line is controlled to start transmitting the reset voltage, and the reset voltage is continuously transmitted until the third pulse ends; Preferably, during the hold frame, the data line is controlled to continuously transmit the reset voltage; Preferably, the light-emitting control transistor, the driving transistor, and the light-emitting device are connected in series between a first power line and a second power line, and the first power line transmits a first power signal; a plurality of hold frames are included between two adjacent write frames; the driving method of the pixel circuit further includes: For any two hold frames between two adjacent write frames, the voltage difference between the reset voltage transmitted by the data line and the first power signal in the preceding hold frame is controlled to be less than or equal to the voltage difference between the reset voltage transmitted by the data line and the first power signal in the following hold frame.

9. The driving method for the pixel circuit according to claim 1, characterized in that, The pixel circuit further includes: a second initialization transistor, connected to the anode of the light-emitting device and connected to a fourth scan signal; the driving method of the pixel circuit further includes: In each of the display frames, the control of the fourth scan signal has at least one turn-on pulse for controlling the second initialization transistor to turn on, and each turn-on pulse of the fourth scan signal is located within the cutoff pulse of the light emission control signal; Preferably, some of the display frames are write frames, and the remaining display frames are hold frames; The driving method for the pixel circuit further includes: during the hold frame, controlling the second scan signal to maintain a potential for controlling the threshold compensation transistor to turn off.

10. A display device, characterized in that, include: A display panel and a driving component; the display panel includes multiple pixel circuits, and the driving component is connected to the display panel; The driving component is used to drive each pixel circuit using the driving method of the pixel circuit according to any one of claims 1-9.

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