Display device

Abstract

The present disclosure provides a display device in which a first transistor is a P-type MOSFET, a second transistor is an N-type MOSFET, and a gate of the first transistor, a source of the first transistor, and a drain of the second transistor are connected to each other in a plurality of electrostatic discharge circuits.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to, for example, but not limited to, display apparatus. Background Technology

[0002] Display devices are used in a variety of electronic devices, such as televisions, mobile phones, laptops, and tablets.

[0003] In display devices, various display devices are used, such as self-emissive organic light-emitting displays (OLEDs), liquid crystal displays (LCDs) that require a separate light source, and light-emitting diode displays that include light-emitting diodes (LEDs).

[0004] Recently, various anti-static circuits have been used to prevent damage to display devices due to static electricity. Specifically, static electricity can be generated during the manufacturing process of the display device. Alternatively, static electricity can be introduced into the display device from the outside after manufacturing.

[0005] Static electricity introduced into a display device can damage various components within it. To address this issue, an electrostatic discharge circuit is incorporated into the display device to release the static electricity, thereby protecting the internal components.

[0006] However, electrostatic discharge (ESD) circuits include various components. This means that these components can also be damaged by static electricity. If a component in an ESD circuit is damaged, the circuit may not function properly.

[0007] In this situation, externally introduced static electricity may not be discharged, components in the display device may be damaged by static electricity, and the display device may not be able to drive properly. Alternatively, even if the externally introduced static electricity is discharged, the display device may not be able to drive smoothly due to a damaged electrostatic discharge circuit. Summary of the Invention

[0008] This disclosure was made in view of the above-mentioned problems and other limitations associated with the relevant technology.

[0009] Therefore, one aspect of this disclosure is to provide a display device including an electrostatic discharge circuit. Specifically, one aspect of this disclosure is to provide a display device including an electrostatic discharge circuit that prevents damage from electrostatic discharge.

[0010] According to one aspect of this disclosure, the above-mentioned effects and other technical effects can be achieved by providing a display device, the display device including a display panel including a plurality of pixels and an electrostatic discharge circuit unit, and a plurality of electrostatic discharge circuits disposed in the electrostatic discharge circuit unit, wherein each of the plurality of electrostatic discharge circuits includes a first transistor and a second transistor, wherein the first transistor is a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) and the second transistor is an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), wherein each of the first transistor and the second transistor includes a gate, a source and a drain, and wherein the gate of the first transistor, the source of the first transistor and the drain of the second transistor are electrically connected to each other.

[0011] It should be understood that the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure. In the drawings: Figure 1 This is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0014] Figure 3 This is a circuit diagram of an electrostatic discharge circuit according to a conventional embodiment.

[0015] Figure 4 This shows that static electricity is introduced into the system according to... Figure 3 The circuit diagram shows the situation in the electrostatic discharge circuit.

[0016] Figure 5 It is based on Figure 3 A cross-sectional view of the first transistor in the electrostatic discharge circuit.

[0017] Figure 6 It is based on Figure 3 A cross-sectional view of the second transistor in the electrostatic discharge circuit.

[0018] Figure 7 This is a circuit diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure.

[0019] Figure 8 This shows that static electricity is introduced into the system according to... Figure 7 The circuit diagram shows the situation in the electrostatic discharge circuit.

[0020] Figure 9 This is a cross-sectional view of the fourth transistor in the electrostatic discharge circuit.

[0021] Figure 10 This is a circuit diagram of an electrostatic discharge circuit according to another embodiment of the present disclosure.

[0022] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and depictions of these elements may be enlarged. Detailed Implementation

[0023] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The order of the described process steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein, and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may be chosen solely for ease of writing and may therefore differ from the names used in actual products.

[0024] The advantages and features of this disclosure and its implementation will be illustrated by the following examples described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0025] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings to describe the examples of this disclosure are merely illustrative, and therefore, this disclosure is not limited to the details shown. Unless otherwise stated, the same reference numerals denote the same elements throughout the specification. In the following description, detailed descriptions will be omitted where such descriptive detail would unnecessarily obscure important aspects of this disclosure. Where terms such as “comprising,” “having,” and “including” are used as described in this disclosure, an additional part may be added unless “only” is used. Singular terms may include plural forms unless otherwise stated.

[0026] When interpreting a component, it is assumed to include the error range, even if there is no separate explicit description of the error range.

[0027] When describing positional relationships, for example, when using terms such as “upper,” “above,” “lower,” and “next,” one or more parts may be positioned between two other parts unless “only” or “directly” is used. Terms such as “below,” “lower,” “above,” and “upper” may be used herein to describe relationships between elements as shown in the accompanying drawings. It should be understood that these terms are spatially relative and based on the orientation depicted in the drawings.

[0028] The description of time relationships can include cases where time priority is described as "after", "following", or "before", and is not sequential unless "immediately" or "directly" is used.

[0029] Although terms such as first and second are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can be a second component within the technical concept of this disclosure.

[0030] It should be understood that although various elements may be described herein using terms such as “first,” “second,” “A,” “B,” “(a),” and “(b),” these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Furthermore, the term “may” fully encompasses all the meanings and scope of the term “capable,” and vice versa.

[0031] Features of each of the various examples disclosed herein can be partially or completely combined or integrated with each other, various interoperability and driving mechanisms are technically possible, and each example can be implemented independently of each other or can be implemented together in a related relationship.

[0032] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. All components of each display device / apparatus according to all embodiments of the present disclosure are operatively combined and configured.

[0033] Figure 1 This is a schematic perspective view of a display device 1000 according to an embodiment of the present disclosure.

[0034] The display device 1000 may include a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, and a power supply unit 500.

[0035] In the following description, the display device 1000 according to this disclosure will be an organic light-emitting display device. However, this disclosure is not limited thereto. For example, the display device according to this disclosure may be a display device other than an organic light-emitting display device.

[0036] The display panel 100 may include a display area for displaying images and a non-display area disposed outside the display area. The non-display area may surround the display area, but is not limited thereto.

[0037] Multiple gate lines GL1 to GLn (where n is a natural number greater than 1) and multiple data lines DL1 to DLm (where m is a natural number greater than 1) can be arranged in the display area. The multiple gate lines GL and the multiple data lines DL can intersect each other.

[0038] The display panel 100 may include pixel units 110 and electrostatic discharge circuit units 120. Pixel units 110 may be disposed in the display area, and electrostatic discharge circuit units 120 may be disposed in the non-display area. Pixel units 110 may extend from the display area and may also be disposed in a portion of the non-display area, but are not limited thereto.

[0039] Figure 1 The electrostatic discharge circuit unit 120 is shown disposed on one side of the pixel unit 110, but is not limited thereto. For example, the electrostatic discharge circuit unit 120 may be disposed on the other side of the pixel unit 110. Alternatively, the electrostatic discharge circuit unit 120 may be disposed on the upper or lower side of the pixel unit 110.

[0040] Pixel unit 110 may include multiple pixels P. The multiple pixels P may be disposed in the area where multiple gate lines GL and multiple data lines DL intersect. That is, the multiple pixels P may be arranged in a matrix form including multiple rows and multiple columns.

[0041] Each of the multiple pixels P can receive a scan signal through multiple gate lines GL. Additionally, each of the multiple pixels P can receive a data signal through multiple data lines DL.

[0042] The electrostatic discharge circuit unit 120 may include multiple electrostatic discharge circuits (ESDCs). The multiple EDCs can suppress static electricity introduced into the display panel 100 to protect the display panel 100 from the effects of static electricity.

[0043] The gate driver 200 can receive a gate driver control signal from the timing controller 400. The gate driver 200 can supply a scan signal to the gate line GL according to the gate driver control signal.

[0044] The gate driver 200 can be disposed in the non-display area on one or both sides of the display area of ​​the display panel 100 by means of GIP (Gate In-Panel Driver), but is not limited thereto.

[0045] The data driver 300 can receive data driver control signals and image data from the timing controller 400. The data driver 300 can convert the image data into a data voltage according to the data driver control signals. Additionally, the data driver 300 can supply the converted data voltage to the data line DL.

[0046] The timing controller 400 can control the operating timing of the gate driver 200 and the data driver 300. The timing controller 400 can generate gate driver control signals, data driver control signals and image data based on the timing signals supplied from the host system.

[0047] The timing controller 400 can supply gate driver control signals to the gate driver 200.

[0048] The gate driver control signals may include a gate start signal and a gate clock signal. The gate start signal may be a signal that controls the output timing of a first scan signal of the gate driver 200. Additionally, the gate clock signal may be a signal used to shift the gate start signal. Furthermore, the gate driver control signals may further include various signals used to control the gate driver.

[0049] The timing controller 400 can supply data driver control signals and image data to the data driver 300.

[0050] The power supply unit 500 can generate various voltages required for driving each of the display panel 100, gate driver 200, data driver 300, and timing controller 400. Furthermore, the power supply unit 500 can supply the generated voltages to each of the display panel 100, gate driver 200, data driver 300, and timing controller 400.

[0051] The power supply unit 500 can supply a high-potential voltage EVDD and a low-potential voltage EVSS to multiple pixels P of the display panel 100. The high-potential voltage EVDD and the low-potential voltage EVSS can be voltages used to drive the multiple pixels P.

[0052] The power supply unit 500 can supply the gate power supply voltage VCC, the gate high voltage VGH, and the gate low voltage VGL to the gate driver 200.

[0053] The gate power supply voltage VCC can be the voltage used to drive the gate driver 200. Additionally, the gate high voltage VGH and gate low voltage VGL can set the scan signal of the gate driver 200. Specifically, the scan signal generated by the gate driver 200 can be output as a voltage with a positive gate high voltage VGH and a negative gate low voltage VGL.

[0054] The power supply unit 500 can supply the data power voltage VCC and the data drive voltage VDD to the data driver 300.

[0055] The data power supply voltage VCC can be the voltage used to drive the data driver 300. Additionally, the data voltage of the data driver 300 can be set by the data drive voltage VDD. Specifically, the data driver 300 can receive image data from the timing controller 400 and generate a data voltage in response to the data drive voltage VDD.

[0056] Figure 2 This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0057] Reference Figure 2 A pixel P may include a driving transistor DT, a switching transistor ST, a capacitor C, and a light-emitting device ED. The driving transistor DT, the switching transistor ST, and the capacitor C may be configured to drive the light-emitting device ED.

[0058] The driving transistor DT can be positioned between the high-potential voltage line EVDDL and the light-emitting device ED. The driving transistor DT can regulate the driving current. Specifically, the driving transistor DT can regulate the current flowing from the high-potential voltage line EVDDL to the light-emitting device ED based on the voltage difference between its gate and source.

[0059] The gate of the driving transistor DT can be connected to the first electrode of the switching transistor ST. The first electrode (source or drain) can be connected to the anode of the light-emitting device ED, and the second electrode (drain or source) can be connected to the high-potential voltage line EVDDL supplied with a high-potential voltage EVDD.

[0060] The switching transistor ST can be driven by the scan signal SC of the gate line GL. When the switching transistor ST is turned on by the scan signal SC, the switching transistor ST can supply the data voltage V_data of the data line DL to the gate of the driving transistor DT.

[0061] The gate of the switching transistor ST can be connected to the gate line GL, the first electrode can be connected to the gate of the driving transistor DT, and the second electrode can be connected to the data line DL.

[0062] A capacitor C can be placed between the gate and source of the driving transistor DT. The capacitor C can store the voltage difference between the gate voltage and the source voltage of the driving transistor DT.

[0063] Figure 2 The driving transistor DT and the switching transistor ST are shown to be formed from N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but are not limited thereto. For example, the driving transistor DT and the switching transistor ST can be P-type MOSFETs.

[0064] Furthermore, the first electrode can be the source and the second electrode can be the drain, but it is not limited to these. For example, the first electrode can be the drain and the second electrode can be the source.

[0065] The light-emitting device (ED) emits light according to the current supplied through the driving transistor DT. The anode of the ED can be connected to the source of the driving transistor DT, and the cathode of the ED can be connected to the low-potential voltage line EVSSL, which is supplied with a low-potential voltage EVSS. The low-potential voltage EVSS can be a voltage lower than the high-potential voltage EVDD.

[0066] When the light-emitting device (ED) is an organic light-emitting diode (OLED), the ED may include an anode, a hole transport layer, a light-emitting layer, an electron transport layer, and a cathode.

[0067] When a voltage is applied to the anode and cathode via the driving transistor DT, the switching transistor ST, and the capacitor C, holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and can recombine with each other in the light-emitting layer. Therefore, the light-emitting device ED can emit light.

[0068] Figure 2 A pixel P comprising two transistors and one capacitor is disclosed, but is not limited thereto. For example, pixel P may include three or more transistors or two or more capacitors.

[0069] Alternatively, each of the plurality of pixels P may be further connected to wiring other than the high-potential voltage line EVDDL, the low-potential voltage line EVSSL, the gate line GL, and the data line DL to further receive voltages other than the high-potential voltage EVDD, the low-potential voltage EVSS, the scan signal SC, and the data voltage V_data.

[0070] For example, the power supply unit 500 can supply initialization voltage to multiple pixels P, and each of the multiple pixels P can further include an initialization voltage line. In this case, each of the multiple pixels P receives the initialization voltage through the initialization voltage line, and a specific electrode of the driving transistor DT or the switching transistor ST can be initialized to a specific voltage.

[0071] Figure 3 This is a circuit diagram of the electrostatic discharge circuit ESDC1 according to a conventional embodiment.

[0072] Reference Figure 3 The electrostatic discharge circuit ESDC1 may include a first transistor T1, a second transistor T2, and a resistor R.

[0073] The first transistor T1 and the second transistor T2 can be the same type of MOSFET. Figure 3 The first transistor T1 and the second transistor T2 are shown to be P-type MOSFETs, but this disclosure is not limited thereto.

[0074] The gate and source of the first transistor T1 can be connected to signal line SL, and the drain of the first transistor T1 can be connected to gate low voltage line VGLL. Gate low voltage line VGLL can be a wiring that supplies gate low voltage VGL from power supply unit 500.

[0075] The gate and drain of the second transistor T2 can be connected to the gate high voltage line VGHL, and the source of the second transistor T2 can be connected to the signal line SL. The gate high voltage line VGHL can be a wiring that supplies the gate high voltage VGH from the power supply unit 500.

[0076] The gate of the first transistor T1, the source of the first transistor T1, and the source of the second transistor T2 can be connected to the same node via signal line SL.

[0077] The signal line SL can be any of various wirings used to apply signals to the pixels P of the display panel 100.

[0078] For example, the signal line SL can be a data line DL used to apply a data voltage to the pixel P, or a wiring branch from the data line DL.

[0079] Alternatively, the signal line SL can be any of a variety of wiring used to apply a signal to the gate driver 200.

[0080] For example, the signal line SL can be a gate start signal line for applying a gate start signal to the gate driver 200 or a branch line from the gate start signal line. Alternatively, the signal line SL can be a gate clock signal line for applying a gate clock signal to the gate driver 200 or a branch line from the gate clock signal line.

[0081] The resistor R can be connected between the gate low voltage line VGLL and the gate high voltage line VGHL. That is, the resistor R can be connected between the drain of the first transistor T1 and the source of the second transistor T2.

[0082] When a high-voltage static charge flows into the electrostatic discharge circuit ESDC1, the resistor R makes the gate low-voltage line VGLL and the gate high-voltage line VGHL relatively equal to each other, compared to the high-voltage static charge. The resistor R can be several... Up to several hundred However, it is not limited to this.

[0083] Figure 4 This shows that electrostatic ES is introduced into according to Figure 3 The circuit diagram for the electrostatic discharge circuit ESDC1 is shown. Furthermore, Figure 5 It is based on Figure 3 A cross-sectional view of the first transistor T1 in the electrostatic discharge circuit ESDC1. Furthermore, Figure 6 It is based on Figure 3 A cross-sectional view of the second transistor T2 of the electrostatic discharge circuit ESDC1.

[0084] Reference Figure 4 Static electricity (ES) can be introduced into the electrostatic discharge circuit ESDC1. The static electricity (ES) can be generated during the manufacturing process of the display device 1000. Alternatively, after the display device 1000 is manufactured, the static electricity (ES) can be introduced into the display device 1000 from the outside.

[0085] Static electricity ES can be introduced into the electrostatic discharge circuit ESDC1 through the signal line SL. When static electricity ES is applied to the signal line SL, the gate and source of the first transistor T1 are connected to the signal line SL, so static electricity ES can be quickly applied to the gate and source of the first transistor T1 through the signal line SL.

[0086] In this case, refer to Figure 5 The first transistor T1 may include a gate G1, an active layer A1, a source S1, and a drain D1.

[0087] The active layer A1 can be disposed on the substrate SUB. The active layer A1 may contain at least one oxide selected from indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGO), and indium gallium oxide (IGO), but is not limited thereto.

[0088] The gate G1 can be disposed on the active layer A1. The gate G1 can contain a metallic material, such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti or Cr, but is not limited thereto.

[0089] A gate insulating layer GI can be disposed between the gate G1 and the active layer A1 to insulate the gate G1 from the active layer A1. The gate insulating layer GI can be made of silicon nitride (SiN). x ) or silicon oxide (SiO)x It can be formed by a single layer or multiple layers of ), but is not limited thereto.

[0090] The source S1 and drain D1 can be positioned on the active layer A1 while facing each other.

[0091] The passivation layer PAS is disposed between the source S1 and the gate G1, and between the drain D1 and the gate G1, and can insulate the source S1 and the drain D1 from the gate G1. In addition, each of the source S1 and the drain D1 can contact and be electrically connected to the active layer A1 through contact holes disposed in the gate insulating layer GI and the passivation layer PAS.

[0092] like Figure 4 As shown, the static electricity ES applied by the signal line SL can be rapidly applied to the gate G1 and source S1 of the first transistor T1. Therefore, the same charge can be introduced into the gate G1 and source S1 of the first transistor T1.

[0093] In other words, the same charge can be applied to the gate G1 located above the gate insulating layer GI and the active layer A1 located below the gate insulating layer GI. Therefore, the gate G1 located above the gate insulating layer GI and the active layer A1 located below the gate insulating layer GI can be uncharged. Therefore, the first transistor T1 can normally discharge electrostatic discharge ES.

[0094] Meanwhile, when static electricity ES is applied to signal line SL, since the source S2 of the second transistor T2 is connected to signal line SL, static electricity ES can be quickly applied to the source S2 of the second transistor T2.

[0095] However, compared to the source S2 of the second transistor T2, the static electricity ES can be applied to the gate G2 and the drain D2 of the second transistor T2 relatively slowly.

[0096] The static electricity ES applied to signal line SL can be applied as a resistor R through the source S1 and drain D1 of the first transistor T1. Therefore, the static electricity ES is not immediately applied to the gate G2 and drain D2 of the second transistor T2. Specifically, after the static electricity ES passes through resistor R, it can be applied to the gate G2 and drain D2 of the second transistor T2.

[0097] In other words, when static electricity ES passes through resistor R, the time it takes for static electricity ES to be transferred to the gate G2 and drain D2 of the second transistor T2 can be delayed. Therefore, compared to the source S2 of the second transistor T2, static electricity ES can be applied to the gate G2 and drain D2 of the second transistor T2 relatively slowly.

[0098] In this situation, static electricity ES is momentarily applied to the source S2 of the second transistor T2 for a short period of time, but static electricity ES is not applied to the gate G2 of the second transistor T2, and the gate G2 of the second transistor T2 can be in a floating state.

[0099] In this case, refer to Figure 6 Similar to the first transistor T1, the second transistor T2 may include a gate G2, an active layer A2, a source S2, and a drain D2.

[0100] like Figure 4 As shown, the static electricity ES applied by the signal line SL can be rapidly applied to the source S2 of the second transistor T2. However, the static electricity ES can be applied relatively slowly to the gate G2 and drain D2 of the second transistor T2. Therefore, for a short period of time, the static electricity ES is instantaneously applied to the source S2 of the second transistor T2, but the gate G2 of the second transistor T2 can be in a floating state.

[0101] Therefore, in a short period of time, charge can be introduced into the source S2 of the second transistor T2, but charge may not be introduced into the gate G2 of the second transistor T2.

[0102] In other words, in the second transistor T2, a large charge difference may occur between the gate G2 disposed above the gate insulating layer GI and the active layer A2 disposed below the gate insulating layer GI. Because the charges applied to the gate G2 disposed above the gate insulating layer GI and the active layer A2 disposed below the gate insulating layer GI are different, the gate G2 disposed above the gate insulating layer GI and the active layer A2 disposed below the gate insulating layer GI will become charged.

[0103] If a high-voltage static electricity ES is instantaneously applied to the second transistor T2 within a short period of time, the gate insulating layer GI may be damaged, and the gate insulating layer GI may fail to perform its insulating function properly. In other words, the second transistor T2 may not be driven normally.

[0104] In this situation, the gate insulating layer GI in the second transistor T2 is damaged, and the second transistor T2 may degrade. Therefore, the second transistor T2 may not properly discharge the electrostatic discharge ES, and there may be a problem that the electrostatic discharge circuit ESDC1 is not properly driven.

[0105] Furthermore, when the display device 1000 is driven, the threshold voltage of the second transistor T2 may change due to the damage to the gate insulating layer GI. Therefore, excessive current may flow in the channel region of the second transistor T2, potentially causing thermal damage.

[0106] Thermal damage may affect the wiring connected to the second transistor T2. For example, the gate low voltage line VGLL or the gate high voltage line VGHL may be affected, but this disclosure is not limited thereto.

[0107] On the other hand, resistor R is connected between the gate low voltage line VGLL and the gate high voltage line VGHL. When the display device 1000 is driven, resistor R connected between the gate low voltage line VGLL and the gate high voltage line VGHL can serve as a path for leakage current. Therefore, the power consumption of the display device 1000 can be reduced.

[0108] To address this issue, this disclosure is made public. Figure 7 The electrostatic discharge circuit ESDC2 is shown.

[0109] Reference Figure 7 The electrostatic discharge circuit ESDC2 may include a third transistor T3 and a fourth transistor T4.

[0110] The third transistor T3 and the fourth transistor T4 can be different types of MOSFETs. The third transistor T3 can be a P-type MOSFET, and the fourth transistor T4 can be an N-type MOSFET.

[0111] The gate and source of the third transistor T3 can be connected to signal line SL, and the drain of the third transistor T3 can be connected to the first gate low voltage line VGLL1. The first gate low voltage line VGLL1 can be a wiring from the power supply unit 500 that supplies the gate low voltage VGL.

[0112] The gate and source of the fourth transistor T4 can be connected to the second gate low voltage line VGLL2, and the drain of the fourth transistor T4 can be connected to the signal line SL. The second gate low voltage line VGLL2 can be a wiring branched from the first node n1 of the first gate low voltage line VGLL1. That is, the first gate low voltage line VGLL1 and the second gate low voltage line VGLL2 can be connected to the same node.

[0113] The gate, source, and drain of the third transistor T3 can be electrically connected to each other. Alternatively, the gate, source, and drain of the third transistor T3 and the fourth transistor T4 can be connected to the same node via signal line SL.

[0114] The drain of the third transistor T3, the gate of the fourth transistor T4, and the source of the fourth transistor T4 can be electrically connected to each other. Furthermore, as described above, since the second gate low voltage line VGLL2 is a branch from the first node n1 of the first gate low voltage line VGLL1, the drain of the third transistor T3, the gate of the fourth transistor T4, and the source of the fourth transistor T4 can be connected to the same node via the first gate low voltage line VGLL1 and the second gate low voltage line VGLL2.

[0115] The signal line SL can be any of various wirings used to apply signals to the pixels P of the display panel 100. For example, the signal line SL can be a data line DL used to apply data voltage to the pixel P, or a wiring branching from the data line DL.

[0116] Alternatively, the signal line SL can be any of various wirings used to apply a signal to the gate driver 200. For example, the signal line SL can be a gate start signal line or a branch line branching from the gate start signal line for applying a gate start signal to the gate driver 200. Alternatively, the signal line SL can be a gate clock signal line or a branch line branching from the gate clock signal line for applying a gate clock signal to the gate driver 200.

[0117] Figure 8 This shows that electrostatic ES is introduced into according to Figure 7 The circuit diagram for the electrostatic discharge circuit ESDC2 is shown. Furthermore, Figure 9 It is based on Figure 7 A cross-sectional view of the fourth transistor T4 of the electrostatic discharge circuit ESDC2.

[0118] Reference Figure 8 Static electricity (ES) may be introduced into the electrostatic discharge circuit ESDC2. ES can be applied to ESDC2 via signal line SL. When ES is applied to signal line SL, since the gate and source of the third transistor T3 are connected to signal line SL, ES can be rapidly applied to the gate and source of the third transistor T3 via signal line SL.

[0119] Similar to Figure 5 The first transistor T1 described herein, and the third transistor T3 may include a gate G3 (not shown), an active layer A3 (not shown), a source S3 (not shown), and a drain D3 (not shown). Additionally, a gate insulating layer GI may be disposed between the gate G3 and the active layer A3 to insulate the gate G3 from the active layer A3.

[0120] As mentioned above Figure 5As described, the static electricity ES applied by the signal line SL can be rapidly applied to the gate G3 and source S3 of the third transistor T3. Therefore, the same charge can be introduced into the gate G3 and source S3 of the third transistor T3.

[0121] In other words, the same charge can be applied to the gate G3 located above the gate insulating layer GI and the active layer A3 located below the gate insulating layer GI. Therefore, the gate G3 located above the gate insulating layer GI and the active layer A3 located below the gate insulating layer GI can be uncharged. Therefore, the third transistor T3 can normally discharge the electrostatic discharge ES.

[0122] At the same time, when static electricity ES is applied to signal line SL, the drain of the fourth transistor T4 is connected to signal line SL, so that static electricity ES can be quickly applied to the source of the fourth transistor T4.

[0123] Since the gate and source of the fourth transistor T4 are connected to the second gate low voltage line VGLL2, which branches from the first node n1 of the first gate low voltage line VGLL1, static electricity ES can be quickly applied to the gate of the fourth transistor T4.

[0124] In this case, refer to Figure 9 Similar to the first transistor T1, the fourth transistor T4 may include a gate G4, an active layer A4, a source S4, and a drain D4. A gate insulating layer GI may be disposed between the gate G4 and the active layer A4 to insulate the gate G4 from the active layer A4.

[0125] As mentioned above Figure 7 As described, the static electricity ES transferred by the second gate low-voltage line VGLL2 can be rapidly applied to the gate G4 and source S4 of the fourth transistor T4. Therefore, the same charge can be introduced into the gate G4 and source S4 of the fourth transistor T4.

[0126] In other words, the same charge can be applied to the gate G4 located above the gate insulating layer GI and the active layer A4 located below the gate insulating layer GI. Therefore, the gate G4 located above the gate insulating layer GI and the active layer A4 located below the gate insulating layer GI can be uncharged. Therefore, the fourth transistor T4 can normally discharge the electrostatic discharge ES.

[0127] In conclusion, with Figure 3 Compared to the conventional electrostatic discharge circuit ESDC1 disclosed in the paper, Figure 7The electrostatic discharge circuit ESDC2 disclosed herein can stably discharge static electricity ES by preventing damage to the components within the electrostatic discharge circuit ESDC2 caused by transient static electricity ES.

[0128] Specifically, Figure 3 The electrostatic discharge circuit ESDC1 disclosed herein uses the same type of transistors, but the electrostatic discharge circuit ESDC2 of this disclosure uses different types of transistors. Specifically, the electrostatic discharge circuit ESDC2 of this disclosure uses a third transistor T3 as a P-type MOSFET and a fourth transistor T4 as an N-type MOSFET.

[0129] therefore, Figure 3 The electrostatic discharge circuit ESDC1 disclosed herein uses a gate low voltage line VGLL and a gate high voltage line VGHL, which are wirings that apply different voltages to each other. However, the electrostatic discharge circuit ESDC2 of this disclosure can use only the gate low voltage line VGLL. Therefore, the wiring of the electrostatic discharge circuit ESDC2 can be further simplified.

[0130] In addition, as mentioned above, Figure 3 The conventional electrostatic discharge circuit ESDC1 disclosed herein uses a resistor R to make the gate low voltage line VGLL and the gate high voltage line VGHL relatively equal when a high voltage electrostatic discharge ES is introduced. However, since the electrostatic discharge circuit ESDC2 of this disclosure only uses the gate low voltage line VGLL, this resistor can be omitted. Figure 3 The resistor R in the conventional electrostatic discharge circuit ESDC1 disclosed in the paper.

[0131] The electrostatic discharge circuit ESDC2 disclosed herein can prevent electrostatic discharge due to the omission of resistor R. Figure 3 The problem of instantaneous transfer delay of electrostatic discharge ES caused by the resistor R in the conventional electrostatic discharge circuit ESDC1 disclosed in the paper is solved. In other words, the gate G4 of the fourth transistor T4 can be prevented from being momentarily floating for a short period of time.

[0132] Therefore, this disclosure can prevent damage to the gate insulating layer GI and degradation of the fourth transistor T4. Thus, the electrostatic discharge circuit ESDC2 of this disclosure can prevent damage caused by transient static electricity ES, and the electrostatic discharge circuit ESDC2 can be driven stably.

[0133] Additionally, when the display device 1000 is driven, Figure 3 The resistor R in the conventional electrostatic discharge circuit ESDC1 shown can be used as a path for leakage current. However, since the electrostatic discharge circuit ESDC2 of this disclosure does not include resistor R, leakage current can be prevented when the display device 1000 is driven. Therefore, power consumption reduction of the display device 1000 can be prevented.

[0134] Furthermore, since the electrostatic discharge circuit ESDC2 of this disclosure does not include a resistor R, the types of wiring that can be used as signal lines SL can be increased.

[0135] Specifically, Figure 3 The conventional electrostatic discharge circuit ESDC1 disclosed herein can use at least one of the data line DL, the gate start signal line, and the gate clock signal line as the signal line SL. That is, Figure 3 The conventional electrostatic discharge circuit ESDC1 disclosed herein can use wiring for applying AC voltage instead of DC voltage as signal line SL.

[0136] When the conventional electrostatic discharge circuit ESDC1 uses wiring for applying DC voltage to signal line SL, the resistor R in the conventional electrostatic discharge circuit ESDC1 can be used as a path for leakage current. In this case, the power consumption of the display device 1000 may increase. Therefore, the conventional electrostatic discharge circuit ESDC1 can use only the wiring for applying AC voltage as signal line SL.

[0137] On the other hand, as described above, the electrostatic discharge circuit ESDC2 of this disclosure can omit the configuration of resistor R. Therefore, even if the electrostatic discharge circuit ESDC2 of this disclosure uses wiring for applying DC voltage as signal line SL, there will be no problem of increased power consumption of the display device 1000 due to leakage current.

[0138] Similar to Figure 3 The conventional electrostatic discharge circuit ESDC1 disclosed herein, and the electrostatic discharge circuit ESDC2 disclosed herein, can use wiring for applying AC voltage to signal line SL. For example, the electrostatic discharge circuit ESDC2 disclosed herein can use at least one of data line DL, gate start signal line, and gate clock signal line as signal line SL, or use wiring branching from at least one of data line DL, gate start signal line, and gate clock signal line.

[0139] Furthermore, the electrostatic discharge circuit ESDC2 of this disclosure can use wiring for applying DC voltage to the signal line SL. For example, the electrostatic discharge circuit ESDC2 of this disclosure can use either the high-potential voltage line EVDDL or the low-potential voltage line EVSSL as the signal line SL, or use wiring branching from either the high-potential voltage line EVDDL or the low-potential voltage line EVSSL.

[0140] In addition, the electrostatic discharge circuit ESDC2 disclosed herein can use wiring for applying various AC or DC voltages for driving the display device 1000 as signal lines SL.

[0141] For example, when the plurality of pixels P of this disclosure further includes an initialization voltage line that receives an initialization voltage for initializing a specific electrode of a drive transistor DT or a switch transistor ST, the electrostatic discharge circuit ESDC2 of this disclosure can use the initialization voltage line or wiring branched from the initialization voltage line as a signal line SL.

[0142] exist Figure 7 In the previous work, only one electrostatic discharge circuit ESDC2 was disclosed, but this disclosure is not limited thereto. Figure 10 This is a circuit diagram of an electrostatic discharge circuit according to another embodiment of the present disclosure. (Refer to...) Figure 10 The first electrostatic discharge circuit ESDC3-1 and the second electrostatic discharge circuit ESDC3-2 can be set continuously.

[0143] The drain of the third transistor T3 in the first electrostatic discharge circuit ESDC3-1 and the drain of the third transistor T3 in the second electrostatic discharge circuit ESDC3-2 can be electrically connected to each other. The drain of the third transistor T3 in the first electrostatic discharge circuit ESDC3-1 and the drain of the third transistor T3 in the second electrostatic discharge circuit ESDC3-2 can be connected to the first gate low voltage line VGLL1.

[0144] The drain of the third transistor T3 in the first electrostatic discharge circuit ESDC3-1 and the drain of the third transistor T3 in the second electrostatic discharge circuit ESDC3-2 can be connected to the same node via the first gate low voltage line VGLL1.

[0145] The third transistor T3 of the first electrostatic discharge circuit ESDC3-1 and the third transistor T3 of the second electrostatic discharge circuit ESDC3-2 can be connected to the same first gate low voltage line VGLL1.

[0146] The gate, source, and fourth transistor T4 of the first electrostatic discharge circuit ESDC3-1, the gate, and source of the fourth transistor T4 of the second electrostatic discharge circuit ESDC3-2 can be electrically connected to each other. The gate, source, and second source of the fourth transistor T4 of the first electrostatic discharge circuit ESDC3-1, the fourth transistor T4 of the second electrostatic discharge circuit ESDC3-2, and the fourth transistor T4 of the second electrostatic discharge circuit ESDC3-2 can be connected to the second gate low-voltage line VGLL2.

[0147] The gate of the fourth transistor T4 in the first electrostatic discharge circuit ESDC3-1, the source of the fourth transistor T4 in the first electrostatic discharge circuit ESDC3-1, the gate of the fourth transistor T4 in the second electrostatic discharge circuit ESDC3-2, and the source of the fourth transistor T4 in the second electrostatic discharge circuit ESDC3-2 can be connected to the same node through the second gate low voltage line VGLL2.

[0148] The fourth transistor T4 of the first electrostatic discharge circuit ESDC3-1 and the fourth transistor T4 of the second electrostatic discharge circuit ESDC3-2 can be connected to the same second gate low voltage line VGLL2. The second gate low voltage line VGLL2 can be a wiring branched from the first node n1 of the first gate low voltage line VGLL1.

[0149] The gate and source of the third transistor T3 in the first electrostatic discharge circuit ESDC3-1 can be connected to the first signal line SL1, and the gate and source of the third transistor T3 in the second electrostatic discharge circuit ESDC3-2 can be connected to the second signal line SL2.

[0150] The drain of the fourth transistor T4 in the first electrostatic discharge circuit ESDC3-1 can be connected to the first signal line SL1, and the drain of the fourth transistor T4 in the second electrostatic discharge circuit ESDC3-2 can be connected to the second signal line SL2. That is, the first electrostatic discharge circuit ESDC3-1 and the second electrostatic discharge circuit ESDC3-2 can be connected to different signal lines SL.

[0151] The first signal line SL1 and the second signal line SL2 can be unconnected to each other.

[0152] When static electricity is introduced through the first signal line SL1, it can be discharged through the first electrostatic discharge circuit ESDC3-1. Conversely, when static electricity is introduced through the second signal line SL2, it can be discharged through the second electrostatic discharge circuit ESDC3-2.

[0153] In other words, since the first electrostatic discharge circuit ESDC3-1 and the second electrostatic discharge circuit ESDC3-2 are arranged consecutively, the number of signal lines SL through which static electricity can be introduced increases, making it easier to release the static electricity introduced into the display panel 100.

[0154] It will be apparent to those skilled in the art that this disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations can be made to this disclosure without departing from the technical concept or scope thereof. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel includes multiple pixels and an electrostatic discharge circuit unit. as well as Multiple electrostatic discharge circuits are disposed within the electrostatic discharge circuit unit. Each of the plurality of electrostatic discharge circuits includes a first transistor and a second transistor. The first transistor is a P-type MOSFET. The second transistor is an N-type MOSFET. Each of the first transistor and the second transistor includes a gate, a source, and a drain. The gate, source, and drain of the first transistor are electrically connected to each other.

2. The display device according to claim 1, wherein, Each of the plurality of electrostatic discharge circuits further includes a signal line, and The signal line is connected to the gate of the first transistor, the source of the first transistor, and the drain of the second transistor.

3. The display device of claim 2, further comprising a data driver configured to apply data voltages to the plurality of pixels via a plurality of data lines, and in, The signal line is any one of the plurality of data lines or a branch of any one of the plurality of data lines.

4. The display device according to claim 2, further comprising: A gate driver, the gate driver being configured to apply a gate signal to the plurality of pixels; as well as A timing controller configured to apply a gate start signal to the gate driver via a gate start signal line, and The signal line is either the gate start signal line or a wiring branched from the gate start signal line.

5. The display device according to claim 1, wherein, The drain of the first transistor, the gate of the second transistor, and the source of the second transistor are electrically connected to each other.

6. The display device according to claim 5, wherein, Each of the plurality of electrostatic discharge circuits also includes a power supply line, and The power line is connected to the drain of the first transistor, the gate of the second transistor, and the source of the second transistor.

7. The display device according to claim 6, further comprising: A gate driver, the gate driver being configured to apply a gate signal to the plurality of pixels; as well as A power supply unit configured to apply a gate low voltage to the gate driver, and The power line receives the low voltage at the gate.

8. The display device according to claim 7, wherein, The power line also includes a first line that receives a first voltage from the power supply unit and a second line that branches off from a first node of the first line. Wherein, the first line is connected to the drain of the first transistor, and The second line is connected to the gate and the source of the second transistor.

9. The display device according to claim 1, wherein, The plurality of electrostatic discharge circuits include a first electrostatic discharge circuit and a second electrostatic discharge circuit. The first electrostatic discharge circuit includes a first signal line, and the second electrostatic discharge circuit includes a second signal line. In the first electrostatic discharge circuit, the first signal line is connected to the gate of the first transistor, the source of the first transistor, and the drain of the second transistor. In the second electrostatic discharge circuit, the second signal line is connected to the gate of the first transistor, the source of the first transistor, and the drain of the second transistor.

10. The display device according to claim 9, wherein, The first signal line and the second signal line are not connected.

11. The display device according to claim 9, wherein, The drain of the first transistor in the first electrostatic discharge circuit is electrically connected to the drain of the first transistor in the second electrostatic discharge circuit, and Wherein, the gate and the source of the second transistor in the first electrostatic discharge circuit are electrically connected to the gate and the source of the second transistor in the second electrostatic discharge circuit.

12. The display device according to claim 11, further comprising: A gate driver, the gate driver being configured to apply a gate signal to the plurality of pixels; as well as A power supply unit configured to apply a gate low voltage to the gate driver. The first electrostatic discharge circuit includes a first line for receiving the low gate voltage and a second line branching from the first line. In the first electrostatic discharge circuit, the first line is connected to the drain of the first transistor, and In the first electrostatic discharge circuit, the second line is connected to the gate and the source of the second transistor.

13. The display device according to claim 12, wherein, The first and second lines extend into the second electrostatic discharge circuit. In the second electrostatic discharge circuit, the first line is connected to the drain of the first transistor, and In the second electrostatic discharge circuit, the second line is connected to the gate and the source of the second transistor.

14. A display device, comprising: The display panel includes multiple pixels and an electrostatic discharge circuit. as well as A gate driver that uses a power supply voltage to generate a scan signal applied to a pixel among the plurality of pixels to scan the pixel; A power cord through which the power voltage is supplied to the electrostatic discharge circuit; as well as A signal line is provided for applying a first signal to the pixel to drive the pixel, or for applying a second signal to the gate driver to control the gate driver. The electrostatic discharge circuit includes: A first transistor of the first type is turned on in response to a first logic signal; and The second transistor of the second type is turned on in response to a second logic signal opposite to the first logic signal. The gate, source, and drain of the first transistor are electrically connected to the signal line, and... The drain of the first transistor, the gate of the second transistor, and the source of the second transistor are electrically connected to the power supply line.

15. The display device of claim 14, further comprising a data driver configured to apply a data voltage to a data line connected to the pixel, and in, The signal line is the data line used to apply the first signal, including the data voltage, to the pixel, or a wiring branching from the data line.

16. The display device of claim 14, further comprising a timing controller configured to apply a gate start signal to the gate driver via a gate start signal line. in, The gate start signal is a signal that controls the timing of the scan signal, and The signal line is either the gate start signal line or a branch line from the gate start signal line used to apply the first signal, including the gate start signal, to the gate driver.

17. The display device of claim 14, further comprising a timing controller configured to apply a gate clock signal to the gate driver via a gate clock signal line. in, The gate clock signal is a signal that shifts the gate start signal applied to the gate driver to control the timing of the scan signal, and The signal line is either the gate clock signal line or a branch line that is used to apply the second signal, including the gate clock signal, to the gate driver.

18. The display device according to claim 14, wherein, The first transistor is a p-type MOSFET transistor, and The second transistor is an n-type MOSFET transistor.

19. The display device according to claim 14, further comprising: A second electrostatic discharge circuit, the second electrostatic discharge circuit including a third transistor of the first type and a fourth transistor of the second type; as well as A second signal line and a third signal are applied to a second pixel among the plurality of pixels to drive the second pixel, or a fourth signal for controlling the gate driver is applied to the gate driver through the second signal line. The gate of the third transistor, the source of the fourth transistor, and the drain of the fourth transistor are electrically connected to the second signal line, and The drain of the third transistor, the gate of the fourth transistor, and the source of the fourth transistor are electrically connected to the power supply line.

20. The display device of claim 19, further comprising a data driver, the data driver being configured to: A first data voltage is applied to the first data line connected to the pixel, and A second data voltage is applied to the second data line connected to the second pixel. in, The signal line is either a first data line or a wiring branching from the first data line used to apply the first signal, including the first data voltage, to the pixel. The second signal line is either a second data line or a branch of the second data line used to apply the third signal, including the second data voltage, to the second pixel.

Images