Pixel circuit, pixel array, display panel and electronic device

Abstract

The application discloses a pixel circuit, a pixel array, a display panel and an electronic device, and belongs to the technical field of display. The pixel circuit comprises a pixel driving unit and a plurality of light emitting units, each of the light emitting units comprises a light emitting diode and a corresponding light emitting control circuit; wherein the pixel driving unit and the plurality of light emitting control circuits in the plurality of light emitting units are connected to a first node, the light emitting diode in each of the light emitting units is connected with the corresponding light emitting control circuit; each of the light emitting control circuits is used for controlling the corresponding light emitting diode to reset and emit light, the pixel driving unit is used for providing driving current to the plurality of light emitting units, the plurality of light emitting control circuits are turned on at different times, so that the driving current flows into the plurality of light emitting diodes corresponding to the plurality of light emitting control circuits at different times, and the plurality of light emitting diodes emit light at different times.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a pixel circuit, pixel array, display panel, and electronic device. Background Technology

[0002] Glass-substrate OLED (Organic Light-Emitting Diode) displays refer to display panels where a TFT (Thin Film Transistor) backplane and OLED light-emitting devices are fabricated on a glass substrate. Glass-substrate OLEDs offer good dimensional stability and flatness, and glass exhibits superior thermal and dimensional stability compared to plastic films. This facilitates high-precision photolithography and alignment, making it suitable for high PPI (Pixels Per Inch) and miniaturized pixels.

[0003] However, the pixel circuitry and wiring of the TFT backplane in glass-substrate OLEDs occupy a relatively large area. Furthermore, due to limitations such as the minimum linewidth, minimum pixel pitch, and alignment error budget required for economical mass production of display lines, it is difficult to reduce the size of the pixel circuitry and wiring. As a result, the minimum pixel pitch achievable with the TFT backplane of glass-substrate OLEDs is relatively large, leading to a lower PPI for glass-substrate displays. Summary of the Invention

[0004] The purpose of this application is to provide a pixel circuit, pixel array, display panel, and electronic device that can increase the PPI of a glass substrate display screen.

[0005] In a first aspect, embodiments of this application provide a pixel circuit, which includes a pixel driving unit and multiple light-emitting units. Each light-emitting unit includes a light-emitting diode and a corresponding light-emitting control circuit. The pixel driving unit and the multiple light-emitting control circuits in the multiple light-emitting units are all connected to a first node. The light-emitting diode in each light-emitting unit is connected to its corresponding light-emitting control circuit. Each light-emitting control circuit is used to control the corresponding light-emitting diode to reset and emit light. The pixel driving unit is used to provide driving current to the multiple light-emitting units. The multiple light-emitting control circuits are turned on in a time-division manner, so that the driving current flows into the multiple light-emitting diodes corresponding to the multiple light-emitting control circuits in a time-division manner, causing the multiple light-emitting diodes to emit light in a time-division manner.

[0006] Secondly, embodiments of this application provide a pixel array including multiple pixel circuits as described in the first aspect.

[0007] Thirdly, embodiments of this application provide a display panel, including a glass substrate and a pixel array as described in the second aspect; the glass substrate is disposed on the pixel array.

[0008] Fourthly, embodiments of this application provide an electronic device, including a housing, a main body, and a display panel as described in the third aspect; the main body is disposed within the housing and connected to the display panel.

[0009] The pixel circuit provided in this application includes a pixel driving unit and multiple light-emitting units, each light-emitting unit including a light-emitting diode and a corresponding light-emitting control circuit. The pixel driving unit and the multiple light-emitting control circuits in the multiple light-emitting units are all connected to a first node, and the light-emitting diode in each light-emitting unit is connected to its corresponding light-emitting control circuit. Each light-emitting control circuit controls the corresponding light-emitting diode to reset and emit light. The pixel driving unit provides driving current to the multiple light-emitting units. The multiple light-emitting control circuits are turned on in a time-division manner, so that the driving current flows into the multiple light-emitting diodes corresponding to the multiple light-emitting control circuits in a time-division manner, causing the multiple light-emitting diodes to emit light in a time-division manner. Through the above pixel circuit, multiple light-emitting diodes can share a single pixel driving unit for driving and emitting light, which can reduce the number of pixel driving units, thereby reducing the number of transistors. This reduces the minimum pixel pitch achievable by the glass substrate TFT backplane, thereby increasing the PPI of the glass substrate display screen. Attached Figure Description

[0010] Figure 1 One of the schematic diagrams of a pixel circuit provided in an embodiment of this application;

[0011] Figure 2 This is one of the timing diagrams for the pixel circuit provided in the embodiments of this application;

[0012] Figure 3 A second schematic diagram of a pixel circuit provided in an embodiment of this application;

[0013] Figure 4 This is the second timing diagram of the pixel circuit provided in the embodiments of this application;

[0014] Figure 5 A third schematic diagram of the pixel circuit provided in an embodiment of this application;

[0015] Figure 6 This is the third timing diagram of the pixel circuit provided in the embodiments of this application;

[0016] Figure 7 This is a structural block diagram of a pixel array provided in an embodiment of this application;

[0017] Figure 8 This is a structural block diagram of a display panel provided in an embodiment of this application;

[0018] Figure 9 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0019] Figure 10 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0020] Figure label:

[0021] 100 - Pixel circuit, 102 - Pixel driving unit, 104 - Light-emitting unit, 106 - Light-emitting control circuit, OLED - Light-emitting diode, T1 - First transistor, T2 - Second transistor, T3 - Third transistor, T4 - Fourth transistor, T5 - Fifth transistor, T6 - Sixth transistor, T7 - ​​Seventh transistor, T8 - Eighth transistor, C1 - Storage capacitor, D - First node, S - Second node, G - Third node, S1 - First switch signal, S2 - Second switch signal, S3 - Third switch signal, S4 - Fourth switch signal, EMO - Common light emission enable signal, EMi - branch light emission enable signal, Vdata - display data signal, Vref1 - first reference voltage, Vref2 - second reference voltage, Vref3 - third reference voltage, ELVDD - first power supply voltage, ELVSS - second power supply voltage, 200 - pixel array, 300 - display panel, 302 - glass substrate, 304 - active driving layer, 306 - pixel electrode and insulating layer, 308 - light emission layer, 310 - cathode layer, 312 - encapsulation layer, 400 - electronic device, 402 - housing, 404 - main body. Detailed Implementation

[0022] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] The following is combined with Figures 1 to 10 The pixel circuits, pixel arrays, display panels, and electronic devices of the embodiments of this application will be described in detail.

[0026] like Figure 1 As shown, this application embodiment provides a pixel circuit 100. The pixel circuit 100 includes a pixel driving unit 102 and a plurality of light-emitting units 104.

[0027] Each light-emitting unit 104 includes a light-emitting diode (OLED) and a corresponding light-emitting control circuit 106.

[0028] In some feasible implementations, the pixel driving unit 102 and the plurality of light-emitting control circuits 106 in the plurality of light-emitting units 104 are all connected to the first node D.

[0029] In some feasible implementations, the light-emitting diode (OLED) in each light-emitting unit 104 is connected to the corresponding light-emitting control circuit 106.

[0030] That is, the multiple light-emitting units 104 are connected in parallel.

[0031] In some feasible implementations, each light-emitting control circuit 106 is used to control the corresponding light-emitting diode (OLED) to reset and emit light.

[0032] In some feasible implementations, the pixel driving unit 102 is used to provide driving current to a plurality of light-emitting units 104, and the light-emitting diode OLED is able to emit light under the action of the driving current.

[0033] In some feasible implementations, multiple light-emitting control circuits 106 are turned on in a time-sharing manner so that driving current flows into multiple light-emitting diodes (OLEDs) corresponding to the multiple light-emitting control circuits 106 in a time-sharing manner, so that the multiple light-emitting diodes (OLEDs) emit light in a time-sharing manner.

[0034] In this way, multiple OLEDs share a single pixel driving unit 102 for driving and emitting light, reducing the number of pixel driving units 102, thereby reducing the number of transistors and the pixel size, thus improving the display resolution and PPI. Furthermore, by controlling the time-sharing emission of multiple OLEDs, the panel can be illuminated in sections or groups, reducing the number of light-emitting units 104 that are simultaneously turned on, thereby reducing the panel's peak current and mitigating power supply network voltage drop and ground bounce noise, improving the luminous stability of large-size, high-resolution panels. Additionally, it facilitates power consumption control and time-sharing driving of the panel, thereby reducing panel power consumption and increasing driving margin.

[0035] In practical applications, multiple light-emitting diodes (OLEDs) can be located in the same pixel row, the same pixel column, or arranged in a matrix; no specific restrictions are imposed here.

[0036] Furthermore, the topology of multiple light-emitting diode (OLED) cells sharing a single pixel driving unit 102 enables the overall circuit to have good engineering feasibility and scalability. Specifically, the aforementioned topology can be easily reused, reducing circuit design complexity, and it supports multi-branch expansion, adapting to different resolutions and partition numbers.

[0037] The pixel circuit 100 according to an embodiment of this application includes a pixel driving unit 102 and a plurality of light-emitting units 104. Each light-emitting unit 104 includes a light-emitting diode (OLED) and a corresponding light-emitting control circuit 106. The pixel driving unit 102 and the plurality of light-emitting control circuits 106 in the plurality of light-emitting units 104 are all connected to a first node D. The OLED in each light-emitting unit 104 is connected to the corresponding light-emitting control circuit 106. Each light-emitting control circuit 106 controls the corresponding OLED to reset and emit light. The pixel driving unit 102 provides driving current to the plurality of light-emitting units 104. The plurality of light-emitting control circuits 106 are turned on in a time-division manner, so that the driving current flows into the plurality of OLEDs corresponding to the plurality of light-emitting control circuits 106 in a time-division manner, causing the plurality of OLEDs to emit light in a time-division manner. Through the above-described pixel circuit 100, multiple OLEDs share a single pixel driving unit 102 for driving and emitting light, which reduces the number of pixel driving units 102, thereby reducing the number of transistors. This reduces the minimum pixel pitch achievable by the glass substrate TFT backplane, thereby increasing the PPI of the glass substrate display screen.

[0038] According to some embodiments of this application, such as Figure 1 , Figure 3 and Figure 5 As shown, the pixel driving unit 102 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a storage capacitor C1.

[0039] The first terminal of the first transistor T1 is connected to the first node D, the second terminal of the first transistor T1 is connected to the second node S, and the control terminal of the first transistor T1 is connected to the third node G.

[0040] In some feasible implementations, the first transistor T1 is a driving transistor used to provide driving current to the light-emitting diode OLED during the light-emitting stage of the OLED, so as to drive the light-emitting diode OLED to emit light.

[0041] In this circuit, the first node D is the drain of the first transistor T1, the second node S is the source of the first transistor T1, and the third node G is the gate of the first transistor T1.

[0042] In some feasible implementations, the first terminal of the second transistor T2 is used to receive the display data signal Vdata, and the second terminal of the second transistor T2 is connected to the second node S.

[0043] The second transistor T2 is used to control whether the display data signal Vdata is written to the second node S.

[0044] In some feasible implementations, the first terminal of the third transistor T3 is connected to the first node D, and the second terminal of the third transistor T3 is connected to the third node G.

[0045] The third transistor T3 is used to control the first transistor T1 to perform threshold voltage compensation, so as to store the threshold voltage of the first transistor T1 in the third node G.

[0046] In some feasible implementations, the first terminal of the fourth transistor T4 is used to receive the first reference voltage Vref1, and the second terminal of the fourth transistor T4 is connected to the third node G.

[0047] The fourth transistor T4 is used to control whether the first reference voltage Vref1 is written to the third node G. In other words, the fourth transistor T4 is used to control the third node G to be reset.

[0048] In some feasible implementations, the first terminal of the fifth transistor T5 is used to receive the first power supply voltage ELVDD, and the second terminal of the fifth transistor T5 is connected to the second node S.

[0049] The fifth transistor T5 is used to control the on / off state of the transmission path from the first power supply voltage ELVDD to the first transistor T1.

[0050] In some feasible implementations, the first terminal of the storage capacitor C1 is connected to the first terminal of the fifth transistor T5, and the second terminal of the storage capacitor C1 is connected to the third node G.

[0051] The storage capacitor C1 is used to maintain the key control potential of the pixel driving unit 102.

[0052] Specifically, the storage capacitor C1 is used to store the node potential of the second node S when the display data signal Vdata is written, and to stabilize the node potential of the second node S during the light-emitting phase of the OLED to suppress leakage current and flicker problems, thereby improving the brightness stability of the driven display and the display effect at low grayscale. Furthermore, the storage capacitor C1 is less sensitive to process deviations, device leakage current, and noise disturbances, which can improve pixel yield and light emission consistency.

[0053] According to the pixel circuit 100 of this application embodiment, the pixel driving unit 102 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a storage capacitor C1. The first terminal of the first transistor T1 is connected to a first node D, the second terminal of the first transistor T1 is connected to a second node S, and the control terminal of the first transistor T1 is connected to a third node G. The first terminal of the second transistor T2 is used to receive a display data signal Vdata, and the second terminal of the second transistor T2 is connected to the second node S. The first terminal of the third transistor T3 is connected to the first node D, and the second terminal of the third transistor T3 is connected to the third node G. The first terminal of the fourth transistor T4 is used to receive a first reference voltage Vref1, and the second terminal of the fourth transistor T4 is connected to the third node G. The first terminal of the fifth transistor T5 is used to receive a first power supply voltage ELVDD, and the second terminal of the fifth transistor T5 is connected to the second node S. The first terminal of the storage capacitor C1 is connected to the first terminal of the fifth transistor T5, and the second terminal of the storage capacitor C1 is connected to the third node G. Thus, the pixel driving unit 102 can realize basic data writing, threshold voltage compensation, and light emission driving functions, thereby realizing display driving.

[0054] According to some embodiments of this application, such as Figure 1 , Figure 3 and Figure 5 As shown, each light-emitting control circuit 106 includes a sixth transistor T6 and a seventh transistor T7.

[0055] In this circuit, the first terminal of the sixth transistor T6 is connected to the first node D, the second terminal of the sixth transistor T6 is connected to the anode of the light-emitting diode OLED, and the cathode of the light-emitting diode OLED is used to receive the second power supply voltage ELVSS.

[0056] In some feasible implementations, the sixth transistor T6 is used to control whether the driving current provided by the first transistor T1 is transmitted to the corresponding light-emitting diode OLED, that is, the sixth transistor T6 is used to control whether the corresponding light-emitting diode OLED emits light.

[0057] In some feasible implementations, the first terminal of the seventh transistor T7 is used to receive the second reference voltage Vref2, and the second terminal of the seventh transistor T7 is connected to the anode of the light-emitting diode OLED.

[0058] Specifically, the seventh transistor T7 controls whether the second reference voltage Vref2 is written into the anode of the OLED, that is, the seventh transistor T7 controls the reset of the OLED anode. This effectively eliminates residual charge in pixel nodes, reduces image retention and memory effects, suppresses false emission caused by leakage, reduces the risk of abnormal bright spots and dark state lift-up, and improves the consistency of the initial pixel potential, enhancing brightness uniformity and crosstalk suppression.

[0059] According to the pixel circuit 100 of this application embodiment, each light-emitting control circuit 106 includes a sixth transistor T6 and a seventh transistor T7. The first terminal of the sixth transistor T6 is connected to the first node D, and the second terminal of the sixth transistor T6 is connected to the anode of the light-emitting diode (OLED). The cathode of the OLED is used to receive the second power supply voltage ELVSS. The first terminal of the seventh transistor T7 is used to receive the second reference voltage Vref2, and the second terminal of the seventh transistor T7 is connected to the anode of the OLED. This facilitates reset control and individual light-emitting control of each OLED, thereby achieving time-division multiplexing of light-emitting diodes and ensuring the accuracy of the display driving.

[0060] According to some embodiments of this application, such as Figure 3 As shown, the control terminals of the second transistor T2 and the third transistor T3 receive the same signal.

[0061] Specifically, the control terminal of the fourth transistor T4 is used to receive the first switch signal S1, the control terminals of the second transistor T2 and the third transistor T3 are both used to receive the second switch signal S2, the control terminal of each seventh transistor T7 is used to receive the third switch signal S3, the control terminal of the fifth transistor T5 is used to receive the common light emission enable signal EM0, and the control terminal of the sixth transistor T6 is used to receive the branch light emission enable signal EMi.

[0062] Among them, the common light emission enable signal EM0 is used to realize the global control of multiple light emission units 104, while the branch light emission enable signal EMi is used to enable each light emission unit 104 independently, so as to realize the group light emission of the light emission diode OLED and reduce the peak current and voltage drop.

[0063] Where i is the ordinal number of the sixth transistor T6.

[0064] For example, the number of the sixth transistor T6 and the number of light-emitting diodes OLED are both N, where N is a positive integer greater than 1. In this case, i is a positive integer less than or equal to N, that is, i takes any integer from 1 to N.

[0065] For ease of explanation, the multiple sixth transistors T6 are referred to as T61 to T6 respectively.N The branch light-emitting enable signals EMi corresponding to the multiple sixth transistors T6 are denoted as EM1 to EMN, and the multiple light-emitting diodes OLED are denoted as OLED1 to OLED2. N In this way, by dividing the light emission enable signal EMi into multiple branches, time-division driving of multiple light-emitting diodes (OLEDs) can be achieved, thereby enabling multiple OLEDs to share a single pixel driving unit 102.

[0066] Each working cycle of the pixel circuit 100 includes multiple working stages, each corresponding to a multiple light-emitting unit 104. In the i-th working stage, only the branch light emission enable signal EMi received by the sixth transistor T6 in the i-th light-emitting unit 104 is valid, that is, only the light-emitting diode OLED in the i-th light-emitting unit 104 emits light.

[0067] That is, in the first working stage, the branch light-emitting enable signal EM1 corresponding to the first light-emitting unit 104 outputs a valid level sequence, while the branch light-emitting enable signals corresponding to the other light-emitting units 104 are invalid. In the second working stage, the branch light-emitting enable signal EM2 corresponding to the second light-emitting unit 104 outputs a valid level sequence, while the branch light-emitting enable signals corresponding to the other light-emitting units 104 are invalid. And so on, in the Nth working stage, the branch light-emitting enable signal EMN corresponding to the Nth light-emitting unit 104 outputs a valid level sequence, while the branch light-emitting enable signals corresponding to the other light-emitting units 104 are invalid.

[0068] In some feasible implementations, before controlling the OLED to emit light in each working stage, the anode of the OLED is reset to reset the state of the OLED, thereby eliminating the influence of the previous OLED driving and isolating multiple OLEDs in terms of driving time and working state, thus ensuring the accuracy of driving display.

[0069] In some feasible implementations, the timing control logic is the same across different working stages.

[0070] In other words, the working timing of the pixel circuit 100 is characterized by a cyclic timing structure of "reset → drive one light-emitting diode (OLED) → OLED emits light → reset → drive the next light-emitting diode (OLED) → OLED emits light".

[0071] For example, both the sixth transistor T6 and the seventh transistor T7 are PMOS (P-channel metal-oxide-semiconductor). In this case, the operating timing of the pixel circuit 100 during a frame or line refresh process can be as follows: Figure 2 As shown. In the first operating phase P1, the third switching signal S3 first goes low, and multiple seventh transistors T7 are turned on, OLED1 to OLED... N Simultaneously, the anode of OLED1 is reset, EM1 goes low again, T61 turns on, and OLED1 emits light. During the second operating phase P2, the third switching signal S3 first goes low, and multiple seventh transistors T7 turn on, illuminating OLED1. N Simultaneously, the anode is reset, EM2 goes low again, T62 turns on, and OLED2 emits light. This process continues in the Nth operating phase, P... N Internally, the third switch signal S3 first goes low, and multiple seventh transistors T7 are turned on, OLED1 to OLED... N The anode is simultaneously reset, EMN goes low again, T6 N Conductivity, OLED N Glowing light.

[0072] Specifically, when the control terminals of the second transistor T2 and the third transistor T3 receive the same signal, each operating phase may include a reset period, a voltage compensation and data writing period, and a light emission period.

[0073] During the i-th operating phase, in the reset period, the third node G and the anode of the OLED are reset. In the voltage compensation and data writing period, the anode of the OLED continues to reset, and the first transistor T1 performs threshold voltage compensation and writes display data. In the light-emitting period, the OLED in the i-th light-emitting unit 104 emits light, while the other OLEDs do not emit light.

[0074] During the reset period and the voltage compensation and data writing period, the common light emission enable signal EM0 and the branch light emission enable signal EMi are both in an invalid state, and the fifth transistor T5 and the sixth transistor T6 are both turned off to avoid the light emission diode OLED from emitting light incorrectly.

[0075] In some feasible implementations, the level of the display data signal Vdata is stabilized during display data writing to provide the grayscale data required for the display driver.

[0076] In some feasible implementations, the validity period of the second switch signal S2 is located within the stable level range of the display data signal Vdata, or the validity period of the second switch signal S2 at least partially overlaps with the stable level range of the display data signal Vdata. This improves the reliability and noise immunity of writing the display data signal Vdata, thereby reducing flickering and grayscale deviation problems caused by write errors.

[0077] According to the pixel circuit 100 of this application embodiment, the control terminal of the fourth transistor T4 is used to receive the first switch signal S1, the control terminals of the second transistor T2 and the third transistor T3 are both used to receive the second switch signal S2, the control terminals of each of the seventh transistors T7 in the plurality of light-emitting control circuits 106 are all used to receive the third switch signal S3, the control terminal of the fifth transistor T5 is used to receive the common light-emitting enable signal EMO, and the control terminal of the sixth transistor T6 is used to receive the branch light-emitting enable signal EMi. Each working cycle of the pixel circuit 100 includes multiple working stages, each working stage including a reset period, a voltage compensation and data writing period, and a light-emitting period. In the i-th working stage: during the reset period, the third node G and the anode of the light-emitting diode OLED are controlled to be reset. During the voltage compensation and data writing period, the anode of the light-emitting diode OLED is controlled to remain reset, and the first transistor T1 is controlled to perform threshold voltage compensation and display data writing. During the light-emitting period, only the light-emitting diode OLED in the i-th light-emitting unit 104 is controlled to emit light, where i is a positive integer greater than or equal to 1. In this way, time-division driving of multiple light-emitting diodes (OLEDs) is achieved, allowing multiple OLEDs to share a single pixel driving unit 102. This reduces the number of pixel driving units 102, the number of transistors, and the minimum pixel pitch, thereby increasing the PPI of the glass substrate display.

[0078] According to some embodiments of this application, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors.

[0079] Specifically, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all PMOS transistors.

[0080] At this point, during the i-th working phase:

[0081] During the reset period, both the first switch signal S1 and the third switch signal S3 go low, the fourth transistor T4 and the seventh transistor T7 are turned on, the first reference voltage Vref1 is written to the third node G, and the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED, so as to reset the third node G and the anode of the light-emitting diode OLED.

[0082] The second reference voltage Vref2 is less than the turn-on voltage of the light-emitting diode (OLED) to avoid accidental emission.

[0083] During the voltage compensation and data writing period, the first switch signal S1 goes high, the fourth transistor T4 is turned off, the third switch signal S3 remains low, the seventh transistor T7 remains on, the second switch signal S2 goes low, the second transistor T2 and the third transistor T3 are both turned on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G to perform threshold voltage compensation and display data writing for the first transistor T1.

[0084] During the light-emitting period, the third switch signal S3 goes high, the seventh transistor T7 is turned off, the common light-emitting enable signal EM0 and the branch light-emitting enable signal EMi of the i-th light-emitting unit 104 both go low, the fifth transistor T5 and the sixth transistor T6 in the i-th light-emitting unit 104 both turn on, and the driving current flows only into the light-emitting diode OLED in the i-th light-emitting unit 104 to drive the light-emitting diode OLED in the i-th light-emitting unit 104 to emit light.

[0085] For example, the operating timing of the pixel circuit 100 during a frame or line refresh process can be as follows: Figure 4 As shown.

[0086] Specifically, during the first operating phase P1: In the reset period t1, both the first switch signal S1 and the third switch signal S3 go low, the fourth transistor T4 and the seventh transistor T7 are both turned on, the first reference voltage Vref1 is written to the third node G, and the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED. In the voltage compensation and data writing period t2, the first switch signal S1 goes high, the fourth transistor T4 is turned off, the third switch signal S3 remains low, the seventh transistor T7 remains on, the second switch signal S2 goes low, the second transistor T2 and the third transistor T3 are both turned on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. In the light-emitting period t3, the third switch signal S3 goes high, the seventh transistor T7 is turned off, EM1 and the common light-emitting enable signal EM0 both go low, T61 and the fifth transistor T5 are both turned on, and OLED1 emits light.

[0087] In some feasible implementations, during the second operating phase P2: during the reset period t1, both the first switch signal S1 and the third switch signal S3 go low, both the fourth transistor T4 and the seventh transistor T7 are turned on, the first reference voltage Vref1 is written to the third node G, and the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED. During the voltage compensation and data writing period t2, the first switch signal S1 goes high, the fourth transistor T4 is turned off, the third switch signal S3 remains low, the seventh transistor T7 remains on, the second switch signal S2 goes low, both the second transistor T2 and the third transistor T3 are turned on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. During the light-emitting period t3, the third switch signal S3 goes high, the seventh transistor T7 is turned off, EM2 and the common light-emitting enable signal EM0 both go low, T62 and the fifth transistor T5 are turned on, and OLED2 emits light.

[0088] In some feasible implementations, in the Nth working phase P N Internally: During the reset period t1, both the first switch signal S1 and the third switch signal S3 go low, the fourth transistor T4 and the seventh transistor T7 are both turned on, the first reference voltage Vref1 is written to the third node G, and the second reference voltage Vref2 is written to the anode of the light-emitting diode (OLED). During the voltage compensation and data writing period t2, the first switch signal S1 goes high, the fourth transistor T4 is turned off, the third switch signal S3 remains low, the seventh transistor T7 remains on, the second switch signal S2 goes low, and both the second transistor T2 and the third transistor T3 are turned on. The display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. During the light-emitting period t3, the third switch signal S3 goes high, the seventh transistor T7 is turned off, EMN and the common light-emitting enable signal EM0 both go low, and T6... N Both the fifth transistor T5 and the OLED are turned on. N Glowing light.

[0089] According to the pixel circuit 100 of the present application embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors. During the i-th operating phase: During the reset phase, by controlling the first switch signal S1 and the third switch signal S3 to both go low, the fourth transistor T4 and the seventh transistor T7 are turned on, and the first reference voltage Vref1 is written to the third node G, and the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED; During the voltage compensation and data writing phase, by controlling the first switch signal S1 to go high and the third switch signal S3 to remain low, the fourth transistor T4 is turned off, the seventh transistor T7 remains on, and by controlling the second switch signal S2 to go low, the second transistor T2 and the third transistor T3 are turned on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G; During the light emission phase, by controlling the third switch signal S3 to go high, the seventh transistor T7 is turned off, and by controlling the common light emission enable signal EM0 and the branch light emission enable signal EMi of the i-th light emission unit 104 to both go low, the fifth transistor T5 and the sixth transistor T6 in the i-th light emission unit 104 are turned on, and the driving current is controlled to flow only into the light-emitting diode OLED in the i-th light emission unit 104. In this way, time-division driving of multiple light-emitting diodes (OLEDs) is achieved, allowing multiple OLEDs to share a single pixel driving unit 102. This reduces the number of pixel driving units 102, the number of transistors, and the minimum pixel pitch, thereby increasing the PPI of the glass substrate display.

[0090] According to some embodiments of this application, such as Figure 5 As shown, the pixel driving unit 102 also includes an eighth transistor T8.

[0091] The first terminal of the eighth transistor T8 is used to receive the third reference voltage Vref3, and the second terminal of the eighth transistor T8 is connected to the second node S.

[0092] In some feasible implementations, the eighth transistor T8 is used to control whether the third reference voltage Vref3 is written to the second node S. That is, the eighth transistor T8 is used to control the second node S, i.e., the source of the first transistor T1, to reset, so as to improve the low-frequency flicker problem.

[0093] In practical applications, the first reference voltage Vref1, the second reference voltage Vref2, and the third reference voltage Vref3 can be adjusted or programmably controlled to adapt to different refresh rates, brightness modes, and compensation strategies, thereby improving the configurability of the panel.

[0094] In some feasible implementations, the control terminal of the second transistor T2 and the control terminal of the third transistor T3 receive different signals.

[0095] Specifically, the control terminal of the fourth transistor T4 is used to receive the first switch signal S1, the control terminal of the second transistor T2 is used to receive the second switch signal S2, the control terminals of the eighth transistor T8 and each of the seventh transistors T7 are used to receive the third switch signal S3, the control terminal of the third transistor T3 is used to receive the fourth switch signal S4, the control terminal of the fifth transistor T5 is used to receive the common light emission enable signal EM0, and the control terminal of the sixth transistor T6 is used to receive the branch light emission enable signal EMi.

[0096] In some feasible implementations, when the control terminals of the second transistor T2 and the third transistor T3 receive different signals, each working cycle of the pixel circuit 100 includes multiple working stages, and each working stage includes a reset period, a voltage compensation and data writing period, a voltage compensation and reset period, and a light emission period.

[0097] During the i-th working phase, the third node G is reset during the reset period. During the voltage compensation and data writing period, the first transistor T1 performs threshold voltage compensation and writes display data. During the voltage compensation and reset period, the first transistor T1 continues to perform threshold voltage compensation, and the second node S and the anode of the OLED are reset. During the light emission period, the OLED in the i-th light emission unit 104 emits light, while the other OLEDs do not emit light.

[0098] According to the pixel circuit 100 of this application embodiment, the pixel driving unit 102 further includes an eighth transistor T8. The first terminal of the eighth transistor T8 is used to receive a third reference voltage Vref3, and the second terminal of the eighth transistor T8 is connected to the second node S. The control terminal of the fourth transistor T4 is used to receive a first switching signal S1, the control terminal of the second transistor T2 is used to receive a second switching signal S2, the control terminals of the eighth transistor T8 and each of the seventh transistors T7 in the plurality of light-emitting control circuits are used to receive a third switching signal S3, the control terminal of the third transistor T3 is used to receive a fourth switching signal S4, the control terminal of the fifth transistor T5 is used to receive a common light-emitting enable signal EMO, and the control terminal of the sixth transistor T6 is used to receive a branch light-emitting enable signal EMi. Each operating cycle of the pixel circuit 100 includes multiple operating stages, each operating stage including a reset period, a voltage compensation and data writing period, a voltage compensation and reset period, and a light-emitting period. During the i-th working phase: During the reset period, the third node G is reset; during the voltage compensation and data writing period, the first transistor T1 is controlled to perform threshold voltage compensation and display data writing; during the voltage compensation and reset period, the first transistor T1 continues to perform threshold voltage compensation, and the second node S and the anode of the OLED are reset; during the light emission period, only the OLED in the i-th light emission unit 104 is controlled to emit light, where i is a positive integer greater than or equal to 1. In this way, while achieving time-division driving of multiple OLEDs, the threshold voltage compensation time of the first transistor T1 is increased. This reduces the number of transistors, thereby increasing the PPI of the display screen, and improves the accuracy of display driving. Furthermore, resetting the source of the driving transistor before controlling the OLED to emit light can improve the low-frequency flicker problem.

[0099] According to some embodiments of this application, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors, and the third transistor T3 and the fourth transistor T4 are both N-type transistors.

[0100] Specifically, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all PMOS, and the third transistor T3 and the fourth transistor T4 are both NMOS (N-Channel Metal Oxide Semiconductor).

[0101] At this point, during the i-th working phase:

[0102] During the reset period, the first switch signal S1 goes high, the fourth transistor T4 turns on, and the first reference voltage Vref1 is written to the third node G to reset the third node G.

[0103] During the voltage compensation and data writing period, the first switch signal S1 goes low, the fourth transistor T4 is turned off, the second switch signal S2 goes low, the second transistor T2 is turned on, the fourth switch signal S4 goes high, the third transistor T3 is turned on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G to perform threshold voltage compensation and display data writing for the first transistor T1.

[0104] During the voltage compensation and reset period, the fourth switch signal S4 remains high, the third transistor T3 remains on, and the threshold voltage of the first transistor T1 continues to be written to the third node G to continue threshold voltage compensation for the first transistor T1. Thus, continuing threshold voltage compensation for the first transistor T1 after the display data is written improves the potential stability of the third node G and enhances grayscale retention capability.

[0105] Furthermore, during the voltage compensation and reset period, the third switch signal S3 goes low, and both the seventh transistor T7 and the eighth transistor T8 are turned on. The second reference voltage Vref2 is written to the anode of the OLED to reset the anode of the OLED. Simultaneously, the third reference voltage Vref3 is written to the second node S to reset the second node S. In this way, the reset actions of the OLED and the second node S are completed before the OLED's light-emitting phase, which reduces the brightness jump caused by the OLED's light-emitting transient and improves the low-frequency flicker problem.

[0106] During the light-emitting period, the third switch signal S3 goes high, the seventh transistor T7 and the eighth transistor T8 are both turned off, the fourth switch signal S4 goes low, the third transistor T3 is turned off, the common light-emitting enable signal EM0 and the branch light-emitting enable signal EMi of the i-th light-emitting unit 104 both go low, the fifth transistor T5 and the sixth transistor T6 in the i-th light-emitting unit 104 are both turned on, and the driving current flows only into the light-emitting diode OLED in the i-th light-emitting unit 104 to drive the light-emitting diode OLED in the i-th light-emitting unit 104 to emit light.

[0107] For example, the operating timing of the pixel circuit 100 during a frame or line refresh process can be as follows: Figure 6 As shown.

[0108] Specifically, during the first operating phase P1: In the reset period t1, the first switch signal S1 goes high, the fourth transistor T4 turns on, and the first reference voltage Vref1 is written to the third node G. In the voltage compensation and data writing period t2, the first switch signal S1 goes low, the fourth transistor T4 turns off, the second switch signal S2 goes low, the second transistor T2 turns on, the fourth switch signal S4 goes high, the third transistor T3 turns on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. In the voltage compensation and reset period t4, the fourth switch signal S4 remains high, the third transistor T3 remains on, the threshold voltage of the first transistor T1 continues to be written to the third node G, the third switch signal S3 goes low, the seventh transistor T7 and the eighth transistor T8 both turn on, the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED, and the third reference voltage Vref3 is written to the second node S. During the light-emitting period t3, the third switch signal S3 goes high and the fourth switch signal S4 goes low. The seventh transistor T7, the eighth transistor T8 and the third transistor T3 are all turned off. EM1 and the common light-emitting enable signal EM0 both go low. T61 and the fifth transistor T5 are both turned on, and OLED1 emits light.

[0109] In some feasible implementations, during the second operating phase P2: during the reset period t1, the first switch signal S1 goes high, the fourth transistor T4 turns on, and the first reference voltage Vref1 is written to the third node G. During the voltage compensation and data writing period t2, the first switch signal S1 goes low, the fourth transistor T4 turns off, the second switch signal S2 goes low, the second transistor T2 turns on, the fourth switch signal S4 goes high, the third transistor T3 turns on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. During the voltage compensation and reset period t4, the fourth switch signal S4 remains high, the third transistor T3 remains on, the threshold voltage of the first transistor T1 continues to be written to the third node G, the third switch signal S3 goes low, the seventh transistor T7 and the eighth transistor T8 both turn on, the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED, and the third reference voltage Vref3 is written to the second node S. During the light-emitting period t3, the third switch signal S3 goes high and the fourth switch signal S4 goes low. The seventh transistor T7, the eighth transistor T8 and the third transistor T3 are all turned off. EM2 and the common light-emitting enable signal EM0 both go low. T62 and the fifth transistor T5 are both turned on, and OLED2 emits light.

[0110] In some feasible implementations, in the Nth working phase P NInternally: During the reset period t1, the first switch signal S1 goes high, the fourth transistor T4 turns on, and the first reference voltage Vref1 is written to the third node G. During the voltage compensation and data writing period t2, the first switch signal S1 goes low, the fourth transistor T4 turns off, the second switch signal S2 goes low, the second transistor T2 turns on, the fourth switch signal S4 goes high, and the third transistor T3 turns on. The display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. During the voltage compensation and reset period t4, the fourth switch signal S4 remains high, the third transistor T3 remains on, the threshold voltage of the first transistor T1 continues to be written to the third node G, the third switch signal S3 goes low, the seventh transistor T7 and the eighth transistor T8 both turn on, the second reference voltage Vref2 is written to the anode of the light-emitting diode OLED, and the third reference voltage Vref3 is written to the second node S. During the light-emitting period t3, the third switch signal S3 goes high, the fourth switch signal S4 goes low, the seventh transistor T7, the eighth transistor T8, and the third transistor T3 are all turned off, and EMN and the common light-emitting enable signal EM0 both go low. T6 N Both the fifth transistor T5 and the OLED are turned on. N Glowing light.

[0111] According to the pixel circuit 100 of this application embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors, and the third transistor T3 and the fourth transistor T4 are both N-type transistors. During the i-th operating phase: during the reset period, by controlling the first switch signal S1 to go high, the fourth transistor T4 is turned on, and the first reference voltage Vref1 is written to the third node G. During the voltage compensation and data writing period, by controlling the first switch signal S1 to go low, the fourth transistor T4 is turned off, and by controlling the second switch signal S2 to go low and the fourth switch signal S4 to go high, the second transistor T2 and the third transistor T3 are turned on, and the display data signal Vdata and the threshold voltage of the first transistor T1 are both written to the third node G. During the voltage compensation and reset period, by keeping the fourth switch signal S4 at a high level, the third transistor T3 remains on, and the threshold voltage of the first transistor T1 continues to be written to the third node G. Simultaneously, by changing the third switch signal S3 to a low level, the seventh transistor T7 and the eighth transistor T8 are turned on, and the second reference voltage Vref2 is written to the anode of the OLED, while the third reference voltage Vref3 is written to the second node S. During the light emission period, by changing the third switch signal S3 to a high level and the fourth switch signal S4 to a low level, the seventh transistor T7, the eighth transistor T8, and the third transistor T3 are turned off. Furthermore, by changing the common light emission enable signal EM0 and the branch light emission enable signal EMi of the i-th light emission unit 104 to a low level, the fifth transistor T5 and the sixth transistor T6 in the i-th light emission unit 104 are turned on, ensuring that the driving current flows only into the OLED in the i-th light emission unit 104. This enables time-division driving of multiple OLEDs, reducing the number of transistors and increasing the PPI of the display. Furthermore, it increases the threshold voltage compensation time of the first transistor T1, improving the accuracy of the display driving. In addition, resetting the source of the driving transistor before controlling the OLED to emit light can improve the low-frequency flicker problem.

[0112] According to some embodiments of this application, such as Figure 7 As shown, this application embodiment also provides a pixel array 200. The pixel array 200 includes a plurality of pixel circuits 100 as described in any of the above embodiments. The pixel array 200 provided in this application embodiment includes the pixel circuits 100 as described in any of the above embodiments and can achieve the same technical effect; therefore, to avoid repetition, it will not be described again here.

[0113] According to some embodiments of this application, such as Figure 8As shown in the figure, this application embodiment also provides a display panel 300. The display panel 300 includes a glass substrate 302 and the pixel array 200 from the above embodiments. The display panel 300 provided in this application embodiment includes the pixel array 200 from the above embodiments and achieves the same technical effects; therefore, to avoid repetition, it will not be described again here.

[0114] The glass substrate 302 is disposed on the pixel array 200.

[0115] In some feasible implementations, the number of glass substrates 302 may be two, and the pixel array 200 is disposed between the two glass substrates 302.

[0116] Specifically, such as Figure 9 As shown, the display panel 300 may specifically include a glass substrate 302, an active driving layer 304, a pixel electrode and insulating layer 306, a light-emitting layer 308, a cathode layer 310, and an encapsulation layer 312.

[0117] The glass substrate 302 is used to provide mechanical support and a process platform.

[0118] In some feasible implementations, the active driving layer 304 is the TFT backplane.

[0119] In some feasible implementations, the pixel electrode and the insulating layer 306 are used to define the sub-pixel region and complete the electrical connection.

[0120] In some feasible implementations, the light-emitting layer 308 includes a hole and electron transport layer for emitting RGB (Red-Green-Blue, three primary colors) light or white light, and may also be provided with a color filter.

[0121] In some feasible implementations, the cathode layer 310 may be made of a thin metal to balance transmittance and resistance.

[0122] In some feasible implementations, the encapsulation layer 312 is used to isolate water and oxygen in order to extend the service life of the display panel 300 and improve the operational reliability of the display panel 300.

[0123] In some feasible implementations, the pixel array 200 is disposed within the active driving layer 304, the pixel electrode and insulating layer 306, the light-emitting layer 308, and the cathode layer 310.

[0124] According to some embodiments of this application, such as Figure 10As shown in the figure, this application embodiment also provides an electronic device 400. The electronic device 400 includes a housing 402, a main body 404, and a display panel 300 as described in the above embodiments. The electronic device 400 provided in this application embodiment includes the display panel 300 as described in the above embodiments and achieves the same technical effects; therefore, to avoid repetition, it will not be described again here.

[0125] The main body 404 is housed inside the housing 402 and is connected to the display panel 300.

[0126] It should be noted that the electronic device 400 in this application embodiment includes mobile electronic devices and non-mobile electronic devices.

[0127] In practical applications, the electronic device 400 can be a terminal or other devices besides a terminal. For example, the electronic device 400 can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments of this application do not specifically limit it.

[0128] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0129] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes a pixel driving unit and multiple light-emitting units, each of which includes a light-emitting diode and a corresponding light-emitting control circuit. The pixel driving unit and the multiple light-emitting control circuits in the multiple light-emitting units are all connected to the first node, and the light-emitting diode in each light-emitting unit is connected to the corresponding light-emitting control circuit. Each of the light-emitting control circuits is used to control the corresponding light-emitting diode to reset and emit light. The pixel driving unit is used to provide driving current to the plurality of light-emitting units. The plurality of light-emitting control circuits are turned on in a time-division manner so that the driving current flows into the plurality of light-emitting diodes corresponding to the plurality of light-emitting control circuits in a time-division manner, so that the plurality of light-emitting diodes emit light in a time-division manner.

2. The pixel circuit according to claim 1, characterized in that, The pixel driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor; The first terminal of the first transistor is connected to the first node, the second terminal of the first transistor is connected to the second node, and the control terminal of the first transistor is connected to the third node. The first terminal of the second transistor is used to receive display data signals, and the second terminal of the second transistor is connected to the second node; The first terminal of the third transistor is connected to the first node, and the second terminal of the third transistor is connected to the third node; The first terminal of the fourth transistor is used to receive the first reference voltage, and the second terminal of the fourth transistor is connected to the third node; The first terminal of the fifth transistor is used to receive the first power supply voltage, and the second terminal of the fifth transistor is connected to the second node; The first end of the storage capacitor is connected to the first end of the fifth transistor, and the second end of the storage capacitor is connected to the third node.

3. The pixel circuit according to claim 2, characterized in that, Each of the light-emitting control circuits includes a sixth transistor and a seventh transistor; The first terminal of the sixth transistor is connected to the first node, the second terminal of the sixth transistor is connected to the anode of the light-emitting diode, and the cathode of the light-emitting diode is used to receive the second power supply voltage; The first terminal of the seventh transistor is used to receive the second reference voltage, and the second terminal of the seventh transistor is connected to the anode of the light-emitting diode.

4. The pixel circuit according to claim 3, characterized in that, The control terminal of the fourth transistor is used to receive the first switch signal, the control terminals of the second transistor and the third transistor are both used to receive the second switch signal, the control terminals of each of the seventh transistors in the plurality of light-emitting control circuits are all used to receive the third switch signal, the control terminal of the fifth transistor is used to receive the common light-emitting enable signal, and the control terminal of the sixth transistor is used to receive the branch light-emitting enable signal. Each working cycle of the pixel circuit includes multiple working stages, and each working stage includes a reset period, a voltage compensation and data writing period, and a light emission period. During the i-th working phase: During the reset period, the third node and the anode of the light-emitting diode are controlled to be reset; During the voltage compensation and data writing period, the anode of the light-emitting diode is kept reset, and the first transistor is controlled to perform threshold voltage compensation and display data writing. During the light-emitting period, only the light-emitting diode in the i-th light-emitting unit is controlled to emit light, where i is a positive integer greater than or equal to 1.

5. The pixel circuit according to claim 4, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type transistors; during the i-th operating phase: During the reset period, by controlling the first switch signal and the third switch signal to both become low level, the fourth transistor and the seventh transistor are turned on, and the first reference voltage is written to the third node, and the second reference voltage is written to the anode of the light-emitting diode; During the voltage compensation and data writing period, by controlling the first switch signal to go high and the third switch signal to stay low, the fourth transistor is turned off and the seventh transistor is kept on. By controlling the second switch signal to go low, the second transistor and the third transistor are turned on, and the display data signal and the threshold voltage of the first transistor are both written to the third node. During the light-emitting period, the seventh transistor is turned off by controlling the third switch signal to go high, and the fifth transistor and the sixth transistor in the i-th light-emitting unit are turned on by controlling the common light-emitting enable signal and the branch light-emitting enable signal of the i-th light-emitting unit to go low, thereby controlling the driving current to flow only into the light-emitting diode in the i-th light-emitting unit.

6. The pixel circuit according to claim 3, characterized in that, The pixel driving unit further includes an eighth transistor; The first terminal of the eighth transistor is used to receive the third reference voltage, and the second terminal of the eighth transistor is connected to the second node; The control terminal of the fourth transistor is used to receive the first switch signal, the control terminal of the second transistor is used to receive the second switch signal, the control terminals of the eighth transistor and each of the seventh transistors in the plurality of light-emitting control circuits are used to receive the third switch signal, the control terminal of the third transistor is used to receive the fourth switch signal, the control terminal of the fifth transistor is used to receive the common light-emitting enable signal, and the control terminal of the sixth transistor is used to receive the branch light-emitting enable signal. Each working cycle of the pixel circuit includes multiple working stages, and each working stage includes a reset period, a voltage compensation and data writing period, a voltage compensation and reset period, and a light emission period. During the i-th working phase: During the reset period, the third node is controlled to reset; During the voltage compensation and data writing period, the first transistor is controlled to perform threshold voltage compensation and display data writing; During the voltage compensation and reset period, the first transistor is controlled to continue performing threshold voltage compensation, and the second node and the anode of the light-emitting diode are controlled to be reset. During the light-emitting period, only the light-emitting diode in the i-th light-emitting unit is controlled to emit light, where i is a positive integer greater than or equal to 1.

7. The pixel circuit according to claim 6, characterized in that, The first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type transistors, and the third transistor and the fourth transistor are both N-type transistors; During the i-th working phase: During the reset period, by controlling the first switch signal to go high, the fourth transistor is turned on, and the first reference voltage is written to the third node. During the voltage compensation and data writing period, the first switch signal is controlled to go low to turn off the fourth transistor, and the second switch signal is controlled to go low and the fourth switch signal is controlled to go high to turn on the second transistor and the third transistor, thereby controlling the display data signal and the threshold voltage of the first transistor to be written to the third node. During the voltage compensation and reset period, by controlling the fourth switch signal to remain high, the third transistor is kept on, and the threshold voltage of the first transistor is controlled to continue to be written to the third node. By controlling the third switch signal to become low, the seventh transistor and the eighth transistor are turned on, and the second reference voltage is controlled to be written to the anode of the light-emitting diode. The third reference voltage is written to the second node. During the light-emitting period, by controlling the third switch signal to go high and the fourth switch signal to go low, the seventh transistor, the eighth transistor, and the third transistor are turned off. By controlling the common light-emitting enable signal and the branch light-emitting enable signal of the i-th light-emitting unit to go low, the fifth transistor and the sixth transistor in the i-th light-emitting unit are turned on, and the driving current is controlled to flow only into the light-emitting diode in the i-th light-emitting unit.

8. A pixel array, characterized in that, It includes multiple pixel circuits as described in any one of claims 1 to 7.

9. A display panel, characterized in that, Includes a glass substrate and the pixel array as described in claim 8; The glass substrate is disposed on the pixel array.

10. An electronic device, characterized in that, Includes a housing, a main body, and a display panel as described in claim 9; The main body is disposed inside the housing and is connected to the display panel.

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