Display device and display driving method

Abstract

Disclosed are a display device and a display driving method. The display device includes a display panel in which a plurality of subpixels driven by a subpixel circuit including a driving transistor are arranged in a display area; a data driving circuit that supplies a data voltage during a display driving period and a first sensing data voltage during a sensing driving period through a plurality of data lines connected to the plurality of subpixels; a gate driving circuit that supplies a gate signal through a plurality of gate lines connected to the plurality of subpixels; a power management circuit that supplies power required to drive the display panel, the data driving circuit, and the gate driving circuit; and a switching circuit that generates a second sensing data voltage using an auxiliary voltage transmitted through a plurality of auxiliary lines and the first sensing data voltage transmitted through the plurality of data lines by controlling a connection between the plurality of auxiliary lines and the plurality of data lines extended from the power management circuit.

Description

Technical Field

[0001] Exemplary embodiments of this disclosure relate to display devices and display driving methods, and more specifically, to display devices and display driving methods capable of effectively compensating for and checking display devices by shortening the threshold voltage sensing time of the driving transistor. Background Technology

[0002] Display devices used to display images using digital data include liquid crystal displays (LCDs) that use liquid crystals and organic light-emitting display devices that use organic light-emitting diodes (OLEDs).

[0003] In display devices, organic light-emitting diodes (OLEDs) utilize self-emissive light-emitting diodes (LEDs), thus offering advantages in terms of fast response speed, contrast ratio, luminous efficiency, brightness, and viewing angle. In this case, the LEDs can be implemented using either inorganic or organic materials.

[0004] An organic light-emitting display device includes an organic light-emitting diode disposed in each of a plurality of sub-pixels arranged on a display panel, and the brightness represented by each sub-pixel can be controlled to display an image by causing the organic light-emitting diode to emit light through a voltage flowing through the organic light-emitting diode.

[0005] In this configuration, a light-emitting element and a driving transistor for driving the light-emitting element are disposed in each sub-pixel defined in the display panel. Due to manufacturing processes or driving time, characteristic values ​​such as threshold voltage or mobility of the driving transistor in each sub-pixel can vary between sub-pixels. Consequently, brightness deviations (i.e., brightness non-uniformity) may occur between sub-pixels, and image quality may degrade.

[0006] Specifically, the sensing drive for sensing the characteristic values ​​of the driving transistor can be performed during the inspection process before the display device is shipped, or during the power-on process, power-off process, or blank period of the driving process after the display device is shipped.

[0007] For example, assuming it takes 30ms to sense the feature value of the driving transistor for all subpixels in a horizontal row, an ultra-high definition (UHD) display device might require a sensing time of 2,160 rows × 4 colors (red, green, white, and blue) × 30ms = approximately 260 seconds.

[0008] If the threshold voltage of the driving transistors is detected during the transport of the display devices and compensation is performed on 10,000 display devices, it would take approximately 722 hours, which is difficult. This problem is further amplified when the display devices consist of large, high-definition screens.

[0009] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter art, and the description in this section does not limit this disclosure. Summary of the Invention

[0010] The inventors have recognized the problems that may occur in the driving of display devices in related technologies. Therefore, exemplary embodiments of this disclosure can provide display devices and display driving methods capable of shortening the threshold voltage sensing time of driving transistors.

[0011] Exemplary embodiments of this disclosure may provide a display device and a display driving method capable of sensing the threshold voltage of a driving transistor at high speed by shortening the saturation time of the driving transistor through the overshoot of the data voltage.

[0012] Exemplary embodiments of this disclosure can provide a display device and a display driving method capable of reducing sensing errors caused by saturation voltage errors of the driving transistors through gradual control of overshoot data voltage.

[0013] Exemplary embodiments of this disclosure may provide a display device and a display driving method capable of reducing the deviation of the threshold voltage at each location by controlling an auxiliary voltage applied via an auxiliary line connected to a data line.

[0014] The exemplary embodiments disclosed herein are not limited to the purposes mentioned in this specification, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0015] A display device according to an exemplary embodiment of the present disclosure may include: a display panel, wherein a plurality of sub-pixels driven by a sub-pixel circuit including a driving transistor are arranged in a display area; a data driving circuit configured to supply a data voltage during a display driving period via a plurality of data lines connected to the plurality of sub-pixels and to supply a first sensing data voltage via a data line during a sensing driving period; a gating driving circuit configured to supply a gating signal via a plurality of gating lines connected to the plurality of sub-pixels; a power management circuit configured to supply power required for driving the display panel, the data driving circuit, and the gating driving circuit; and a switching circuit configured to generate a second sensing data voltage by controlling the connection between a plurality of auxiliary lines and a plurality of data lines extending from the power management circuit, using an auxiliary voltage transmitted via the plurality of auxiliary lines and a first sensing data voltage transmitted via the plurality of data lines.

[0016] A display device according to another exemplary embodiment of the present disclosure may include: a data driving circuit configured to supply a data voltage during a display driving period and a first sensing data voltage during a sensing driving period via multiple data lines connected to multiple sub-pixels; a power management circuit configured to supply power required to drive the data driving circuit; and a switching circuit configured to generate a second sensing data voltage by controlling the connection between multiple auxiliary lines and multiple data lines extending from the power management circuit, using an auxiliary voltage transmitted via the multiple auxiliary lines and the first sensing data voltage transmitted via the multiple data lines.

[0017] The display driving method according to an exemplary embodiment of the present disclosure is a method for sensing a threshold voltage of a driving transistor included in a plurality of sub-pixels arranged to display an image on a display panel, and may include an initialization step, a tracking step, and a sampling step. The initialization step initializes the gate node and source node of the driving transistor. The tracking step tracks the voltage of the source node of the driving transistor. The sampling step samples the voltage of the source node after the voltage of the source node of the driving transistor has saturated. The tracking step includes a pulse period and a slope period. During the pulse period, a sensed data voltage applied to the gate node of the driving transistor is generated as a pulse waveform of a first sense level. During the slope period, the sensed data voltage gradually decreases to a second sense level after the pulse period.

[0018] According to exemplary embodiments of the present disclosure, a display device and a display driving method capable of shortening the threshold voltage sensing time of the driving transistor can be provided.

[0019] According to exemplary embodiments of the present disclosure, a display device and a display driving method can be provided that can sense the threshold voltage of a driving transistor at high speed by shortening the saturation time of the driving transistor through the overshoot of the data voltage.

[0020] According to exemplary embodiments of the present disclosure, a display device and a display driving method can be provided that can reduce sensing errors caused by saturation voltage errors of driving transistors by gradually controlling the overshoot data voltage.

[0021] According to exemplary embodiments of the present disclosure, a display device and a display driving method can be provided that are capable of reducing the deviation of the threshold voltage at each position by controlling an auxiliary voltage applied via an auxiliary line connected to a data line.

[0022] According to exemplary embodiments of the present disclosure, a display device and a display driving method that can shorten manufacturing time through process optimization can be provided.

[0023] The effects of the exemplary embodiments disclosed herein are not limited to those described above, and other effects will be apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0024] This disclosure will be more fully understood from the following detailed description and accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0025] Figure 1 The structure of the display device is shown according to an exemplary embodiment of the present disclosure.

[0026] Figure 2 This is an exemplary system implementation diagram of a display device according to an exemplary embodiment of the present disclosure.

[0027] Figure 3 A subpixel equivalent circuit of a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0028] Figure 4 A compensation circuit for a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0029] Figure 5 This is a diagram used to explain the operation of sensing the threshold voltage of a driving transistor in a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 6 The diagram illustrates the variation of the sensed data voltage applied during a period of time for sensing the threshold voltage of the driving transistor and the source node voltage of the driving transistor in a display device according to an exemplary embodiment of the present disclosure.

[0031] Figure 7 It is a graph specifically illustrating the level change of the sensing data voltage applied during a period of time for sensing the threshold voltage of the driving transistor in a display device according to an exemplary embodiment of the present disclosure.

[0032] Figure 8 This is an experimental diagram showing the change in the source node voltage of a driving transistor while changing a first sensing level of a sensing data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0033] Figure 9 This is an experimental diagram showing the measurement of the change in the source node voltage of a driving transistor in a display device according to an exemplary embodiment of the present disclosure, for cases where the sensed data voltage includes a slope period and cases where the sensed data voltage does not include a slope period.

[0034] Figure 10An example is shown of the arrangement of data lines and auxiliary lines for controlling the sensing data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0035] Figure 11 The connection structure of data lines and auxiliary lines in a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0036] Figure 12 The layout of the gating border area where the auxiliary lines are located in the display panel of a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0037] Figure 13 and Figure 14 This is a signal waveform diagram illustrating, as an example, the generation of a sensing data voltage by synthesizing an auxiliary voltage and a data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0038] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0039] In the following, some exemplary embodiments of this disclosure will be described in detail with reference to the exemplary drawings.

[0040] The described processing steps and / or operations are illustrative; however, the order of steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may have been chosen merely for convenience in drafting the specification and may therefore differ from the names used in actual products.

[0041] In the following description of examples or exemplary embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or exemplary embodiments that may be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar parts, even if the same reference numerals and symbols are shown in different drawings. Furthermore, in the following description of examples or exemplary embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may obscure the subject matter of some exemplary embodiments of the invention.

[0042] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. shown in the accompanying drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0043] The dimensions of the various components shown in the accompanying drawings, including size and thickness, are shown for ease of description, and this disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions of the components shown in the various accompanying drawings, including relative size, position, and thickness, are part of this disclosure.

[0044] Terms used herein, such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed by,” “composed of,” are generally intended to allow for the addition of additional components unless the term is used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0045] When using terms such as “on top of,” “above,” “above,” “below,” “below,” “next to,” “under,” “near,” “close to,” “adjacent to,” “on the side of,” or “near” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used with the terms “exactly” or “directly.”

[0046] Spatially relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” etc., may be used in this document to describe the relationship between one element or feature and another element or feature as illustrated in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if an element in the figure is inverted, an element described as “below” or “below” other elements or features would be oriented as “above” other elements or features. Thus, the exemplary term “below” can include both lower and upper orientations. Similarly, the exemplary terms “above” or “above” can include both upper and lower orientations.

[0047] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” are used herein to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but merely to distinguish the corresponding element from other elements.

[0048] When it is mentioned that the first element is "connected or coupled to" the second element, or "in contact or overlaps" with the second element, it should be interpreted that not only can the first element be connected or coupled to the second element, or "in contact or overlap" with the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact or overlap" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlap," etc.

[0049] When time-related terms such as “after,” “next,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately.”

[0050] The term “exemplary” is used to indicate that something is an example or illustration. “Aspect” refers to an exemplary aspect. “Implementation,” “example,” “aspect,” etc., should not be construed as superior to or best of other implementations. Unless otherwise stated, implementation, example, exemplary implementation, aspect, etc., may refer to one or more implementations, one or more examples, one or more exemplary implementations, one or more aspects, etc.

[0051] The term "at least one" should be understood to include all possible combinations that can be suggested from one or more related projects. For example, "at least one of the first, second, or third projects" can mean each of the first, second, or third projects, and can also mean all possible combinations that can be suggested from two or more of the first, second, and third projects.

[0052] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include light-emitting elements, etc., as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0053] Furthermore, when referring to any size, relative dimensions, etc., the numerical values ​​of the component or feature, or the corresponding information (e.g., level, range, etc.), should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.), even if no relevant description is specified. Additionally, the term "can" fully encompasses all the meanings of the term "able to".

[0054] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, as defined in commonly used dictionaries, shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0055] In this disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode are used interchangeably. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any aspect of this disclosure can be a drain electrode in another aspect of this disclosure, and a drain electrode in any aspect of this disclosure can be a source electrode in another aspect of this disclosure.

[0056] Features of the various embodiments of this disclosure may be partially or wholly adhered to or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0057] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0058] Figure 1 The structure illustrates a display device according to an exemplary embodiment of the present disclosure.

[0059] Reference Figure 1 A display device 100 according to an exemplary embodiment of the present disclosure may include: a display panel 110, wherein a plurality of gating lines GL and data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix; a gating drive circuit 120 configured to drive the plurality of gating lines GL; a data drive circuit 130 configured to supply data voltage through the plurality of data lines DL; a timing controller 140 configured to control the gating drive circuit 120 and the data drive circuit 130; and a power management circuit 150.

[0060] The display panel 110 displays an image in the display area based on the gating signal transmitted from the gating drive circuit 120 through multiple gating lines GL and the data voltage transmitted from the data drive circuit 130 through multiple data lines DL.

[0061] The gating signal transmitted from the gating drive circuit 120 may include a scan signal used as a control signal for driving sub-pixels, a light emission signal used as a control signal for the light emission operation of the light emission element, or a sensing signal used as a control signal for sensing the voltage of a specific node.

[0062] Multiple subpixels SP can be composed of red (R) subpixels, green (G) subpixels, and blue (B) subpixels, or they can be composed of red (R) subpixels, green (G) subpixels, blue (B) subpixels, and white (W) subpixels. However, this disclosure is not limited to this. Multiple subpixel SPs constituting a unit pixel can be modified in various ways in terms of color and configuration as needed.

[0063] For example, each of the plurality of sub-pixels SP can emit light with a different wavelength from each other. For example, the plurality of sub-pixels SP may include red sub-pixels, green sub-pixels, and blue sub-pixels, wherein the red, green, and blue sub-pixels may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SP may include red, green, blue, and white sub-pixels, wherein the red, green, blue, and white sub-pixels may be arranged in a repeating manner, or the red, green, blue, and white sub-pixels may be arranged in a quadrilateral pattern. For example, the red, blue, and green sub-pixels may be arranged sequentially along the row direction, or the red, blue, green, and white sub-pixels may be arranged sequentially along the row direction. However, in embodiments of this disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited and can be configured in various forms according to light-emitting characteristics, device lifetime, and device specifications.

[0064] Furthermore, depending on their light-emitting characteristics, sub-pixels can have different light-emitting areas. For example, a sub-pixel that emits light of a different color than the blue sub-pixel can have a different light-emitting area than the blue sub-pixel. For example, red, blue, and green sub-pixels, or red, blue, white, and green sub-pixels, can each have different light-emitting areas.

[0065] For example, in the display panel 110, multiple pixels can be arranged in a matrix, and each pixel is composed of sub-pixels SP of different colors, such as white sub-pixels, red sub-pixels, green sub-pixels and blue sub-pixels, and each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0066] A subpixel SP may include a thin-film transistor (TFT) formed in the area where a data line DL and a gate line GL intersect, a light-emitting element such as a micro LED that emits light according to the data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0067] For example, if a display device 100 with a resolution of 2,800 × 1,290 consists of three sub-pixels SP representing red (R), green (G), and blue (B), then 2,800 gating lines GL and a total of 1,290 × 3 = 3,870 data lines DL connected to the three sub-pixels RGB respectively can be provided. Furthermore, the sub-pixels SP can be positioned at the points where these gating lines GL and data lines DL intersect.

[0068] The gating drive circuit 120 is controlled by the timing controller 140, and controls the driving timing for multiple sub-pixels SP by sequentially outputting gating signals to multiple gating lines GL disposed on the display panel 110.

[0069] In a display device 100 with a resolution of 2,800 × 1,290, the case where gating signals are output sequentially from the first gating line to the second,800th gating line for 2,800 gating lines GL can be referred to as 2,800-phase drive. Alternatively, the case where gating signals are output sequentially in units of four gating lines GL, such as gating signals being output sequentially from the first gating line to the fourth gating line, and then gating signals being output sequentially from the fifth gating line to the eighth gating line, is referred to as 4-phase drive. That is, the case where gating signals are output sequentially for each A gating line GL can be referred to as A-phase drive.

[0070] In this configuration, the gating drive circuit 120 may include one or more gating drive integrated circuits (GDICs), and depending on the driving method, the gating drive circuit 120 may be located on only one side or both sides of the display panel 110. Alternatively, the gating drive circuit 120 may be embedded in the bezel area of ​​the display panel 110 and implemented as a gating in-panel (GIP).

[0071] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, according to the timing of the gating signal applied through the gating line GL, the data voltage is output to each data line DL, and each sub-pixel SP connected to the data line DL displays an image with brightness corresponding to the data voltage.

[0072] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 via a tape auto-bonding (TAB) method or a chip-on-glass (COG) method, or may be directly disposed on the display panel 110.

[0073] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) method, in which case each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0074] The timing controller 140 supplies various control signals to the gating drive circuit 120 and the data drive circuit 130, and controls the operation of the gating drive circuit 120 and the data drive circuit 130. That is, the timing controller 140 controls the gating drive circuit 120 to output gating signals according to the timing implemented in each frame, and on the other hand, sends the image data DATA received from the outside to the data drive circuit 130.

[0075] In this configuration, the timing controller 140 receives various timing signals, including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a master clock MCLK, and image data DATA, from the external host system 200. Here, the horizontal synchronization signal indicates the time taken to display a horizontal line on the screen, and the vertical synchronization signal indicates the time taken to display one frame. The data enable signal may correspond to a signal indicating the time period for supplying data voltage to the pixels.

[0076] The host system 200 can be any of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0077] Therefore, the timing controller 140 uses various timing signals received from the host system 200 to generate control signals and sends the control signals to the gating drive circuit 120 and the data drive circuit 130.

[0078] For example, to control the gating drive circuit 120, the timing controller 140 outputs various gating control signals, including a gating start pulse GSP, a gating clock GCLK, and a gating output enable signal GOE. Here, the gating start pulse GSP controls the timing of the start of operation of one or more gating driver integrated circuits (GDICs) constituting the gating drive circuit 120. Additionally, the gating clock GCLK is a clock signal typically input to one or more gating driver integrated circuits (GDICs) and controls the shift timing of the gating signals. Furthermore, the gating output enable signal GOE specifies the timing information for one or more gating driver integrated circuits (GDICs).

[0079] In addition, to control the data drive circuit 130, the timing controller 140 outputs various data control signals, including the source start pulse SSP, the source clock SCLK, and the source output enable signal SOE. Here, the source start pulse SSP controls the timing of data sampling by one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source clock SCLK is a clock signal that controls the timing of the sampled data in the source driver integrated circuit SDIC. The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0080] The display device 100 may include a power management circuit 150 that supplies various voltages or currents to the display panel 110, the gating drive circuit 120 and the data drive circuit 130, or controls the various voltages or currents to be supplied.

[0081] The power management circuit 150 regulates the DC input voltage Vin supplied from the host system 200 to generate the power required to drive the display panel 100, the gating drive circuit 120, and the data drive circuit 130.

[0082] Furthermore, the sub-pixel SP is located at the intersection of the gate line GL and the data line DL, and a light-emitting element can be disposed in each sub-pixel SP. For example, a micro-LED display device includes a light-emitting element such as a micro-LED in each sub-pixel SP, and an image can be displayed by controlling the current flowing through the light-emitting element according to the data voltage.

[0083] The display device 100 can be of various types, such as a micro LED display, a liquid crystal display (LCD), an organic light-emitting display (OLED), and a plasma display panel (PDP).

[0084] Figure 2 This is an exemplary system implementation diagram of a display device according to an exemplary embodiment of the present disclosure.

[0085] Reference Figure 2In a display device 100 according to an exemplary embodiment of the present disclosure, the display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images.

[0086] The non-display area NDA can be a region adjacent to the display area DA. Further, the non-display area NDA can be a region adjacent to and configured to surround the display area DA. For example, the non-display area NDA can be located in the edge region surrounding the display area DA of the displayed image. However, this disclosure is not limited thereto.

[0087] For example, the non-display area NDA may include a first non-display area located outside the display area DA along a first direction, a second non-display area located outside the display area DA along a second direction intersecting the first direction, a third non-display area located outside the display area DA along a direction opposite to the first direction, and a fourth non-display area located outside the display area DA along a direction opposite to the second direction.

[0088] For example, the boundary region between the display area DA and the non-display area NDA can be curved, allowing the non-display area NDA to lie below the display area. In this case, when a user looks at the display device from the front, little or no non-display area NDA may be visible to the user.

[0089] The data driving circuit 130 may include multiple source driver integrated circuits (SDICs) and may be implemented using a chip-on-film (COF) method. Each of the multiple source driver integrated circuits (SDICs) may be mounted on a circuit film (CF) connected to the non-display area NDA of the display panel 110. Here, the circuit film (CF) is also referred to as a flexible printed circuit.

[0090] The gating drive circuit 120 can be implemented as an in-panel gating (GIP) type. In the following text, the gating drive circuit 120 implemented as a GIP type can also be referred to as a "gating drive panel circuit GPC".

[0091] The gating drive panel circuit GPC can be formed in the non-display area NDA of the display panel 110. The gating drive panel circuit GPC can be located in both the non-display area NDA located on one outer side of the display area DA and the non-display area NDA located on the other outer side of the display area DA.

[0092] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other devices 140, 150, 160, etc., and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0093] The circuit film CF on which the active driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB. That is, one side of the circuit film CF on which the active driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printed circuit board SPCB.

[0094] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board (CPCB).

[0095] The timing controller 140 can perform all control functions related to the driving of the display panel 110, and can control the operation of multiple source driver integrated circuits (SDICs) and gating driver panel circuits (GPCs).

[0096] The power management circuit 150 can supply voltage or current to multiple source driver integrated circuits (SDICs) and gating driver panel circuits (GPCs), or control the various voltages or currents to be supplied.

[0097] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitally connected via at least one connecting cable (CBL). Here, for example, the connecting cable CBL can be one of a flexible printed circuit (FPC) and a flexible flat cable (FFC).

[0098] At least one source printed circuit board (SPCB) and control printed circuit board (CPCB) can be integrated and implemented as a single printed circuit board.

[0099] The display device 100 according to an exemplary embodiment of the present disclosure may further include a level shifter 160 for adjusting the voltage level of a signal. For example, the level shifter 160 may be disposed on a control printed circuit board (CPCB) or a source printed circuit board (SPCB).

[0100] Level shifter 160 can output the signal required for gating drive to the gating drive panel circuit GPC. Power management circuit 150 can output a signal to level shifter 160. Level shifter 160 can adjust the voltage level of the signal input from power management circuit 150. The signal whose voltage level is adjusted by level shifter 160 can be input to gating drive panel circuit GPC.

[0101] For example, level shifter 160 can output multiple clock signals with different phases to gating driver panel circuit GPC. Gating driver panel circuit GPC can generate multiple gating signals (e.g., scan signals, sense signals, etc.) based on multiple clock signals input from level shifter 160, and output multiple gating signals to multiple gating lines GL.

[0102] The non-display area NDA of the display panel 110 may include a gating border area GBA. The gating border area GBA may refer to the area in which the gating drive panel circuit GPC is set and the various wiring connected to the gating drive panel circuit GPC. The gating drive panel circuit GPC is a GIP type gating drive circuit 120.

[0103] Various wiring connected to the strobe driver panel circuit (GPC) can include multiple clock lines, high-level strobe voltage lines, and low-level strobe voltage lines.

[0104] Figure 3 A subpixel equivalent circuit of a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0105] Reference Figure 3 In a display device 100 according to an exemplary embodiment of the present disclosure, each of a plurality of sub-pixels SP disposed on a display panel 110 may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0106] The subpixel circuit SPC may include a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, and a storage capacitor Cst. In this case, since the subpixel circuit SPC of each subpixel SP includes three transistors DRT, SCT, and SENT, as well as one capacitor Cst, the subpixel circuit can be referred to as having a 3T1C structure.

[0107] The active layer of a transistor can be formed from semiconductor materials, such as oxide semiconductors, amorphous semiconductors, or polycrystalline semiconductors, but is not limited to these.

[0108] Oxide semiconductor materials offer excellent leakage current prevention and relatively low manufacturing costs. Oxide semiconductors can be made from metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals and their oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Specifically, oxide semiconductors can include, but are not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0109] Polycrystalline semiconductor materials exhibit high mobility due to the fast movement speed of charge carriers such as electrons and holes, resulting in low energy consumption and excellent reliability. Polycrystalline semiconductors can be made of polycrystalline silicon (poly-Si), but are not limited to this.

[0110] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited to this.

[0111] The light-emitting element ED may include an anode electrode AND and a cathode electrode CAT, and may include a light-emitting layer EL located between the anode electrode AND and the cathode electrode CAT.

[0112] One of the anode electrode AND and the cathode electrode CAT can be a pixel electrode connected to a transistor such as a driving transistor DRT, while the other can be a common electrode to which a common voltage is applied. Here, the pixel electrode is an electrode set for each sub-pixel SP, and the common electrode is an electrode set for all sub-pixels SP. For example, the common voltage can be a high potential voltage EVDD as a high-level common voltage or a low potential voltage EVSS as a low-level common voltage. Here, the high potential voltage EVDD is also referred to as the pixel driving voltage, and the low potential voltage EVSS is also referred to as the base voltage.

[0113] The anode AND can be a pixel electrode connected to a transistor such as the driving transistor DRT, and the cathode CAT can be a common electrode to which a low potential voltage EVSS is applied.

[0114] For example, the light-emitting element (ED) can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot light-emitting element.

[0115] The driving transistor DRT is a transistor used to drive the light-emitting element ED, and may include a first node N1, a second node N2 and a third node N3.

[0116] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT and can be electrically connected to the source or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT can be the source or drain node of the driving transistor DRT, can be electrically connected to the source or drain node of the sensing transistor SENT, and can also be electrically connected to the anode AND of the light-emitting element ED. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL that supplies the high potential voltage EVDD.

[0117] The scanning transistor SCT is controlled by a scanning signal SC, which is a gating signal and can be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scanning transistor SCT can be turned on or off according to the scanning signal SC supplied from the scanning signal line SCL, which is a type of gating line GL, to control the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0118] The scanning transistor SCT can be turned on by a scanning signal SC with a turn-on level voltage to transmit the data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0119] Here, if the scanning transistor SCT is an N-type transistor, the on-state voltage of the scanning signal SC can be a high-level voltage. If the scanning transistor SCT is a P-type transistor, the on-state voltage of the scanning signal SC can be a low-level voltage.

[0120] The sensing transistor SENT can be controlled by a sensing signal SE, which serves as a gating signal, and can be connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL. In other words, the sensing transistor SENT can be turned on or off according to the sensing signal SE supplied from the sensing signal line GL, which is another type of gating line, to control the connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0121] The sensing transistor SENT can be turned on by a sensing signal SE with a conduction level voltage to transfer the reference voltage Vref supplied from the reference voltage line RVL to the second node N2 of the driving transistor DRT. Here, the sensing signal SE can be considered as a second scan signal, different from the scan signal SC.

[0122] In addition, the sensing transistor SENT can be turned on by a sensing signal SE with a conduction level voltage to transfer the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0123] Here, if the sensing transistor SENT is an N-type transistor, the on-state voltage of the sensing signal SE can be a high-level voltage. If the sensing transistor SENT is a P-type transistor, the on-state voltage of the sensing signal SE can be a low-level voltage.

[0124] The sensing transistor SENT, which transmits the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL, can be used for sensing drive to sense the feature value of the sub-pixel SP. In this case, the voltage transmitted to the reference voltage line RVL can be either a voltage used to calculate the feature value of the sub-pixel SP, or a voltage reflecting the feature value of the sub-pixel SP.

[0125] In this disclosure, the feature values ​​of the sub-pixel SP can be feature values ​​of the driving transistor DRT or the light-emitting element ED. For example, the feature values ​​of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT. The feature values ​​of the light-emitting element ED can include the threshold voltage of the light-emitting element ED.

[0126] A storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst can be charged with an amount of charge corresponding to the voltage difference between its terminals, and it can be used to maintain this voltage difference for a predetermined frame time. Therefore, the corresponding sub-pixel SP can emit light within the predetermined frame time.

[0127] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an N-type transistor or a P-type transistor. In this disclosure, for ease of description, it is illustrated that each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is N-type.

[0128] The storage capacitor Cst may not be a parasitic capacitor (e.g., Cgs, Cgd) existing between the gate node and source node (or drain node) of the driving transistor DRT, but may be an external capacitor intentionally designed to be outside the driving transistor DRT.

[0129] The subpixel SP shown here is merely an example and can be modified in various ways by further including one or more transistors or one or more capacitors.

[0130] The display device 100 disclosed herein can perform a process of sensing characteristic values ​​(e.g., threshold voltage) of the driving transistor DRT before transport or during the driving process, and compensate for deviations in the characteristic values.

[0131] Figure 4 A compensation circuit for a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0132] Reference Figure 4 The compensation circuit of the display device 100 according to an exemplary embodiment of the present disclosure is a circuit capable of performing sensing and compensation processing on the feature values ​​of circuit elements in the sub-pixel SP. Here, circuit elements may refer to light-emitting elements (ED) and driving transistors (DRT), etc.

[0133] The compensation circuit may include a power switching transistor SPRE, a sampling switching transistor SAM, an analog-to-digital converter ADC, a compensator COMP, and a memory MEM, etc.

[0134] The power switching transistor SPRE controls the connection between the reference voltage line RVL and the reference voltage supply node Nref. The reference voltage Vref output from the power management circuit 150 is supplied to the reference voltage supply node Nref, and the reference voltage Vref supplied to the reference voltage supply node Nref can be applied to the reference voltage line RVL through the power switching transistor SPRE.

[0135] The sampling switch transistor (SAM) controls the connection between the analog-to-digital converter (ADC) and the reference voltage line RVL. If the ADC is connected to the reference voltage line RVL via the sampling switch transistor (SAM), the ADC can convert the voltage (e.g., analog voltage) of the connected reference voltage line RVL into a sensed value corresponding to a digital value.

[0136] Depending on the state of the sub-pixel SP, a line capacitor Crv1 can be formed between the reference voltage line RLV and ground GND. The voltage of the reference voltage line RLV corresponds to the amount of charge on the line capacitor Crv1.

[0137] The analog-to-digital converter (ADC) can provide sensing data, including the sensed values, to the compensator (COMP).

[0138] The compensator COMP can detect the characteristic value (e.g., threshold voltage) of the driving transistor DRT included in the corresponding sub-pixel SP based on the sensing data supplied from the analog-to-digital converter ADC, calculate the compensation value for reducing the deviation between the driving transistors DRT based on the characteristic value, and store the compensation value in the memory MEM.

[0139] For example, the compensation value is information calculated to reduce the threshold voltage deviation of the light-emitting element ED or the threshold voltage deviation of the driving transistor DRT, and may include gain and offset for data changes.

[0140] The timing controller 140 can use the compensation value stored in the memory MEM to change the image data and supply the changed image data to the data drive circuit 130.

[0141] The data drive circuit 130 can use a digital-to-analog converter (DAC) to convert the altered image data into a data voltage Vdata corresponding to the analog voltage and output the data voltage, thereby achieving compensation.

[0142] The analog-to-digital converter (ADC), the power switching transistor (SPRE), and the sampling switching transistor (SAM) can be included in the source driver integrated circuit (SDIC). Here, the source driver integrated circuit (SDIC) is an integrated circuit that constitutes the data driving circuit 130 and may include a digital-to-analog converter (DAC).

[0143] The compensator COMP can be included in the timing controller 140.

[0144] As described above, the display device 100 according to an exemplary embodiment of the present disclosure can perform compensation processing to reduce the characteristic value deviation between the driving transistors DRT. Additionally, in order to perform the compensation processing, the display device 100 can perform sensing drive to identify the characteristic value deviation between the driving transistors DRT.

[0145] In this case, the voltage applied through the data line DL during the sensing drive period for sensing the feature values ​​of sub-pixels SP, including the driving transistor DRT, can be distinguished as the sensing data voltage Vdata_SEN, compared to the data voltage Vdata applied through the data line DL during the display drive period for displaying an image on the display panel 110.

[0146] Figure 5 This is a diagram used to explain the operation of sensing the threshold voltage of a driving transistor in a display device according to an exemplary embodiment of the present disclosure.

[0147] Reference Figure 5 In a display device 100 according to an exemplary embodiment of the present disclosure, the time period for sensing the threshold voltage of the driving transistor DRT (e.g., a sensing driving time period) may include an initialization time period T1, a tracking time period T2, and a sampling time period T3.

[0148] The initialization period T1 can be the period used to initialize the first node N1 and the second node N2 of the driving transistor DRT.

[0149] During the initialization period T1, the voltage V1 of the first node N1 of the driving transistor DRT can be initialized to the sense data voltage Vdata_SEN, and the voltage V2 of the second node N2 of the driving transistor DRT can be initialized to the sense reference voltage Vref.

[0150] During the initialization period T1, the scanning transistor SCT and the sensing transistor SENT can be turned on, and the power switching transistor SPRE can be turned on.

[0151] The tracking period T2 can be the period used to track the voltage V2 of the second node N2 of the driving transistor DRT, which reflects the threshold voltage Vth of the driving transistor DRT.

[0152] During the tracking period T2, the power switching transistor SPRE can be turned off or the sensing transistor SENT can be turned off.

[0153] Therefore, during the tracking period T2, the first node N1 of the driving transistor DRT is in a constant voltage state with the sensed data voltage Vdata_SEN, but the second node N2 of the driving transistor DRT can be in a floating state. Therefore, the voltage V2 of the second node N2 of the driving transistor DRT can vary during the tracking period T2.

[0154] During the tracking period T2, the voltage V2 of the second node N2 of the driving transistor DRT can rise until the voltage V2 of the second node N2 of the driving transistor DRT reflects the threshold voltage Vth of the driving transistor DRT.

[0155] During the initialization period T1, the voltage difference between the first node N1 and the second node N2 of the driving transistor DRT can be equal to or greater than the threshold voltage Vth of the driving transistor DRT. Therefore, if the tracking period T2 begins, the driving transistor DRT is in the on state and conducts current. Consequently, if the tracking period T2 begins, the voltage V2 of the second node N2 of the driving transistor DRT may rise. However, during the tracking period T2, the voltage V2 of the second node N2 of the driving transistor DRT will not rise continuously.

[0156] Towards the latter half of the tracking period T2, the voltage rise of the second node N2 of the driving transistor DRT decreases, and eventually, the voltage V2 of the second node N2 of the driving transistor DRT can saturate.

[0157] The saturation voltage V2 of the second node N2 of the driving transistor DRT can correspond to the difference between the sensed data voltage Vdata_SEN and the threshold voltage Vth (Vdata_SEN - Vth), or the difference between the sensed data voltage Vdata_SEN and the threshold voltage deviation ΔVth (Vdata_SEN - ΔVth). Here, the threshold voltage Vth can be a negative threshold voltage (negative Vth) or a positive threshold voltage (positive Vth).

[0158] If the voltage V2 of the second node N2 of the driving transistor DRT is saturated, the sampling period T3 can begin.

[0159] The sampling period T3 is the period used to measure the threshold voltage Vth of the driving transistor DRT or a voltage reflecting the change of the threshold voltage (e.g., Vdata_SEN-Vth, Vdata_SEN-ΔVth).

[0160] Sampling period T3 is the step where the analog-to-digital converter (ADC) detects the sensed voltage Vsen through the reference voltage line RVL. Here, the voltage of the reference voltage line RVL can correspond to the voltage of the second node N2 of the driving transistor DRT, and can also correspond to the charging voltage of the line capacitor Crv1 formed on the reference voltage line RVL.

[0161] The voltage sensed by the analog-to-digital converter (ADC) during sampling period T3 can be obtained by subtracting the threshold voltage Vth from the sensed data voltage Vdata_SEN (Vdata_SEN - Vth), or by subtracting the deviation ΔVth of the threshold voltage from the sensed data voltage Vdata_SEN (Vdata_SEN - ΔVth). Here, the threshold voltage Vth can be a positive or negative threshold voltage.

[0162] During the tracking period T2, the saturation time Tsat that takes for the voltage V2 of the second node N2 of the driving transistor DRT to rise and saturate can be the length of the tracking period T2, and can be the threshold voltage Vth of the driving transistor DRT or the time that its change is reflected in the voltage of the second node N2 of the driving transistor DRT (i.e., V2 = Vdata_SEN - Vth).

[0163] The saturation time Tsat can occupy a large portion of the entire time period used to sense the threshold voltage Vth of the driving transistor DRT. When the threshold voltage Vth of the driving transistor DRT is sensed, the voltage V2 of the second node N2 of the driving transistor DRT may require a considerable amount of time (e.g., the saturation time Tsat) to rise and saturate.

[0164] As described above, the sensing drive method for sensing the threshold voltage of the driving transistor DRT can be called slow mode because a long saturation time Tsat is required until the voltage state of the second node N2 of the driving transistor DRT indicates the threshold voltage of the driving transistor DRT.

[0165] The display device 100 of this disclosure can shorten the saturation time of the voltage V2 of the second node N2 of the driving transistor DRT by controlling the data voltage Vdata during the tracking period T2.

[0166] Figure 6 The diagram illustrates the variation of the sensed data voltage applied during a period of time for sensing the threshold voltage of the driving transistor and the source node voltage of the driving transistor in a display device according to an exemplary embodiment of the present disclosure.

[0167] Reference Figure 6According to an exemplary embodiment of the present disclosure, the display device 100 can control the level of the sensing data voltage Vdata_SEN applied to the gate node corresponding to the first node N1 of the driving transistor DRT, so as to shorten the time for sensing the threshold voltage Vth of the driving transistor DRT.

[0168] In other words, the display device 100 of this disclosure can control the level of the sensing data voltage Vdata_SEN applied to the gate node of the driving transistor DRT to change during the sensing drive segment, so as to shorten the saturation time of the source node voltage corresponding to the second node N2 of the driving transistor DRT.

[0169] Specifically, the time period used to sense the threshold voltage of the driving transistor DRT may include an initialization time period T1, a tracking time period T2, and a sampling time period T3.

[0170] During the initialization period T1, the scan transistor SCT is turned on by the on-level scan signal SC. Additionally, during initialization period T1, the sensing transistor SENT is turned on by the on-level sensing signal SE, and the power switching transistor SPRE is turned on. Therefore, the second node N2 of the driving transistor DRT is initialized to the sensing reference voltage Vref. During initialization period T1, the sensing data voltage Vdata_SEN can remain at 0V.

[0171] The tracking period T2 may include a pulse period Tp and a slope period Ts. During the pulse period Tp, a sensing data voltage Vdata_SEN is applied at a first sensing level SEN1. During the slope period Ts, the sensing data voltage Vdata_SEN gradually decreases from the first sensing level SEN1 to the second sensing level SEN2.

[0172] The pulse period Tp can be referred to as the interval during which the sensing data voltage Vdata_SEN is applied as a pulse signal for the first sensing level SEN1, and the slope period Ts can be referred to as the interval during which the sensing data voltage Vdata_SEN changes from the first sensing level SEN1 to the second sensing level SEN2 with a constant slope.

[0173] Sampling period T3 is initiated when a specific time has elapsed after the end of the slope period Ts. If the sampling switch transistor SAM is turned on during sampling period T3, the voltage at the second node N2 of the driving transistor DRT can be sensed via the reference voltage line RVL.

[0174] From the end of the slope period Ts to the sampling period T3, the sensed data voltage Vdata_SEN maintains the second sense level SEN2. The second sense level SEN2 can be a value lower than the first sense level SEN1. When the sampling period T3 ends, the sensor data voltage Vdata_SEN is cut off to 0V.

[0175] Therefore, the sensing data voltage Vdata_SEN applied to the gate node of the driving transistor DRT during the sensing drive period can maintain the first sensing level SEN1 during the pulse period Tp, and then gradually decrease from the first sensing level SEN1 to the second sensing level SEN2 during the slope period Ts.

[0176] Thus, if the sensed data voltage Vdata_SEN is temporarily overtuned to the first sensed level SEN1, the voltage of the first node N1 of the driving transistor DRT will temporarily increase, causing the potential difference between the two ends of the storage capacitor Cst connected between the first node N1 and the second node N2 of the driving transistor DRT to temporarily increase, thereby increasing the charging speed of the storage capacitor Cst.

[0177] Therefore, if the sensing data voltage Vdata_SEN of tracking period T2 is controlled by the pulse period Tp and the slope period Ts, the saturation time Tsat2 used to saturate the voltage V2 of the second node N2 of the driving transistor DRT can be shorter than the conventional saturation time Tsat1.

[0178] As a result, during the sensing drive period of the threshold voltage Vth used for sensing drive transistor DRT, the voltage saturation rate of the second node N2 corresponding to the sensing node can be increased.

[0179] However, if the first sensing level SEN1 of the sensing data voltage Vdata_SEN is set too high during the pulse period Tp, the level of the saturation voltage may increase without reflecting the deviation of the threshold voltage Vth of the driving transistor DRT due to the overcharge voltage in the storage capacitor Cst.

[0180] Therefore, in order to accurately detect the threshold voltage Vth of the driving transistor DRT, the first sensing level SEN1 of the sensing data voltage Vdata_SEN can be maintained within a specific range during the pulse period Tp, but the sensing data voltage Vdata_SEN is gradually reduced during the slope period Ts.

[0181] Figure 7 It is a graph specifically illustrating the level change of the sensing data voltage applied during a period of time for sensing the threshold voltage of the driving transistor in a display device according to an exemplary embodiment of the present disclosure.

[0182] Reference Figure 7 In a display device 100 according to an exemplary embodiment of the present disclosure, the tracking period T2 for the segment of sensing the threshold voltage Vth of the driving transistor DRT may include a pulse period Tp and a slope period Ts. In the pulse period Tp, the sensing data voltage Vdata_SEN is applied as a pulse waveform of a first sensing level SEN1. In the slope period Ts, the sensing data voltage Vdata_SEN gradually decreases from the first sensing level SEN1 to a second sensing level SEN2.

[0183] The pulse period TP can be an interval in which a sensing data voltage Vdata_SEN is applied such that the first sensing level SEN1 has a pulse amplitude Vp higher than the second sensing level SEN2 corresponding to the target voltage of the sampling period T3, and the slope period Ts can be an interval in which the sensing data voltage Vdata_SEN changes from the first sensing level SEN1 to the second sensing level SEN2 with a constant slope. Therefore, the first sensing level SEN1 has a pulse amplitude Vp higher than the second sensing level SEN2.

[0184] In this case, the first sensing level SEN1 of the pulse period Tp and the slope of the slope period Ts can be set high enough to increase the charging speed of the storage capacitor Cst, but can be set within the range where the source node of the driving transistor DRT can return to the target voltage level.

[0185] Figure 8 This is an experimental diagram showing the change in the source node voltage of a driving transistor while sensing a first sensing level of a data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0186] Reference Figure 8 According to an exemplary embodiment of the present disclosure, the display device 100 may apply a sensing data voltage Vdata_SEN at the beginning of the tracking period T2, during the pulse period Tp, with a first sensing level SEN1 having a pulse amplitude Vp higher than the second sensing level SEN2.

[0187] Here, the first pulse amplitude Vp1 can represent 10% of the second sensing level SEN2, the second pulse amplitude Vp2 can represent 20% of the second sensing level SEN2, and the third pulse amplitude Vp3 can represent 30% of the second sensing level SEN2.

[0188] Reference Figure 8In each case where a sensing data voltage Vdata_SEN with a first pulse amplitude Vp1, a second pulse amplitude Vp2, and a third pulse amplitude Vp3 is applied to the segment of the threshold voltage Vth used for sensing the driving transistor DRT, the time for the voltage V2 of the second node N2 of the driving transistor DRT to saturate is reduced.

[0189] However, if the pulse amplitude Vp increases excessively, the voltage V2 at the second node N2 of the driving transistor DRT may not reflect the deviation of the threshold voltage Vth, and the level of the saturation voltage may increase.

[0190] Therefore, the pulse amplitude Vp of the first sensing level SEN1 of the sensing data voltage Vdata_SEN applied during the pulse period Tp of the tracking period T2 can be in the range of 25% to 60% of the second sensing level SEN2 of the sampling period T3.

[0191] Figure 9 This is an experimental diagram showing the measurement of the change in the source node voltage of a driving transistor in a display device according to an exemplary embodiment of the present disclosure, for cases where the sensed data voltage includes a slope period and cases where the sensed data voltage does not include a slope period.

[0192] Reference Figure 9 According to an exemplary embodiment of the present disclosure, the display device 100 may apply a sensing data voltage Vdata_SEN at a first sensing level SEN1 with a pulse amplitude Vp higher than the second sensing level SEN2 at the beginning of the tracking period T2, during the pulse period Tp, thereby shortening the saturation time of the voltage V2 of the second node N2 of the driving transistor DRT.

[0193] However, if the first sensing level SEN1 increases excessively, the voltage level of the second node N2 of the driving transistor DRT will deviate from the deviation range of the driving transistor DRT due to the overcharging of the storage capacitor Cst, and an error may occur in the sensing voltage of the threshold voltage Vth of the driving transistor DRT.

[0194] Therefore, the display device 100 of this disclosure may include a pulse period Tp in which a sensing data voltage Vdata_SEN with a pulsed first sensing level SEN1 is applied at the beginning of the tracking period T2, and may include a slope period Ts in which the sensing data voltage Vdata_SEN gradually decreases from the first sensing level SEN1 to the second sensing level SEN2 after the pulse period Tp.

[0195] As a result, the display device 100 of this disclosure can prevent errors in the sensing voltage of the threshold voltage Vth of the driving transistor DRT while shortening the saturation time of the voltage V2 of the second node N2 of the driving transistor DRT.

[0196] According to an exemplary embodiment of the present disclosure, the display device 100 can control a slope period Ts in which the sensing data voltage Vdata_SEN gradually decreases from a first sensing level SEN1 to a second sensing level SEN2 during a tracking period T2, thereby shortening the time for sensing the threshold voltage Vth of the driving transistor DRT, and simultaneously accurately sensing the deviation of the threshold voltage Vth.

[0197] For example, if the threshold voltage Vth of the driving transistor DRT deviates by 3.5V, the threshold voltage Vth of the driving transistor DRT can be accurately sensed by setting the pulse period Tp and the slope period Ts of the sense data voltage Vdata_SEN to be the same (i.e., Tp=Ts).

[0198] Furthermore, if the time interval of the slope period Ts differs from the time interval of the pulse period Tp by 10% or more, it may deviate from the sensing error range of the threshold voltage Vth of the driving transistor DRT. Therefore, the slope period Ts of the sensed data voltage Vdata_SEN can be set to differ from the pulse period Tp by 10% or less.

[0199] Furthermore, since the level of the data voltage Vdata applied from the data driving circuit 130 to the display panel 110 is determined by reflecting the grayscale of the image, there is a limitation for the data driving circuit 130 to gradually control the level of the sensed data voltage Vdata_SEN during the slope period Ts.

[0200] Therefore, the display device 100 of this disclosure can electrically connect the data line DL and the auxiliary line, and use the auxiliary voltage applied through the auxiliary line to control the level of the sensed data voltage Vdata_SEN.

[0201] Figure 10 An example is shown of the arrangement of data lines and auxiliary lines for controlling the sensing data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0202] Reference Figure 10 The display device 100 according to an exemplary embodiment of the present disclosure may include an auxiliary line AL that extends from the power management circuit 150 along the non-display area NDA of the display panel 110 and is electrically connected to the data line DL.

[0203] The auxiliary voltage generated in the power management circuit 150 can be applied to the auxiliary line AL, and the auxiliary line AL can be electrically connected to the data line DL, to which the data voltage Vdata is applied. Therefore, the data voltage Vdata applied through the data line DL and the auxiliary voltage applied through the auxiliary line AL are combined in the segment for the threshold voltage Vth of the sensing drive transistor DRT, thereby generating the sensing data voltage Vdata_SEN applied to the first node N1 of the driving transistor DRT.

[0204] In this case, since the auxiliary voltage applied through the auxiliary line AL does not have the grayscale level limitation like the data voltage Vdata, the slope of the voltage level can be controlled more precisely.

[0205] Furthermore, during data transmission via the data line DL, the data voltage Vdata transmitted from the source driver integrated circuit SDIC constituting the data driver circuit 130 may have an RC delay that depends on the distance.

[0206] Therefore, the auxiliary line AL, to which the auxiliary voltage is applied, can be connected to the data line DL at a location away from the source driver integrated circuit SDIC to compensate for the RC delay of the data voltage Vdata. In other words, the switch circuit 170 can be located on the opposite side of the data driver circuit 130 within the display panel 110.

[0207] Figure 11 The connection structure of data lines and auxiliary lines in a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0208] Reference Figure 11 The display device 100 according to an exemplary embodiment of the present disclosure may include a switching circuit 170 connected to a data line DL that applies a data voltage Vdata to it from a data driving circuit 130 and an auxiliary line AL that applies an auxiliary voltage to it from a power management circuit 150.

[0209] For example, when a unit pixel includes three sub-pixels, the first data line DL1 that sends the data voltage Vdata to the sub-pixel SP of the first color (e.g., red) can be connected to the first auxiliary line AL1, the second data line DL2 that sends the data voltage Vdata to the sub-pixel SP of the second color (e.g., green) can be connected to the second auxiliary line AL2, and the third data line DL3 that sends the data voltage Vdata to the sub-pixel SP of the third color (e.g., blue) can be connected to the third auxiliary line AL3.

[0210] For example, when a unit pixel comprises four sub-pixels, the first data line DL1, which sends the data voltage Vdata to the sub-pixel SP of the first color (e.g., red), can be connected to the first auxiliary line AL1, and the second data line DL2, which sends the data voltage Vdata to the sub-pixel SP of the second color (e.g., green), can be connected to the second auxiliary line AL2. Additionally, the third data line DL3, which sends the data voltage Vdata to the sub-pixel SP of the third color (e.g., blue), can be connected to the third auxiliary line AL3, and the fourth data line DL4, which sends the data voltage Vdata to the sub-pixel SP of the fourth color (e.g., white), can be connected to the fourth auxiliary line AL4.

[0211] When a unit pixel comprises four sub-pixels, the switching circuit 170 may include a first switching transistor SW1 for connecting the first data line DL1 and the first auxiliary line AL1, a second switching transistor SW2 for connecting the second data line DL2 and the second auxiliary line AL2, a third switching transistor SW3 for connecting the third data line DL3 and the third auxiliary line AL3, and a fourth switching transistor SW4 for connecting the fourth data line DL4 and the fourth auxiliary line AL4. Here, as an example, the case where a pixel consists of four sub-pixels of red, green, blue, and white is shown. However, if a pixel consists of three sub-pixels of red, green, and blue, the switching circuit 170 may include the first switching transistor SW1 through the third switching transistor SW3.

[0212] The gate and source (or drain) nodes of the first switching transistor SW1 can be connected to the first auxiliary line AL1, and the drain (or source) node of the first switching transistor SW1 can be connected to the first data line DL1. The gate and source (or drain) nodes of the second switching transistor SW2 can be connected to the second auxiliary line AL2, and the drain (or source) node of the second switching transistor SW2 can be connected to the second data line DL2. Furthermore, the gate and source (or drain) nodes of the third switching transistor SW3 can be connected to the third auxiliary line AL3, and the drain (or source) node of the third switching transistor SW3 can be connected to the third data line DL3. Additionally, the gate and source (or drain) nodes of the fourth switching transistor SW4 can be connected to the fourth auxiliary line AL4, and the drain (or source) node of the fourth switching transistor SW4 can be connected to the fourth data line DL4, but this is not a limitation.

[0213] Therefore, if a first auxiliary voltage of the conduction level is applied to the first auxiliary line AL1, the first switching transistor SW1 is turned on, allowing the first auxiliary line AL1 and the first data line DL1 to be electrically connected. Furthermore, if a second auxiliary voltage of the conduction level is applied to the second auxiliary line AL2, the second switching transistor SW2 is turned on, allowing the second auxiliary line AL2 and the second data line DL2 to be electrically connected. Furthermore, if a third auxiliary voltage of the conduction level is applied to the third auxiliary line AL3, the third switching transistor SW3 is turned on, allowing the third auxiliary line AL3 and the third data line DL3 to be electrically connected. Furthermore, if a fourth auxiliary voltage of the conduction level is applied to the fourth auxiliary line AL4, the fourth switching transistor SW4 is turned on, allowing the fourth auxiliary line AL4 and the fourth data line DL4 to be electrically connected.

[0214] Therefore, the display device 100 of this disclosure can use the switching circuit 170 to apply an auxiliary voltage in the segment of the threshold voltage Vth used for sensing the driving transistor DRT, thereby electrically connecting the auxiliary line AL and the data line DL, and precisely controlling the sensing data voltage Vdata_SEN.

[0215] In this case, the auxiliary line AL used to apply the auxiliary voltage can be located in the area where the gating drive panel circuit is set in the display panel 110.

[0216] Figure 12 The layout of the gating border area where the auxiliary lines are located in the display panel of a display device according to an exemplary embodiment of the present disclosure is shown as an example.

[0217] Reference Figure 12 In a display panel 110 according to an exemplary embodiment of the present disclosure, the gating border area GBA may include a clock signal line area CLA, a first power line area PLA1, a gating drive panel circuit area GPCA, and a second power line area PLA2.

[0218] The gate driver panel circuit area GPCA can be the area where the gate driver panel circuit GPC is set. In this case, various wiring for providing power, voltage, and signals to the gate driver panel circuit GPC can be arranged around the gate driver panel circuit area GPCA. Therefore, in the gate frame area GBA, the clock signal line area CLA, the first power line area PLA1, and the second power line area PLA2 can be formed around the gate driver panel circuit area GPCA.

[0219] For example, the clock signal line region CLA and the first power line region PLA1 can be located on one side of the gating drive panel circuit region GPCA, while the second power line region PLA2 can be located on the other side of the gating drive panel circuit region GPCA. Therefore, the gating drive panel circuit region GPCA can be located on one side of the second power line region PLA2, while the display region DA can be located on the other side of the second power line region PLA2, but this disclosure is not limited thereto.

[0220] The clock signal line area (CLA) can be an area equipped with clock signal lines for transmitting various clock signals to the gating drive panel circuit (GPC).

[0221] The first power line region PLA1 can be a region provided with multiple first power lines. The multiple first power lines may include at least one gating high-potential voltage line for transmitting at least one gating high-potential voltage to the gating drive panel circuit GPC.

[0222] The second power line region PLA2 can be a region with multiple second power lines. The multiple second power lines may include at least one gating low-potential voltage line for transmitting at least one gating low-potential voltage to the gating drive panel circuit GPC.

[0223] The auxiliary line AL for transmitting auxiliary voltage can be located in the second power line area PLA2, which is close to the display area DA.

[0224] The clock signal line area CLA can include the carry clock signal line area CRC, the scan clock signal line area SCC, and the sense clock signal line area SEC.

[0225] The carry clock signal line area (CRC) can be an area with a carry clock signal line for sending a carry clock signal to the gating drive panel circuit (GPC).

[0226] The scan clock signal line area SCC can be an area provided with scan clock signal lines for sending scan clock signals to the gating drive panel circuit GPC.

[0227] The sensing clock signal line area SEC can be an area provided with sensing clock signal lines for sending sensing clock signals to the gating drive panel circuit GPC.

[0228] The gating drive panel circuit (GPC) located in the gating drive panel circuit area GPCA can include a first gating drive panel circuit (GPC #1) and a second gating drive panel circuit (GPC #2).

[0229] The first gating drive panel circuit GPC #1 may include a first output buffer block BUF #1, a first logic block LOGIC #1, and a first real-time sensing control block RT #1.

[0230] The first output buffer block BUF #1 can be configured to output the first scan signal SC1 and the first sensing signal SE1 to the first scan signal line SCL1 and the first sensing signal line SENL1 ​​connected to the first sub-pixel SP, respectively. For example, the first scan signal SC1 can be the nth scan signal SC(n), and the first sensing signal SE1 can be the nth sensing signal SE(n).

[0231] The first logic block LOGIC #1 can be configured to control the operation of the first output buffer block BUF #1 by controlling the voltages of the Q nodes and QB nodes of the first gating driver panel circuit GPC #1, respectively.

[0232] The second gating driver panel circuit GPC #2 can consist of only the second output buffer block BUF #2 and the second logic block LOGIC #2.

[0233] The second output buffer block BUF #2 can be configured to output the second scan signal SC2 and the second sensing signal SE2 to the second scan signal line SCL2 and the second sensing signal line SENL2 connected to the second sub-pixel SP, respectively. For example, the second scan signal SC2 can be the (n+1)th scan signal SC(n+1), and the second sensing signal SE2 can be the (n+1)th sensing signal SE(n+1).

[0234] The second logic block LOGIC #2 can be configured to control the operation of the second output buffer block BUF #2 by controlling the voltages of the Q nodes and QB nodes of the second gating driver panel circuit GPC #2, respectively.

[0235] As described above, the first gating drive panel circuit GPC #1 may include a first output buffer block BUF #1, a first logic block LOGIC #1, and a first real-time sensing control block RT #1, and the second gating drive panel circuit GPC #2 may only include a second output buffer block BUF #2 and a second logic block LOGIC #2, without the real-time sensing control block. The first real-time sensing control block RT #1 may be shared by the first gating drive panel circuit GPC #1 and the second gating drive panel circuit GPC #2. Therefore, the size of the gating frame area GBA can be significantly reduced.

[0236] The first real-time sensing control block RT #1 can be configured to control the operation of the first output buffer block BUF #1, such that the first output buffer block BUF #1 outputs the first scan signal SC1 and the first sensing signal SE1 for sensing drive to the first sub-pixel SP where real-time sensing drive is performed by controlling the voltages of the Q node and QB node of the first gating drive panel circuit GPC #1 respectively during the first real-time sensing drive period (e.g., the first blank period).

[0237] At least one specific node of the first logic block LOGIC #1 and at least one specific node of the second logic block LOGIC #2 can be electrically connected to each other.

[0238] Figure 13 and Figure 14 This is a signal waveform diagram illustrating, as an example, the generation of a sensing data voltage by synthesizing an auxiliary voltage and a data voltage in a display device according to an exemplary embodiment of the present disclosure.

[0239] First, refer to Figure 13 According to an exemplary embodiment of the present disclosure, the display device 100 can generate a sensing data voltage by applying an auxiliary voltage VAL through an auxiliary line AL during a tracking period T2 in the segment of the threshold voltage Vth used for sensing the driving transistor DRT.

[0240] Specifically, during the tracking period T2, the data driving circuit 130 transmits the first sensed data voltage Vdata_SEN1 via the data line DL. Furthermore, the power management circuit 150 transmits the auxiliary voltage VAL via the auxiliary line AL. Since the switching circuit 170 is turned on by the auxiliary voltage VAL, the second sensed data voltage Vdata_SEN2 can be generated from the first sensed data voltage Vdata_SEN1 and the auxiliary voltage VAL.

[0241] For example, during the tracking period T2, the data driving circuit 130 can supply the first sensing data voltage Vdata_SEN1 of the third sensing level SEN3 to the data line DL. Furthermore, the power management circuit 150 can apply an auxiliary voltage VAL higher than the first sensing level SEN1 during the pulse period Tp within the tracking period T2, and gradually decrease it to the second sensing level SEN2 during the slope period Ts.

[0242] As a result, the second sensing data voltage Vdata_SEN2 applied to the gate node of the driving transistor DRT through the data line DL during the tracking period T2 is formed into a pulse waveform of the first sensing level SEN1 during the pulse period Tp, and gradually decreases to the second sensing level SEN2 during the slope period Ts.

[0243] In addition, refer to Figure 14 The display device 100 of this disclosure can apply a first sensing data voltage Vdata_SEN1 and an auxiliary voltage VAL in an overshoot manner during a pulse period Tp within a tracking period T2.

[0244] For example, the data driving circuit 130 can apply a first sense data voltage Vdata_SEN1, which has a first sense level SEN1 in the pulse period Tp and a second sense level SEN2 in the slope period Ts, to the data line DL.

[0245] In addition, the power management circuit 150 can apply an auxiliary voltage VAL to the auxiliary line AL, which has a first sensing level SEN1 during the pulse period Tp, but gradually decreases to a second sensing level SEN2 during the slope period Ts.

[0246] With the first sensing data voltage Vdata_SEN1 and the auxiliary voltage VAL, the second sensing data voltage Vdata_SEN2 maintains the first sensing level SEN1 during the pulse period Tp, but can exhibit a waveform that gradually decreases from a level lower than the first sensing level SEN1 to the second sensing level SEN2 during the slope period Ts.

[0247] Therefore, the display device 100 of this disclosure applies a second sensing data voltage Vdata_SEN2 with a first sensing level SEN1 in a pulse form during the pulse period Tp of the tracking period T2, and gradually decreases from the first sensing level SEN1 to the second sensing level SEN2 during the slope period Ts, thereby shortening the sensing time of the threshold voltage Vth of the driving transistor DRT and improving the sensing accuracy.

[0248] The display device according to an exemplary embodiment of the present disclosure can be described as follows.

[0249] The display device disclosed herein may include a display panel in which a plurality of sub-pixels driven by a sub-pixel circuit having driving transistors are arranged in a display area; a data driving circuit configured to supply data voltages to the plurality of sub-pixels via a plurality of data lines; a gating driving circuit configured to supply gating signals to the plurality of sub-pixels via a plurality of gating lines; a power management circuit configured to supply power required to drive the display panel, the data driving circuit, and the gating driving circuit; and a switching circuit configured to generate a sensed data voltage by controlling the connection between the plurality of auxiliary lines extending from the power management circuit and the plurality of data lines, the sensed data voltage being obtained by combining an auxiliary voltage transmitted via the plurality of auxiliary lines with a data voltage transmitted via the plurality of data lines.

[0250] Multiple auxiliary lines can be extended along the non-display area outside the display area.

[0251] The non-display area may include a gating drive panel circuit area, in which the gating drive circuit is configured as a gated-in-panel (GIP) type; a clock signal line area, in which a clock signal line for sending a clock signal to the gating drive circuit is provided; a first power line area, in which a gating high potential voltage line for transmitting a gating high potential voltage to the gating drive circuit is provided outside the gating drive panel circuit area; and a second power line area, in which the plurality of auxiliary lines and a gating low potential voltage line for transmitting a gating low potential voltage to the gating drive circuit are provided between the gating drive panel circuit area and the display area.

[0252] The gating drive panel circuit area includes a first gating drive panel circuit and a second gating drive panel circuit. The first gating drive panel circuit includes a first output buffer block, a first logic block, and a first real-time sensing control block. The second gating drive panel circuit includes a second output buffer block and a second logic block. The first real-time sensing control block is shared by both the first gating drive panel circuit and the second gating drive panel circuit.

[0253] The switching circuit can be located on the opposite side of the data drive circuit in the display panel.

[0254] The switching circuit may include a first switching transistor, wherein a first auxiliary line is connected to the gate node and the source node, and a first data line is connected to the drain node; a second switching transistor, wherein a second auxiliary line is connected to the gate node and the source node, and a second data line is connected to the drain node; and a third switching transistor, wherein a third auxiliary line is connected to the gate node and the source node, and a third data line is connected to the drain node.

[0255] The switching circuit may further include a fourth switching transistor, in which a fourth auxiliary line is connected to the gate node and the source node, and a fourth data line is connected to the drain node.

[0256] The sensing data voltage can be generated during the sensing drive period when the threshold voltage of the sensing drive transistor is used to sense the data.

[0257] The sensing drive period may include: an initialization period for initializing the gate node and source node of the driving transistor; a tracking period for tracking the voltage of the source node of the driving transistor; and a sampling period for sampling the voltage of the source node after the voltage of the source node of the driving transistor has saturated. In this case, the tracking period may include a pulse period for applying a pulse waveform of the sensed data voltage; and a slope period in which the sensed data voltage gradually decreases after the pulse period.

[0258] The sensed data voltage can be maintained at a first sense level during the initialization period, at a second sense level during the pulse period within the tracking interval, and at a third sense level during the sampling interval. In this case, the second sense level can be 25% to 60% higher than the third sense level.

[0259] The slope period can have the same time interval as the pulse period.

[0260] The data driving circuit can maintain the sensed data voltage at the third sense level during the tracking period, and the power management circuit can maintain the auxiliary voltage at a level higher than the second sense level during the pulse period, and can gradually reduce the auxiliary voltage to the third sense level during the slope period.

[0261] The data driving circuit can maintain the sensed data voltage at a second sense level during the pulse period and at a third sense level during the slope period. The power management circuit can maintain the auxiliary voltage at the second sense level during the pulse period and gradually reduce the auxiliary voltage to the third sense level during the slope period.

[0262] A display device according to another exemplary embodiment of the present disclosure may include: a data driving circuit configured to supply a data voltage during a display driving period and a first sensing data voltage during a sensing driving period via multiple data lines connected to multiple sub-pixels; a power management circuit configured to supply power required to drive the data driving circuit; and a switching circuit configured to generate a second sensing data voltage by controlling the connection between multiple auxiliary lines and multiple data lines extending from the power management circuit, using an auxiliary voltage transmitted via the multiple auxiliary lines and the first sensing data voltage transmitted via the multiple data lines.

[0263] The display driving method disclosed herein is a driving method for sensing a threshold voltage of a driving transistor, the driving transistor comprising a plurality of sub-pixels arranged to display an image on a display panel. The display driving method may include: an initialization step for initializing the gate node and source node of the driving transistor; a tracking step for tracking the voltage of the source node of the driving transistor; and a sampling step for sampling the voltage of the source node after the voltage of the source node of the driving transistor has saturated. In this case, the tracking step may include: generating a sensed data voltage applied to the gate node of the driving transistor as a pulse waveform during a pulse period; and gradually decreasing the sensed data voltage after the pulse period during a slope period.

[0264] The sensing data voltage can be generated by combining the data voltage transmitted through multiple data lines set in the display area of ​​the display panel and the auxiliary voltage transmitted through multiple auxiliary lines set in the non-display area of ​​the display panel.

[0265] The sensed data voltage can be maintained at a first sense level during the initialization period, at a second sense level during the pulse period within the tracking period, and at a third sense level during the sampling period. In this case, the second sense level can be 25% to 60% higher than the third sense level.

[0266] The slope period can have the same time interval as the pulse period.

[0267] During the tracking step, the data voltage is maintained at the third sensing level. During the pulse period, the auxiliary voltage is maintained at a level higher than the second sensing level. During the slope period, the auxiliary voltage can be gradually reduced to the third sensing level.

[0268] During the pulse period, the data voltage and auxiliary voltage can be maintained at the second sensing level, and during the slope period, the data voltage can be maintained at the third level, while the auxiliary voltage can be gradually reduced to the third sensing level.

[0269] The above description is provided to enable those skilled in the art to implement and use the technical concept of the invention, and is given in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described exemplary embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other exemplary embodiments and applications without departing from the spirit and scope of the invention. The above description and figures are provided for illustrative purposes only, illustrating the technical concept of the invention. That is, the disclosed exemplary embodiments are intended to illustrate the scope of the technical idea of ​​the invention.

[0270] Cross-references to related applications

[0271] This application claims priority and benefit to Korean Patent Application No. 10-2025-0055319, filed on April 28, 2025, the entire contents of which are hereby expressly incorporated herein by reference for all purposes.

Claims

1. A display device, the display device comprising: A display panel in which a plurality of sub-pixels driven by sub-pixel circuits including driving transistors are arranged in a display area; A data driving circuit is configured to supply a data voltage during a display driving period and a first sensing data voltage during a sensing driving period via multiple data lines connected to the plurality of sub-pixels. A gating driving circuit, the gating driving circuit being configured to supply gating signals through multiple gating lines connected to the plurality of sub-pixels; A power management circuit, configured to supply power required to drive the display panel, the data driving circuit, and the gating driving circuit; as well as A switching circuit configured to generate a second sensing data voltage by controlling the connection between a plurality of auxiliary lines extending from the power management circuit and the plurality of data lines, using an auxiliary voltage transmitted through the plurality of auxiliary lines and a first sensing data voltage transmitted through the plurality of data lines.

2. The display device according to claim 1, wherein, The multiple auxiliary lines extend along the non-display area outside the display area.

3. The display device according to claim 2, wherein, The non-display area includes: A gating drive panel circuit area, wherein the gating drive circuit is configured in the gating drive panel circuit area by a gating GIP type within the panel; A clock signal line region is provided in which clock signal lines are provided for sending clock signals to the gating drive circuit; A first electric field line region, wherein a high-potential voltage line for transmitting a high-potential voltage to the gating drive circuit is disposed outside the gating drive panel circuit region; and In the second power line region, the plurality of auxiliary lines and the gating low potential voltage line for transmitting the gating low potential voltage to the gating drive circuit are disposed between the gating drive panel circuit region and the display region.

4. The display device according to claim 3, wherein, The gating drive panel circuit area includes a first gating drive panel circuit and a second gating drive panel circuit. The first gating drive panel circuit includes a first output buffer block, a first logic block, and a first real-time sensing control block. The second gating drive panel circuit includes a second output buffer block and a second logic block, and The first real-time sensing control block is shared by both the first gating drive panel circuit and the second gating drive panel circuit.

5. The display device according to claim 1, wherein, The switching circuit is located on the opposite side of the data driving circuit in the display panel.

6. The display device according to claim 1, wherein, The switching circuit includes: A first switching transistor, wherein a first auxiliary line is connected to the gate node and the source node, and a first data line is connected to the drain node; A second switching transistor, wherein a second auxiliary line is connected to the gate node and the source node, and a second data line is connected to the drain node; and The third switching transistor has a third auxiliary line connected to the gate node and the source node, and a third data line connected to the drain node.

7. The display device according to claim 6, wherein, The switching circuit also includes: A fourth switching transistor, wherein a fourth auxiliary line is connected to the gate node and the source node, and a fourth data line is connected to the drain node.

8. The display device according to claim 1, wherein, The second sensing data voltage is generated during the sensing drive period used to sense the threshold voltage of the driving transistor.

9. The display device according to claim 8, wherein, The sensing drive period includes: An initialization period is used to initialize the gate node and source node of the driving transistor; A tracking period, the tracking period being used to track the voltage of the source node of the driving transistor; and The sampling period is used to sample the voltage of the source node after the voltage of the source node of the driving transistor has saturated. The tracking period includes: A pulse period in which the second sensed data voltage is applied as a pulse waveform of the first sensed level; and During the slope period, the second sensed data voltage gradually decreases to the second sensed level after the pulse period.

10. The display device according to claim 9, wherein, The first sensing level has a level that is 25% to 60% higher than the second sensing level.

11. The display device according to claim 10, wherein, The slope period has the same time interval as the pulse period.

12. The display device according to claim 10, wherein, The data driving circuit maintains the first sensed data voltage at the second sensed level during the tracking period, and The power management circuit maintains the auxiliary voltage at a level higher than the first sensing level during the pulse period, and gradually reduces the auxiliary voltage to the second sensing level during the slope period.

13. The display device according to claim 9, wherein, The data driving circuit maintains the first sensed data voltage at the first sensed level during the pulse period, and maintains the first sensed data voltage at the second sensed level during the slope period. The power management circuit maintains the auxiliary voltage at the first sensing level during the pulse period and gradually reduces the auxiliary voltage to the second sensing level during the slope period.

14. A display device comprising: A data driving circuit is configured to supply a data voltage during a display driving period and a first sensing data voltage during a sensing driving period via multiple data lines connected to multiple sub-pixels. A power management circuit, configured to supply the power required to drive the data drive circuit; as well as A switching circuit configured to generate a second sensing data voltage by controlling the connection between a plurality of auxiliary lines extending from the power management circuit and the plurality of data lines, using an auxiliary voltage transmitted through the plurality of auxiliary lines and a first sensing data voltage transmitted through the plurality of data lines.

15. A display driving method for sensing a threshold voltage of a driving transistor, the driving transistor being included in a plurality of sub-pixels arranged to display an image on a display panel, the display driving method comprising: An initialization step, wherein the initialization step is used to initialize the gate node and source node of the driving transistor; A tracking step, wherein the tracking step is used to track the voltage of the source node of the driving transistor; as well as A sampling step, wherein the sampling step is used to sample the voltage of the source node after the voltage of the source node of the driving transistor has saturated. The tracking steps include: During the pulse period, the sensed data voltage applied to the gate node of the driving transistor is generated as a pulse waveform of the first sense level; and During the slope period, the sensing data voltage is gradually reduced to the second sensing level after the pulse period.

16. The display driving method according to claim 15, wherein, The sensing data voltage is generated using a first sensing data voltage transmitted via multiple data lines disposed in the display area of ​​the display panel and an auxiliary voltage transmitted via multiple auxiliary lines disposed in the non-display area of ​​the display panel.

17. The display driving method according to claim 16, wherein, The first sensing level has a level that is 25% to 60% higher than the second sensing level.

18. The display driving method according to claim 17, wherein, The slope period has the same time interval as the pulse period.

19. The display driving method according to claim 17, wherein, During the tracking step, the first sensed data voltage is maintained at the second sensed level. During the pulse period, the auxiliary voltage is maintained at a level higher than the first sensing level, and During the slope period, the auxiliary voltage gradually decreases to the second sensing level.

20. The display driving method according to claim 19, wherein, During the pulse period, the first sensing data voltage and the auxiliary voltage are maintained at the first sensing level, and During the slope period, the first sensing data voltage remains at the second sensing level, and the auxiliary voltage gradually decreases to the second sensing level.

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