A display panel and display device

Abstract

The application discloses a display panel and a display device, which comprise a first voltage selection module and a plurality of pixel circuits, the pixel circuit comprising a driving module, a compensation module and a light-emitting module; the first voltage selection module is connected with at least one pixel circuit; the driving module comprises a double-gate transistor, the first electrode of the double-gate transistor is connected with the first voltage selection module, the second gate of the double-gate transistor is connected with the first electrode of the double-gate transistor, and the double-gate transistor is used for driving the light-emitting module to emit light; the compensation module is connected between the second electrode of the double-gate transistor and the first gate of the double-gate transistor; wherein the first voltage selection module is used for transmitting a first power supply voltage or a second power supply voltage to the first electrode of the double-gate transistor in time sharing mode; the first power supply voltage is used for simultaneously resetting the first electrode of the double-gate transistor and the first gate of the double-gate transistor. The application can realize the super-high PPI display arrangement, and solve the display uniformity and residual image problems.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread.

[0003] Display panels include pixel circuits. However, existing pixel circuits struggle to effectively address display uniformity and ghosting issues while achieving ultra-high pixel density (Pixels Per Inch, PPI) display arrangements. Summary of the Invention

[0004] This invention provides a display panel and display device that can solve the problems of display uniformity and ghosting while achieving ultra-high PPI display layout.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: a first voltage selection module and a plurality of pixel circuits, wherein the pixel circuits include a driving module and a compensation module; the first voltage selection module is connected to at least one pixel circuit, the driving module includes a dual-gate transistor, the dual-gate transistor including a first terminal, a second terminal, a first gate and a second gate, the first terminal of the dual-gate transistor being connected to the first voltage selection module, and the second gate of the dual-gate transistor being connected to the first terminal of the dual-gate transistor; the compensation module is connected between the second terminal of the dual-gate transistor and the first gate of the dual-gate transistor; wherein the first voltage selection module is used to transmit a first power supply voltage or a second power supply voltage to the first terminal of the dual-gate transistor in a time-division manner; the first power supply voltage is used to simultaneously reset the first terminal and the first gate of the dual-gate transistor.

[0006] Optionally, the first voltage selection module includes a first input terminal, a second input terminal, a first control terminal, a second control terminal, and a first output terminal; the first output terminal is connected to the first electrode of the dual-gate transistor, the first input terminal is connected to a first power supply voltage, and the second input terminal is connected to a second power supply voltage; the first voltage selection module is used to transmit the first power supply voltage to the first electrode of the dual-gate transistor in response to the signal of the first control terminal during the initialization phase; and is used to transmit the second power supply voltage to the first electrode of the dual-gate transistor in response to the signal of the second control terminal during the threshold voltage characteristic adjustment phase; wherein, within one frame, the initialization phase is located before the threshold voltage characteristic adjustment phase.

[0007] Optionally, the first voltage selection module includes a first transistor and a second transistor. The gate of the first transistor serves as the first control terminal of the first voltage selection module, the first electrode of the first transistor serves as the first input terminal of the first voltage selection module, and the second electrode of the first transistor serves as the first output terminal of the first voltage selection module. The gate of the second transistor serves as the second control terminal of the first voltage selection module, the first electrode of the second transistor serves as the second input terminal of the first voltage selection module, and the second electrode of the second transistor serves as the first output terminal of the first voltage selection module.

[0008] Optionally, the first transistor and the second transistor have the same channel type, the first control terminal is connected to the first control signal, and the second control terminal is connected to the second control signal; wherein the first control signal and the second control signal are inverse signals to each other.

[0009] Optionally, the first control signal and the second control signal are global signals.

[0010] Optionally, the first transistor and the second transistor have different channel types, and the first control terminal and the second control terminal are connected to the fifth control signal.

[0011] Optionally, the display panel also includes multiple first power lines and multiple second power lines, wherein the first power lines are used to provide a first power voltage to the corresponding first voltage selection module, and the second power lines are used to provide a second power voltage to the corresponding first voltage selection module.

[0012] Optionally, the control terminal of the compensation module is connected to the first scan line, and the first scan line transmits a first scan signal; the compensation module is used to turn on in response to a first turn-on pulse of the first scan signal during the initialization phase to transmit the first power supply voltage to the first gate of the dual-gate transistor; and to turn on in response to a second turn-on pulse of the first scan signal during the compensation phase; during the threshold voltage characteristic adjustment phase, the compensation module is configured to turn off by the first scan signal; within one frame, the threshold voltage characteristic adjustment phase is located between the initialization phase and the compensation phase.

[0013] Optionally, the duration of the second conduction pulse of the first scan signal is longer than the duration of the first conduction pulse of the first scan signal.

[0014] Optionally, the first gate of the dual-gate transistor is the top gate, and the second gate of the dual-gate transistor is the bottom gate.

[0015] Optionally, the first gate of the dual-gate transistor is the bottom gate, and the second gate of the dual-gate transistor is the top gate.

[0016] Optionally, the pixel circuit further includes a data writing module and a first storage module; the first storage module is connected between the first node and the first gate of the dual-gate transistor, and is used to store the voltage difference between the first node and the first gate of the dual-gate transistor; the first end of the data writing module is connected to a data line, and the second end of the data writing module is connected to the first node; the data writing module is used to transmit the initialization voltage input to the data line to the first node during the initialization phase; and to transmit the data voltage input to the data line to the first node during the data writing phase; wherein, within a frame, the data writing phase is located after the initialization phase.

[0017] Optionally, the display panel further includes a second voltage selection module, which includes a third input terminal, a fourth input terminal, a third control terminal, a fourth control terminal, and a second output terminal; the second output terminal is connected to the data line; the third input terminal is connected to an initialization voltage, and the fourth input terminal is connected to a data voltage; the second voltage selection module is used to transmit the initialization voltage to the data line in response to the signal from the third control terminal during the initialization phase; and is used to transmit the data voltage to the data line in response to the signal from the fourth control terminal during the data writing phase.

[0018] Optionally, the second voltage selection module includes a third transistor and a fourth transistor; the gate of the third transistor serves as the third control terminal of the second voltage selection module, the first terminal of the third transistor serves as the third input terminal of the second voltage selection module, and the second terminal of the third transistor serves as the second output terminal of the second voltage selection module; the gate of the fourth transistor serves as the fourth control terminal of the second voltage selection module, the first terminal of the fourth transistor serves as the fourth input terminal of the second voltage selection module, and the second terminal of the fourth transistor serves as the second output terminal of the second voltage selection module.

[0019] Optionally, the third transistor and the fourth transistor have the same channel type, the third control terminal is connected to the third control signal, and the fourth control terminal is connected to the fourth control signal; wherein the third control signal and the fourth control signal are inverted signals.

[0020] Optionally, the third and fourth control signals are global signals.

[0021] Optionally, the third transistor and the fourth transistor have different channel types, and the third control terminal and the fourth control terminal are connected to the sixth control signal.

[0022] Optionally, the control terminal of the data writing module is connected to the second scan line, and the second scan line transmits the second scan signal; the data writing module is used to transmit the initialization voltage input to the data line to the first node in response to the first conduction pulse of the second scan signal during the initialization phase; and to transmit the data voltage input to the data line to the first node in response to the second conduction pulse of the second scan signal during the data writing phase.

[0023] Optionally, the control terminal of the compensation module is connected to the first scan line, and the first scan line transmits a first scan signal; the first scan signal includes a first conduction pulse and a second conduction pulse. The duration of the first conduction pulse of the first scan signal is greater than the duration of the second conduction pulse of the second scan signal; the duration of the second conduction pulse of the first scan signal is less than the duration of the first conduction pulse of the second scan signal.

[0024] Optionally, the pixel circuit further includes a light emission control module and a light emission module; the light emission control module is disposed between the second terminal of the dual-gate transistor and the first terminal of the light emission module, and the second terminal of the light emission module is connected to a third power supply line; the control terminal of the light emission control module is connected to the light emission control line; the light emission control module is used to turn on the light emission control signal on the light emission control line in response to the initialization phase and the light emission phase.

[0025] Optionally, the first power supply voltage is used to simultaneously reset the first terminal of the dual-gate transistor, the first gate of the dual-gate transistor, and the first terminal of the light-emitting module.

[0026] Optionally, the light emission control module is used to turn off during the threshold voltage characteristic adjustment stage, the compensation stage, and the data writing stage.

[0027] Optionally, the control terminal of the compensation module is connected to the first scan line, and the first scan line transmits the first scan signal; within one frame, the start time of the turn-on pulse of the first scan signal is earlier than the start time of the turn-off pulse of the light emission control signal, and later than the start time of the first turn-on pulse of the second scan signal, the end time of the turn-on pulse of the first scan signal is earlier than the end time of the first turn-on pulse of the second scan signal, and the end time of the first turn-on pulse of the second scan signal is earlier than the end time of the turn-off pulse of the light emission control signal.

[0028] Optionally, the data writing module includes a data writing transistor, the compensation module includes a compensation transistor, and the light emission control module includes a light emission control transistor; the gate of the compensation transistor is connected to a first scan line, the first terminal of the compensation transistor is connected to the second terminal of the dual-gate transistor, and the second terminal of the compensation transistor is connected to the first gate of the dual-gate transistor; the gate of the data writing transistor is connected to a second scan line, the first terminal of the data writing transistor is connected to a data line, and the second terminal of the data writing transistor is connected to a first node; the gate of the light emission control transistor is connected to a light emission control line, the first terminal of the light emission control transistor is connected to the second terminal of the dual-gate transistor, and the second terminal of the light emission control transistor is connected to the first end of the light emission module.

[0029] Optionally, the data writing transistor is a four-terminal device with a first gate and a second gate. The first gate of the data writing transistor is connected to the second scan line, and the second gate of the data writing transistor is connected to the second terminal of the data writing transistor.

[0030] Optionally, the compensation transistor is a four-terminal device with a first gate and a second gate, wherein the first gate of the compensation transistor is connected to the first scan line, and the second gate of the compensation transistor is connected to the second terminal of the compensation transistor.

[0031] Optionally, the compensation transistor is a four-terminal device with a first gate and a second gate. The first gate of the compensation transistor is connected to a first scan line, and the second gate of the compensation transistor is connected to a first voltage control signal line. The first voltage control signal line is used to transmit voltage to the second gate of the compensation transistor to control the threshold voltage of the compensation transistor.

[0032] Optionally, the first power supply line is multiplexed as a first voltage control signal line.

[0033] Optionally, the second power supply line can be multiplexed as a second voltage control signal line.

[0034] Optionally, the dual-gate transistor and the light-emitting control transistor are polycrystalline silicon thin-film transistors, and the compensation transistor and the data writing transistor are oxide thin-film transistors; the display panel also includes a substrate and a first active layer and a second active layer sequentially stacked in a direction away from the substrate; the channel regions of the dual-gate transistor and the light-emitting control transistor are located in the first active layer; the channel regions of the compensation transistor and the data writing transistor are located in the second active layer; the orthographic projection of the first active layer on the substrate and the orthographic projection of the second active layer on the substrate have an overlapping portion.

[0035] Optionally, in a frame, the operation of a pixel circuit includes an initialization phase, a threshold voltage characteristic adjustment phase, a compensation phase, a data writing phase, and a light emission phase performed sequentially. The initialization phase of each pixel circuit is performed simultaneously, the threshold voltage characteristic adjustment phase of each pixel circuit is performed simultaneously, the compensation phase of each pixel circuit is performed simultaneously, the data writing phase of each row of pixel circuits is performed row by row, and the light emission phase of each pixel circuit is performed simultaneously.

[0036] Optionally, the pixel circuit further includes a second storage module connected between the first node and the first electrode of the dual-gate transistor, for storing the voltage difference between the first node and the first electrode of the dual-gate transistor.

[0037] Secondly, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0038] The display panel provided in this embodiment of the invention includes a first voltage selection module and multiple pixel circuits. Each pixel circuit includes a driving module and a compensation module. The driving module includes a dual-gate transistor (DMT), with its second gate connected to its first terminal. The first voltage selection module transmits either a first power supply voltage or a second power supply voltage to the first terminal of the DMT in a time-division multiplexing manner. This eliminates the need for an additional second gate control signal line; automatic adjustment of the second gate potential can be achieved solely through voltage switching at the first terminal of the DMT. This simplifies signal routing, saves layout space, and enables ultra-high PPI display layouts. During the initialization phase, the first power supply voltage is transmitted to both the first terminal and the first gate of the DMT, simultaneously resetting both terminals and the first gate. This effectively eliminates residual charge from the previous frame, resolving the ghosting problem. The compensation module is turned on during the initialization and compensation phases and turned off during the threshold voltage characteristic adjustment phase. The same compensation module performs three functions—reset on, characteristic adjustment off, and compensation on—at different phases, eliminating the need for additional functional modules and further reducing the number of transistors. Simultaneously, during the threshold voltage characteristic adjustment phase, the first voltage selection module transmits a second power supply voltage to the first terminal of the dual-gate transistor, making the gate-source voltage of the dual-gate transistor a large negative voltage, thereby adjusting the characteristics of the dual-gate transistor and restoring the threshold voltage to its initial state. Furthermore, the compensation module is activated during the compensation phase to compensate for the threshold voltage of the dual-gate transistor. Through the above methods, the display panel of this embodiment effectively solves the problems of display uniformity and ghosting while reducing the number of transistors and signal traces to achieve an ultra-high PPI display arrangement, thus improving the display effect.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the connection structure between a first voltage selection module and a pixel circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another connection structure between the first voltage selection module and the pixel circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the connection structure between a second voltage selection module and a pixel circuit provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another connection structure between the second voltage selection module and the pixel circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 13 This is a driving timing waveform diagram of a pixel circuit provided in an embodiment of the present invention; Figure 14 This is a simulation waveform diagram of the timing node voltage of a pixel circuit drive provided by an embodiment of the present invention; Figure 15 This is a simulation waveform diagram showing the effect of threshold voltage fluctuation of driving transistor on luminous current in a pixel circuit according to an embodiment of the present invention; Figure 16 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 17 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 18 This is another simulation waveform diagram of the timing node voltage of the pixel circuit driving provided by the embodiment of the present invention; Figure 19 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 20 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 21 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0044] In recent years, Virtual Reality (VR) technology has been widely applied in various fields, and its demand for high-resolution displays is increasing. Currently, mature pixel circuits such as the 7T1C circuit have complete functions, but due to the large number of thin-film transistors (TFTs), ultra-high PPI cannot be achieved due to limitations in process technology. On the other hand, the conventional 2T1C circuit solution has fewer TFT devices, which can significantly improve PPI, but this solution lacks functions such as gate initialization and anode initialization, or cannot achieve functions such as threshold voltage compensation inside the pixel, often causing display problems such as image retention and uneven display, and thus cannot meet application requirements.

[0045] Based on the above reasons, embodiments of the present invention provide a display panel and a display device that can achieve ultra-high PPI display arrangement while simultaneously realizing gate reset of driving transistors, anode reset of light-emitting elements, and threshold compensation, thereby improving display uniformity and reducing image retention. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. (Reference) Figure 1 and Figure 2 The display panel includes a first voltage selection module 10 and multiple pixel circuits 20, each pixel circuit 20 including a driving module 110 and a compensation module 120.

[0046] The first voltage selection module 10 is connected to at least one pixel circuit 20. The driving module 110 includes a dual-gate transistor M1, which includes a first terminal S, a second terminal D, a first gate G, and a second gate. The first terminal S of the dual-gate transistor M1 is connected to the first voltage selection module 10, and the second gate of the dual-gate transistor M1 is connected to the first terminal S of the dual-gate transistor M1.

[0047] The compensation module 120 is connected between the second electrode D of the dual-gate transistor M1 and the first gate G of the dual-gate transistor M1.

[0048] The first voltage selection module 10 is used to transmit a first power supply voltage VDDL or a second power supply voltage VDDH to the first terminal S of the dual-gate transistor M1 in a time-division manner; the first power supply voltage VDDL is used to simultaneously reset the first terminal S of the dual-gate transistor M1 and the first gate of the dual-gate transistor.

[0049] Specifically, the display panel includes a display area AA and a non-display area NAA. The display panel includes multiple first voltage selection modules 10. The first voltage selection modules 10 are located in the non-display area NAA, and the pixel circuits 20 are located in the display area AA.

[0050] In some embodiments, the display panel further includes multiple signal transmission lines 100, with the output terminal of the first voltage selection module 10 connected to each signal transmission line 100 in a one-to-one correspondence; each signal transmission line 100 is connected to the first terminal of the dual-gate transistor M1 of a column of pixel circuits 20. In this configuration, the output terminal of the first voltage selection module 10 is connected to the first terminal S of the dual-gate transistor M1 of each row of pixel circuits in the column of pixel circuits 20 via a signal transmission line 100. The first voltage selection module 10 provides a first power supply voltage VDDL or a second power supply voltage VDDH to the signal transmission line in a time-division multiplexing manner, and the first terminal S of the dual-gate transistor M1 of each pixel circuit in the column of pixel circuits 20 simultaneously receives the voltage. This configuration results in neat wiring and is suitable for display panels with conventional resolutions. Figure 1 This situation is illustrated.

[0051] In other embodiments, a first voltage selection module 10 is connected to two or more columns of pixel circuits 20. In this configuration, the output of the first voltage selection module 10 is connected to multiple signal transmission lines, each corresponding to one column of pixel circuits 20. The first voltage selection module 10 simultaneously transmits the same voltage to multiple signal transmission lines, causing the first terminal S of the dual-gate transistors M1 in the multiple columns of pixel circuits 20 to simultaneously receive either a first power supply voltage VDDL or a second power supply voltage VDDH. This approach reduces the number of first voltage selection modules 10, which is beneficial for reducing bezel size and is suitable for narrow bezel designs.

[0052] In other embodiments, two or more first voltage selection modules 10 are connected to the same column of pixel circuits 20. In this configuration, the first terminal S of the dual-gate transistor M1 of the same column of pixel circuits 20 is connected to the output terminals of two first voltage selection modules 10. Multiple first voltage selection modules 10 provide a first power supply voltage VDDL or a second power supply voltage VDDH to the column of pixel circuits 20 either in a time-sharing or collective manner. This approach improves the reliability of voltage transmission, prevents the failure of a single first voltage selection module 10 from causing the entire column of pixel circuits 20 to fail, and reduces the load on each first voltage selection module 10, thereby improving the stability of voltage transmission. This configuration is suitable for large-size or high-resolution display panels.

[0053] In this embodiment, the first power supply voltage VDDL, the second power supply voltage VDDH, and the third power supply voltage VSS are all DC voltage signals. Specifically, the first power supply voltage VDDL ≤ 0, and the second power supply voltage VDDH > 0, i.e., VDDL ≤ 0 < VDDH. For example, VDDL can be -5V, and VDDH can be 5V. The first power supply voltage VDDL is a low-level voltage used to reset the first terminal S and the first gate G of the dual-gate transistor M1 during the initialization phase. The second power supply voltage VDDH is a high-level voltage used to switch the potential of the first terminal S of the dual-gate transistor M1 from VDDL to VDDH during the threshold voltage characteristic adjustment phase, thereby forming a large negative gate-source voltage between the gate and the first terminal of the dual-gate transistor M1 to adjust the characteristics of the dual-gate transistor M1.

[0054] Within a single frame, the operation of a pixel circuit includes at least the sequential initialization phase, threshold voltage characteristic adjustment phase, and compensation phase.

[0055] During the initialization phase, the first voltage selection module 10 transmits the first power supply voltage VDDL to the first terminal S of the dual-gate transistor M1, resetting the potential of the first terminal S of the dual-gate transistor M1 to the first power supply voltage VDDL. Simultaneously, the compensation module 120 is turned on, connecting the second terminal D of the dual-gate transistor M1 to its first gate G. Since the second gate of the dual-gate transistor M1 is connected to its first terminal S, the potential VB of the second gate of the dual-gate transistor M1 is equal to the first power supply voltage VDDL. The first power supply voltage VDDL is a low-level voltage, which is applied to the second gate of the dual-gate transistor M1, causing the threshold voltage of the dual-gate transistor M1 to adjust in the positive direction, thereby turning on the dual-gate transistor M1. After the dual-gate transistor M1 is turned on, the charge on the second terminal D of the dual-gate transistor M1 is discharged through the first terminal S. The first gate G of the dual-gate transistor M1 is synchronously reset through the compensation module 120 and the second terminal D, thus initializing the first terminal S and the first gate G of the dual-gate transistor M1 to eliminate the influence of residual charge from the previous frame on the display of the current frame.

[0056] During the threshold voltage characteristic adjustment stage, the first voltage selection module 10 transmits the second power supply voltage VDDH to the first terminal S of the dual-gate transistor M1, switching the potential of the first terminal S of the dual-gate transistor M1 from the first power supply voltage VDDL to the second power supply voltage VDDH. The compensation module 120 is turned off, and the first gate G of the dual-gate transistor M1 is in a floating state, maintaining the potential at the end of the initialization stage. At this time, the gate-source voltage of the dual-gate transistor M1 is a large negative voltage. This negative gate-source voltage subjects the dual-gate transistor M1 to a strong electric field perpendicular to its channel direction and a weak electric field parallel to its channel direction. Under this electric field, traps causing threshold voltage Vth drift at the gate oxide layer and channel interface of the dual-gate transistor M1 capture or release charges, restoring the threshold voltage of the dual-gate transistor M1 to its initial state. This improves image retention and enhances display uniformity, ensuring the quality of subsequent displays.

[0057] During the compensation phase, the first voltage selection module 10 maintains the transmission of the second power supply voltage VDDH to the first terminal S of the dual-gate transistor M1. The compensation module 120 is turned on, connecting the second terminal D of the dual-gate transistor M1 to its first gate G. As the gate-source voltage of the dual-gate transistor M1 gradually approaches its threshold voltage, the dual-gate transistor M1 gradually turns off from the on state. During this process, the potential of the second terminal D of the dual-gate transistor M1 and the potential of the first gate G rise synchronously and gradually. When the dual-gate transistor M1 is turned off, the potential of the first gate G of the dual-gate transistor M1 is clamped to the sum of the second power supply voltage VDDH and the threshold voltage of the dual-gate transistor M1. The threshold voltage information of the dual-gate transistor M1 is stored in the first gate G of the dual-gate transistor M1 to achieve compensation for the threshold voltage of the dual-gate transistor M1.

[0058] The display panel provided in this embodiment of the invention includes a first voltage selection module and multiple pixel circuits. Each pixel circuit includes a driving module and a compensation module. The driving module includes a dual-gate transistor (DMT), with its second gate connected to its first terminal. The first voltage selection module transmits a first power supply voltage or a second power supply voltage to the first terminal of the DMT in a time-division multiplexing manner. This eliminates the need for an additional second gate control signal line; automatic adjustment of the second gate potential can be achieved solely through voltage switching at the first terminal of the DMT. This simplifies signal routing, saves layout space, and enables ultra-high PPI display layouts. During the initialization phase, the first power supply voltage is transmitted to both the first terminal and the first gate of the DMT, simultaneously resetting both terminals and the first gate. This effectively eliminates residual charge from the previous frame, resolving the ghosting problem. The compensation module is turned on during the initialization and compensation phases and turned off during the threshold voltage characteristic adjustment phase. The same compensation module performs three functions—reset on, characteristic adjustment off, and compensation on—at different phases, eliminating the need for additional functional modules and further reducing the number of transistors. Simultaneously, during the threshold voltage characteristic adjustment phase, the first voltage selection module transmits a second power supply voltage to the first terminal of the dual-gate transistor, making the gate-source voltage of the dual-gate transistor a large negative voltage. This adjusts the characteristics of the dual-gate transistor, restoring its threshold voltage to its initial state. Furthermore, the compensation module is activated during the compensation phase to compensate for the threshold voltage of the dual-gate transistor. Through these methods, the display panel of this embodiment effectively solves the problems of display uniformity and ghosting while reducing the number of transistors and signal traces to achieve an ultra-high PPI display arrangement, thus improving the display effect.

[0059] Figure 3 This is a schematic diagram of the connection structure between a first voltage selection module and a pixel circuit provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another connection structure between the first voltage selection module and the pixel circuit provided in an embodiment of the present invention. Figure 3 and Figure 4 As shown, the first voltage selection module 10 includes a first input terminal, a second input terminal, a first control terminal, a second control terminal, and a first output terminal.

[0060] The first output terminal is connected to the first gate S of the dual-gate transistor M1, the first input terminal is connected to the first power supply voltage VDDL, and the second input terminal is connected to the second power supply voltage VDDH.

[0061] The first voltage selection module 10 is used to transmit the first power supply voltage VDDL to the first terminal S of the dual-gate transistor M1 in response to the signal of the first control terminal during the initialization phase, and to transmit the second power supply voltage VDDH to the first terminal S of the dual-gate transistor M1 in response to the signal of the second control terminal during the threshold voltage characteristic adjustment phase; wherein, within one frame, the initialization phase is located before the threshold voltage characteristic adjustment phase.

[0062] Optionally, the first voltage selection module 10 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 serves as the first control terminal of the first voltage selection module 10, the first electrode of the first transistor T1 serves as the first input terminal of the first voltage selection module 10, and the second electrode of the first transistor T1 serves as the first output terminal of the first voltage selection module 10.

[0063] The gate of the second transistor T2 serves as the second control terminal of the first voltage selection module 10, the first terminal of the second transistor T2 serves as the second input terminal of the first voltage selection module 10, and the second terminal of the second transistor T2 serves as the first output terminal of the first voltage selection module 10.

[0064] Optionally, such as Figure 3 As shown, the first transistor T1 and the second transistor T2 have the same channel type, both being P-channel transistors. The first control terminal is connected to the first control signal SW1, and the second control terminal is connected to the second control signal SW2; wherein the first control signal SW1 and the second control signal SW2 are inverted signals. During the initialization phase, the first control signal SW1 is low, the second control signal SW2 is high, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first power supply voltage VDDL is transmitted to the first terminal S of the dual-gate transistor M1 via the first transistor T1. During the threshold voltage characteristic adjustment phase, the first control signal SW1 is high, the second control signal SW2 is low, the first transistor T1 is turned off, the second transistor T2 is turned on, and the second power supply voltage VDDH is transmitted to the first terminal S of the dual-gate transistor M1 via the second transistor T2.

[0065] Optionally, the first control signal SW1 and the second control signal SW2 are global signals.

[0066] Specifically, the global signal refers to the common signal transmitted to all pixel circuits in the display panel, which has the same voltage level for each pixel circuit at the same time. The first control signal SW1 and the second control signal SW2 are transmitted as global signals to the first control terminal and the second control terminal of each first voltage selection module 10 in the display panel, respectively.

[0067] by Figure 3Taking the illustrated embodiment as an example, when the first control signal SW1 is low, the first transistors T1 of all the first voltage selection modules 10 in the display panel are simultaneously turned on, and the first terminal S of the dual-gate transistor M1 of each pixel circuit 20 is simultaneously connected to the first power supply voltage VDDL, thereby enabling the initialization phase of all pixel circuits to be performed simultaneously. When the second control signal SW2 is low, the second transistors T2 of all the first voltage selection modules 10 in the display panel are simultaneously turned on, and the first terminal S of the dual-gate transistor M1 of each pixel circuit 20 is simultaneously connected to the second power supply voltage VDDH, thereby enabling the threshold voltage characteristic adjustment phase of all pixel circuits to be performed simultaneously.

[0068] By setting the first control signal SW1 and the second control signal SW2 as global signals, it is not necessary to provide control signals for each row of pixel circuits separately, which reduces the number of control signal lines in the display panel and helps to reduce the bezel width. At the same time, the initialization stage and threshold voltage characteristic adjustment stage of all pixel circuits are performed simultaneously, ensuring the consistency and uniformity of the display in each area of ​​the display panel.

[0069] Optionally, such as Figure 4 As shown, the first transistor T1 and the second transistor T2 have different channel types, and the first control terminal and the second control terminal are connected to the fifth control signal SW5. That is, one of the first transistor T1 and the second transistor T2 can be an N-channel transistor, and the other can be a P-channel transistor. For example, the first transistor T1 is a P-channel transistor, and the second transistor T2 is an N-channel transistor. During the initialization phase, the fifth control signal SW5 is at a low level, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first power supply voltage VDDL is transmitted to the first terminal S of the dual-gate transistor M1 through the first transistor T1; during the threshold voltage characteristic adjustment phase, the fifth control signal SW5 is at a high level, the first transistor T1 is turned off, the second transistor T2 is turned on, and the second power supply voltage VDDH is transmitted to the first terminal S of the dual-gate transistor M1 through the second transistor T2. This solution only requires one fifth control signal SW5 to achieve the same time-division transmission function, reducing the number of global control signal lines in the display panel, freeing up wiring space, and facilitating further reduction of the bezel width.

[0070] Optionally, the display panel also includes multiple first power lines and multiple second power lines, wherein the first power lines are used to provide a first power voltage VDDL to the corresponding first voltage selection module 10, and the second power lines are used to provide a second power voltage VDDH to the corresponding first voltage selection module 10.

[0071] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 5As shown, the pixel circuit 20 also includes a data writing module 130 and a first storage module 140. The first storage module 140 is connected between the first node N1 and the first gate G of the dual-gate transistor M1, and is used to store the voltage difference between the first node N1 and the first gate G of the dual-gate transistor M1.

[0072] The first end of the data writing module 130 is connected to the data line DL, and the second end of the data writing module 130 is connected to the first node N1. The data writing module 130 is used to transmit the initialization voltage Vini input to the data line DL to the first node N1 during the initialization phase; and to transmit the data voltage Vdata input to the data line DL to the first node N1 during the data writing phase; wherein, within one frame, the data writing phase is located after the initialization phase.

[0073] Specifically, in this embodiment, the data line DL is a multiplexed signal line. During the initialization phase, the data line DL carries the initialization voltage Vini, and during the data writing phase, it carries the data voltage Vdata. The data writing module 130 is turned on during both the initialization and data writing phases, transmitting the voltage signal on the data line DL to the first node N1. This embodiment uses the data writing module 130 to transmit the initialization voltage Vini and the data voltage Vdata to the first node N1 in a time-division manner, eliminating the need for separate signal lines and writing transistors for Vini and Vdata. This reduces the number of transistors and signal lines in the pixel circuit, which is beneficial for improving pixel density.

[0074] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention. For example... Figure 6 As shown, the display panel also includes a second voltage selection module 30, which includes a third input terminal, a fourth input terminal, a third control terminal, a fourth control terminal, and a second output terminal. The second output terminal is connected to the data line DL; the third input terminal is connected to the initialization voltage Vini, and the fourth input terminal is connected to the data voltage Vdata. The second voltage selection module 30 is used to transmit the initialization voltage Vini to the data line DL in response to the signal from the third control terminal during the initialization phase; and to transmit the data voltage Vdata to the data line DL in response to the signal from the fourth control terminal during the data writing phase.

[0075] In some embodiments, the display panel includes a plurality of second voltage selection modules 30, which are disposed in the non-display area NAA of the display panel. The display panel also includes a plurality of data lines DL, with the second output terminal of each second voltage selection module 30 connected to a corresponding data line DL. Each data line DL is connected to the first terminal of a data writing module 130 of a column of pixel circuits 20. In this configuration, the output terminal of the second voltage selection module 30 is connected to the first terminal of the data writing module 130 of each row of pixel circuits in the corresponding column of pixel circuits 20 via a data line DL. During the initialization phase, the second voltage selection module 30 transmits an initialization voltage Vini to the data line DL, and the data writing module 130 of each pixel circuit in the column of pixel circuits 20 simultaneously receives the initialization voltage Vini. During the data writing phase, the second voltage selection module 30 transmits a data voltage Vdata to the data line DL, and the data writing module 130 of each pixel circuit 20 sequentially receives the data voltage Vdata during its respective conduction period.

[0076] In other embodiments, a second voltage selection module 30 is connected to two or more columns of pixel circuits 20. In this configuration, the second output terminal of the second voltage selection module 30 is connected to multiple data lines DL, each data line DL corresponding to one column of pixel circuits 20. The second voltage selection module 30 simultaneously transmits the same voltage to the multiple data lines DL, causing the first terminal of the data writing module 130 of the multiple columns of pixel circuits 20 to simultaneously receive either the initialization voltage Vini or the data voltage Vdata. This approach reduces the number of second voltage selection modules 30, which is beneficial for reducing bezel size and is suitable for narrow bezel designs.

[0077] In other embodiments, two or more second voltage selection modules 30 are connected to the same column of pixel circuits 20. In this configuration, the data line DL of the same column of pixel circuits 20 is connected to the second output terminals of at least two second voltage selection modules 30, and the multiple second voltage selection modules 30 provide the initialization voltage Vini or data voltage Vdata to the column of pixel circuits 20 in a time-sharing or collective manner. This approach can improve the reliability of voltage transmission, avoid the failure of a single second voltage selection module 30 causing data writing failure of the entire column of pixel circuits 20, and reduce the load on each second voltage selection module 30, thereby improving the stability of voltage transmission. This method is suitable for large-size or high-resolution display panels.

[0078] By placing the second voltage selection module 30 in the non-display area NAA, the pixel circuit 20 in the display area AA does not need to have separate signal lines and selection switches for the initialization voltage Vini and the data voltage Vdata. This simplifies the pixel circuit structure, reduces the number of signal traces in the display area AA, and thus improves the transmittance of the display panel. Simultaneously, the second voltage selection module 30 uses the data line DL to transmit the initialization voltage Vini and the data voltage Vdata in a time-division multiplexing manner, further reducing the number of signal lines in the display panel. This is beneficial for narrow bezel design and reduces the manufacturing cost of the display panel.

[0079] Figure 7 This is a schematic diagram of the connection structure between a second voltage selection module and a pixel circuit provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of another connection structure between the second voltage selection module and the pixel circuit provided in an embodiment of the present invention. Figure 7 and Figure 8 As shown, optionally, the second voltage selection module 30 includes a third transistor T3 and a fourth transistor T4.

[0080] The gate of the third transistor T3 serves as the third control terminal of the second voltage selection module 30, the first terminal of the third transistor T3 serves as the third input terminal of the second voltage selection module 30, and the second terminal of the third transistor T3 serves as the second output terminal of the second voltage selection module 30. The gate of the fourth transistor T4 serves as the fourth control terminal of the second voltage selection module 30, the first terminal of the fourth transistor T4 serves as the fourth input terminal of the second voltage selection module 30, and the second terminal of the fourth transistor T4 serves as the second output terminal of the second voltage selection module 30. Optionally, such as Figure 7 As shown, the third transistor T3 and the fourth transistor T4 have the same channel type, both being P-channel transistors. The third control terminal is connected to the third control signal SW3, and the fourth control terminal is connected to the fourth control signal SW4. The third control signal SW3 and the fourth control signal SW4 are inverted signals. During the initialization phase, the third control signal SW3 is low, the fourth control signal SW4 is high, the third transistor T3 is turned on, and the fourth transistor T4 is turned off. The initialization voltage Vini is transmitted to the data line DL via the third transistor T3. During the data writing phase, the third control signal SW3 is high, the fourth control signal SW4 is low, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. The data voltage Vdata is transmitted to the data line DL via the fourth transistor T4.

[0081] Optionally, the third control signal SW3 and the fourth control signal SW4 are global signals. By setting the third control signal SW3 and the fourth control signal SW4 as global signals, it is not necessary to provide independent initialization voltage and data voltage control signals for each row or column pixel circuit, which reduces the number of control signal lines in the display panel and helps to reduce the bezel width; at the same time, the initialization phase of all pixel circuits is performed simultaneously, ensuring the consistency and uniformity of the display in each area of ​​the display panel.

[0082] Optionally, such as Figure 8 As shown, the third transistor T3 is a P-channel transistor, and the fourth transistor T4 is an N-channel transistor, meaning that the third transistor T3 and the fourth transistor T4 have different channel types. The third and fourth control terminals are connected to the sixth control signal SW6. During the initialization phase, the sixth control signal SW6 is low, the third transistor T3 is turned on, and the fourth transistor T4 is turned off. The initialization voltage Vini is transmitted to the data line DL via the third transistor T3. During the data writing phase, the sixth control signal SW6 is high, the third transistor T3 is turned off, and the fourth transistor T4 is turned on. The data voltage Vdata is transmitted to the data line DL via the fourth transistor T4. This solution requires only one sixth control signal SW6 to achieve the same time-division multiplexing function, reducing the number of global control signal lines in the display panel, freeing up wiring space, and facilitating further reduction in bezel width.

[0083] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 9 As shown, the pixel circuit also includes a light-emitting control module 150 and a light-emitting module 160; the light-emitting control module 150 is disposed between the second terminal D of the dual-gate transistor M1 and the first terminal of the light-emitting module 160, and the second terminal of the light-emitting module 160 is connected to the third power supply line L3. The control terminal of the light-emitting control module 150 is connected to the light-emitting control line EL; the light-emitting control module 150 is used to turn on the light-emitting control signal EM on the light-emitting control line EL in response to the initialization phase and the light-emitting phase.

[0084] Specifically, the third power line L3 is used to provide a third power supply voltage VSS to the second terminal of the light-emitting module 160. The light-emitting module 160 includes a light-emitting device D1, which can be a light-emitting diode (LED), an organic light-emitting diode (OLED), or other electroluminescent device. The anode of the light-emitting device D1 serves as the first terminal of the light-emitting module 160, and the cathode of the light-emitting device D1 serves as the second terminal of the light-emitting module 160. Optionally, the third power line L3 can be a global signal line, and the third power supply voltage VSS transmitted on the third power line L3 is a global signal. That is, when the display panel includes multiple pixel circuits 20, the voltage value and timing waveform of the third power supply voltage VSS connected to all pixel circuits 20 are the same.

[0085] In some embodiments, the third power supply voltage is ≤0, and the absolute value of the first power supply voltage VDDL is greater than the absolute value of the third power supply voltage VSS. With this configuration, during the initialization phase, when the first terminal S of the dual-gate transistor M1 and the first terminal of the light-emitting module 160 are reset to the first power supply voltage VDDL, since the absolute value of the first power supply voltage VDDL received by the second terminal of the light-emitting module 160 is greater than the absolute value of the third power supply voltage VSS, no forward conduction voltage difference is formed between the first and second terminals of the light-emitting module 160. This prevents the light-emitting module 160 from being accidentally lit during the initialization phase, ensuring the dark state performance of the display panel during the non-light-emitting phase. Furthermore, the third power supply line L3 can be a global signal line, and the third power supply voltage VSS is a global signal. That is, when the display panel includes multiple pixel circuits 20, the voltage value and timing waveform of the third power supply voltage VSS connected to all pixel circuits 20 are the same.

[0086] Optionally, the first power supply voltage VDDL, the second power supply voltage VDDH, and the third power supply voltage VSS are all DC voltage signals. Compared to the traditional approach that requires an external driver IC to generate complex AC pulse waveforms to charge and discharge pixel nodes, this application only needs to use the first voltage selection module 10 located in the non-display area NAA to perform simple timing selection of the two DC power supplies, thus completing the potential switching of the first electrode S of the driver transistor. This reduces the architectural complexity and design threshold of the driver IC. Furthermore, since DC power signals do not have the frequency loss and parasitic capacitance coupling problems of AC signals, it can effectively improve the power supply stability and signal integrity of the display panel under ultra-high PPI configurations.

[0087] Optionally, the first power supply voltage VDDL is used to simultaneously reset the first terminal S of the dual-gate transistor M1, the first gate G of the dual-gate transistor M1, and the first terminal of the light-emitting module 160. The first terminal of the light-emitting module 160 is connected to the second terminal D of the dual-gate transistor M1 through the light-emitting control module 150. During the initialization phase, the light-emitting control signal EM on the light-emitting control line EL is at the on level, the light-emitting control module 150 is turned on, and the second terminal D of the dual-gate transistor M1 is connected to the first terminal of the light-emitting module 160. At this time, the dual-gate transistor M1 is turned on, and a conduction path is formed between the second terminal D and the first terminal S of the dual-gate transistor M1. The first power supply voltage VDDL is transmitted to the first terminal S of the dual-gate transistor M1 through the first voltage selection module 10, then transmitted to the second terminal D through the conduction path of the dual-gate transistor M1, and then transmitted to the first terminal of the light-emitting module 160 through the light-emitting control module 150. At the same time, the compensation module 120 is turned on, connecting the second terminal D and the first gate G of the dual-gate transistor M1. Therefore, the first power supply voltage VDDL simultaneously discharges charge and initializes the potential of the first terminal S and the first gate G of the dual-gate transistor M1 and the first terminal of the light-emitting module 160 through the same conduction path, that is, the three nodes are simultaneously reset to the first power supply voltage VDDL. In this way, during the initialization phase, it is not necessary to reset different nodes in a time-division manner, nor is it necessary to set a separate reset transistor for the first terminal of the light-emitting module. A comprehensive reset of the key nodes of the driving module and the anode of the light-emitting module can be completed in the same stage. This not only simplifies the structure and timing design of the pixel circuit and reduces the number of transistors, but also completely removes the charge remaining on the anode from the previous frame, effectively avoiding ghosting and uneven brightness caused by residual anode charge, and improving display uniformity and display effect.

[0088] Optionally, the pixel circuit 20 further includes a second storage module 170, which is connected between the first node N1 and the first terminal S of the dual-gate transistor M1, and is used to store the voltage difference between the first node N1 and the first terminal S of the dual-gate transistor M1.

[0089] Optionally, the first storage module 140 includes a first capacitor C1, the first end of the first capacitor C1 is connected to the first node N1, and the second end of the first capacitor C1 is connected to the first gate G of the dual-gate transistor M1.

[0090] Optionally, the second storage module 170 includes a second capacitor C2. The first terminal of the second capacitor C2 is connected to the first node N1, and the second terminal of the second capacitor C2 is connected to the first terminal S of the dual-gate transistor M1.

[0091] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 10 and Figure 11 As shown, optionally, the data writing module 130 includes a data writing transistor M2, the compensation module 120 includes a compensation transistor M3, and the light emission control module 150 includes a light emission control transistor M4.

[0092] The gate of the compensation transistor M3 is connected to the first scan line GL1, the first terminal of the compensation transistor M3 is connected to the second terminal D of the dual-gate transistor M1, and the second terminal of the compensation transistor M3 is connected to the first gate G of the dual-gate transistor M1.

[0093] The gate of the data writing transistor M2 is connected to the second scan line GL2, the first terminal of the data writing transistor M2 is connected to the data line DL, and the second terminal of the data writing transistor M2 is connected to the first node N1.

[0094] The gate of the light-emitting control transistor M4 is connected to the light-emitting control line EL, the first terminal of the light-emitting control transistor M4 is connected to the second terminal D of the dual-gate transistor M1, and the second terminal of the light-emitting control transistor M4 is connected to the first terminal of the light-emitting module 160.

[0095] Specifically, in the dual-gate transistor M1, one of the first gate G and the second gate is the bottom gate, and the other is the top gate. For example, the first gate G of the dual-gate transistor M1 is the top gate, and the second gate of the dual-gate transistor M1 is the bottom gate. Both of these gate position configurations can achieve the dual-gate control function described in the embodiments of this application. The specific configuration can be flexibly selected according to actual process requirements and layout design, and this application does not impose specific limitations on it. Figure 10 The schematic diagram illustrates the case where the first gate G of the dual-gate transistor M1 is the top gate and the second gate is the bottom gate. Figure 11 The diagram illustrates the case where the first gate G of the dual-gate transistor M1 is the bottom gate and the second gate is the top gate.

[0096] The dual-gate transistor M1 is a P-channel transistor, the light-emitting control transistor M4 is a P-channel transistor, and the data writing transistor M2 and the compensation transistor M3 are N-channel transistors. For example, the dual-gate transistor M1 and the light-emitting control transistor M4 can be polysilicon thin-film transistors (PSTs). The data writing transistor M2 and the compensation transistor M3 can be oxide thin-film transistors (e.g., IGZO TFTs). By setting the dual-gate transistor M1 and the light-emitting control transistor M4 to P-channel type, and the data writing transistor M2 and the compensation transistor M3 to N-channel type, the high mobility of the P-channel LTPS transistor and the low leakage current of the N-channel oxide transistor can be utilized. This ensures the driving capability and response speed of the pixel circuit while reducing the risk of leakage current and improving display quality. Simultaneously, the different conduction level characteristics of the P-channel and N-channel transistors allow for more flexible timing design of the control signals, simplifying the driving timing.

[0097] When the data writing transistor M2 is an oxide thin-film transistor, it can be a three-terminal or a four-terminal device. When the data writing transistor M2 is a three-terminal device, its connection method is as described in the above embodiment: the gate of the data writing transistor M2 serves as the control terminal of the data writing module 130 and is connected to the second scan line GL2; the first terminal of the data writing transistor M2 is connected to the data line DL; and the second terminal of the data writing transistor M2 is connected to the first node N1.

[0098] Optionally, when the data writing transistor M2 is a four-terminal device, the data writing transistor M2 includes a first gate and a second gate. In some embodiments, the first gate of the data writing transistor M2 is connected to a second scan line, and the second gate of the data writing transistor M2 is connected to a second terminal of the data writing transistor M2. In other embodiments, the first gate of the data writing transistor M2 is connected to a second scan line GL2, and the second gate of the data writing transistor M2 is connected to a second voltage control signal line Vb2. The second voltage control signal line Vb2 is used to transmit voltage to the second gate of the data writing transistor M2 to control the threshold voltage of the data writing transistor M2.

[0099] When the compensation transistor M3 is an oxide thin-film transistor, it can be a three-terminal or a four-terminal device. When the compensation transistor M3 is a three-terminal device, its connection method is as described in the above embodiment: the gate of the compensation transistor M3 serves as the control terminal of the compensation module 120 and is connected to the first scan line GL1; the first terminal of the compensation transistor M3 is connected to the second terminal D of the dual-gate transistor M1; and the second terminal of the compensation transistor M3 is connected to the first gate G of the dual-gate transistor M1.

[0100] Optionally, the compensation transistor M3 is a four-terminal device having a first gate and a second gate. When the compensation transistor M3 is a four-terminal device, it includes a first gate and a second gate. In some embodiments, the first gate of the compensation transistor M3 is connected to a first scan line GL1, and the second gate of the compensation transistor M3 is connected to a second terminal of the compensation transistor M3. In other embodiments, the first gate of the compensation transistor M3 is connected to the first scan line GL1, and the second gate of the compensation transistor M3 is connected to a first voltage control signal line Vb1. The first voltage control signal line Vb1 is used to transmit voltage to the second gate of the compensation transistor M3 to control the threshold voltage of the compensation transistor M3.

[0101] Optionally, the first power line L1 and the second power line L2 are multiplexed into a first voltage control signal line Vb1. The first power line L1 and the second power line L2 are also multiplexed into a second voltage control signal line Vb2. By multiplexing the first power line L1 and the second power line L2 into the first voltage control signal line Vb1 and the second voltage control signal line Vb2, it is unnecessary to set separate control signal lines for the first gate G of the dual-gate transistor M1 and the second gate of the data writing transistor M2. This reduces the number of signal lines in the display panel, freeing up wiring space and facilitating further reduction in pixel size and bezel width, thus achieving an ultra-high PPI display layout. Simultaneously, the multiplexing method reduces coupling interference between signal lines, which helps improve the signal transmission stability and display uniformity of the display panel.

[0102] Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 12 As shown, optionally, the data writing transistor M2 and the compensation transistor M3 can also be P-channel transistors, which can be low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). In this case, the data writing transistor M2 and the compensation transistor M3 are three-terminal devices. The gate of the data writing transistor M2 is connected to the second scan line GL2, the first terminal of the data writing transistor M2 is connected to the data line DL, and the second terminal of the data writing transistor M2 is connected to the first node N1; the gate of the compensation transistor M3 is connected to the first scan line GL1, the first terminal of the compensation transistor M3 is connected to the second terminal D of the dual-gate transistor M1, and the second terminal of the compensation transistor M3 is connected to the first gate G of the dual-gate transistor M1.

[0103] By setting the data writing transistor M2 and the compensation transistor M3 as oxide thin-film transistors or LTPS thin-film transistors, the transistor type can be flexibly selected according to actual process requirements and display panel performance requirements. When using oxide thin-film transistors, their low leakage current characteristics can be fully utilized to improve the image quality stability of the display panel at low refresh rates; when using LTPS thin-film transistors, their high mobility characteristics can be fully utilized to improve the response speed of the display panel at high refresh rates.

[0104] Figure 13 This is a driving timing waveform diagram of a pixel circuit provided in an embodiment of the present invention. Figure 14 This is a simulation waveform diagram of the node voltage of a pixel circuit driving timing provided in an embodiment of the present invention. This driving timing can be used... Figure 10 and Figure 11 The pixel circuit shown.

[0105] refer to Figure 10 , Figure 11 , Figure 13 and Figure 14 Within a single frame, the pixel circuit's operation includes the sequential initialization phase t1, threshold voltage characteristic adjustment phase t2, compensation phase t3, data writing phase t4, and light emission phase t5. Here, VS represents the potential of the first terminal of the dual-gate transistor M1, VG represents the potential of the first gate of the dual-gate transistor M1, VN1 represents the potential of the first node N1, VGS represents the gate-source voltage difference of the dual-gate transistor M1, VD represents the potential of the second terminal of the dual-gate transistor M1, Vanode represents the potential of the anode of the light-emitting device D1, and I_oled represents the driving current generated by the dual-gate transistor M1.

[0106] The control terminal of the compensation module 120 is connected to the first scan line GL1, and the first scan line GL1 transmits the first scan signal S1. The compensation module 120 is used to turn on the first conduction pulse pulse11 in response to the first scan signal S1 during the initialization phase t1, so as to transmit the first power supply voltage VDDL to the first gate G of the dual gate transistor M1; and to turn on the second conduction pulse pulse12 in response to the first scan signal S1 during the compensation phase.

[0107] During the threshold voltage characteristic adjustment phase t2, the compensation module 120 is configured to be turned off by the first scan signal S1; within one frame, the threshold voltage characteristic adjustment phase t2 is located between the initialization phase t1 and the compensation phase t3.

[0108] The control terminal of the data writing module 130 is connected to the second scan line GL2, and the second scan line GL2 transmits the second scan signal S2. The data writing module 130 is used to turn on in response to the first conduction pulse 21 of the second scan signal S2 during the initialization phase t1, transmitting the initialization voltage Vini input to the data line DL to the first node N1; and during the data writing phase t4, to turn on in response to the second conduction pulse 22 of the second scan signal S2, transmitting the data voltage Vdata input to the data line DL to the first node N1. Optionally, the light emission control module 150 is used to turn off during the threshold voltage characteristic adjustment phase t2, the compensation phase t3, and the data writing phase t4.

[0109] Specifically, refer to Figure 10 , Figure 11 and Figure 13 The first scan signal S1 has two conduction pulses: a first conduction pulse 11 and a second conduction pulse 12. The first conduction pulse 11 corresponds to the initialization stage t1, and the second conduction pulse 12 corresponds to the compensation stage t3. Through the two conduction pulses of the first scan signal S1, the compensation module 120 is turned on in the initialization stage t1 and the compensation stage t3, respectively, and turned off in the threshold voltage characteristic adjustment stage t2. The second scan signal S2 also has two conduction pulses: a first conduction pulse 21 and a second conduction pulse 22. The first conduction pulse 21 corresponds to the initialization stage t1, the threshold voltage characteristic adjustment stage t2, and the compensation stage t3, and the second conduction pulse 22 corresponds to the data writing stage t4. Through the two conduction pulses of the second scan signal S2, the data writing module 130 remains on during the initialization phase t1, the threshold voltage characteristic adjustment phase t2, and the compensation phase t3, maintaining the transmission of the initialization voltage Vini input from the data line DL to the first node N1, so that the potential of the first node N1 and the first storage module 140 remains stable in the above three phases; and it is turned on during the data writing phase t4, transmitting the data voltage Vdata input from the data line DL to the first node N1, realizing the writing of the data voltage. The timing coordination of the two conduction pulses of the first scan signal S1 and the two conduction pulses of the second scan signal S2 allows the pixel circuit of this embodiment to simultaneously reset the first terminal S, the first gate G of the dual-gate transistor M1, and the first terminal of the light-emitting module 160 during the initialization phase t1; restore the threshold voltage of the dual-gate transistor M1 to its initial state during the threshold voltage characteristic adjustment phase t2; compensate the threshold voltage of the dual-gate transistor M1 during the compensation phase t3; and write the data voltage during the data writing phase t4.

[0110] Optionally, the duration of the second conduction pulse 12 of the first scan signal S1 is longer than the duration of the first conduction pulse 11 of the first scan signal S1. Setting the duration of the compensation phase t3 to be longer than that of the initialization phase t1 ensures that the threshold voltage of the dual-gate transistor M1 is fully compensated, improving the compensation effect and display uniformity.

[0111] Optionally, the duration of the first conduction pulse pulse11 of the first scan signal S1 is longer than the duration of the second conduction pulse pulse22 of the second scan signal S2. Setting the duration of the initialization phase t1 to be longer than that of the data writing phase t4 ensures that each node is fully reset, effectively eliminates residual charge from the previous frame, and solves the ghosting problem.

[0112] Optionally, the duration of the second conduction pulse 12 of the first scan signal S1 is less than the duration of the first conduction pulse 21 of the second scan signal S2. Setting the duration of the first conduction pulse 21 of the second scan signal S2 to be greater than the duration of the second conduction pulse 12 of the first scan signal S1 ensures that the data writing transistor M2 remains on during the initialization phase t1, the threshold voltage characteristic adjustment phase t2, and the compensation phase t3. This avoids potential fluctuations in the first node N1 caused by the premature turn-off of the data writing transistor M2, which could affect the accuracy and stability of the compensation effect.

[0113] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the dual-gate transistor M1, and the light-emitting control transistor M4 are P-channel transistors, while the data writing transistor M2 and the compensation transistor M3 are N-channel transistors. The P-channel transistors have a low on-state and a high off-state; the N-channel transistors have a high on-state and a low off-state. Based on these transistor types, the operation process at each stage is as follows: During the initialization phase t1, the first scan signal S1 provides a first conduction pulse pulse11 (high-level pulse), the second scan signal S2 provides a first conduction pulse (high-level pulse), and the light emission control signal EM is at a low level. At this time, the data writing module 130 responds to the first conduction pulse pulse21 of the second scan signal S2 and conducts, transmitting the initialization voltage Vini on the data line DL to the first node N1, that is, the potential VN1 of the first node N1 = Vini. The compensation module 120 responds to the first conduction pulse11 of the first scan signal S1 and conducts, connecting the second terminal D of the dual-gate transistor M1 to the first gate G. The light emission control module 150 responds to the low level of the light emission control signal EM and connects the second terminal D of the dual-gate transistor M1 to the first terminal of the light emission module 160. At the same time, the first voltage selection module 10 transmits the first power supply voltage VDDL to the first terminal S of the dual-gate transistor M1, so that the potential of the first terminal S of the dual-gate transistor M1 is reset to the first power supply voltage VDDL. Since the second gate of the dual-gate transistor M1 is connected to the first terminal S, the potential VB of the second gate is equal to the first power supply voltage VDDL. The first power supply voltage VDDL is a low-level voltage, which is applied to the second gate of the dual-gate transistor M1, causing the threshold voltage of the dual-gate transistor M1 to adjust in the positive direction, thereby turning on the dual-gate transistor M1. After the dual-gate transistor M1 is turned on, the charge at the second terminal D of the dual-gate transistor M1 is discharged through the first terminal S. The first gate G of the dual-gate transistor M1 is synchronously reset by being connected to the second terminal D through the compensation module 120. The first terminal of the light-emitting module 160 is synchronously reset by being connected to the second terminal D through the light-emitting control module 150. Thus, the first terminal S, the first gate G of the dual-gate transistor M1, and the first terminal of the light-emitting module 160 are simultaneously reset.

[0114] During the threshold voltage characteristic adjustment phase t2, the first scan signal S1 is low, and the compensation transistor M3 is turned off. The second scan signal S2 provides the second conduction pulse pulse22, turning on the data writing transistor M2 and transmitting the initialization voltage Vini to the first node N1 to stabilize the potential of the first node N1 and the first storage module 140. The light emission control signal EM is high, and the light emission control transistor M4 is turned off. At this time, the first gate G of the dual-gate transistor M1 is in a floating state, and the potential of the first gate G of the dual-gate transistor M1 is maintained at the potential at the end of the initialization phase t1 (i.e., VDDL). The first voltage selection module 10 transmits the second power supply voltage VDDH to the first terminal S of the dual-gate transistor M1, switching the potential of the first terminal S of the dual-gate transistor M1 from the first power supply voltage VDDL to the second power supply voltage VDDH. At this time, the gate-source voltage of the dual-gate transistor M1 is a relatively large negative voltage (VG-VS≈VDDL-VDDH). This negative gate-source voltage subjects the dual-gate transistor M1 to a strong electric field perpendicular to the channel direction and a weak electric field parallel to the channel direction. Under the influence of this electric field, traps causing threshold voltage Vth drift at the gate oxide layer and channel interface of the dual-gate transistor M1 capture or release charges, restoring the threshold voltage of the dual-gate transistor M1 to its initial state, thereby improving image retention and enhancing display uniformity.

[0115] During compensation phase t3, the first scan signal S1 provides the second conduction pulse pulse12, turning on the compensation transistor M3 and connecting the second terminal D of the dual-gate transistor M1 to the first gate G. The second scan signal S2 remains high, and the data writing transistor M2 remains on, continuing to transmit the initialization voltage Vini to the first node N1. The light emission control signal EM remains high, and the light emission control transistor M4 remains off. The first voltage selection module 10 continues to transmit the second power supply voltage VDDH to the first terminal S of the dual-gate transistor M1. As the gate-source voltage of the dual-gate transistor M1 gradually approaches its threshold voltage, the dual-gate transistor M1 gradually turns off from the on state. During this process, the potential of the second terminal D of the dual-gate transistor M1 gradually rises synchronously with the potential of the first gate G. When the dual-gate transistor M1 is turned off, the potential VG of the first gate G of the dual-gate transistor M1 is clamped to the sum of VDDH and the threshold voltage of the dual-gate transistor M1 (i.e., VG=VDDH+Vth). The threshold voltage information of the dual-gate transistor M1 is stored in the first gate G of the dual-gate transistor M1 to achieve compensation for the threshold voltage of the dual-gate transistor M1.

[0116] During the data writing phase t4, the first scan signal S1 is low, and the compensation transistor M3 is turned off. The second scan signal S2 provides the second conduction pulse, turning on the data writing transistor M2 and transmitting the data voltage Vdata input from the data line DL to the first node N1. This causes the potential of the first node N1 to jump from the initial voltage Vini to the data voltage Vdata, i.e., the voltage change of the first node N1 is ΔVN1 = Vdata - Vini. The light emission control signal EM remains high, and the light emission control transistor M4 is turned off. Since the first capacitor C1 is connected between the first node N1 and the first gate G of the dual-gate transistor M1, the potential jump of the first node N1 is coupled to the first gate G of the dual-gate transistor M1 through the first storage module 140, causing the potential of the first gate G of the dual-gate transistor M1 to jump further from VDDH + Vth at the end of the compensation phase t3. At this time, the potential of the first gate G of the dual-gate transistor M1 is: VG = (Vdata - Vini) × [c1 / (c1 + Cgs)] + (VDDH + Vth). Where c1 is the capacitance of the first capacitor C1, and Cgs is the parasitic capacitance between the first gate G and the second terminal D of the dual-gate transistor M1. Thus, the data voltage Vdata is written into the first gate G of the dual-gate transistor M1.

[0117] During the light-emitting stage t5, the first scan signal S1 is low, and the compensation transistor M3 is turned off. The second scan signal S2 is low, and the data writing transistor M2 is turned off. The light-emitting control signal EM is low, and the light-emitting control transistor M4 is turned on. The dual-gate transistor M1 turns on according to the potential of the first gate G and the first terminal S, generating a driving current. At this time, the difference between the gate-source voltage VGS and the threshold voltage Vth of the dual-gate transistor M1 is: VGS-Vth=(Vdata-Vini)×[c1 / (c1+Cgs)]; The drive current I_oled generated by the dual-gate transistor M1 is: I_oled=(1 / 2)×μ×Cox×(W / L)×(VGS-Vth) 2 ; That is: I_oled=(1 / 2)×μ×Cox×(W / L)×[(Vdata-Vini) 2 ×(c1 / (c1+Cgs)) 2 ]; Where μ is the carrier mobility, Cox is the gate oxide capacitance per unit area of ​​the dual-gate transistor M1, and W / L is the channel width-to-length ratio of the dual-gate transistor M1.

[0118] The driving current is transmitted to the light-emitting module 160 via the light-emitting control transistor M4, driving the light-emitting module 160 to emit light. As shown in the above equation, the driving current I_oled is independent of the threshold voltage Vth of the dual-gate transistor M1, thus compensating for the threshold voltage of the dual-gate transistor M1, ensuring the consistency of the driving current between different pixel circuits, and improving display uniformity. Simultaneously, the driving current I_oled is related to the data voltage Vdata; by adjusting the magnitude of the data voltage Vdata, the brightness of the light-emitting module 160 can be controlled, achieving grayscale display. Furthermore, the expression for the driving current I_oled does not include the first power supply voltage VDDL and the second power supply voltage VDDH; therefore, fluctuations in the power supply voltage will not affect the magnitude of the driving current, further improving the brightness and stability of the display panel.

[0119] In this embodiment, the first scan signal S1 controls the compensation transistor M3 to turn on during the initialization phase t1 and the compensation phase t3 by setting two conduction pulses, and turns it off during the threshold voltage characteristic adjustment phase t2. Through this timing configuration, the same compensation transistor M3 performs a reset conduction function during the initialization phase t1, a characteristic adjustment off function during the threshold voltage characteristic adjustment phase t2, and a compensation conduction function during the compensation phase t3, thus realizing the same transistor performing different functions at different stages. The data writing transistor M2 remains on during the initialization phase t1, the threshold voltage characteristic adjustment phase t2, and the compensation phase t3, and also remains on during the data writing phase t4, turning off during the light emission phase t5. During the initialization phase t1 to the compensation phase t3, the data writing transistor M2 performs the initialization voltage transmission function, transmitting the initialization voltage Vini to the first node N1 and maintaining the first node's potential stability; during the data writing phase t4, it performs the data voltage transmission function, transmitting the data voltage Vdata to the first node N1. The light-emitting control transistor M4 is turned on during the initialization phase t1, turned off during the threshold voltage characteristic adjustment phase t2, the compensation phase t3, and the data writing phase t4, and turned on during the light-emitting phase t5. During the initialization phase t1, the light-emitting control transistor M4 serves as the reset path conduction function, allowing the first power supply voltage VDDL to be transmitted to the first terminal of the light-emitting module 160 via the dual-gate transistor M1 and the light-emitting control transistor M4, achieving synchronous reset of the first terminal of the light-emitting module 160. During the light-emitting phase t5, it serves as the light-emitting path conduction function, allowing the drive current generated by the dual-gate transistor M1 to be transmitted to the light-emitting module 160 via the light-emitting control transistor M4, driving the light-emitting module 160 to emit light. Through the switching and coordination of the on and off states of the transistors at different stages, the pixel circuit's reset function, threshold voltage characteristic adjustment function, threshold voltage compensation function, data writing function, and light-emitting function are realized. Each function is executed sequentially in different time periods without interference.

[0120] Figure 15 This is a simulation waveform diagram showing the effect of threshold voltage fluctuation of the driving transistor on the luminous current in a pixel circuit according to an embodiment of the present invention. To verify the compensation and repair effect of the pixel circuit and driving timing described in this application embodiment on the threshold voltage Vth offset of the driving transistor (i.e., dual-gate transistor M1), Figure 15 The simulation results show the current when there are different offsets in the bottom gate threshold voltage of the driving transistor.

[0121] like Figure 15 As shown, the simulation employed three sets of operating conditions calibrated with different initial Vth offsets, represented by curves of different colors. The blue curve indicates a negative offset in the bottom-gate Vth of the driving transistor, meaning the offset of the bottom-gate threshold voltage of the driving transistor is equal to -0.2V, and the driving current generated during the light emission stage is 34.24nA. The brown curve indicates that the bottom-gate Vth of the driving transistor is at the nominal reference value, meaning the offset of the bottom-gate threshold voltage of the driving transistor is equal to 0V, and the reference driving current generated during the light emission stage is 33.69nA. The red curve indicates a positive offset in the bottom-gate Vth of the driving transistor, meaning the offset of the bottom-gate threshold voltage of the driving transistor is equal to 0.2V, and the driving current generated during the light emission stage is 33.12nA. Quantitative analysis using the nominal value (brown curve) as a reference shows that the light emission current deviation under the negative offset condition is approximately +1.63%, and the light emission current deviation under the positive offset condition is approximately -1.69%. Therefore, the solution of this application effectively suppresses the current fluctuation caused by the ±0.2V threshold voltage Vth dispersion to within ±1.6% by constructing a narrow window negative VGS stress during the threshold voltage characteristic adjustment stage t2. Thus, the embodiment of this application can effectively eliminate image quality inconsistencies caused by differences in TFT device processes while simplifying pixel circuitry to support ultra-high PPI display layout, significantly improving the overall uniformity and display quality of the display panel.

[0122] Figure 16 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used for... Figure 12 The pixel circuit shown. Figure 12 The pixel circuit shown is Figure 10 The only difference in the pixel circuits shown is that the data writing transistor M2 and the compensation transistor M3 are P-channel transistors. Because the types of the data writing transistor M2 and the compensation transistor M3 change from N-channel to P-channel, the polarity of the control signal level changes accordingly. Specifically, in Figure 16In the driving timing shown, the first conduction pulse 11 and the second conduction pulse 12 of the first scan signal S1 are both low-level pulses, and the first conduction pulse 21 and the second conduction pulse 22 of the second scan signal S2 are also both low-level pulses. That is, the conduction pulses of the first scan signal S1 and the second scan signal S2 change from high-level pulses to low-level pulses. Meanwhile, the light emission control signal EM is low in the initialization stage t1 and the light emission stage t5, and high in the threshold voltage characteristic adjustment stage t2, the compensation stage t3, and the data writing stage t4. The timing logic of each stage is ANDed with... Figure 10 The pixel circuit shown is the same, that is, the initialization stage t1, the threshold voltage characteristic adjustment stage t2, the compensation stage t3, the data writing stage t4, and the light emission stage t5 are performed sequentially, and the timing coordination of each signal is the same as... Figure 12 The same applies, so I won't go into details here.

[0123] Figure 17 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. Figure 18 This is another simulation waveform diagram of the timing node voltage of the pixel circuit driving provided by the embodiment of the present invention.

[0124] This driver timing can be used Figure 10 and Figure 11 The pixel circuit shown. Figure 17 The driving timing shown is Figure 13 The difference in the driving timing shown is: Figure 17 The driving timing shown does not include the threshold voltage characteristic adjustment stage t2; that is, within one frame, it only includes the initialization stage t1, the compensation stage t2, the data writing stage t3, and the light emission stage t4, which are performed sequentially. Here, VN2 represents the potential at the first terminal of the data writing module 130.

[0125] Specifically, in Figure 17 In the driving timing shown, the first scan signal S1 contains only one conduction pulse, which corresponds to the compensation phase t2. The second scan signal S2 contains two conduction pulses: a first conduction pulse pulse21 and a second conduction pulse pulse22, where the first conduction pulse pulse21 corresponds to the initialization phase t1 and the compensation phase t2, and the second conduction pulse pulse22 corresponds to the data writing phase t3. The light emission control signal EM is low in the initialization phase t1, high in the compensation phase t2 and the data writing phase t3, and low in the light emission phase t4.

[0126] Within one frame, the start time of the turn-on pulse of the first scan signal S1 is earlier than the start time of the turn-off pulse of the light emission control signal EM, and later than the start time of the first turn-on pulse pulse 21 of the second scan signal S2. The end time of the turn-on pulse of the first scan signal S1 is earlier than the end time of the first turn-on pulse pulse 21 of the second scan signal S2, and the end time of the first turn-on pulse pulse 21 of the second scan signal S2 is earlier than the end time of the turn-off pulse of the light emission control signal EM.

[0127] Specifically, the start time of the turn-on pulse of the first scan signal S1 is later than the start time of the first turn-on pulse pulse21 of the second scan signal S2. This ensures that the data writing transistor M2 turns on before the compensation transistor M3, allowing the initialization voltage Vini to be written to the first node N1 first and establish a stable low potential. This prevents incomplete reset of the first gate G of the dual-gate transistor M1 due to the compensation transistor M3 turning on before the potential of the first node N1 is stable. Simultaneously, the start time of the turn-on pulse of the first scan signal S1 is earlier than the start time of the turn-off pulse of the light-emitting control signal EM. This ensures that the compensation transistor M3 is turned on before the light-emitting control transistor M4 is turned off, allowing the path between the second terminal D of the dual-gate transistor M1 and the first gate G to be established first. This prevents the second terminal D of the dual-gate transistor M1 from being left floating due to the light-emitting control transistor M4 turning off first, thus affecting the reset effect.

[0128] The end time of the turn-on pulse of the first scan signal S1 is earlier than the end time of the first turn-on pulse pulse21 of the second scan signal S2. This ensures that the compensation transistor M3 is turned off before the data writing transistor M2 is turned off, avoiding charge crosstalk between the first node N1 and the first gate G of the dual-gate transistor M1 caused by the simultaneous conduction of the compensation transistor M3 and the data writing transistor M2, thus ensuring the stability of the compensation stage t2. Simultaneously, the end time of the first turn-on pulse pulse21 of the second scan signal S2 is earlier than the end time of the turn-off pulse of the light-emitting control signal EM. This ensures that the data writing transistor M2 is turned off only after the light-emitting control transistor M4 is turned off, allowing the first node N1 to maintain a stable potential before the light-emitting control transistor M4 is turned off. This prevents the first node N1 from being floating and subject to noise interference due to the data writing transistor M2 being turned off first.

[0129] because Figure 17 The driving timing shown eliminates the threshold voltage characteristic adjustment stage. The first scan signal S1 only needs to provide a turn-on pulse to achieve the compensation function, making the timing setup simpler and placing lower demands on the timing output of the driver chip. This helps reduce the difficulty and cost of IC development and is suitable for applications with low characteristic adjustment requirements. Detailed working processes for each stage can be found in the above description. Figure 12The descriptions of the corresponding stages in the driving timing shown are not repeated here.

[0130] Figure 19 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 20 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. Figure 20 The driving timing can be used Figure 19 The pixel circuit shown.

[0131] like Figure 19 As shown, in the first voltage selection module 10, the first transistor T1 is a P-channel transistor, and the second transistor T2 is an N-channel transistor, meaning that the channel types of the first transistor T1 and the second transistor T2 are different. The gates of the first transistor T1 and the second transistor T2 are connected to the fifth control signal SW5. During the initialization phase, the fifth control signal SW5 is low, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first power supply voltage VDDL is transmitted to the first terminal S of the dual-gate transistor M1 through the first transistor T1. During the threshold voltage characteristic adjustment phase, the fifth control signal SW5 is high, the first transistor T1 is turned off, the second transistor T2 is turned on, and the second power supply voltage VDDH is transmitted to the first terminal S of the dual-gate transistor M1 through the second transistor T2. Because the channel types of the first transistor T1 and the second transistor T2 are different, they can be switched between time-division multiplexing and turning off using the same fifth control signal SW5, without the need to set two separate, mutually inverted control signals.

[0132] In the second voltage selection module 30, the third transistor T3 is a P-channel transistor, and the fourth transistor T4 is an N-channel transistor, meaning that the channel types of the third transistor T3 and the fourth transistor T4 are different. The gates of the third transistor T3 and the fourth transistor T4 are connected to the sixth control signal SW6. During the initialization phase, the sixth control signal SW6 is low, the third transistor T3 is turned on, the fourth transistor T4 is turned off, and the initialization voltage Vini is transmitted to the data line DL via the third transistor T3. During the data writing phase, the sixth control signal SW6 is high, the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the data voltage Vdata is transmitted to the data line DL via the fourth transistor T4. Similarly, because the channel types of the third transistor T3 and the fourth transistor T4 are different, they can be switched between time-division multiplexing and turning off using the same sixth control signal SW6, without the need to set two separate, mutually inverted control signals.

[0133] Figure 20 The driving timing shown is Figure 13The difference in the driving timing shown is that the fifth control signal SW5 and the sixth control signal SW6 are introduced. The fifth control signal SW5 is low at initialization stage t1, high at threshold voltage characteristic adjustment stage t2, and remains high at compensation stage t3, data writing stage t4, and light emission stage t5. The sixth control signal SW6 is low at initialization stage t1, remains low at threshold voltage characteristic adjustment stage t2 and compensation stage t3, jumps to high at data writing stage t4, and remains high at light emission stage t5. The timing coordination of the remaining signals (i.e., the first scan signal S1, the second scan signal S2, and the light emission control signal EM) is the same as... Figure 13 The same applies, so I won't go into details here.

[0134] like Figure 13 , Figure 16 and Figure 20 As shown, the initialization phase t1 of each pixel circuit is performed simultaneously, the threshold voltage characteristic adjustment phase t2 of each pixel circuit is performed simultaneously, the compensation phase t3 of each pixel circuit is performed simultaneously, the data writing phase t4 of each row of pixel circuits is performed row by row, and the light emission phase t5 of each pixel circuit is performed simultaneously. That is, the initialization phase t1 of the pixel circuit is denoted as the initialization phase of the display panel, the compensation phase of the pixel circuit is denoted as the compensation phase of the display panel, the threshold voltage characteristic adjustment phase t2 of the pixel circuit is also the threshold voltage characteristic adjustment phase t2 of the display panel, and the light emission phase t5 of the pixel circuit is also the light emission phase of the display panel. The data writing phase t3 of the display panel includes the data writing phase of each row of pixel circuits.

[0135] like Figure 13 , Figure 16 and Figure 20 As shown, the first control signal SW1, the second control signal SW2, the third control signal SW3, the fourth control signal SW4, the fifth control signal SW5 and the sixth control signal SW6 are all global signals. These signals act on all pixel circuits in the display panel to control the voltage selection state of the first voltage selection module 10 and the second voltage selection module 30 around each pixel circuit at different stages.

[0136] The first scan signal S1 is a global signal. This signal acts on all pixel circuits in the display panel to control the compensation module 120 of each pixel circuit to be turned on simultaneously in the initialization phase t1 and the compensation phase t3, and turned off simultaneously in the threshold voltage characteristic adjustment phase t2, thereby realizing the synchronous operation of all pixel circuits in the initialization phase and the compensation phase.

[0137] The light emission control signal EM is a global signal. This signal is used to control the light emission control module 150 of all pixel circuits to be turned on simultaneously in the initialization phase t1 and the light emission phase t5, and to be turned off simultaneously in the threshold voltage characteristic adjustment phase t2, the compensation phase t3, and the data writing phase t4.

[0138] The second scan signal S2 is a row-by-row shift signal. The display panel includes multiple second scan lines. The pixel circuit of the i-th row is connected to the i-th second scan line. The second scan signal transmitted on the i-th second scan line is denoted as S2(row_i). Here, i is a positive integer greater than or equal to 1 and less than or equal to N, and N is the total number of rows of pixel circuits in the display panel.

[0139] Specifically, S2(row_1) represents the second scan signal corresponding to the first row of pixel circuits, and S2(row_N) represents the second scan signal corresponding to the Nth row (i.e., the last row) of pixel circuits. During the data writing phase t4, the second conduction pulses pulse22 on each second scan line are sequentially shifted and transmitted row by row according to the order of S2(row_1) to S2(row_N), so that the data writing modules 130 of each row of pixel circuits are sequentially turned on, realizing the row-by-row writing of the data voltage Vdata. During the initialization phase t1, the threshold voltage characteristic adjustment phase t2, and the compensation phase t3, the first conduction pulses pulse21 provided on each second scan line appear simultaneously and overlap, in conjunction with the aforementioned global signals (such as S1 and EM), to achieve global synchronous reset, characteristic adjustment, and compensation of all pixel circuits.

[0140] Furthermore, both the first scan signal S1 and the light emission control signal EM are global signals, directly provided by the driver IC of the non-display area (NAA) of the display panel, and transmitted to all pixel circuits through global signal lines, without needing to be generated by the gate drive circuit. The second scan signal S2 is configured as a line-by-line shift signal.

[0141] To achieve row-by-row shifting of the second scan signal S2, a gate driving circuit for generating the second scan signal S2 is provided in the non-display area NAA of the display panel. This gate driving circuit includes multiple cascaded shift registers for outputting row-by-row shift pulse signals S2(row_1) to S2(row_N), thereby enabling row-by-row selection of the data writing module 130 for each row of pixel circuits. Compared to the traditional display panel scheme that requires configuring corresponding gate driving circuits for multiple sets of signals such as the first scan signal, the second scan signal, and the light emission control signal, the embodiment of this invention provides the first scan signal S1 and the light emission control signal EM directly as global signals by the driver chip without relying on the gate driving circuit for generation. Therefore, in this embodiment, there is only one set of gate driving circuits, which is used to generate the aforementioned second scan signal S2. This single-set gate driving circuit layout greatly reduces the number of gate driving circuit sets required in the non-display area, significantly reduces the bezel size of the display panel, and further meets the requirements of ultra-high PPI display layouts for narrow bezel design.

[0142] Figure 21 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. For example... Figure 10 and Figure 21 As shown, the dual-gate transistor M1 and the light-emitting control transistor M4 are polysilicon thin-film transistors, while the compensation transistor M3 and the data writing transistor M2 are oxide thin-film transistors.

[0143] The display panel also includes a substrate 101 and a first active layer 102 and a second active layer 103 sequentially stacked along a direction away from the substrate 101. The channel regions of the dual-gate transistor M1 and the light-emitting control transistor M4 are located in the first active layer 102. The channel regions of the compensation transistor M3 and the data writing transistor M2 are located in the second active layer 103; the orthographic projections of the first active layer 102 and the second active layer 103 on the substrate 101 overlap. This design facilitates saving layout space and achieving ultra-high PPI display layouts.

[0144] Based on the display panel provided in the above embodiments, and in accordance with the same inventive concept, this application also provides a display device, including the display panel provided in any embodiment of the present invention. The display device provided in the embodiments of the present invention can be other display devices with display functions, such as wearable products, computers, televisions, and vehicle-mounted display devices; the present invention does not impose specific limitations on these. The display device provided in the embodiments of the present invention has the beneficial effects of the display panel provided in the embodiments of the present invention. For details, please refer to the specific descriptions of the display panel in the above embodiments; these descriptions will not be repeated here.

[0145] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: A first voltage selection module and multiple pixel circuits, wherein the pixel circuits include a driving module and a compensation module; The first voltage selection module is connected to at least one pixel circuit. The driving module includes a dual-gate transistor, which includes a first electrode, a second electrode, a first gate, and a second gate. The first electrode of the dual-gate transistor is connected to the first voltage selection module, and the second gate of the dual-gate transistor is connected to the first electrode of the dual-gate transistor. The compensation module is connected between the second terminal of the dual-gate transistor and the first gate of the dual-gate transistor; The first voltage selection module is used to transmit a first power supply voltage or a second power supply voltage to the first terminal of the dual-gate transistor in a time-division manner; the first power supply voltage is used to simultaneously reset the first terminal of the dual-gate transistor and the first gate of the dual-gate transistor.

2. The display panel according to claim 1, characterized in that, The first voltage selection module includes a first input terminal, a second input terminal, a first control terminal, a second control terminal, and a first output terminal; The first output terminal is connected to the first electrode of the dual-gate transistor, the first input terminal is connected to the first power supply voltage, and the second input terminal is connected to the second power supply voltage. The first voltage selection module is configured to transmit a first power supply voltage to the first terminal of the dual-gate transistor in response to a signal from the first control terminal during the initialization phase; and to transmit a second power supply voltage to the first terminal of the dual-gate transistor in response to a signal from the second control terminal during the threshold voltage characteristic adjustment phase; wherein, within one frame, the initialization phase is prior to the threshold voltage characteristic adjustment phase.

3. The display panel according to claim 2, characterized in that, The control terminal of the compensation module is connected to the first scan line, and the first scan line transmits the first scan signal. The compensation module is used to turn on in response to the first conduction pulse of the first scan signal during the initialization phase, so as to transmit the first power supply voltage to the first gate of the dual-gate transistor. And during the compensation phase, the second conduction pulse responding to the first scan signal is turned on; During the threshold voltage characteristic adjustment phase, the compensation module is configured to be turned off by the first scan signal; within one frame, the threshold voltage characteristic adjustment phase is located between the initialization phase and the compensation phase; Preferably, the duration of the second conduction pulse of the first scan signal is longer than the duration of the first conduction pulse of the first scan signal.

4. The display panel according to claim 1, characterized in that, The pixel circuit also includes a data writing module and a first storage module; The first storage module is connected between the first node and the first gate of the dual-gate transistor, and is used to store the voltage difference between the first node and the first gate of the dual-gate transistor; The first end of the data writing module is connected to the data line, and the second end of the data writing module is connected to the first node. The data writing module is used to transmit the initialization voltage input by the data line to the first node during the initialization phase; and to transmit the data voltage input by the data line to the first node during the data writing phase; wherein, within one frame, the data writing phase is located after the initialization phase. Preferably, the display panel further includes a second voltage selection module, which includes a third input terminal, a fourth input terminal, a third control terminal, a fourth control terminal, and a second output terminal. The second output terminal is connected to the data line; the third input terminal is connected to the initialization voltage, and the fourth input terminal is connected to the data voltage; The second voltage selection module is used to transmit the initialization voltage to the data line in response to the signal of the third control terminal during the initialization phase; and to transmit the data voltage to the data line in response to the signal of the fourth control terminal during the data writing phase.

5. The display panel according to claim 4, characterized in that, The pixel circuit also includes a light-emitting control module and a light-emitting module; The light-emitting control module is disposed between the second terminal of the dual-gate transistor and the first terminal of the light-emitting module, and the second terminal of the light-emitting module is connected to the third power supply line; The control terminal of the light-emitting control module is connected to the light-emitting control line; the light-emitting control module is used to activate the light-emitting control signal on the light-emitting control line during the initialization phase and the light-emitting phase. Preferably, the first power supply voltage is used to simultaneously reset the first terminal of the dual-gate transistor, the first gate of the dual-gate transistor, and the first terminal of the light-emitting module; Preferably, the control terminal of the compensation module is connected to the first scan line, and the first scan line transmits the first scan signal; Within one frame, the start time of the turn-on pulse of the first scan signal is earlier than the start time of the turn-off pulse of the light emission control signal and later than the start time of the first turn-on pulse of the second scan signal. The end time of the turn-on pulse of the first scan signal is earlier than the end time of the first turn-on pulse of the second scan signal, and the end time of the first turn-on pulse of the second scan signal is earlier than the end time of the turn-off pulse of the light emission control signal.

6. The display panel according to claim 5, characterized in that, The data writing module includes a data writing transistor, the compensation module includes a compensation transistor, and the light emission control module includes a light emission control transistor. The gate of the compensation transistor is connected to the first scan line, the first terminal of the compensation transistor is connected to the second terminal of the dual-gate transistor, and the second terminal of the compensation transistor is connected to the first gate of the dual-gate transistor. The gate of the data writing transistor is connected to the second scan line, the first terminal of the data writing transistor is connected to the data line, and the second terminal of the data writing transistor is connected to the first node; The gate of the light-emitting control transistor is connected to the light-emitting control line, the first terminal of the light-emitting control transistor is connected to the second terminal of the dual-gate transistor, and the second terminal of the light-emitting control transistor is connected to the first terminal of the light-emitting module; Preferably, the data writing transistor is a four-terminal device having a first gate and a second gate, wherein the first gate of the data writing transistor is connected to the second scan line, and the second gate of the data writing transistor is connected to the second terminal of the data writing transistor; Preferably, the compensation transistor is a four-terminal device having a first gate and a second gate, wherein the first gate of the compensation transistor is connected to a first scan line, and the second gate of the compensation transistor is connected to the second terminal of the compensation transistor.

7. The display panel according to claim 6, characterized in that, The dual-gate transistor and the light-emitting control transistor are polycrystalline silicon thin-film transistors, and the compensation transistor and the data writing transistor are oxide thin-film transistors. The display panel further includes a substrate and a first active layer and a second active layer sequentially stacked along a direction away from the substrate; The channel regions of the dual-gate transistor and the light-emitting control transistor are located in the first active layer; The channel regions of the compensation transistor and the data writing transistor are located in the second active layer; The orthographic projections of the first active layer and the second active layer on the substrate have an overlapping portion.

8. The display panel according to claim 1, characterized in that, In one frame, the operation of the pixel circuit includes, in sequence, an initialization phase, a threshold voltage characteristic adjustment phase, a compensation phase, a data writing phase, and a light emission phase; The initialization phase of each pixel circuit is performed simultaneously, the threshold voltage characteristic adjustment phase of each pixel circuit is performed simultaneously, the compensation phase of each pixel circuit is performed simultaneously, the data writing phase of each row of pixel circuits is performed row by row, and the light emission phase of each pixel circuit is performed simultaneously.

9. The display panel according to claim 1, characterized in that, The pixel circuit further includes a second storage module, which is connected between the first node and the first electrode of the dual-gate transistor, and is used to store the voltage difference between the first node and the first electrode of the dual-gate transistor.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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