A gate driving circuit, an array substrate and a display panel

Abstract

The application discloses a gate driving circuit, an array substrate and a display panel. The gate driving circuit comprises: a plurality of cascaded first gate driving units; the width of the conductive channel of the output transistor of the first M-stage first gate driving unit at the frontmost position and the width of the conductive channel of the output transistor of the first N-stage first gate driving unit at the last position are greater than the width of the conductive channel of the output transistor of the first K-stage first gate driving unit at the middle position; and / or the length of the conductive channel of the output transistor of the first M-stage first gate driving unit at the frontmost position and the length of the conductive channel of the output transistor of the first N-stage first gate driving unit at the last position are less than the length of the conductive channel of the output transistor of the first K-stage first gate driving unit at the middle position. The application effectively improves the ESD resistance of the first gate driving unit at the upper and lower edges of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit, an array substrate, and a display panel. Background Technology

[0002] GIP (Gate in Panel) technology refers to the technology of directly integrating gate driving circuits on the glass substrate of the display panel. The gate driving circuits are located on the left and right edges of the display panel and are cascaded. This technology is different from the traditional external IC driving method. By integrating the gate driving circuit inside the panel, a narrow bezel design can be achieved and production costs can be reduced.

[0003] The gate drive circuit located at the top and bottom edges of the display panel is susceptible to electrostatic discharge (ESD), which can cause the gate drive circuit to malfunction. Summary of the Invention

[0004] This invention provides a gate driving circuit, an array substrate, and a display panel to solve the problem that the gate driving circuits at the top and bottom edges of the display panel are easily affected by ESD, causing them to malfunction.

[0005] In a first aspect, the present invention provides a gate driving circuit, wherein the gate driving circuit includes: a plurality of cascaded first gate driving units;

[0006] The first gate driving unit is used to output the gate driving signal. Multiple cascaded first gate driving units include the first M-stage first gate driving unit, the last N-stage first gate driving unit, and the middle K-stage first gate driving unit. The first gate driving unit includes an output transistor connected to the output terminal. Wherein, M is an integer greater than or equal to 1, N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1.

[0007] The width of the conductive channel of the output transistor of the first gate driving unit of the first Mth stage is greater than the width of the conductive channel of the output transistor of the first gate driving unit of the middle Kth stage, and the width of the conductive channel of the output transistor of the last Nth stage is greater than the width of the conductive channel of the output transistor of the middle Kth stage; and / or, the length of the conductive channel of the output transistor of the first gate driving unit of the first Mth stage is less than the length of the conductive channel of the output transistor of the middle Kth stage, and the length of the conductive channel of the output transistor of the last Nth stage is less than the length of the conductive channel of the output transistor of the middle Kth stage.

[0008] Optionally, the output transistors of the first gate driving unit in the first M stage include a first output transistor and a second output transistor; the output transistors of the last N stage first gate driving unit include a third output transistor and a fourth output transistor; and the output transistors of the middle K stage first gate driving unit include a fifth output transistor and a sixth output transistor.

[0009] The widths of the conductive channels of the first, second, third, and fourth output transistors are all greater than the width of the conductive channel of the fifth output transistor; the widths of the conductive channels of the first, second, third, and fourth output transistors are all greater than the width of the conductive channel of the sixth output transistor.

[0010] And / or, the lengths of the conductive channels of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor are all less than the length of the conductive channel of the fifth output transistor; the lengths of the conductive channels of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor are all less than the length of the conductive channel of the sixth output transistor.

[0011] Optionally, the first gate driving unit of the first M-stage further includes at least one seventh output transistor and at least one eighth output transistor; the first gate driving unit of the last N-stage further includes at least one ninth output transistor and at least one tenth output transistor.

[0012] At least one seventh output transistor is connected in parallel with the first output transistor, at least one eighth output transistor is connected in parallel with the second output transistor; at least one ninth output transistor is connected in parallel with the third output transistor, and at least one tenth output transistor is connected in parallel with the fourth output transistor.

[0013] Optionally, the width and length of the conductive channel of the seventh output transistor are equal to the width and length of the conductive channel of the first output transistor, and the width and length of the conductive channel of the eighth output transistor are equal to the width and length of the conductive channel of the second output transistor.

[0014] The width and length of the conductive channel of the ninth output transistor are equal to the width and length of the conductive channel of the third output transistor, and the width and length of the conductive channel of the tenth output transistor are equal to the width and length of the conductive channel of the fourth output transistor.

[0015] Optionally, the gate driving circuit further includes: at least one second gate driving unit;

[0016] At least one of the first gate driving units in the first M-stage and the last N-stage is provided with a second gate driving unit, which serves as a backup for the corresponding first gate driving unit.

[0017] In a second aspect, the present invention provides an array substrate, wherein the array substrate includes a plurality of cascaded first gate driving units; the plurality of cascaded first gate driving units include a first M-stage first gate driving unit, a last N-stage first gate driving unit, and an intermediate K-stage first gate driving unit; the first gate driving unit includes an output transistor connected to an output terminal; wherein M is an integer greater than or equal to 1, N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1.

[0018] The array substrate includes:

[0019] The substrate has a first gate driving unit located on one side of it.

[0020] The output transistor of the first gate driving unit of the first M-stage includes a first source / drain and a first active region; the output transistor of the last N-stage first gate driving unit includes a second source / drain and a second active region; and the output transistor of the middle K-stage first gate driving unit includes a third source / drain and a third active region.

[0021] The number of first via pairs connecting the first source / drain and the first active region is greater than the number of third via pairs connecting the third source / drain and the third active region, and the number of second via pairs connecting the second source / drain and the second active region is greater than the number of third via pairs connecting the third source / drain and the third active region.

[0022] Optionally, along the width direction of the conductive channel of the output transistor, the width of the first active region is greater than the width of the third active region, and the width of the second active region is greater than the width of the third active region.

[0023] And / or, the spacing of the first via pair is less than the spacing of the third via pair, and the spacing of the second via pair is less than the spacing of the third via pair.

[0024] Optionally, the output transistors of the first gate driving unit in the first M stage include a first output transistor and a second output transistor; the output transistors of the last N stage first gate driving unit include a third output transistor and a fourth output transistor; the output transistors of the middle K stage first gate driving unit include a fifth output transistor and a sixth output transistor; the first M stage first gate driving unit further includes at least one seventh output transistor connected in parallel with the first output transistor and at least one eighth output transistor connected in parallel with the second output transistor; the last N stage first gate driving unit further includes at least one ninth output transistor connected in parallel with the third output transistor and at least one tenth output transistor connected in parallel with the fourth output transistor.

[0025] The first output transistor includes a first source / drain and a first active region; the second output transistor includes a first source / drain and a first active region; the third output transistor includes a second source / drain and a second active region; the fourth output transistor includes a second source / drain and a second active region; the fifth output transistor includes a third source / drain and a third active region; and the sixth output transistor includes a third source / drain and a third active region.

[0026] The seventh output transistor includes a fourth source / drain and a fourth active region; the eighth output transistor includes a fourth source / drain and a fourth active region; the ninth output transistor includes a fifth source / drain and a fifth active region; and the tenth output transistor includes a fifth source / drain and a fifth active region.

[0027] The number of fourth via pairs connecting the fourth source / drain and the fourth active region is the same as the number of first via pairs, and the number of fifth via pairs connecting the fifth source / drain and the fifth active region is the same as the number of second via pairs.

[0028] Optionally, along the width direction of the conductive channel of the output transistor, the width of the fourth active region is equal to the width of the first active region, and the width of the fifth active region is equal to the width of the second active region.

[0029] And / or, the spacing of the fourth via pair is equal to the spacing of the first via pair, and the spacing of the fifth via pair is equal to the spacing of the second via pair.

[0030] Thirdly, the present invention provides a display panel, wherein the display panel includes the array substrate provided in the second aspect above.

[0031] The technical solution of this invention involves setting the width of the conductive channel of the output transistor of the first M-stage first gate driving unit to be greater than the width of the conductive channel of the output transistor of the middle K-stage first gate driving unit, and the width of the conductive channel of the output transistor of the last N-stage first gate driving unit to be greater than the width of the conductive channel of the output transistor of the middle K-stage first gate driving unit. And / or, the length of the conductive channel of the output transistor of the first M-stage first gate driving unit is less than the length of the conductive channel of the output transistor of the middle K-stage first gate driving unit, and the length of the conductive channel of the output transistor of the last N-stage first gate driving unit is less than the length of the conductive channel of the output transistor of the middle K-stage first gate driving unit. This results in the number of first via pairs connecting the first source, first drain, and first active region of the output transistor of the first M-stage first gate driving unit being greater than the number of third via pairs connecting the third source, third drain, and third active region of the output transistor of the middle K-stage first gate driving unit, and the number of second via pairs connecting the second source, second drain, and second active region of the output transistor of the last N-stage first gate driving unit being greater than the number of second via pairs connecting the second source, second drain, and second active region of the output transistor of the last N-stage first gate driving unit. The increased number of via pairs connecting the third source, third drain, and third active region of the output transistors in the intermediate K-level first gate drive units ensures that even when the conductive channels between some first via pairs and some second via pairs in the output transistors of the first M-level and last N-level first gate drive units are damaged by electrostatic discharge, the output transistors of the first M-level and last N-level first gate drive units can still ensure that the output gate drive signal potential is raised to the required value per unit time. This maintains the thrust capability even when ESD damages part of the conductive channel, thereby improving the ESD resistance of the first M-level and last N-level first gate drive units. Each row of pixels can also receive normal gate drive signals, and the entire operation of the display panel remains unaffected.

[0032] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a gate driving unit provided by related technologies;

[0035] Figure 2 This is a schematic diagram of a pixel circuit structure provided by related technologies;

[0036] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the circuit structure of the first gate driving unit of the Mth stage provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the circuit structure of the last N-stage first gate driving unit provided in an embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram of the circuit structure of an intermediate K-stage first gate driving unit provided in an embodiment of the present invention;

[0040] Figure 7 This is a cross-sectional structural schematic diagram of the output transistor of the first gate driving unit of the first M-stage or the last gate driving unit of the first N-stage provided in an embodiment of the present invention.

[0041] Figure 8 This is a top view of an output transistor of the first gate driving unit of the first M-stage or the last gate driving unit of the first N-stage provided in an embodiment of the present invention.

[0042] Figure 9 This is a schematic cross-sectional view of the output transistor of the intermediate K-stage first gate driving unit provided in an embodiment of the present invention.

[0043] Figure 10 This is a top view of the output transistor of the intermediate K-stage first gate driving unit provided in an embodiment of the present invention;

[0044] Figure 11 This is a schematic diagram of another circuit structure of the first gate driving unit of the first M-stage provided in an embodiment of the present invention;

[0045] Figure 12 This is a schematic diagram of another circuit structure of the last N-stage first gate driving unit provided in an embodiment of the present invention;

[0046] Figure 13 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] Figure 1 This is a schematic diagram of a gate driving unit provided by related technologies, such as... Figure 1As shown, the first terminal of the first transistor M1 is connected to the input signal EIN, the control terminal of the first transistor M1 is connected to the first clock signal line ECK1, the second terminal of the first transistor M1 is connected to the control terminal of the second transistor M2, the first terminal of the second transistor M2 is connected to the first clock signal line ECK1, and the second terminal of the second transistor M2 is connected to the second terminal of the third transistor M3. The first terminal of the third transistor M3 is connected to the first level signal VGL. The control terminal of the third transistor M3 is connected to the first clock signal line ECK1. The second terminal of the third transistor M3 is connected to the first terminal of the thirteenth transistor M13. The control terminal of the thirteenth transistor M13 is connected to the first level signal VGL. The second terminal of the thirteenth transistor M13 is connected to the first terminal of the twelfth transistor M12. The control terminal of the twelfth transistor M12 is connected to the first level signal VGL. The second terminal of the twelfth transistor M12 is connected to the control terminal of the fourth transistor M4. The first terminal of the fourth transistor M4 is connected to the second level signal VGH. The second terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5. The control terminal of the fifth transistor M5 is connected to the second clock signal line ECK2. The second terminal of the fifth transistor M5 is connected to the second terminal of the first transistor M1. The control terminal of the eighth transistor M8 is connected to the second terminal of the thirteenth transistor M13. The first terminal of the eighth transistor M8 is connected to the second clock signal line ECK2. The second terminal of the eighth transistor M8 is connected to the first terminal of the seventh transistor M7. The first capacitor C1 is connected between the control terminal and the second terminal of the eighth transistor M8. The control terminal of the seventh transistor M7 is connected to the second clock signal line ECK2. The second terminal of the seventh transistor M7 is connected to the control terminal of the ninth transistor M9. The first terminal of the sixth transistor M6 is connected to the second terminal of the seventh transistor M7. The second terminal of the sixth transistor M6 is connected to the second level signal VGH. The control terminal of the sixth transistor M6 is connected to the first terminal of the eleventh transistor M11. The control terminal of the eleventh transistor M11 is connected to the first level signal VGL. The second terminal of the eleventh transistor M11 is connected to the control terminal of the tenth transistor M10. The first terminal of the ninth transistor M9 is connected to the second level signal VGH. The second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10 and serves as the output terminal of the gate drive unit 1, outputting the gate drive signal Eout. The second terminal of the tenth transistor M10 is connected to the first level signal VGL. The second capacitor C2 is connected between the control terminal of the tenth transistor M10 and the second clock signal line ECK2. The third capacitor C5 is connected between the control terminal and the first terminal of the ninth transistor M9. The first transistor M1 to the thirteenth transistor M13 in the gate driving unit 1 can all be P-type transistors, and the ninth transistor M9 and the tenth transistor M10 are the output transistors of the gate driving unit 1.

[0050] The output of gate driving unit 1 is connected to the gate line of the display area. The gate lines located at the top and bottom edges of the display area are more susceptible to ESD, causing the gate driving circuit 1 at the top and bottom edges of the display panel to easily couple electrostatic discharge, damaging the ninth transistor M9 and the tenth transistor M10. This results in a smaller effective channel width W for the ninth transistor M9 and the tenth transistor M10, further reducing their conduction capability. The formula for calculating the transistor's on-state current Ids is as follows:

[0051]

[0052] Where W is the channel width of the transistor, L is the channel length of the transistor, u is the carrier mobility, Cox is the gate oxide capacitance of the transistor, Vgs is the voltage between the gate and source of the transistor, Vds is the voltage between the drain and source of the transistor, and Vth is the threshold voltage of the transistor.

[0053] As can be seen from the above calculation formula, the reduced equivalent channel width W of the ninth transistor M9 and the tenth transistor M10 will lead to a reduction in the on-current Ids of the ninth transistor M9 and the tenth transistor M10, which in turn will result in a decrease in the output voltage of the gate drive unit 1 or even no output.

[0054] Figure 2 This is a schematic diagram of a pixel circuit provided by related technologies. The gate drive signal output by the gate drive unit can be connected to the control terminal of the transistor in the pixel circuit. For example... Figure 2The fourteenth transistor M14 has its first terminal connected to the data voltage signal Vdata, its control terminal connected to the second scan signal Scan2, its second terminal connected to the first terminal of the fifteenth transistor M15, its second terminal connected to the first power supply signal VDD, and its control terminal connected to the light emission control signal EM. The sixteenth transistor M16 has its first terminal connected to the second terminal of the fourteenth transistor M14, its second terminal connected to the first terminal of the eighteenth transistor M18, its control terminal connected to the light emission control signal EM, and its second terminal connected to the anode of the light-emitting diode (OLED). The cathode of the OLED is connected to the second power supply signal VSS. The seventeenth transistor M17 has its first terminal connected to the control terminal of the sixteenth transistor M16, its second terminal connected to the first terminal of the nineteenth transistor M19, and its second terminal connected to the first terminal of the eighteenth transistor M18. The control terminals of both the seventeenth and nineteenth transistors are connected to the second scan signal Scan2. The first terminal of the 22nd transistor M22 is connected to the anode of the OLED, and the second terminal of the 22nd transistor M22 is connected to the initialization signal Vref. The control terminal of the 22nd transistor M22 is connected to the first scan signal Scan1. The first terminal of the 20th transistor M20 is connected to the second terminal of the 22nd transistor M22. The control terminals of the 20th transistor M20 and the 21st transistor M21 are connected to the first scan signal Scan1. The second terminal of the 20th transistor M20 is connected to the first terminal of the 21st transistor M21. The first terminal of the fourth capacitor C4 is connected to the first power supply signal VDD, and the second terminal of the fourth capacitor C4 is connected to the second terminal of the 21st transistor M21. The 14th transistor M14 to the 22nd transistor M22 in the pixel circuit 2 can all be P-type transistors.

[0055] like Figure 1 and Figure 2 As shown, Figure 1 The gate drive signal Eout output from the output terminal of the provided gate drive unit 1 can be Figure 2 The light emission control signal EM in the middle can also be used for Figure 2The first scan signal Scan1 or the second scan signal Scan2 in the display is connected to the gate line, for example, the output terminal of the gate driving unit 1 is connected to the gate line, and the control terminals of the eighteenth transistor M18 and the fifteenth transistor M15 are connected to the gate line. During the waiting period from power-on to the display stage, the gate driving signal Eout output by the output terminal of the gate driving unit 1 is the second level signal VGH. At this time, the first power supply signal VDD and the second power supply signal VSS have been output normally. If the voltage of the second level signal VGH output by the gate driving unit 1 decreases due to static electricity, the fifteenth transistor M15 and the eighteenth transistor M18 will be slightly turned on, and the control terminal of the sixteenth transistor M16 will be in a floating state. It is easy for it to also be in a slightly turned-on state due to coupling, thereby causing the light-emitting diode OLED to emit light during the waiting period, resulting in abnormal operation of the pixel circuit 2.

[0056] In view of the above, the embodiments of the present invention provide the following technical solutions:

[0057] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the circuit structure of the first gate driving unit of the Mth stage provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the circuit structure of the first gate driving unit of the last N-stage according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the circuit structure of an intermediate K-stage first gate driving unit provided in an embodiment of the present invention, as shown below. Figures 3-6As shown, the display panel includes a gate driving circuit 20, which includes multiple cascaded first gate driving units 11. The first gate driving units 11 output a gate driving signal Eout. The multiple cascaded first gate driving units 11 include a first M-stage first gate driving unit 11, a last N-stage first gate driving unit 11, and an intermediate K-stage first gate driving unit 11. Each first gate driving unit 11 includes an output transistor 111 connected to an output terminal. Here, M is an integer greater than or equal to 1, N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1. The width of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the width of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11, and the width of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is greater than the width of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11. And / or, the length of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is less than the length of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11, and the length of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is less than the length of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11.

[0058] Specifically, the display panel may include a display area and a non-display area. The display area may be configured with an array of pixels, and the non-display area may be configured with a gate driving circuit 20. The gate driving circuit 20 includes multiple cascaded first gate driving units 11. The multiple cascaded first gate driving units 11 may output a gate driving signal Eout. The gate driving signal Eout may be transmitted to the gate line connected to each row of pixels to drive the pixels in the display area row by row.

[0059] The first gate driving unit 11 of the first M stage can include the first gate driving unit 11 of the first stage to the first gate driving unit 11 of the Mth stage. The first gate driving unit 11 of the last N stage can include the first gate driving unit 11 of the Nth stage from the end to the last stage. The first gate driving unit 11 of the middle K stage can include the first gate driving unit 11 of the (M+1)th stage to the first gate driving unit 11 of the (N-1)th stage from the end.

[0060] In this embodiment of the invention, the width of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the width of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11, and the width of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is greater than the width of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. This ensures that when a portion of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 and the output transistor 111 of the last N-stage first gate driving unit 11 is damaged by coupled electrostatic discharge, the output transistors 111 of the first M-stage first gate driving unit 11 and the output transistor 111 of the last N-stage first gate driving unit 11 can ensure that the potential of the output gate driving signal Eout is raised to the required value within a unit time, thus maintaining the thrust capability even when a portion of the conductive channel is damaged by ESD.

[0061] The conductive channel of the output transistor 111 of the first gate driving unit 11 can be multiple conductive channels connected in parallel. The width of the conductive channel of the output transistor 111 of the first gate driving unit 11 is the sum of the widths of the multiple conductive channels connected in parallel. The length of the conductive channel of the output transistor 111 of the first gate driving unit 11 is the length of a single conductive channel among the multiple conductive channels connected in parallel. The present invention sets the length of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 to be less than the length of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11, and the length of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 to be less than the length of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. This can effectively increase the number of parallel conductive channels in the output transistors 111 of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11, thereby increasing the width of the conductive channels of the output transistors 111 of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11. When the output transistors 111 of the first M-stage gate drive unit 11 and the last N-stage gate drive unit 11 are partially damaged by coupled electrostatic discharge, the output transistors 111 of the first M-stage gate drive unit 11 and the last N-stage gate drive unit 11 can ensure that the potential of the output gate drive signal Eout is raised to the required value within a unit time, thus maintaining the thrust capability even when the conductive channel is partially damaged by ESD.

[0062] Figure 7 This is a cross-sectional structural diagram of the output transistor of the first gate driving unit of the first M-stage or the last gate driving unit of the first N-stage provided by an embodiment of the present invention. Figure 8 This is a top view of an output transistor of either the first gate driving unit of the Mth stage or the last gate driving unit of the Nth stage provided in an embodiment of the present invention. Figure 9 This is a schematic cross-sectional view of the output transistor of the intermediate K-stage first gate driving unit provided in an embodiment of the present invention. Figure 10 This is a top view of the output transistor of the intermediate K-stage first gate driving unit provided in an embodiment of the present invention, as shown below. Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, the output transistor 111 of the first gate driving unit 11 in the first M stage may include a first active region 21 located on one side of the substrate 30, a first insulating region 31 located on the side of the first active region 21 away from the substrate 30, a first source 41 and a first drain 51 located on the side of the first insulating region 31 away from the substrate 30, the first source 41 and the first drain 51 being arranged in a cross pattern, and multiple first sources 41 and multiple first drains 51 being connected together. A second insulating region 61 is located on the side of the first insulating region 31 away from the substrate 30, and a forked first gate 71 is located on the side of the second insulating region 61 away from the substrate 30. Finally, the output transistor 111 of the N-stage first gate driving unit 11 may include a second active region 22 located on one side of the substrate 30, a third insulating region 32 located on the side of the second active region 22 away from the substrate 30, a second source 42 and a second drain 52 located on the side of the third insulating region 32 away from the substrate 30, the second source 42 and the second drain 52 being arranged in a cross pattern, and multiple second sources 42 and multiple second drains 52 being connected together. A fourth insulating region 62 is located on the side of the third insulating region 32 away from the substrate 30, and a forked second gate 72 is located on the side of the fourth insulating region 62 away from the substrate 30.

[0063] Each of the first insulating regions 31 can be provided with a first contact hole 311 and a second contact hole 312. The first source electrode 41 contacts the first active region 21 through the first contact hole 311, and the first drain electrode 51 contacts the first active region 21 through the second contact hole 312. Adjacent first contact holes 311 and second contact holes 312 form a first via pair. Each of the third insulating regions 32 can be provided with a third contact hole 321 and a fourth contact hole 322. The second source electrode 42 contacts the second active region 22 through the third contact hole 321, and the second drain electrode 52 contacts the second active region 22 through the fourth contact hole 322. Adjacent third contact holes 321 and fourth contact holes 322 form a second via pair.

[0064] Figure 8This diagram shows a top view of the first active region 21, first contact hole 311, second contact hole 312, first source 41 within the first contact hole 311, and first drain 51 within the second contact hole 312 of the output transistor 111 of the first gate driving unit 11 in the first M-stage. Other film layers of the output transistor 111 in the first gate driving unit 11 in the first M-stage are not shown. Figure 8 As shown in the image. Figure 8 The top view structure of the second active region 22, the third contact hole 321, the fourth contact hole 322, the second source 42 in the third contact hole 321, and the second drain 52 in the fourth contact hole 322 of the output transistor 111 of the last N-stage first gate driving unit 11 is also shown. Other films of the output transistor 111 of the last N-stage first gate driving unit 11 are not shown. Figure 8 As shown in the image.

[0065] like Figure 4 , Figure 5 , Figure 9 and Figure 10 As shown, the output transistor 111 of the intermediate K-stage first gate driving unit 11 may include a third active region 23 located on one side of the substrate 30, a fifth insulating region 33 located on the side of the third active region 23 away from the substrate 30, a third source 43 and a third drain 53 located on the side of the fifth insulating region 33 away from the substrate 30, the third source 43 and the third drain 53 being arranged in a cross pattern, and multiple third sources 43 and multiple third drains 53 being connected together. A sixth insulating region 63 is located on the side of the fifth insulating region 33 away from the substrate 30, and a forked third gate 73 is located on the side of the sixth insulating region 63 away from the substrate 30.

[0066] The fifth insulating region 33 may be provided with a fifth contact hole 331 and a sixth contact hole 332. The third source electrode 43 contacts the third active region 23 through the fifth contact hole 331, and the third drain electrode 53 contacts the third active region 23 through the sixth contact hole 332. Adjacent fifth contact holes 331 and sixth contact holes 332 constitute a third via pair.

[0067] Figure 10 This diagram shows a top view of the third active region 23, the fifth contact hole 331, the sixth contact hole 332, the third source 43 within the fifth contact hole 331, and the third drain 53 within the sixth contact hole 332 of the output transistor 111 of the intermediate K-stage first gate driving unit 11. Other film layers of the output transistor 111 of the intermediate K-stage first gate driving unit 11 are not shown. Figure 10 As shown in the image.

[0068] like Figures 4-10As shown, the first active region 21 of the output transistor 111 of the first gate driving unit 11 of the first M-stage can include multiple first conductive channels 211 located between the first source 41 and the first drain 51. The first conductive channel 211 is the region of the first active region 21 between the first source 41 and the first drain 51 when the output transistor 111 of the first M-stage first gate driving unit 11 is turned on. The width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is the sum of the widths W1 of the multiple first conductive channels 211. The length La of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is the length L1 of a single first conductive channel 211.

[0069] The second active region 22 of the output transistor 111 of the last N-stage first gate driving unit 11 may include multiple second conductive channels 221 located between the second source 42 and the second drain 52. The second conductive channel 221 is the region of the second active region 22 between the second source 42 and the second drain 52 when the output transistor 111 of the last N-stage first gate driving unit 11 is turned on. Similarly, the width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is the sum of the widths W2 of the multiple second conductive channels 221. The length Lb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is the length L2 of a single second conductive channel 221.

[0070] The third active region 23 of the output transistor 111 of the intermediate K-stage first gate driving unit 11 may include multiple third conductive channels 231 located between the third source 43 and the third drain 53. The third conductive channel 231 is the region of the third active region 23 between the third source 43 and the third drain 53 when the output transistor 111 of the intermediate K-stage first gate driving unit 11 is turned on. Similarly, the width Wc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11 is the sum of the widths W3 of the multiple third conductive channels 231. The length Lc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11 is the length L3 of a single third conductive channel 231.

[0071] like Figure 8 and Figure 10As shown, in this embodiment of the invention, the width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is set to be greater than the width Wc of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. That is, the width W1 of the first conductive channel 211 can be set to be greater than the width W3 of the third conductive channel 231, so that along the width direction of the conductive channel, the number of first via pairs formed by the adjacent first contact holes 311 and second contact holes 312 of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the number of third via pairs formed by the adjacent fifth contact holes 331 and sixth contact holes 332 of the output transistor 111 of the middle K-stage first gate driving unit 11. In this embodiment of the invention, the width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is set to be greater than the width Wc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11. That is, the width W2 of the second conductive channel 221 can be set to be greater than the width W3 of the third conductive channel 231. This results in the number of second via pairs formed by adjacent third contact holes 321 and fourth contact holes 322 of the output transistor 111 of the last N-stage first gate driving unit 11 along the width direction of the conductive channel being greater than the number of third via pairs formed by adjacent fifth contact holes 331 and sixth contact holes 332 of the output transistor 111 of the intermediate K-stage first gate driving unit 11.

[0072] And / or, in embodiments of the present invention, the length La of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is set to be less than the length Lc of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. That is, the length L1 of the first conductive channel 211 can be set to be less than the length L3 of the third conductive channel 231, such that along the length direction of the conductive channel, in the same space, the number of rows of the first contact holes 311 and the second contact holes 312 is greater than the number of rows of the fifth contact holes 331 and the sixth contact holes 332. The number of first via pairs formed by the adjacent first contact holes 311 and the second contact holes 312 of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the number of third via pairs formed by the adjacent fifth contact holes 331 and the sixth contact holes 332 of the output transistor 111 of the middle K-stage first gate driving unit 11. Furthermore, since the number of rows of the first contact hole 311 and the second contact hole 312 is greater than the number of rows of the fifth contact hole 331 and the sixth contact hole 332, the number of first conductive channels 211 between adjacent first contact holes 311 and second contact holes 312 is greater than the number of third conductive channels 231 between adjacent fifth contact holes 331 and sixth contact holes 332. Therefore, the width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the width Wc of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. In this embodiment of the invention, the length Lb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is set to be less than the length Lc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11. That is, the length L2 of the second conductive channel 221 can be set to be less than the length L3 of the third conductive channel 231. This makes it so that along the length direction of the conductive channel, in the same space, the number of rows of third contact holes 321 and fourth contact holes 322 is greater than the number of rows of fifth contact holes 331 and sixth contact holes 332. The number of second via pairs formed by adjacent third contact holes 321 and fourth contact holes 322 of the output transistor 111 of the last N-stage first gate driving unit 11 is greater than the number of third via pairs formed by adjacent fifth contact holes 331 and sixth contact holes 332 of the output transistor 111 of the intermediate K-stage first gate driving unit 11. Furthermore, since the number of rows of the third contact hole 321 and the fourth contact hole 322 is greater than the number of rows of the fifth contact hole 331 and the sixth contact hole 332, the number of second conductive channels 221 between adjacent third contact holes 321 and fourth contact holes 322 is greater than the number of third conductive channels 231 between adjacent fifth contact holes 331 and sixth contact holes 332. Therefore, the width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is greater than the width Wc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11.

[0073] Compared to the size of the output transistor 111 of the middle K-stage first gate driving unit 11, the sizes of the output transistors 111 of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11 are designed differently. Along the width direction of the conductive channel, the sizes of the output transistors 111 of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11 are twice the size of the output transistor 111 of the middle K-stage first gate driving unit 11. That is, the width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 and the width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 are twice the width Wc of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. The number of first via pairs is twice the number of third via pairs, and the number of second via pairs is twice the number of third via pairs.

[0074] And / or, provided that the process and performance of the output transistor 111 can be guaranteed, compared to the length Lc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11, the length La of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 and the length Lb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 are reduced. This allows for an increase in the number of first via pairs and second via pairs within the same space, and also increases the width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 and the width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11. The length La and width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11, and the length Lb and width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11, must meet the characteristic requirements of the switching transistor.

[0075] The technical solution of this invention involves setting the width of the conductive channel of the output transistor of the first M-stage first gate driving unit to be greater than the width of the conductive channel of the output transistor of the middle K-stage first gate driving unit, and the width of the conductive channel of the output transistor of the last N-stage first gate driving unit to be greater than the width of the conductive channel of the output transistor of the middle K-stage first gate driving unit. And / or, the length of the conductive channel of the output transistor of the first M-stage first gate driving unit is less than the length of the conductive channel of the output transistor of the middle K-stage first gate driving unit, and the length of the conductive channel of the output transistor of the last N-stage first gate driving unit is less than the length of the conductive channel of the output transistor of the middle K-stage first gate driving unit. This results in the number of first via pairs connecting the first source, first drain, and first active region of the output transistor of the first M-stage first gate driving unit being greater than the number of third via pairs connecting the third source, third drain, and third active region of the output transistor of the middle K-stage first gate driving unit, and the number of second via pairs connecting the second source, second drain, and second active region of the output transistor of the last N-stage first gate driving unit being greater than the number of second via pairs connecting the second source, second drain, and second active region of the output transistor of the last N-stage first gate driving unit. The increased number of via pairs connecting the third source, third drain, and third active region of the output transistors in the intermediate K-level first gate drive units ensures that even when the conductive channels between some first via pairs and some second via pairs in the output transistors of the first M-level and last N-level first gate drive units are damaged by electrostatic discharge, the output transistors of the first M-level and last N-level first gate drive units can still ensure that the output gate drive signal potential is raised to the required value per unit time. This maintains the thrust capability even when ESD damages part of the conductive channel, thereby improving the ESD resistance of the first M-level and last N-level first gate drive units. Each row of pixels can also receive normal gate drive signals, and the entire operation of the display panel remains unaffected.

[0076] Optionally, based on the above embodiments, refer to... Figures 4-10The output transistors 111 of the first gate driving unit 11 in the first M-stage include a first output transistor M9-1 and a second output transistor M10-1. The output transistors 111 of the last N-stage first gate driving unit 11 include a third output transistor M9-2 and a fourth output transistor M10-2. The output transistors 111 of the middle K-stage first gate driving unit 11 include a fifth output transistor M9-3 and a sixth output transistor M10-3. The widths of the conductive channels of the first output transistor M9-1, the second output transistor M10-1, the third output transistor M9-2, and the fourth output transistor M10-2 are all greater than the width of the conductive channel of the fifth output transistor M9-3. The widths of the conductive channels of the first output transistor M9-1, the second output transistor M10-1, the third output transistor M9-2, and the fourth output transistor M10-2 are all greater than the width of the conductive channel of the sixth output transistor M10-3. And / or, the lengths of the conductive channels of the first output transistor M9-1, the second output transistor M10-1, the third output transistor M9-2, and the fourth output transistor M10-2 are all less than the length of the conductive channel of the fifth output transistor M9-3. The lengths of the conductive channels of the first output transistor M9-1, the second output transistor M10-1, the third output transistor M9-2, and the fourth output transistor M10-2 are all less than the length of the conductive channel of the sixth output transistor M10-3.

[0077] Specifically, Figure 7 and Figure 8 The schematic diagram of the output transistor 111 of the first gate driving unit 11 of the first M stage or the output transistor 111 of the last N stage can be used as a schematic diagram of the first output transistor M9-1, the second output transistor M10-1, the third output transistor M9-2 and the fourth output transistor M10-2. Figure 9 and Figure 10 The schematic diagram of the output transistor 111 of the intermediate K-stage first gate drive unit 11 shown can be used as a schematic diagram of the fifth output transistor M9-3 and the sixth output transistor M10-3.

[0078] The first output transistor M9-1 and the second output transistor M10-1 serve as the output transistors 111 of the first M-stage first gate driving unit 11. The length and width of the conductive channels of the first output transistor M9-1 and the second output transistor M10-1 are the same as the length La and width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11. The third output transistor M9-2 and the fourth output transistor M10-2 serve as the output transistors 111 of the last N-stage first gate driving unit 11. The length and width of the conductive channels of the third output transistor M9-2 and the fourth output transistor M10-2 are the same as the length Lb and width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11. The fifth output transistor M9-3 and the sixth output transistor M10-3 serve as the output transistors 111 of the intermediate K-stage first gate driving unit 11. The length and width of the conductive channels of the fifth output transistor M9-3 and the sixth output transistor M10-3 are the length Lc and width Wc of the conductive channels of the output transistors 111 of the intermediate K-stage first gate driving unit 11.

[0079] Optionally, based on the above embodiments, Figure 11 This is a schematic diagram of another circuit structure of the first gate driving unit of the first M-stage provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another circuit structure of the last N-stage first gate driving unit provided in an embodiment of the present invention, as shown below. Figure 11 and Figure 12 As shown, the first gate driving unit 11 of the first M-stage further includes at least one seventh output transistor T7 and at least one eighth output transistor T8. The last N-stage first gate driving unit 11 further includes at least one ninth output transistor T9 and at least one tenth output transistor T10. At least one seventh output transistor T7 is connected in parallel with the first output transistor M9-1, and at least one eighth output transistor T8 is connected in parallel with the second output transistor M10-1. At least one ninth output transistor T9 is connected in parallel with the third output transistor M9-2, and at least one tenth output transistor T10 is connected in parallel with the fourth output transistor M10-2.

[0080] Specifically, the first output transistor M9-1 can be connected in parallel with one or more seventh output transistors T7, thereby effectively increasing the width of the conductive channel of the first output transistor M9-1. The second output transistor M10-1 can be connected in parallel with one or more eighth output transistors T8, thereby effectively increasing the width of the conductive channel of the second output transistor M10-1. This configuration can effectively increase the driving force of the output transistors of the first M-stage first gate drive unit 11. Even when part of the conductive channel of the output transistor of the first M-stage first gate drive unit 11 is damaged by ESD, the output transistor of the first M-stage first gate drive unit 11 can still ensure that the potential of the output gate drive signal is raised to the required value within a unit time, maintaining the driving force capability even when part of the conductive channel is damaged by ESD, thereby improving the ESD resistance of the first M-stage first gate drive unit 11.

[0081] The third output transistor M9-2 can be connected in parallel with one or more ninth output transistors T9, thereby effectively increasing the width of the conductive channel of the third output transistor M9-2. The fourth output transistor M10-2 can be connected in parallel with one or more tenth output transistors T10, thereby effectively increasing the width of the conductive channel of the fourth output transistor M10-2. This configuration can effectively increase the driving force of the output transistors of the last N-stage first gate drive unit 11. Even when part of the conductive channel of the output transistor of the last N-stage first gate drive unit 11 is damaged by ESD, the output transistor of the last N-stage first gate drive unit can still ensure that the potential of the output gate drive signal is raised to the required value within a unit time, maintaining the driving force capability even when part of the conductive channel is damaged by ESD, thereby improving the ESD resistance of the last N-stage first gate drive unit 11.

[0082] Optionally, based on the above embodiments, refer to... Figure 11 and Figure 12 The width and length of the conductive channel of the seventh output transistor T7 are equal to the width and length of the conductive channel of the first output transistor M9-1. The width and length of the conductive channel of the eighth output transistor T8 are equal to the width and length of the conductive channel of the second output transistor M10-1. The width and length of the conductive channel of the ninth output transistor T9 are equal to the width and length of the conductive channel of the third output transistor M9-2. The width and length of the conductive channel of the tenth output transistor T10 are equal to the width and length of the conductive channel of the fourth output transistor M10-2.

[0083] For details, please refer to Figures 7-11The length and width of the conductive channels of the seventh output transistor T7 and the eighth output transistor T8 can be equal to the length La and width Wa of the conductive channel of the output transistor 111 of the first gate driving unit 11 of the Mth stage, so that the length of the conductive channels of the seventh output transistor T7 and the eighth output transistor T8 can be less than the length Lc of the output transistor of the middle Kth stage first gate driving unit 11, and the width of the conductive channels of the seventh output transistor T7 and the eighth output transistor T8 can be greater than the width Wc of the output transistor of the middle Kth stage first gate driving unit 11.

[0084] Both the seventh output transistor T7 and the eighth output transistor T8 can include a fourth source, a fourth drain, and a fourth active region. The above configuration allows the number of fourth via pairs connecting the fourth source, the fourth drain, and the fourth active region to be greater than the number of third via pairs. Thus, when some conductive channels of the first output transistor M9-1, the second output transistor M10-1, the seventh output transistor T7, and the eighth output transistor T8 are damaged by coupled electrostatic discharge, the first gate drive unit 11 of the first M-stage can still ensure that the potential of the output gate drive signal is raised to the required value within a unit time, maintaining the thrust capability in the event of ESD damage to some conductive channels, thereby improving the ESD resistance of the first gate drive unit of the first M-stage.

[0085] The length and width of the conductive channels of the ninth output transistor T9 and the tenth output transistor T10 can be equal to the length Lb and width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11, so that the length of the conductive channels of the ninth output transistor T9 and the tenth output transistor T10 can be less than the length Lc of the output transistor of the intermediate K-stage first gate driving unit 11, and the width of the conductive channels of the ninth output transistor T9 and the tenth output transistor T10 can be greater than the width Wc of the output transistor of the intermediate K-stage first gate driving unit 11.

[0086] Both the ninth output transistor T9 and the tenth output transistor T10 can include a fifth source, a fifth drain, and a fifth active region. The above configuration allows the number of fifth via pairs connecting the fifth source, the fifth drain, and the fifth active region to be greater than the number of third via pairs. Thus, when some conductive channels of the third output transistor M9-2, the fourth output transistor M10-2, the ninth output transistor T9, and the tenth output transistor T10 are damaged by coupled electrostatic discharge, the last N-stage first gate drive unit 11 can still ensure that the potential of the output gate drive signal is raised to the required value within a unit time, maintaining the thrust capability even when ESD damages some conductive channels, thereby improving the ESD resistance of the last N-stage first gate drive unit.

[0087] Optionally, based on the above embodiments, Figure 13This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, such as... Figure 13 As shown, the gate driving circuit 20 further includes at least one second gate driving unit 12. At least one of the first gate driving units 11 in the first M-stage and the last N-stage first gate driving units 11 is correspondingly provided with a second gate driving unit 12, and the second gate driving unit 12 serves as a backup for the corresponding first gate driving unit 11.

[0088] Specifically, the first gate driving circuit 11 cascaded in the first M stages at the upper edge of the display panel can be correspondingly provided with a second gate driving circuit 12, and the first gate driving circuit 11 cascaded in the last N stages at the lower edge of the display panel can also be correspondingly provided with a second gate driving circuit 12. For example, as... Figure 13 As shown, the first gate driving circuit 11 of the first stage located at the upper edge of the display panel can be correspondingly provided with a second gate driving circuit 12, and the first gate driving circuit 11 of the last stage located at the lower edge of the display panel can be correspondingly provided with a second gate driving circuit 12, that is, M and N are both equal to 1. In some embodiments of the present invention, M and N can be integers greater than 1. For example, the first three stages of the first gate driving circuit 11 located at the upper edge of the display panel can be correspondingly provided with a second gate driving circuit 12, and the last three stages of the first gate driving circuit 11 located at the lower edge of the display panel can be correspondingly provided with a second gate driving circuit 12. In other embodiments of the present invention, the second gate driving circuit 12 can be correspondingly provided only in the last N cascaded first gate driving circuits 11 located at the lower edge of the display panel, in which case N can be equal to 1 or an integer greater than 1.

[0089] The gate drive signals output by the first gate drive circuit 11 and its corresponding second gate drive circuit 12 are the same, and both transmit the gate drive signals to the same gate line. The circuit structure and connection relationship of the second gate drive circuit 12, which corresponds to the first gate drive circuit 11, are identical to those of the first gate drive circuit 11. (Continue to refer to...) Figure 13 The connection relationship between the last stage's first gate drive circuit 11 and its corresponding second gate drive circuit 12 will be used as an example for explanation:

[0090] The final stage first gate driving circuit 11 is correspondingly provided with a second gate driving circuit 12. The final stage first gate driving circuit 11 is connected to the first clock signal line ECK1 and the second clock signal line ECK2, and is connected to the first level signal VGL and the second level signal VGH. The final stage first gate driving circuit 11 is also connected to the output terminal of the previous stage first gate driving circuit 11. The output of the previous stage first gate driving circuit 11 serves as the start signal of the final stage first gate driving circuit 11, and the output terminal of the final stage first gate driving circuit 11 is also connected to the previous stage first gate driving circuit 11. The output of the final stage first gate driving circuit 11 serves as the reset signal of the previous stage first gate driving circuit 11. Therefore, the second gate driving circuit 12, corresponding to the final stage first gate driving circuit 11, is also connected to the first clock signal line ECK1 and the second clock signal line ECK2, and is connected to the first level signal VGL and the second level signal VGH. It is also connected to the output terminal of the previous stage first gate driving circuit 11, and the output terminal of the second gate driving circuit 12, corresponding to the final stage first gate driving circuit 11, is also connected to the previous stage first gate driving circuit 11.

[0091] With this configuration, the first gate driving unit 11 and its corresponding second gate driving unit 12 can achieve parallel output. Even if one of the first gate driving unit 11 or its corresponding second gate driving unit 12 malfunctions, the other can function normally. Therefore, the potential of the gate driving signal output by the combined first gate driving unit 11 and its corresponding second gate driving unit 12 can remain normal, further enhancing the ESD resistance of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11.

[0092] The gate drive unit of the (virtual) dummy row can be used as the second gate drive unit 12 to improve the ESD resistance of the first gate drive unit 11 of the first M stage and the last gate drive unit 11 of the N stage.

[0093] Optionally, based on the above embodiments, this invention provides an array substrate, wherein, as... Figures 3-10As shown, the array substrate includes multiple cascaded first gate driving units 11. The array substrate includes a substrate 30, with the first gate driving units 11 located on one side of the substrate 30. The output transistors 111 of the first M-stage first gate driving units 11 include a first source / drain and a first active region 21; the output transistors 111 of the last N-stage first gate driving units 11 include a second source / drain and a second active region 22; and the output transistors 111 of the middle K-stage first gate driving units 11 include a third source / drain and a third active region 23. The number of first via pairs connecting the first source / drain and the first active region 21 is greater than the number of third via pairs connecting the third source / drain and the third active region 23, and the number of second via pairs connecting the second source / drain and the second active region 22 is greater than the number of third via pairs connecting the third source / drain and the third active region 23.

[0094] Specifically, the number of first via pairs connecting the first source 41 and first drain 51 of the output transistor 111 of the first M-stage first gate driving unit 11 to the first active region 21 is greater than the number of third via pairs connecting the third source 43 and third drain 53 of the output transistor 111 of the intermediate K-stage first gate driving unit 11 to the third active region 23. Similarly, the number of second via pairs connecting the second source 42 and second drain 52 of the output transistor 111 of the last N-stage first gate driving unit 11 to the second active region 22 is greater than the number of third via pairs connecting the third source 43 and third drain 53 of the output transistor 111 of the intermediate K-stage first gate driving unit 11 to the third active region 23. Therefore, even when the conductive channel between a portion of the first via pair and a portion of the second via pair of the output transistors 111 of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11 is damaged by electrostatic coupling, the output transistors 111 of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11 can still ensure that the potential of the output gate driving signal Eout is raised to the required value per unit time, maintaining the thrust capability even when the conductive channel is damaged by ESD, thereby improving the ESD resistance of the first M-stage first gate driving unit 11 and the last N-stage first gate driving unit 11. Each row of pixels can also receive the normal gate driving signal Eout, and the entire operation of the display panel will not be affected.

[0095] Optionally, based on the above embodiments, refer to... Figures 3-10 Along the width direction of the conductive channel of the output transistor, the width of the first active region 21 is greater than the width of the third active region 23, and the width of the second active region 22 is greater than the width of the third active region 23. And / or, the spacing between the first via pairs is less than the spacing between the third via pairs, and the spacing between the second via pairs is less than the spacing between the third via pairs.

[0096] Specifically, along the width direction of the conductive channel of the output transistor, the width of the first active region 21 is set to be greater than the width of the third active region 23, such that along the width direction of the conductive channel, the number of first via pairs formed by adjacent first contact holes 311 and second contact holes 312 of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the number of third via pairs formed by adjacent fifth contact holes 331 and sixth contact holes 332 of the output transistor 111 of the middle K-stage first gate driving unit 11. The width of the second active region 22 is set to be greater than the width of the third active region 23, such that along the width direction of the conductive channel, the number of second via pairs formed by adjacent third contact holes 321 and fourth contact holes 322 of the output transistor 111 of the last N-stage first gate driving unit 11 is greater than the number of third via pairs formed by adjacent fifth contact holes 331 and sixth contact holes 332 of the output transistor 111 of the middle K-stage first gate driving unit 11.

[0097] And / or, the spacing of the first via pair is set to be less than the spacing of the third via pair, such that along the length direction of the conductive channel, in the same space, the number of rows of the first contact hole 311 and the second contact hole 312 is greater than the number of rows of the fifth contact hole 331 and the sixth contact hole 332, and the number of first via pairs formed by the adjacent first contact holes 311 and the second contact holes 312 of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the number of third via pairs formed by the adjacent fifth contact holes 331 and the sixth contact holes 332 of the output transistor 111 of the middle K-stage first gate driving unit 11. Furthermore, since the number of rows of the first contact hole 311 and the second contact hole 312 is greater than the number of rows of the fifth contact hole 331 and the sixth contact hole 332, the number of first conductive channels 211 between adjacent first contact holes 311 and second contact holes 312 is greater than the number of third conductive channels 231 between adjacent fifth contact holes 331 and sixth contact holes 332. Therefore, the width Wa of the conductive channel of the output transistor 111 of the first M-stage first gate driving unit 11 is greater than the width Wb of the conductive channel of the output transistor 111 of the middle K-stage first gate driving unit 11. The spacing of the second via pair is set to be smaller than that of the third via pair, such that, along the length of the conductive channel, in the same space, the number of rows of the third contact hole 321 and the fourth contact hole 322 is greater than the number of rows of the fifth contact hole 331 and the sixth contact hole 332. Finally, the number of second via pairs formed by the adjacent third contact hole 321 and the fourth contact hole 322 of the output transistor 111 of the N-stage first gate driving unit 11 is greater than the number of third via pairs formed by the adjacent fifth contact hole 331 and the sixth contact hole 332 of the output transistor 111 of the intermediate K-stage first gate driving unit 11. Furthermore, since the number of rows of the third contact hole 321 and the fourth contact hole 322 is greater than the number of rows of the fifth contact hole 331 and the sixth contact hole 332, the number of second conductive channels 221 between adjacent third contact holes 321 and fourth contact holes 322 is greater than the number of third conductive channels 231 between adjacent fifth contact holes 331 and sixth contact holes 332. Therefore, the width Wb of the conductive channel of the output transistor 111 of the last N-stage first gate driving unit 11 is greater than the width Wc of the conductive channel of the output transistor 111 of the intermediate K-stage first gate driving unit 11.

[0098] Optionally, based on the above embodiments, refer to... Figures 3-12The first output transistor M9-1 includes a first source / drain and a first active region 21; the second output transistor M10-1 includes a first source / drain and a first active region 22; the third output transistor M9-2 includes a second source / drain and a second active region 22; the fourth output transistor M10-2 includes a second source / drain and a second active region 22; the fifth output transistor M9-3 includes a third source / drain and a third active region 23; the sixth output transistor M10-3 includes a third source / drain and a third active region 23. The seventh output transistor T7 includes a fourth source / drain and a fourth active region; the eighth output transistor T8 includes a fourth source / drain and a fourth active region; the ninth output transistor T9 includes a fifth source / drain and a fifth active region; and the tenth output transistor T10 includes a fifth source / drain and a fifth active region. The number of fourth via pairs connecting the fourth source / drain and the fourth active region is the same as the number of first via pairs, and the number of fifth via pairs connecting the fifth source / drain and the fifth active region is the same as the number of second via pairs.

[0099] Specifically, the number of fourth via pairs connecting the fourth source, fourth drain, and fourth active region is greater than the number of third via pairs. This ensures that when some conductive channels of the first output transistor M9-1, second output transistor M10-1, seventh output transistor T7, and eighth output transistor T8 are damaged by coupled electrostatic discharge, the first gate drive unit 11 of the first M-stage can still ensure that the potential of the output gate drive signal is raised to the required value within a unit time. This maintains the thrust capability even when some conductive channels are damaged by ESD, thereby improving the ESD resistance of the first gate drive unit of the first M-stage.

[0100] The number of fifth via pairs connecting the fifth source, fifth drain, and fifth active region is greater than the number of third via pairs. Therefore, when some conductive channels of the third output transistor M9-2, fourth output transistor M10-2, ninth output transistor T9, and tenth output transistor T10 are damaged by coupled electrostatic discharge, the last N-stage first gate drive unit 11 can still ensure that the potential of the output gate drive signal is raised to the required value per unit time, maintaining the thrust capability in the event of ESD damage to some conductive channels, thereby improving the ESD resistance of the last N-stage first gate drive unit.

[0101] Optionally, based on the above embodiments, refer to... Figures 3-12 Along the width direction of the conductive channel of the output transistor, the width of the fourth active region is equal to the width of the first active region 21, and the width of the fifth active region is equal to the width of the second active region 22. And / or, the spacing between the fourth via pairs is equal to the spacing between the first via pairs, and the spacing between the fifth via pairs is equal to the spacing between the second via pairs.

[0102] Specifically, along the width direction of the conductive channel of the output transistor, the width of the fourth active region is equal to the width of the first active region 21, such that the number of fourth via pairs is the same as the number of first via pairs along the width direction of the conductive channel, meaning the number of fourth via pairs is greater than the number of third via pairs. Similarly, the width of the fifth active region is equal to the width of the second active region 22, such that the number of fifth via pairs is the same as the number of second via pairs along the width direction of the conductive channel, meaning the number of fifth via pairs is greater than the number of third via pairs.

[0103] And / or, the spacing of the fourth via pair is set to be equal to the spacing of the first via pair, such that the number of fourth via pairs is the same as the number of first via pairs along the length of the conductive channel, i.e., the number of fourth via pairs is greater than the number of third via pairs. The spacing of the fifth via pair is set to be equal to the spacing of the second via pair, such that the number of fifth via pairs is the same as the number of second via pairs along the length of the conductive channel, i.e., the number of fifth via pairs is greater than the number of third via pairs.

[0104] The technical solution of this invention, compared with the middle K-level first gate driving unit, differentiates the design of the first M-level first gate driving unit and the last N-level first gate driving unit, where M can be equal to 1 and N can also be equal to 1, so that the increased design space is not large, the layout design changes are not large, and it is easy to control the circuit layout area of ​​the left and right edges of the screen, achieving the effect while maintaining the narrow bezel design.

[0105] This invention provides a display panel, wherein the display panel includes an array substrate provided in any of the above embodiments of this invention, and has the beneficial effects of the array substrate provided in any of the above embodiments of this invention.

[0106] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0107] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: Multiple cascaded first gate drive units; The first gate driving unit is used to output a gate driving signal. The multiple cascaded first gate driving units include the first M-stage first gate driving unit, the last N-stage first gate driving unit, and the middle K-stage first gate driving unit. The first gate driving unit includes an output transistor connected to the output terminal. Wherein, M is an integer greater than or equal to 1, N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1. The width of the conductive channel of the output transistor of the first gate driving unit of the first Mth stage is greater than the width of the conductive channel of the output transistor of the first gate driving unit of the middle Kth stage, and the width of the conductive channel of the output transistor of the last Nth stage is greater than the width of the conductive channel of the output transistor of the middle Kth stage; and / or, the length of the conductive channel of the output transistor of the first gate driving unit of the first Mth stage is less than the length of the conductive channel of the output transistor of the middle Kth stage, and the length of the conductive channel of the output transistor of the last Nth stage is less than the length of the conductive channel of the output transistor of the middle Kth stage.

2. The gate driving circuit according to claim 1, characterized in that, The output transistors of the first gate driving unit in the M-stage include a first output transistor and a second output transistor; the output transistors of the last N-stage first gate driving unit include a third output transistor and a fourth output transistor; the output transistors of the middle K-stage first gate driving unit include a fifth output transistor and a sixth output transistor. The widths of the conductive channels of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor are all greater than the width of the conductive channel of the fifth output transistor; the widths of the conductive channels of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor are all greater than the width of the conductive channel of the sixth output transistor. And / or, the lengths of the conductive channels of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor are all less than the length of the conductive channel of the fifth output transistor; and the lengths of the conductive channels of the first output transistor, the second output transistor, the third output transistor, and the fourth output transistor are all less than the length of the conductive channel of the sixth output transistor.

3. The gate driving circuit according to claim 2, characterized in that, The first gate drive unit of the M-stage also includes at least one seventh output transistor and at least one eighth output transistor; the last first gate drive unit of the N-stage also includes at least one ninth output transistor and at least one tenth output transistor. At least one of the seventh output transistors is connected in parallel with the first output transistor, at least one of the eighth output transistors is connected in parallel with the second output transistor; at least one of the ninth output transistors is connected in parallel with the third output transistor, and at least one of the tenth output transistors is connected in parallel with the fourth output transistor.

4. The gate driving circuit according to claim 3, characterized in that, The width and length of the conductive channel of the seventh output transistor are equal to the width and length of the conductive channel of the first output transistor, and the width and length of the conductive channel of the eighth output transistor are equal to the width and length of the conductive channel of the second output transistor. The width and length of the conductive channel of the ninth output transistor are equal to the width and length of the conductive channel of the third output transistor, and the width and length of the conductive channel of the tenth output transistor are equal to the width and length of the conductive channel of the fourth output transistor.

5. The gate driving circuit according to claim 1, characterized in that, Also includes: At least one second gate driving unit; At least one of the first gate driving units in the first M-stage and the last N-stage is provided with a second gate driving unit, which serves as a backup for the corresponding first gate driving unit.

6. An array substrate, characterized in that, The array substrate includes multiple cascaded first gate driving units; the multiple cascaded first gate driving units include a first gate driving unit of the first M stage, a last gate driving unit of the N stage, and a middle gate driving unit of the K stage; the first gate driving unit includes an output transistor connected to the output terminal; wherein, M is an integer greater than or equal to 1, N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1. The array substrate includes: A substrate, wherein the first gate driving unit is located on one side of the substrate; The output transistor of the first gate driving unit of the first M-stage includes a first source / drain and a first active region; the output transistor of the last N-stage first gate driving unit includes a second source / drain and a second active region; and the output transistor of the middle K-stage first gate driving unit includes a third source / drain and a third active region. The number of first via pairs connecting the first source / drain and the first active region is greater than the number of third via pairs connecting the third source / drain and the third active region, and the number of second via pairs connecting the second source / drain and the second active region is greater than the number of third via pairs connecting the third source / drain and the third active region.

7. The array substrate according to claim 6, characterized in that, Along the width direction of the conductive channel of the output transistor, the width of the first active region is greater than the width of the third active region, and the width of the second active region is greater than the width of the third active region. And / or, the spacing between the first via pair is less than the spacing between the third via pair, and the spacing between the second via pair is less than the spacing between the third via pair.

8. The array substrate according to claim 6, characterized in that, The output transistors of the first gate driving unit in the first M-stage include a first output transistor and a second output transistor; the output transistors of the last N-stage first gate driving unit include a third output transistor and a fourth output transistor; the output transistors of the middle K-stage first gate driving unit include a fifth output transistor and a sixth output transistor; the first M-stage first gate driving unit also includes at least one seventh output transistor connected in parallel with the first output transistor and at least one eighth output transistor connected in parallel with the second output transistor; the last N-stage first gate driving unit also includes at least one ninth output transistor connected in parallel with the third output transistor and at least one tenth output transistor connected in parallel with the fourth output transistor. The first output transistor includes a first source / drain and a first active region; the second output transistor includes a first source / drain and a first active region; the third output transistor includes a second source / drain and a second active region; the fourth output transistor includes a second source / drain and a second active region; the fifth output transistor includes a third source / drain and a third active region; and the sixth output transistor includes a third source / drain and a third active region. The seventh output transistor includes a fourth source / drain and a fourth active region; the eighth output transistor includes a fourth source / drain and a fourth active region; the ninth output transistor includes a fifth source / drain and a fifth active region; and the tenth output transistor includes a fifth source / drain and a fifth active region. The number of fourth via pairs connecting the fourth source / drain and the fourth active region is the same as the number of first via pairs, and the number of fifth via pairs connecting the fifth source / drain and the fifth active region is the same as the number of second via pairs.

9. The array substrate according to claim 8, characterized in that, Along the width direction of the conductive channel of the output transistor, the width of the fourth active region is equal to the width of the first active region, and the width of the fifth active region is equal to the width of the second active region; And / or, the spacing of the fourth via pair is equal to the spacing of the first via pair, and the spacing of the fifth via pair is equal to the spacing of the second via pair.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 6-9.

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