Gate driving circuit, display panel and display device

Abstract

The application discloses a gate driving circuit, a display panel and a display device. The stage transmission circuit is used for controlling the signals of the first node and the second node to be in phase. The partition circuit is used for controlling one of the first node and the first power supply end and the third node to form a current path according to the signal of the second node and a partition control signal. The output circuit is used for controlling one of the second power supply end and the third power supply end and the signal output end to form a current path according to the signal of the third node. In the period in which the partition circuit controls the first power supply end and the third node to form a current path, the output circuit is used for connecting the current path between the third power supply end and the signal output end according to the signal of the third node, so that the time length in which the signal output end receives the third power supply signal supplied by the third power supply end is controllable, and then the time length in which the level of the light-emitting control signal under the action of the third power supply signal is controllable, which can be used for supporting the display panel to realize the peep-proof control of different regions.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] In display panels, privacy protection can be selectively controlled by adjusting whether the light-emitting devices used for privacy protection participate in or not. However, how to ensure that the gate driving circuit provides the required control signals for privacy protection in different areas of the display panel remains a hot research topic. Summary of the Invention

[0003] This application provides a gate driving circuit, a display panel, and a display device for supporting privacy control of different areas of the display panel.

[0004] This application provides a gate driving circuit, including a cascading circuit, a partitioning circuit, and an output circuit. The cascading circuit is electrically connected to a first node and a second node, and is configured to control the signal of the first node to be in phase with the signal of the second node according to a start signal and a clock signal. The partitioning circuit is electrically connected to the first node, the second node, and a third node, and is configured to control one of the first node and a first power supply terminal to form a current path with the third node according to the signal of the second node and a partitioning control signal. The output circuit is electrically connected to the third node, and is configured to control one of the second power supply terminal and a third power supply terminal to form a current path with the signal output terminal of the gate driving circuit according to the signal of the third node. When the partitioning circuit is configured to control the formation of a current path between the first power supply terminal and the third node, the output circuit is configured to control the formation of a current path between the third power supply terminal and the signal output terminal according to the signal of the third node.

[0005] This application also provides a display panel including a plurality of gate driving circuits as described above, the plurality of gate driving circuits being cascaded, and the signal output terminal of each gate driving circuit being used to output a light emission control signal. A plurality of sub-pixels are electrically connected to the plurality of gate driving circuits, and each sub-pixel includes a pixel driving circuit and a first light-emitting device. The pixel driving circuit is configured to control the on / off state of the flow path of the driving current supplied to the first light-emitting device according to the light emission control signal output by the corresponding gate driving circuit.

[0006] This application also provides a display device, including any of the above-described display panels and a timing controller, the timing controller being electrically connected to a plurality of gate driving circuits, and the timing controller being configured to output partition control signals to the plurality of gate driving circuits.

[0007] The above technical solution includes a gate driving circuit comprising a cascading circuit, a partitioning circuit, and an output circuit. The cascading circuit controls the signals of the first node and the second node to be in phase. The partitioning circuit controls the formation of a current path between the first node and one of the first power supply terminals and the third node based on the signals of the second node and the partitioning control signal. This allows the output circuit to control the formation of a current path between one of the second power supply terminals and the third power supply terminal and the signal output terminal of the gate driving circuit based on the signals of the third node, thereby controlling the light-emitting control signal output from the signal output terminal of the gate driving circuit. By controlling the period during which the partitioning circuit controls the formation of the current path between the first power supply terminal and the third node, and by connecting the current path between the third power supply terminal and the signal output terminal based on the signals of the third node, the duration for which the signal output terminal receives the third power supply signal supplied by the third power supply terminal is controlled by the partitioning circuit. This makes the duration of the light-emitting control signal's level under the influence of the third power supply signal controllable, enabling the gate driving circuit to support privacy control in different areas of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0009] Figures 1A-1C This is a schematic block diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure; Figures 2A-2B This is a circuit diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure; Figures 3A-3B This is a timing diagram corresponding to the gate drive circuit of an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of the gate driver according to an exemplary embodiment of the present disclosure; Figures 5A-5D This is a timing diagram corresponding to the gate driver of an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment of this disclosure; Figure 7 This is a schematic block diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure; Figure 8 This is a circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure; Figures 9A-9B This is a timing diagram corresponding to the pixel driving circuit of an exemplary embodiment of this disclosure; Figure 10 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure.

[0010] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0012] It should be noted that the electrical connection referred to in this application can refer to a direct connection or an indirect connection. An indirect connection can be a connection between connected sub-circuits, devices, or nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals. A node referred to in this application can be a junction point for device connections. The names of the circuits involved in the embodiments of this application are for descriptive purposes only and should not be construed as limiting the scope of application or use of each circuit. The descriptions of "first," "second," etc., involved in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" can explicitly or implicitly include at least one of those features. Furthermore, the various technical features in this application can be applied to achieve different combinations, and are not limited to the technical solutions formed by the combinations listed in the embodiments. The technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they lead to can be selectively configured.

[0013] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0014] like Figures 1A-1CThis is a schematic block diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure. This application provides a gate driving circuit GA, including a cascading circuit 10, a partitioning circuit 20, and an output circuit 30.

[0015] The cascade circuit 10 is electrically connected to the first node No1 and the second node No2. The cascade circuit 10 is configured to control the signal of the first node No1 to be in phase with the signal of the second node No2 according to the start signal STV and the clock signal XCK.

[0016] The partitioning circuit 20 is electrically connected to the first node No1, the second node No2 and the third node No3. The partitioning circuit 20 is configured to control one of the first node No1 and the first power supply terminal VA to form a current path with the third node No3 according to the signal of the second node No2 and the partitioning control signal SEN.

[0017] The output circuit 30 is electrically connected to the third node No3. The output circuit 30 is configured to control one of the second power supply terminal VB and the third power supply terminal VC to form a current path with the signal output terminal EOT of the gate drive circuit GA according to the signal of the third node No3.

[0018] When the partition circuit 20 is configured to control the formation of a current path between the first power supply terminal VA and the third node No3, the output circuit 30 is configured to control the formation of a current path between the third power supply terminal VC and the signal output terminal EOT according to the signal of the third node No3. This allows the duration of the third power signal supplied by the third power supply terminal VC to be received by the signal output terminal EOT to be controlled by the partition circuit 20. Consequently, the duration of the light emission control signal EM under the action of the third power signal becomes controllable, thereby enabling the gate drive circuit GA to be used to support the display panel to achieve privacy control in different areas.

[0019] Furthermore, in this application, the cascade circuit 10 controls the signals of the first node No1 and the second node No2 to be in phase, and the partitioning circuit 20 controls one of the first node No1 and the first power supply terminal VA to form a current path with the third node No3 according to the signal of the second node No2 and the partitioning control signal SEN. This can reduce the load corresponding to the first node No1, which is beneficial to improving the working stability of the output circuit 30, thereby improving the output stability of the gate drive circuit GA.

[0020] Optionally, the partition control signal SEN may have a transition between a first level and a second level, so that the partition circuit 20 can switch the signal transmission between the third node No3 and the first node No1 and the first power supply terminal VA according to the first level and the second level of the partition control signal SEN. The first level is either a high level or a low level, and the second level is either a high level or a low level.

[0021] In some embodiments, the partitioning circuit 20 connects the current path between the first power supply terminal VA and the third node No3 according to the signal of the second node No2 and the second level of the partitioning control signal SEN, and the partitioning circuit 20 connects the current path between the first node No1 and the third node No3 according to the signal of the second node No2 and the first level of the partitioning control signal SEN.

[0022] Optionally, the first power supply terminal VA to the third power supply terminal VC can each be a voltage terminal. The first power supply terminal VA is used to provide a first power signal, the second power supply terminal VB is used to provide a second power signal, and the third power supply terminal VC is used to provide a third power signal. The voltage of at least one of the second power signal and the third power signal is different from the voltage of the first power signal.

[0023] Optionally, the first power supply terminal VA can be multiplexed as the second power supply terminal VB or the third power supply terminal VC to reduce the number of power signals used in the gate drive circuit GA, thereby reducing the power consumption of the gate drive circuit GA.

[0024] In some embodiments, the voltage of the first power signal may be different from the voltage of the second power signal. That is, the voltage of the first power signal may be greater than or less than the voltage of the second power signal; while the voltage of the first power signal is the same as the voltage of the third power signal. In other embodiments, the voltage of the first power signal may be different from the voltage of the third power signal, while the voltage of the first power signal is the same as the voltage of the second power signal.

[0025] In some embodiments, when the signal output terminal EOT receives a third power supply signal, the light emission control signal EM has a third level. When the signal output terminal EOT receives a second power supply signal, the light emission control signal EM has a fourth level. The third level is either a high level or a low level, and the fourth level is either a high level or a low level.

[0026] In some embodiments, the voltage value of the third power supply signal is greater than the voltage value of the second power supply signal. The third level of the light emission control signal EM is high, and the fourth level of the light emission control signal EM is low.

[0027] Optionally, the partitioning circuit 20 may include a partitioning control sub-circuit 201 and a partitioning selection sub-circuit 202. The partitioning control sub-circuit 201 is electrically connected to the second node No2 and the fourth node No4, and is configured to control the signal of the fourth node No4 based on the signal of the second node No2 and the partitioning control signal SEN. The partitioning selection sub-circuit 202 is electrically connected to the fourth node No4, and is configured to control one of the first node No1 and the first power supply terminal VA to form a current path with the third node No3 based on the signal of the fourth node No4. This allows the third node No3 to receive the first power supply signal under the control of the signal of the fourth node No4, or to form a current path between the third node No3 and the first node No1 under the control of the signal of the fourth node No4, thereby controlling the signal received by the third node No3. Furthermore, since the partitioning selection sub-circuit 202 can control the signal received by the third node No3 based solely on the signal of the fourth node No4, the design complexity of the partitioning selection sub-circuit 202 can be simplified.

[0028] In some embodiments, when the partition control subcircuit is configured to control the signal of the fourth node to a second level based on the signal of the second node and the first level of the partition control signal, the partition selection subcircuit is configured to connect a current path between the first node and the third node based on the signal of the fourth node. When the partition control subcircuit is configured to control the signal of the fourth node to a first level based on the signal of the second node and the second level of the partition control signal, the partition selection subcircuit is configured to connect a current path between the first power supply terminal and the third node based on the signal of the fourth node, so as to control the formation of a current path between the third node and the first power supply terminal or the first node when the fourth node corresponds to a different level state.

[0029] Optionally, the partition control subcircuit 201 may include a node control subcircuit 2011. The node control subcircuit 2011 is electrically connected to the second node No2 and to the fourth node No4 via the fifth node No5. The node control subcircuit 2011 is configured to control the signal transmission between the partition control line transmitting the partition control signal SEN and the fifth node No5 based on the signal from the second node No2. The partition control subcircuit 201 can control the signal from the fourth node No4 by controlling the signal from the fifth node No5.

[0030] Because the node control sub-circuit 2011 controls the signal transmission between the partition control line and the fifth node No5 according to the signal of the second node No2, when the node control sub-circuit 2011 disconnects the current path between the partition control line and the fifth node No5, the signal of the fifth node No5 will not change due to the level change of the partition control signal SEN. This is beneficial to maintaining the output state of the gate drive circuit GA, so that the level of the light emission control signal EM remains at the third or fourth level for a longer period of time.

[0031] Optionally, during the period when the node control subcircuit 2011 connects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, the output circuit 30 is configured to control the formation of a current path between the third power supply terminal VC and the signal output terminal EOT according to the signal of the third node No3, so that the signal output terminal EOT receives the third power supply signal during the period when the current path is formed between the partition control line and the fifth node No5, so that the light emission control signal EM output by the signal output terminal EOT has a third level. During the period when the node control subcircuit 2011 disconnects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, and the partition selection subcircuit 202 is configured to control the formation of a current path between the first node No1 and the third node No3, the output circuit 30 is configured to control the formation of a current path between the second power supply terminal VB and the signal output terminal EOT according to the signal of the third node No3, so that the light emission control signal EM output by the signal output terminal EOT has a fourth level.

[0032] In some embodiments, during the period when the node control subcircuit 2011 connects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, the partition selection subcircuit 202 controls the formation of a current path between the first node No1 and the third node No3, or the partition selection subcircuit 202 controls the formation of a current path between the first power supply terminal VA and the third node No3, so that during the period when the current path is formed between the partition control line and the fifth node No5, the third node No3 changes to a state that allows the signal output terminal EOT to receive the third power supply signal under the influence of either the first power supply signal or the signal of the first node No1, so that the light emission control signal EM has a third level. Conversely, during the period when the node control subcircuit 2011 disconnects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, when the partition selection subcircuit 202 controls the formation of a current path between the first node No1 and the third node No3 according to the signal of the fourth node No4, the signal output terminal EOT receives the second power supply signal supplied by the second power supply terminal VB, so that the light emission control signal EM has a fourth level under the influence of the signal of the first node No1. During the period when the node control sub-circuit 2011 disconnects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, when the partition selection sub-circuit 202 controls the formation of a current path between the first power supply terminal VA and the third node No3 according to the signal of the fourth node No4, the signal output terminal EOT receives the third power supply signal supplied by the third power supply terminal VC, so that the light emission control signal EM has a third level under the influence of the third power supply signal. Specifically, the partition selection sub-circuit 202 controls the formation of a current path between the third node No3 and the first node No1 or the first power supply terminal VA according to the signal of the fourth node No4.

[0033] Optionally, to control the signal of the fourth node No4 based on the signal of the second node No2 and the partition control signal SEN, the partition control sub-circuit 201 may include a first inverting sub-circuit 2012. The first inverting sub-circuit 2012 is electrically connected between the fourth node No4 and the fifth node No5, and is configured to control the signal of the fourth node No4 to be inverted with the signal of the fifth node No5.

[0034] Optionally, in order to ensure that the partition selection sub-circuit 202 maintains a stable operating state based on the signal of the fourth node No4 during the period when the current path between the partition control line and the fifth node No5 is disconnected, the partition control sub-circuit 201 may also include a storage sub-circuit 2013. The storage sub-circuit 2013 is electrically connected to the fifth node No5 and is configured to maintain the potential of the fifth node No5, thereby causing the first inverting sub-circuit 2012 to maintain the potential of the fourth node No4 under the influence of the potential of the fifth node No5.

[0035] Optionally, in order to control the signal transmission between the first power supply terminal VA and the third node No3, the partition selection sub-circuit 202 may include a first selection sub-circuit 2021, which is electrically connected between the first power supply terminal VA and the third node No3. The first selection sub-circuit 2021 is configured to control the signal transmission between the first power supply terminal VA and the third node No3 according to the signal of the fourth node No4.

[0036] Optionally, in order to control the signal transmission between the first node No1 and the third node No3, the partition selection sub-circuit 202 may include a second selection sub-circuit 2022, which is electrically connected between the first node No1 and the third node No3. The second selection sub-circuit 2022 is configured to control the signal transmission between the first node No1 and the third node No3 according to the signal of the fourth node No4.

[0037] By including a first selection sub-circuit 2021 and a second selection sub-circuit 2022 in the partition selection sub-circuit 202, the signal transmission control between the third node No3 and the first power supply terminal VA and the first node No1 can be made independent, which helps to reduce the control complexity of the received signal of the third node No3.

[0038] In some embodiments, when the first selection sub-circuit 2021 is configured to connect the current path between the first power supply terminal VA and the third node No3 according to the signal of the fourth node No4, the second selection sub-circuit 2022 is configured to disconnect the current path between the first node No1 and the third node No3 according to the signal of the fourth node No4. When the second selection sub-circuit 2022 is configured to connect the current path between the first node No1 and the third node No3 according to the signal of the fourth node No4, the first selection sub-circuit 2021 is configured to disconnect the current path between the first power supply terminal VA and the third node No3 according to the signal of the fourth node No4. By ensuring that the time period for forming a current path between the first node No1 and the third node No3 does not overlap with the time period for forming a current path between the first power supply terminal VA and the third node No3, the probability of the third node No3 being simultaneously affected by the first power supply signal and the signal of the first node No1 is reduced, which is beneficial to improving the working stability of the gate drive circuit GA.

[0039] Optionally, to reduce signal transmission loss between the first node No1 and the third node No3, and further improve the operational reliability of the gate drive circuit GA, the second selection sub-circuit 2022 may include a second inverting sub-circuit 2022a and a transmission gate circuit 2022b. The second inverting sub-circuit 2022a is electrically connected between the fourth node No4 and the sixth node No6, and is configured to control the signal of the sixth node No6 to be inverted compared to the signal of the fourth node No4. The transmission gate circuit 2022b is electrically connected between the first node No1 and the third node No3, and is configured to control the signal transmission between the first node No1 and the third node No3 based on the signals of the fourth node No4 and the sixth node No6.

[0040] In some embodiments, during the period when the first selection sub-circuit 2021 is configured to disconnect the current path between the first power supply terminal VA and the third node No3 according to the signal of the fourth node No4, the transmission gate sub-circuit 2022b is configured to connect the current path between the first node No1 and the third node No3 according to the signals of the fourth node No4 and the sixth node No6. During the period when the first selection sub-circuit 2021 is configured to connect the current path between the first power supply terminal VA and the third node No3 according to the signal of the fourth node No4, the transmission gate sub-circuit 2022b is configured to disconnect the current path between the first node No1 and the third node No3 according to the signals of the fourth node No4 and the sixth node No6, so as to reduce the signal transmission loss between the first node No1 and the third node No3, thereby making the potential change of the third node No3 more consistent with expectations, and thus enabling the output circuit 30 of the gate drive circuit GA to have a stable operating state according to the signal of the third node No3.

[0041] Optionally, to control the signals of the first node No1 and the second node No2, the cascade circuit 10 may include a first sub-circuit 101 and a second sub-circuit 102. The first sub-circuit 101 is electrically connected to the first node No1 via the seventh node No7, and is configured to control the signals of the seventh node No7 and the first node No1 according to the start signal STV and the clock signal XCK. The second sub-circuit 102 is electrically connected to the second node No2 and the seventh node No7, and is configured to control the signal of the second node No2 to be in phase with the signal of the first node No1 according to the signal of the seventh node No7.

[0042] In some embodiments, the second node No2 and the eighth node No8 are the same node. The first sub-circuit 101 may include a startup control sub-circuit 1011 and a third inverting sub-circuit 1012. The startup control sub-circuit 1011 is electrically connected to the seventh node No7 and is configured to control the signal transmission between the seventh node No7 and the first power supply terminal VA and the fourth power supply terminal VD according to the startup signal STV and the clock signal XCK. The third inverting sub-circuit 1012 is electrically connected between the seventh node No7 and the first node No1 and is configured to control the signal of the first node No1 to be inverted with the signal of the seventh node No7, so that the signal of the first node No1 is in phase with the signal of the second node No2.

[0043] In other embodiments, the first node No1 and the seventh node No7 are the same node. The first sub-circuit 101 is configured to control the signal transmission between the start signal line of the transmission start signal STV and the seventh node No7 according to the clock signal XCK. The second sub-circuit 102 includes a fourth inverting sub-circuit 1021 and a fifth inverting sub-circuit 1022. The fourth inverting sub-circuit 1021 is electrically connected between the seventh node No7 and the eighth node No8, and is configured to control the signal of the eighth node No8 to be inverted with the signal of the seventh node No7. The fifth inverting sub-circuit 1022 is electrically connected between the second node No2 and the eighth node No8, and is configured to control the signal of the second node No2 to be inverted with the signal of the eighth node No8, thereby making the signal of the second node No2 in phase with the signal of the seventh node No7.

[0044] Optionally, the second sub-circuit 102 is configured to control the signal transmission between the second node No2 and the first power supply terminal VA and the fourth power supply terminal VD according to the signal of the seventh node No7, so that the second sub-circuit 102 controls the second node No2 to receive the first power supply signal or the fourth power supply signal supplied by the fourth power supply terminal VD according to the signal of the seventh node No7, so that the signal of the second node No2 is in phase with the signal of the first node No1. The voltage of the fourth power supply signal is different from the voltage of the first power supply signal.

[0045] In some embodiments, during the period when the second sub-circuit 102 is configured to connect the current path between the first power supply terminal VA and the second node No2, the node control sub-circuit 2011 is configured to connect the current path between the partition control line and the fifth node No5; during the period when the second sub-circuit 102 is configured to connect the current path between the fourth power supply terminal VD and the second node No2, the node control sub-circuit 2011 is configured to disconnect the current path between the partition control line and the fifth node No5, so as to realize signal transmission control between the partition control line and the fifth node No5 by utilizing the cooperation of the signals of the node control sub-circuit 2011 and the second node No2.

[0046] Optionally, since the first sub-circuit 101 controls the signal of the seventh node No7 according to the start signal STV and the clock signal XCK, and the clock signal XCK is a periodic signal, the first sub-circuit 101 will cause the seventh node No7 to periodically receive the corresponding signal due to the influence of the level change of the clock signal XCK. During the period when the first sub-circuit 101 controls the seventh node No7 not to receive the corresponding signal, in order to maintain the potential of the seventh node No7, the cascade circuit 10 may also include a third sub-circuit 103. The third sub-circuit 103 and the second sub-circuit 102 are electrically connected to the eighth node No8, and the third sub-circuit 103 is electrically connected to the seventh node No7. The third sub-circuit 103 is configured to control the signal transmission between the fourth power supply terminal VD and the seventh node No7 according to the signal of the eighth node No8, and is configured to control the signal transmission between the first power supply terminal VA and the seventh node No7 according to the signal of the eighth node No8 and the clock signal XCK. During the period when the first sub-circuit 101 controls the seventh node No7 not to receive the corresponding signal, the third sub-circuit 103 controls the seventh node No7 to receive the first power signal or the fourth power signal, so as to maintain the potential of the seventh node No7 by using the third sub-circuit 103 in conjunction with the first power signal or the fourth power signal, thereby maintaining the potential of the first node No1 and the second node No2.

[0047] In some embodiments, the second node No2 and the eighth node No8 are the same node. During the period when the start control subcircuit 1011 controls the current path between the seventh node No7 and the first power supply terminal VA and the second power supply terminal VB to be disconnected, the third subcircuit 103 is used to connect the current path between the first node No1 and the first power supply terminal VA or the fourth power supply terminal VD. During the period when the start control subcircuit 1011 controls the current path between the seventh node No7 and the first power supply terminal VA and the fourth power supply terminal VD to be disconnected, the third subcircuit 103 is used in conjunction with the first power supply signal or the fourth power supply signal to maintain the potential of the seventh node No7. Then, during the period when the start control subcircuit 1011 controls the current path between the seventh node No7 and the first power supply terminal VA and the fourth power supply terminal VD to be disconnected, the potentials of the first node No1 and the second node No2 are stabilized.

[0048] In some embodiments, the first node No1 and the seventh node No7 are the same node. During the period when the first sub-circuit 101 disconnects the current path between the start signal line and the seventh node No7, the third sub-circuit 103 connects the current path between the first node No1 and the first power supply terminal VA or the fourth power supply terminal VD. During the period when the current path between the start signal line and the seventh node No7 is disconnected, the third sub-circuit 103, in conjunction with the first power supply signal or the fourth power supply signal, maintains the potential of the seventh node No7. Then, during the period when the current path between the start signal line and the seventh node No7 is disconnected, the potentials of the first node No1 and the second node No2 are stabilized.

[0049] In some embodiments, during the period when the second sub-circuit 102 is configured to connect the current path between the eighth node No8 and the first power supply terminal VA, the third sub-circuit 103 is configured to connect the signal transmission between the fourth power supply terminal VD and the seventh node No7 based on the signal from the eighth node No8. During a portion of the period when the second sub-circuit 102 is configured to connect the current path between the eighth node No8 and the fourth power supply terminal VD, the third sub-circuit 103 is configured to connect the signal transmission between the first power supply terminal VA and the seventh node No7 based on the signal from the eighth node No8 and the clock signal XCK.

[0050] Optionally, to eliminate the influence of residual charge on the operational stability of the gate drive circuit GA, the stage transmission circuit 10 may further include a reset sub-circuit 104, which is electrically connected to the seventh node No7 and is configured to reset the potential of the seventh node No7 according to the reset control signal Res.

[0051] Optionally, the output circuit 30 may include an output control sub-circuit 301 and a gate output sub-circuit 302. The output control sub-circuit 301 is electrically connected between the third node No3 and the ninth node No9, and is configured to control the signal of the ninth node No9 to be inverted with the signal of the third node No3. The gate output sub-circuit 302 is electrically connected between the ninth node No9 and the signal output terminal EOT, and is configured to control one of the second power supply terminal VB and the third power supply terminal VC to form a current path with the signal output terminal EOT according to the signal of the ninth node No9, so that when the partition circuit 20 connects the current path between the first power supply terminal VA and the third node No3, a current path is formed between the signal output terminal EOT and the third power supply terminal VC.

[0052] Optionally, during the period when the node control subcircuit 2011 connects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, and the partition selection subcircuit 202 is configured to connect the current path between the first node No1 and the third node No3, the output control subcircuit 301 is configured to connect the current path between the second power supply terminal VB and the ninth node No9 according to the signal of the third node No3, and the gate output subcircuit 302 is configured to connect the current path between the third power supply terminal VC and the signal output terminal EOT according to the signal of the ninth node No9. During the period when the node control subcircuit 2011 disconnects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, and the partition selection subcircuit 202 is configured to control the formation of a current path between the first node No1 and the third node No3, the output control subcircuit 301 is configured to connect the current path between the third power supply terminal VC and the ninth node No9 according to the signal of the third node No3, and the gate output subcircuit 302 is configured to connect the current path between the second power supply terminal VB and the signal output terminal EOT according to the signal of the ninth node No9, so that the output circuit 30 has a level change under the influence of the signal of the first node No1.

[0053] In some embodiments, during the period when the node control subcircuit 2011 connects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, the partition selection subcircuit 202 is configured to connect the current path between the first node No1 and the third node No3, or the partition selection subcircuit 202 is configured to connect the current path between the first power supply terminal VA and the third node No3. During the period when the partition selection subcircuit 202 is configured to connect the current path between the first power supply terminal VA and the third node No3, the output control subcircuit 301 is configured to connect the current path between the second power supply terminal VB and the ninth node No9 according to the signal of the third node No3, and the gate output subcircuit 302 is configured to connect the current path between the third power supply terminal VC and the signal output terminal EOT according to the signal of the ninth node No9, so that when the partition circuit 20 connects the current path between the first power supply terminal VA and the third node No3, the control signal output terminal EOT receives the third power supply signal.

[0054] In some embodiments, when the voltage of the first power signal is different from the voltage of the second power signal, and the voltage of the first power signal is the same as the voltage of the third power signal, the output circuit 30 includes an output control sub-circuit 301 and a gate output sub-circuit 302.

[0055] In some embodiments, the output circuit 30 may omit the gate output sub-circuit 302, thereby making the ninth node No9 the signal output terminal EOT. That is, the output control sub-circuit 301 is configured to control one of the second power supply terminal and the third power supply terminal VC to form a current path with the signal output terminal EOT according to the signal of the third node No3. Correspondingly, during the period when the node control sub-circuit 2011 connects the current path between the partition control line and the fifth node No5 according to the signal of the second node No2, and the partition selection sub-circuit 202 is configured to connect the current path between the first node No1 and the third node No3, the output control sub-circuit 301 is configured to connect the current path between the third power supply terminal VC and the signal output terminal EOT according to the signal of the third node No3. During the period when the node control subcircuit 2011 disconnects the current path between the partition control line and the fifth node No5 based on the signal from the second node No2, and the partition selection subcircuit 202 is configured to control the formation of a current path between the first node No1 and the third node No3, the output control subcircuit 301 is configured to connect the current path between the second power supply terminal VB and the signal output terminal EOT based on the signal from the third node No3, so that the output circuit 30 has a level variation under the influence of the signal from the first node No1. During the period when the partition selection subcircuit 202 is configured to connect the current path between the first power supply terminal VA and the third node No3, the output control subcircuit 301 is configured to connect the current path between the third power supply terminal VC and the signal output terminal EOT based on the signal from the third node No3, so that when the partition circuit 20 connects the current path between the first power supply terminal VA and the third node No3, the control signal output terminal EOT receives the third power supply signal.

[0056] Optionally, when the voltage of the first power supply signal is different from the voltage of the third power supply signal, and the voltage of the first power supply signal is the same as the voltage of the second power supply signal, the output circuit 30 can omit the setting of the gate output sub-circuit 302.

[0057] In some embodiments, the light emission control signal output when the gate output sub-circuit 302 is omitted in the gate driving circuit GA is out of phase with the light emission control signal output when the gate output sub-circuit 302 is provided in the gate driving circuit GA. Therefore, those skilled in the art can selectively configure the gate output sub-circuit 302 according to different actual needs of the light emission control signal EM.

[0058] Optionally, the gate drive circuit GA can be implemented using at least one of a switching device, a memory device, etc. The switching device may include at least one of a transistor or similar device, and the memory device may include at least one of a capacitor or an inductor.

[0059] like Figures 2A-2BThis is a circuit diagram of a gate driving circuit according to an exemplary embodiment of this disclosure. For ease of understanding this application, [the following is used]. Figures 2A-2B The structure of the gate drive circuit GA in this application will be described using an example.

[0060] Optionally, the node control sub-circuit 2011 of the partition control sub-circuit 201 may include a first partition transistor Tf1. The first partition transistor Tf1 includes a control terminal electrically connected to the second node No2, a first source-drain terminal electrically connected to the partition control line, and a second source-drain terminal electrically connected to the fifth node No5. The first partition transistor Tf1 controls the signal transmission between the partition control line and the fifth node No5 according to the signal of the second node No2.

[0061] In some embodiments, the first partition transistor Tf1 is an N-type oxide transistor. The threshold voltage of the first partition transistor Tf1 is greater than 0. This reduces the probability of the first partition transistor Tf1 being falsely turned on when it is turned off according to the signal of the second node No2 and the partition control signal SEN is low. It also reduces the leakage current between the partition control line and the fifth node No5 during the period when the first partition transistor Tf1 is turned off, thereby improving the operational reliability of the gate drive circuit GA. Furthermore, it can also reduce the impact of the threshold voltage drop of the first partition transistor Tf1 on the signal of the third node No3.

[0062] Optionally, the first inverting sub-circuit 2012 of the partition control sub-circuit 201 may include a second partition transistor Tf2 and a third partition transistor Tf3. The control terminals of the second partition transistor Tf2 and the third partition transistor Tf3 are electrically connected to the fifth node No5. The first source-drain terminal of the second partition transistor Tf2 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the third partition transistor Tf3 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the second partition transistor Tf2 and the third partition transistor Tf3 are electrically connected to the fourth node No4. The second partition transistor Tf2 and the third partition transistor Tf3 are turned on or off according to the signal from the fifth node No5.

[0063] In some embodiments, to reduce the probability that the fourth node No4 simultaneously receives both the first power signal and the fourth power signal, the majority carrier type of the second partition transistor Tf2 can be different from the majority carrier type of the third partition transistor Tf3. Here, the majority carrier of a transistor can be either electrons or holes, and the minority carrier of a transistor can be either electrons or holes.

[0064] In some embodiments, one of the second partition transistor Tf2 and the third partition transistor Tf3 is a P-type transistor, and the other of the second partition transistor Tf2 and the third partition transistor Tf3 is an N-type transistor.

[0065] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the second partition transistor Tf2 is a P-type transistor, and the third partition transistor Tf3 is an N-type transistor, in order to reduce the impact of the threshold loss of the second partition transistor Tf2 and the third partition transistor Tf3 on the signal of the fourth node No4.

[0066] Optionally, the storage sub-circuit 2013 of the partition control sub-circuit 201 may include a first capacitor C1, which is electrically connected between the fourth power supply terminal VD and the fifth node No5. The first capacitor C1 is used to maintain the potential of the fifth node No5 during the period when the first partition transistor Tf1 is turned off.

[0067] Optionally, the first selection sub-circuit 2021 of the partition selection sub-circuit 202 may include a first selection transistor Tx1. The first selection transistor Tx1 includes a control terminal electrically connected to the fourth node No4, a first source-drain terminal electrically connected to the first power supply terminal VA, and a second source-drain terminal electrically connected to the third node No3. The first selection transistor Tx1 is turned on or off according to the signal from the fourth node No4.

[0068] Optionally, the second selection sub-circuit 2022 of the partition selection sub-circuit 202 includes at least one of the second selection transistor Tx2 and the third selection transistor Tx3 to realize signal transmission control between the first node No1 and the third node No3 using at least one of the second selection transistor Tx2 and the third selection transistor Tx3.

[0069] In some embodiments, the second selection sub-circuit 2022 includes a second selection transistor Tx2, which includes a control terminal electrically connected to the fourth node No4, a first source-drain terminal electrically connected to the first node No1, and a second source-drain terminal electrically connected to the third node No3. The second selection transistor Tx2 controls the signal transmission between the first node No1 and the third node No3 according to the signal from the fourth node No4.

[0070] In some embodiments, to reduce the probability that the third node No3 simultaneously forms a current path with both the first power supply terminal VA and the first node No1, the majority carrier type of the first selection transistor Tx1 can be different from the majority carrier type of the second selection transistor Tx2. For example, the first selection transistor Tx1 can be either a P-type transistor or an N-type transistor, and the second selection transistor Tx2 can be either a P-type transistor or an N-type transistor.

[0071] In some embodiments, the second selection transistor Tx2 may include two control terminals, both of which are electrically connected to the fourth node No4.

[0072] In some embodiments, the second selection sub-circuit 2022 includes a second inverting sub-circuit 2022a and a third selection transistor Tx3. The third selection transistor Tx3 includes a control terminal electrically connected to the sixth node No6, a first source-drain terminal electrically connected to the first node No1, and a second source-drain terminal electrically connected to the third node No3. The third selection transistor Tx3 controls the signal transmission between the first node No1 and the third node No3 according to the signal from the sixth node No6.

[0073] In some embodiments, since the third selection transistor Tx3 is controlled by the sixth node No6, and the signal of the sixth node No6 is out of phase with the signal of the fourth node No4, in order to reduce the probability that the third node No3 simultaneously forms a current path with the first power supply terminal VA and the first node No1, the majority carrier type of the first selection transistor Tx1 can be the same as the majority carrier type of the third selection transistor Tx3. For example, the first selection transistor Tx1 and the third selection transistor Tx3 can both be P-type transistors.

[0074] In some embodiments, when the second selection sub-circuit 2022 includes one of the second selection transistor Tx2 and the third transistor T3, the threshold voltage loss of the transistor causes signal transmission loss between the first node No1 and the third node No3, resulting in the signal change of the third node No3 deviating from the expected value. Taking an example where the second selection transistor Tx2 is an N-type transistor and the third selection transistor Tx3 is a P-type transistor, when the second selection sub-circuit 2022 includes only the second selection transistor Tx2, and the signal of the first node No1 is high, the second selection transistor Tx2 is turned on, forming a current transmission path between the third node No3 and the first node No1. When the potential of the third node No3 charges to the difference between the voltage of the fourth node No4 and the threshold voltage of the second selection transistor Tx2, the second selection transistor Tx2 is turned off, preventing the signal of the third node No3 from rising further. Therefore, when using the second selection transistor Tx2 to realize signal transmission between the first node No1 and the third node No3, the second selection transistor Tx2 exhibits a "weak 1" characteristic, causing the voltage of the third node No3 to not reach the expected value when it is high. When the signal at the first node No1 is low, the second selection transistor Tx2 is turned on, forming a current transmission path between the third node No3 and the first node No1. The signal at the third node No3 can then be reduced to the expected voltage. Therefore, when using the second selection transistor Tx2 to achieve signal transmission between the first node No1 and the third node No3, the second selection transistor Tx2 exhibits a "strong 0" characteristic. Similarly, when the second selection sub-circuit 2022 only includes the third selection transistor Tx3, and the signal at the first node No1 is low, using the third selection transistor Tx3 to achieve signal transmission between the first node No1 and the third node No3 will result in the third selection transistor Tx3 exhibiting a "weak 0" characteristic, causing the voltage at the third node No3 to not reach the expected level when it is low. However, when the signal at the first node No1 is high, using the third selection transistor Tx3 to achieve signal transmission between the first node No1 and the third node No3 will result in the third selection transistor Tx3 exhibiting a "strong 1" characteristic, allowing the signal at the third node No3 to rise to the expected voltage. Therefore, when the second selection sub-circuit 2022 includes either the second selection transistor Tx2 or the third transistor T3, the voltage change corresponding to the low level or high level of the third node No3 will deviate from the expected value. If the potential of the third node No3 deviates significantly from the expected value, it can easily cause abnormal operation of the output circuit 30, affecting the operational reliability of the gate drive circuit GA. Therefore, to further improve the operational reliability of the gate drive circuit GA, the second selection sub-circuit 2022 can include both the second selection transistor Tx2 and the third selection transistor Tx3.

[0075] In some embodiments, the second selection sub-circuit 2022 includes a transmission gate sub-circuit 2022b, which includes a second selection transistor Tx2 and a third selection transistor Tx3. The second selection transistor Tx2 and the third selection transistor Tx3 complement each other, so that the voltage corresponding to the third node No3 being low and the voltage corresponding to the third node No3 being high can both reach the expected design, thereby improving the working stability of the output circuit 30 controlled by the third node No3, and thus improving the working reliability of the gate drive circuit GA.

[0076] In some embodiments, the voltage of the first power supply signal supplied by the first power supply terminal VA is greater than the voltage of the fourth power supply signal supplied by the fourth power supply terminal VD. The first selection transistor Tx1 and the third selection transistor Tx3 are both P-type transistors, and the second selection transistor Tx2 is an N-type transistor, so as to reduce the impact of the transistor threshold loss on the signal of the third node No3, while enabling the third node No3 to form a current path with the first power supply terminal VA and the first node No1 in a time-division manner.

[0077] Optionally, when the second selection sub-circuit 2022 includes the second inverting sub-circuit 2022a, the second inverting sub-circuit 2022a may include a fourth selection transistor Tx4 and a fifth selection transistor Tx5. The control terminals of the fourth selection transistor Tx4 and the fifth selection transistor Tx5 are electrically connected to the fourth node No4. The first source-drain terminal of the fourth selection transistor Tx4 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the fifth selection transistor Tx5 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the fourth selection transistor Tx4 and the fifth selection transistor Tx5 are electrically connected to the sixth node No6, so that the signal of the sixth node No6 is inverted with the signal of the fourth node No4 by using the fourth selection transistor Tx4 and the fifth selection transistor Tx5.

[0078] In some embodiments, to reduce the probability that the sixth node No.6 simultaneously receives both the first power signal and the fourth power signal, the majority carrier type of the fourth selection transistor Tx4 can be different from that of the fifth selection transistor Tx5. For example, the fourth selection transistor Tx4 can be either a P-type transistor or an N-type transistor, and the fifth selection transistor Tx5 can be either a P-type transistor or an N-type transistor.

[0079] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the fourth selection transistor Tx4 is a P-type transistor, and the fifth selection transistor Tx5 is an N-type transistor, in order to reduce the impact of the threshold loss of the fourth selection transistor Tx4 and the fifth selection transistor Tx5 on the signal of the sixth node No6.

[0080] In some embodiments, the fifth selection transistor Tx5 may include two control terminals, both of which are electrically connected to the fourth node No4.

[0081] In some embodiments, during the period when the first selection transistor Tx1 is configured to be on according to the signal of the fourth node No4, the second selection transistor Tx2 is configured to be off according to the signal of the fourth node No4, the third selection transistor Tx3 is configured to be off according to the signal of the sixth node No6, the fourth selection transistor Tx4 is configured to be on according to the signal of the fourth node No4, and the fifth selection transistor Tx5 is configured to be off according to the signal of the fourth node No4. During the period when the first selection transistor Tx1 is configured to be off according to the signal of the fourth node No4, the second selection transistor Tx2 is configured to be on according to the signal of the fourth node No4, the third selection transistor Tx3 is configured to be on according to the signal of the sixth node No6, the fourth selection transistor Tx4 is configured to be off according to the signal of the fourth node No4, and the fifth selection transistor Tx5 is configured to be on according to the signal of the fourth node No4, so that the signal of the third node No3 forms a current path between the first power supply terminal VA and the first node No1 in a time-division manner.

[0082] Optionally, when the transmission circuit 10 includes a start control sub-circuit 1011, the start control sub-circuit 1011 may include a first transistor T1, a second transistor T2, and a third transistor T3, such as... Figure 2A As shown. The control terminals of the first transistor T1 and the second transistor T2 are configured to receive a start signal STV. The first source-drain terminal of the first transistor T1 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the second transistor T2 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the first transistor T1 and the second transistor T2 are electrically connected to the first source-drain terminal of the third transistor T3. The control terminal of the third transistor T3 is configured to receive a clock signal XCK. The second source-drain terminal of the third transistor T3 is electrically connected to the seventh node No7. The first transistor T1 is configured to control the signal transmission between the first source-drain terminal of the third transistor T3 and the first power supply terminal VA according to the start signal STV. The second transistor T2 is configured to control the signal transmission between the first source-drain terminal of the third transistor T3 and the fourth power supply terminal VD according to the start signal STV. The third transistor T3 is configured to control the seventh node No7 to receive either the first power supply signal or the fourth power supply signal according to the clock signal XCK.

[0083] In some embodiments, to reduce the probability that the seventh node No.7 simultaneously receives both the first power signal and the fourth power signal, the majority carrier type of the first transistor T1 can be different from that of the second transistor T2. For example, the first transistor T1 can be either a P-type transistor or an N-type transistor, and the second transistor T2 can be either a P-type transistor or an N-type transistor.

[0084] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor, in order to reduce the impact of the threshold loss of the first transistor T1 and the second transistor T2 on the signal of the seventh node No7.

[0085] In some embodiments, the second transistor T2 may include two control terminals, both of which are configured to receive a start signal STV.

[0086] Optionally, the stage transmission circuit 10 includes a third inverting sub-circuit 1012, which may include a fourth transistor T4 and a fifth transistor T5, such as... Figure 2A As shown, the control terminals of the fourth transistor T4 and the fifth transistor T5 are electrically connected to the seventh node No7. The first source-drain terminal of the fourth transistor T4 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the fifth transistor T5 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the fourth transistor T4 and the fifth transistor T5 are electrically connected to the first node No1. The fourth transistor T4 controls the signal transmission between the first power supply terminal VA and the first node No1, and the fifth transistor T5 controls the signal transmission between the fourth power supply terminal VD and the first node No1.

[0087] Optionally, to reduce the probability that the first node No.1 simultaneously receives both the first power signal and the fourth power signal, the majority carrier type of the fourth transistor T4 can be different from that of the fifth transistor T5. For example, the fourth transistor T4 can be either a P-type transistor or an N-type transistor, and the fifth transistor T5 can be either a P-type transistor or an N-type transistor.

[0088] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the fourth transistor T4 is a P-type transistor, and the fifth transistor T5 is an N-type transistor, in order to reduce the impact of the threshold loss of the fourth transistor T4 and the fifth transistor T5 on the signal of the first node No1.

[0089] In some embodiments, the fifth transistor T5 may include two control terminals, both of which are electrically connected to the seventh node No7.

[0090] Optionally, when the second node No2 and the eighth node No8 are the same node, the second sub-circuit 102 of the cascade circuit 10 may include the sixth transistor T6 and the seventh transistor T7, such as... Figure 2A As shown, the control terminals of the sixth transistor T6 and the seventh transistor T7 are electrically connected to the seventh node No7. The first source-drain terminal of the sixth transistor T6 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the seventh transistor T7 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the sixth transistor T6 and the seventh transistor T7 are electrically connected to the second node No2. This allows the sixth transistor T6 and the seventh transistor T7 to work in conjunction with the first power supply signal and the fourth power supply signal to control the potential of the second node No2.

[0091] Optionally, to reduce the probability that the second node No2 simultaneously receives both the first and fourth power signals, the majority carrier type of the sixth transistor T6 can be different from that of the seventh transistor T7. For example, the sixth transistor T6 can be either a P-type transistor or an N-type transistor, while the seventh transistor T7 can be either a P-type transistor or an N-type transistor.

[0092] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the sixth transistor T6 is a P-type transistor, and the seventh transistor T7 is an N-type transistor, in order to reduce the impact of the threshold loss of the sixth transistor T6 and the seventh transistor T7 on the signal of the second node No2.

[0093] In some embodiments, the seventh transistor T7 may include two control terminals, both of which are electrically connected to the seventh node No7.

[0094] Optionally, when the first node No1 and the seventh node No7 are the same node, the first sub-circuit 101 of the cascade circuit 10 may include the first switching transistor Ts1, such as... Figure 2B As shown. The first switching transistor Ts1 includes a control terminal configured to receive a clock signal XCK, a first source-drain terminal configured to receive a start signal STV, and a second source-drain terminal electrically connected to the seventh node No7. The first switching transistor Ts1 is configured to control the signal transmission between the start signal line and the seventh node No7 according to the clock signal XCK.

[0095] Optionally, the second selection sub-circuit 2022 of the transmission circuit 10 includes a fourth inverting sub-circuit 1021, which may include a second switching transistor Ts2 and a third switching transistor Ts3, such as... Figure 2BAs shown. The control terminals of the second switching transistor Ts2 and the third switching transistor Ts3 are electrically connected to the seventh node No7. The first source-drain terminal of the second switching transistor Ts2 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the third switching transistor Ts3 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the second switching transistor Ts2 and the third switching transistor Ts3 are electrically connected to the eighth node No8. This allows the second switching transistor Ts2 and the third switching transistor Ts3 to work in conjunction with the first and fourth power supply signals to control the signal at the eighth node No8 to be inverted compared to the signal at the seventh node No7.

[0096] Optionally, to reduce the probability that the eighth node No.8 simultaneously receives both the first and fourth power signals, the majority carrier type of the second switching transistor Ts2 can be different from that of the third switching transistor Ts3. For example, the second switching transistor Ts2 can be either a P-type transistor or an N-type transistor, and the third switching transistor Ts3 can be either a P-type transistor or an N-type transistor.

[0097] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the second switching transistor Ts2 is a P-type transistor, and the third switching transistor Ts3 is an N-type transistor, in order to reduce the impact of the threshold loss of the second switching transistor Ts2 and the third switching transistor Ts3 on the signal of the eighth node No8.

[0098] In some embodiments, the third switching transistor Ts3 may include two control terminals, both of which are electrically connected to the seventh node No7.

[0099] Optionally, the second selection sub-circuit 2022 of the transmission circuit 10 includes a fifth inverting sub-circuit 1022, which includes a fourth switching transistor Ts4 and a fifth switching transistor Ts5, such as... Figure 2B As shown, the control terminals of the fourth switching transistor Ts4 and the fifth switching transistor Ts5 are electrically connected to the eighth node No8. The first source-drain terminal of the fourth switching transistor Ts4 is electrically connected to the first power supply terminal VA. The first source-drain terminal of the fifth switching transistor Ts5 is electrically connected to the fourth power supply terminal VD. The second source-drain terminals of the fourth switching transistor Ts4 and the fifth switching transistor Ts5 are electrically connected to the second node No2. This allows the fourth switching transistor Ts4 and the fifth switching transistor Ts5 to work in conjunction with the first power supply signal and the fourth power supply signal to control the signal at the second node No2 to be inverted relative to the signal at the eighth node No8.

[0100] Optionally, to reduce the probability that the second node No2 simultaneously receives both the first and fourth power signals, the majority carrier type of the fourth switching transistor Ts4 can be different from that of the fifth switching transistor Ts5. For example, the fourth switching transistor Ts4 can be either a P-type transistor or an N-type transistor, while the fifth switching transistor Ts5 can be either a P-type transistor or an N-type transistor.

[0101] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the fourth switching transistor Ts4 is a P-type transistor, and the fifth switching transistor Ts5 is an N-type transistor, in order to reduce the impact of the threshold loss of the fourth switching transistor Ts4 and the fifth switching transistor Ts5 on the signal of the second node No2.

[0102] In some embodiments, the fifth switching transistor Ts5 may include two control terminals, both of which are electrically connected to the eighth node No8.

[0103] Optionally, the third sub-circuit 103 of the cascade circuit 10 may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10, such as... Figures 2A-2B As shown. The control terminals of the eighth transistor T8 and the ninth transistor T9 are electrically connected to the eighth node No8. The first source-drain terminal of the eighth transistor T8 is electrically connected to the fourth power supply terminal VD. The first source-drain terminal of the ninth transistor T9 is electrically connected to the first power supply terminal VA. The second source-drain terminal of the ninth transistor T9 is electrically connected to the first source-drain terminal of the tenth transistor T10. The control terminal of the tenth transistor T10 is configured to receive the corresponding clock signal XCK. The second source-drain terminals of the eighth transistor T8 and the tenth transistor T10 are electrically connected to the seventh node No7, so as to use the eighth transistor T8 to control the signal transmission between the fourth power supply terminal VD and the seventh node No7, and use the ninth transistor T9 and the tenth transistor T10 to control the signal transmission between the seventh node No7 and the first power supply terminal VA.

[0104] In some embodiments, the voltage of the first power supply signal is greater than the voltage of the fourth power supply signal, the first switching transistor Ts1 or the third transistor T3 is a P-type transistor, the eighth transistor T8 and the tenth transistor T10 are N-type transistors, and the ninth transistor T9 is a P-type transistor.

[0105] In some embodiments, the eighth transistor T8 and the tenth transistor T10 each have two control terminals. The two control terminals of the eighth transistor T8 are electrically connected to the eighth node No8, and the two control terminals of the tenth transistor T10 are configured to receive the clock signal XCK.

[0106] Optionally, the reset sub-circuit 104 of the cascade circuit 10 may include an eleventh transistor T11. The eleventh transistor T11 includes a control terminal configured to receive a reset control signal Res, a first source-drain terminal electrically connected to the fifth power supply terminal VE, and a second source-drain terminal electrically connected to the seventh node No7, so as to use the eleventh transistor T11 in conjunction with the fifth power supply signal supplied by the fifth power supply terminal VE to reset the potential of the seventh node No7.

[0107] In some embodiments, one of the first power supply terminal VA and the second power supply terminal VB is multiplexed as the fifth power supply terminal VE to reduce the number of power supply terminals corresponding to the gate drive circuit GA, thereby reducing the power consumption of the gate drive circuit GA.

[0108] In some embodiments, to reduce the impact of level fluctuations caused by interference or other factors on the output of the gate drive circuit GA, the first power supply terminal VA can be multiplexed as the fifth power supply terminal VE. This allows the reset sub-circuit 104 to control the signal of the second node No2 to be in a state that disconnects the current transmission path between the fifth node No5 and the partition control line, thereby reducing the impact of level fluctuations caused by interference or other factors on the initial operating state of the gate drive circuit GA.

[0109] In some embodiments, when the gate drive circuit GA is applied in a display panel, the eleventh transistor T11 can be turned on when the display panel is powered on, and / or the vertical blanking interval is turned on, to reset the potential of the seventh node No7, thereby giving the gate drive circuit a stable initial operating state.

[0110] Optionally, the output control sub-circuit 301 of the output circuit 30 may include a first output transistor To1 and a second output transistor To2, such as... Figures 2A-2B As shown, the control terminals of the first output transistor To1 and the second output transistor To2 are electrically connected to the third node No3. The first source-drain terminal of the first output transistor To1 is electrically connected to the third power supply terminal VC. The first source-drain terminal of the second output transistor To2 is electrically connected to the second power supply terminal VB. The second source-drain terminals of the first output transistor To1 and the second source-drain terminal of the second output transistor To2 are electrically connected to the ninth node No9. This allows the first output transistor To1 and the second output transistor To2 to work in conjunction with the second and third power supply signals to control the signal of the ninth node No9 to be inverted with the signal of the third node No3.

[0111] Optionally, to reduce the probability that the ninth node No.9 simultaneously receives both the second and third power signals, the majority carrier type of the first output transistor To1 can be different from that of the second output transistor To2. For example, the first output transistor To1 can be either a P-type transistor or an N-type transistor, and the second output transistor To2 can be either a P-type transistor or an N-type transistor.

[0112] In some embodiments, the voltage of the third power supply signal is greater than the voltage of the second power supply signal, the first output transistor To1 is a P-type transistor, and the second output transistor To2 is an N-type transistor, in order to reduce the impact of the threshold loss of the first output transistor To1 and the second output transistor To2 on the signal of the ninth node No9.

[0113] In some embodiments, the second output transistor To2 may include two control terminals, both of which are electrically connected to the third node No3.

[0114] Optionally, the output circuit 30 may include a gate output sub-circuit 302, which includes a third output transistor To3 and a fourth output transistor To4, such as... Figures 2A-2B As shown, the control terminals of the third output transistor To3 and the fourth output transistor To4 are electrically connected to the ninth node No9. The first source-drain terminal of the third output transistor To3 is electrically connected to the third power supply terminal VC. The first source-drain terminal of the fourth output transistor To4 is electrically connected to the second power supply terminal VB. The second source-drain terminals of the third output transistor To3 and the fourth output transistor To4 are electrically connected to the signal output terminal EOT, so that the third output transistor To3 and the fourth output transistor To4 can cooperate with the signal control signal output terminal EOT of the ninth node No9 to receive the second power supply signal or the third power supply signal.

[0115] Optionally, to reduce the probability that the signal output terminal EOT simultaneously receives both the second and third power supply signals, the majority carrier type of the third output transistor To3 can be different from that of the fourth output transistor To4. For example, the third output transistor To3 can be either a P-type transistor or an N-type transistor, while the fourth output transistor To4 can be either a P-type transistor or an N-type transistor.

[0116] In some embodiments, the voltage of the third power supply signal is greater than the voltage of the second power supply signal, the third output transistor To3 is a P-type transistor, and the fourth output transistor To4 is an N-type transistor, in order to reduce the impact of the threshold loss of the third output transistor To3 and the fourth output transistor To4 on the light emission control signal EM.

[0117] In some embodiments, the fourth output transistor To4 may include two control terminals, both of which are electrically connected to the ninth node No9.

[0118] In some embodiments, the majority carrier type of the first output transistor To1 is the same as the majority carrier type of the third output transistor To3, so that the light emission control signal EM is out of phase with the signal of the ninth node No9.

[0119] It should be understood that when the gate output sub-circuit 302 is omitted in the gate drive circuit GA, the output circuit 30 may only include the first output transistor To1 and the second output transistor To2. Accordingly, the power supply terminal electrically connected to the first source-drain terminal of the first output transistor To1 corresponds to the second power supply terminal VB; the power supply terminal electrically connected to the first source-drain terminal of the second output transistor To2 corresponds to the third power supply terminal VC.

[0120] It should be noted that the transistors included in the gate drive circuit GA can be either P-type or N-type transistors. The transistors in the gate drive circuit GA can be implemented as bipolar junction transistors (BJTs), field-effect transistors (FETs), or thin-film transistors (TFTs). When the transistors are implemented as FETs or TFTs, for a single transistor, the control terminal can be the gate, the first source / drain terminal can be one of the source and drain, and the second source / drain terminal can be the other of the source and drain. When the transistors are implemented as bipolar junction transistors, for a single transistor, the control terminal can be the base, the first source / drain terminal can be one of the collector and emitter, and the second source / drain terminal can be the other of the collector and emitter. Each transistor can employ a single-gate or dual-gate design. The active layer of each transistor can include silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The oxide semiconductor materials include indium gallium zinc oxide or indium zinc oxide.

[0121] It should be understood that, Figures 2A-2B This example only illustrates the situation where the first power supply terminal VA, the third power supply terminal VC, and the fifth power supply terminal VE are all high-voltage terminals (VGH), while the second power supply terminal VB and the fourth power supply terminal VD are both low-voltage terminals (VGL). However, in practical applications, this design is not limited to this. The voltage value of the signal supplied by the high-voltage terminal is greater than the voltage value of the signal supplied by the low-voltage terminal. The voltage supplied by the high-voltage terminal can be a relatively high voltage, such as a signal voltage greater than or equal to 10 volts and less than or equal to 20 volts.

[0122] also, Figures 2A-2B The design of each sub-circuit is illustrated only as an example, but this does not limit the gate drive circuit GA of this application to only adopt... Figures 2A-2BBased on the disclosure of this application, those skilled in the art can still modify the design of each sub-circuit of the gate drive circuit GA, and each sub-circuit of the gate drive circuit GA can be implemented in a simpler or more complex form or with more components. These components include, but are not limited to, transistors, capacitors, and other devices.

[0123] Figures 3A-3B This is a timing diagram corresponding to the gate drive circuit of an exemplary embodiment of this disclosure. For ease of understanding the gate drive circuit GA of this application, [the diagram is shown]. Figure 2A Taking the gate drive circuit GA shown as an example, the first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the second partition transistor Tf2, the first selection transistor Tx1, the third selection transistor Tx3, the fourth selection transistor Tx4, the first output transistor To1, and the third output transistor To3 are P-type transistors, and the remaining transistors are N-type transistors. Furthermore, the first power supply terminal VA, the third power supply terminal VC, and the fifth power supply terminal VE are high-voltage terminals VGH, and the second power supply terminal VB and the fourth power supply terminal VD are low-voltage terminals VGL. The working principle of the gate drive circuit GA will be explained using this example. Figures 3A-3B In this circuit, Nos1 represents the signal of the first node No1 in the gate drive circuit GA, Nos2 represents the signal of the second node No2 in the gate drive circuit GA, Nos3 represents the signal of the third node No3 in the gate drive circuit GA, Nos5 represents the signal of the fifth node No5 in the gate drive circuit GA, Nos7 represents the signal of the seventh node No7 in the gate drive circuit GA, and Nos9 represents the signal of the ninth node No9 in the gate drive circuit GA.

[0124] Please continue reading. Figure 3AIn the first stage t1, the start signal STV and clock signal XCK are low, and the partition control signal SEN is either low or high. Transistors T1, T3, T5, T7, and T9 are turned on, transmitting the first power signal to node No7 and the fourth power signal to node No2 and node No1. The signal at node No5 is low, and the second partition transistor Tf2, second selection transistor Tx2, third selection transistor Tx3, and fifth selection transistor Tx5 are turned on. The current path between node No1 and node No3 is connected, and the first output transistor To1 and fourth output transistor To4 are turned on. The light emission control signal EM is low. Transistors T2, T4, T6, T8, T10, T11, Tf1, Tf3, Tx1, Tx4, To2, and To3 are turned off.

[0125] In the second stage t2, the start signal STV is low, the clock signal XCK is high, and the partition control signal SEN is either low or high. Transistors T1, T5, T7, T9, T10, Tf2 (second partition), Tx2 (second selection), Tx3 (third selection), and Tx5 (fifth selection) are turned on, connecting the current path between node No1 and node No3. Output transistors To1 and To4 are turned on, and the light emission control signal EM is low. Transistors T2, T3, T4, T6, T8, T11, Tf1 (first partition), Tf3 (third partition), Tx1 (first selection), Tx4 (fourth selection), To2 (second output), and To3 (third output) are turned off.

[0126] The third stage t3 has the same working state as the first stage t1.

[0127] In stage t4, the start signal STV and clock signal XCK are high, while the partition control signal SEN is low or high. Transistors T2, T5, T7, T9, T10, Tf2 (second partition), Tx2 (second selection), Tx3 (third selection), Tx5 (fifth selection), To1 (first output), and To4 (fourth output) are turned on, and the light emission control signal EM is low. Transistors T1, T3, T4, T6, T8, T11 (eleventh output), Tf1 (first partition), Tf3 (third partition), Tx1 (first selection), Tx4 (fourth selection), To2 (second output), and To3 (third output) are turned off.

[0128] In stage t5, the clock signal XCK and the partition control signal SEN are low, while the start signal STV is high. The second transistor T2, third transistor T3, fourth transistor T4, sixth transistor T6, eighth transistor T8, first partition transistor Tf1, second partition transistor Tf2, second selection transistor Tx2, third selection transistor Tx3, and fifth selection transistor Tx5 are turned on. The current path between the first node No1 and the third node No3 is connected. The second output transistor To2 and the third output transistor To3 are turned on, and the light emission control signal EM is high. The first transistor T1, fifth transistor T5, seventh transistor T7, ninth transistor T9, tenth transistor T10, eleventh transistor T11, third partition transistor Tf3, first selection transistor Tx1, fourth selection transistor Tx4, first output transistor To1, and fourth output transistor To4 are turned off.

[0129] In stage t6, the start signal STV and the partition control signal SEN are low, while the clock signal XCK is high. Transistors T1, T4, T6, T8, Tf1 (first partition), Tf2 (second partition), Tx2 (second selection), Tx3 (third selection), Tx5 (fifth selection), To2 (second output), and To3 (third output) are turned on, and the light emission control signal EM is high. Transistors T2, T3, T5, T7, T9, T10, T11, Tf3 (third partition), Tx1 (first selection), Tx4 (fourth selection), To1 (first output), and To4 (fourth output) are turned off.

[0130] The seventh stage t7 has the same working state as the first stage t1.

[0131] Gate drive circuit (GA) Figure 3B The working principle of the first stage t1 to the fourth stage t4 can be referred to Figure 3A The working principle of the first stage t1 to the fourth stage t4 is obtained, and will not be elaborated here.

[0132] Please continue reading. Figure 2A and Figure 3B In stage t5, the clock signal XCK is low, while the start signal STV and the partition control signal SEN are high. The second transistor T2, third transistor T3, fourth transistor T4, sixth transistor T6, eighth transistor T8, and the first partition transistor Tf1 are turned on. The partition control signal SEN is transmitted to the fifth node No5. The third partition transistor Tf3 is turned on. The fourth power supply signal is transmitted to the fourth node No4. The first selection transistor Tx1 and the fourth selection transistor Tx4 are turned on. The current path between the third node No3 and the first power supply terminal VA is connected. The second output transistor To2 and the third output transistor To3 are turned on. The light emission control signal EM is high. The first transistor T1, fifth transistor T5, seventh transistor T7, ninth transistor T9, tenth transistor T10, eleventh transistor T11, the second partition transistor Tf2, the second selection transistor Tx2, the third selection transistor Tx3, the fifth selection transistor Tx5, the first output transistor To1, and the fourth output transistor To4 are turned off.

[0133] In stage 6 (t6): the start signal STV is low, and the clock signal XCK and the partition control signal SEN are high. Transistors T1, T4, T6, T8, T10, Tf1 (first partition), Tf3 (third partition), Tx1 (first selection), Tx4 (fourth selection), To2 (second output), and To3 (third output) are turned on, and the light emission control signal EM is high. Transistors T1, T3, T5, T7, T9, T11 (eleventh output), Tf2 (second partition), Tx2 (second selection), Tx3 (third selection), Tx5 (fifth selection), To1 (first output), and To4 (fourth output) are turned off.

[0134] In stage 7 (t7): the clock signal XCK and the start signal STV are low, and the partition control signal SEN is high. Transistors T1, T3, T5, T7, T9, Tf3 (third partition transistor), Tx1, Tx4 (first selection transistor), To2 (second output transistor), and To3 (third output transistor) are turned on, and the light emission control signal EM is high. Transistors T2, T4, T6, T8, T10, T11 (tenth transistor), Tf1 (first partition transistor), Tf2 (second partition transistor), Tx2 (second selection transistor), Tx3 (third selection transistor), Tx5 (fifth selection transistor), To1 (first output transistor), and To4 (fourth output transistor) are turned off.

[0135] In the eighth stage t8, following the seventh stage t7, because the first partition transistor Tf1 is in the off state, the first selection transistor Tx1, the fourth selection transistor Tx4, the second output transistor To2, and the third output transistor To3 remain on, so that the light emission control signal EM remains at a high level.

[0136] Because the first partition transistor Tf1 is in the off state before the start of the fifth stage t5 and after the start of the seventh stage t7, the partition control signal SEN transitions from low to high before the start of the fifth stage t5 or after the start of the seventh stage t7. Therefore, the level of the light emission control signal EM will not change due to the partition control signal SEN. Figure 3A As shown. During the period between the start of the fifth stage t5 and the start of the seventh stage t7, because the first partition transistor Tf1 is turned on, the partition control signal SEN transitions from low to high at the first transition time tk1 during this period, causing the first selection transistor Tx1 to turn on, thus enabling the third power supply signal to be transmitted to the signal output terminal EOT. Furthermore, while the partition control signal SEN remains high from the first transition time tk1 until after the start of the seventh stage t7, the first selection transistor Tx1 remains on, ensuring that the light emission control signal EM remains high during the eighth period ti8 after the start of the seventh stage t7. Figure 3B As shown. The first transition time tk1 can be any time in the time interval between the start time of the fifth stage t5 and the start time of the seventh stage t7.

[0137] Therefore, according to Figures 3A-3BIt can be seen that during the period when the partitioning circuit 20 controls the formation of a current path between the first power supply terminal VA and the third node No3, the signal output terminal EOT of the gate drive circuit GA receives the signal from the third power supply terminal VC, causing the light emission control signal EM to have a high level. During the period when the partitioning circuit 20 controls the formation of a current path between the first node No1 and the third node No3, the signal output terminal EOT of the gate drive circuit GA receives the second power supply signal and the third power supply signal in a time-division manner, causing the light emission control signal EM to switch between a high level and a low level. Therefore, by using the cooperation of the partitioning circuit 20 and the partitioning control signal SEN, the duration of the high level of the light emission control signal EM can be controlled.

[0138] It should be understood that, with reference Figure 2A and Figures 3A-3B The relevant explanations can be used to similarly determine the gate drive circuit GA. Figure 2B The working principle of the design shown, and the working principle of the gate drive circuit GA with the third output transistor To3 and the fourth output transistor To4 omitted, and the ninth node No9 and the signal output terminal EOT being the same node, will not be repeated here. It should be noted that when the third output transistor To3 and the fourth output transistor To4 are omitted in the gate drive circuit GA, and the ninth node No9 and the signal output terminal EOT are the same node, the power supply terminal electrically connected to the first source-drain terminal of the first output transistor To1 is the second power supply terminal VB, and the power supply terminal electrically connected to the first source-drain terminal of the second output transistor To2 is the third power supply terminal VC. The third power supply terminal VC can be a low-voltage terminal, and the second power supply terminal VB can be a high-voltage terminal, so that the partition circuit 20 controls the period of current path connection between the first power supply terminal VA and the third node No3, so that the light emission control signal EM is at a low level, thereby realizing the control of the duration of the low level of the light emission control signal EM.

[0139] This application also provides a gate driver GMC, including any of the above-described gate drive circuits GA.

[0140] like Figure 4 This is a schematic diagram of the structure of a gate driver according to an exemplary embodiment of the present disclosure. The gate driver GMC may include multiple cascaded gate driving circuits GA, which are configured to output multiple light emission control signals EM.

[0141] In some embodiments, to reduce the control complexity of multiple gate drive circuits GA, multiple cascaded gate drive circuits GA are electrically connected to a partition control line FL, so that multiple gate drive circuits GA are controlled by the partition control signal SEN transmitted on the same partition control line FL, thereby realizing the control of the output level of multiple light emission control signals EM.

[0142] Optionally, to achieve cascading configuration of multiple gate drive circuits GA, the start signal STV corresponding to the Nth stage gate drive circuit GA(N) can be either the start signal STF or the signal of the second node No2 in the NAth stage gate drive circuit GA(NA). Where N≥1, A≥1, and both N and A are positive integers.

[0143] In some embodiments, the start signal STV corresponding to the first-stage gate drive circuit GA(1) can be the start signal STF, and the start signal STV corresponding to the second-stage gate drive circuit GA(2) can be the signal of the second node No2 in the first-stage gate drive circuit GA(1), and so on, to obtain the start signals STV corresponding to other gate drive circuits GA. Similarly, cascaded designs with A values ​​of 2 or 3 can also be obtained.

[0144] Optionally, the multi-stage gate driver circuit GA can be electrically connected to Z clock lines, which are configured to transmit corresponding clock signals XCK to the multiple gate driver circuits GA. The Z signals transmitted by the Z clock lines have the same phase difference sequentially. The ZK+B-th stage gate driver circuit GA (ZK+B) is electrically connected to the B-th clock line among the Z clock lines. The B-th clock line is configured to transmit the corresponding clock signal XCK to the ZK+B-th stage gate driver circuit GA (ZK+B), thereby reducing the number of clock signals XCK applied by the gate driver GMC and thus reducing power consumption. Where Z ≥ 2, K ≥ 0, and 1 ≤ B ≤ Z.

[0145] In some embodiments, Z=2. The Z clock lines include a first clock line CL1 and a second clock line CL2, as shown below. Figure 4 As shown. The first clock line CL1 is configured to transmit the first clock signal CK1, and the second clock line CL2 is configured to transmit the second clock signal CK2. Specifically, the first clock line CL1 is electrically connected to the 2K+1 stage gate driver circuit GA(2K+1), and is configured to transmit the corresponding clock signal XCK to the 2K+1 stage gate driver circuit GA(2K+1); the second clock line CL2 is electrically connected to the 2K+2 stage gate driver circuit GA(2K+2), and is configured to transmit the corresponding clock signal XCK to the 2K+2 stage gate driver circuit GA(2K+2). Similarly, designs for Z equal to 4, 6, 8, or 12 can also be obtained, which will not be elaborated here.

[0146] Figures 5A-5D This is a timing diagram corresponding to the gate driver of an exemplary embodiment of this disclosure. To facilitate understanding of the gate driver GMC of this application, the gate drive circuit GA is used... Figure 2A The design shown employs multiple gate drive circuits (GAs). Figure 4Taking the design of the gate driver GMC as an example, with the clock signal XCK corresponding to the M-th stage gate driver circuit GA(M) being the first clock signal CK1 and the clock signal XCK corresponding to the M+1-th stage gate driver circuit GA(M+1) being the second clock signal CK2, the working principle of the gate driver GMC is illustrated.

[0147] During the first time period ti1, the start signal STV(M) corresponding to the M-stage gate drive circuit GA(M) is high, the first clock signal CK1 is high, and the second clock signal CK2 and the partition control signal SEN are low. The M-stage gate drive circuit GA(M) has the same characteristics as... Figure 3A The fourth stage t4 has the same operating state, and the gate drive circuit GA(M+1) of the M+1 stage has the same... Figure 3A The third stage t3 has the same operating state, and the gate drive circuit GA(M+2) of the M+2 stage has the same characteristics as... Figure 3A The second stage t2 has the same operating state, and the M+3 stage gate drive circuit GA(M+3) has the same characteristics as... Figure 3A The first stage t1 is the same operating state. Therefore, the Mth stage light emission control signal EM(M) output by the Mth stage gate driver circuit GA(M) to the M+3rd stage light emission control signal EM(M+3) output by the M+3rd stage gate driver circuit GA(M+3) are low. Where M≥1.

[0148] During the second time period ti2, the start signal STV(M) corresponding to the M-stage gate drive circuit GA(M) is high, the first clock signal CK1 and the partition control signal SEN are low, and the second clock signal CK2 is high. The M-stage gate drive circuit GA(M) has the same characteristics as... Figure 3A The fifth stage t5 has the same operating state, and the gate drive circuit GA(M+1) of the M+1 stage has the same... Figure 3A The fourth stage t4 has the same operating state, and the gate drive circuit GA(M+2) of the M+2 stage has the same... Figure 3A The third stage t3 has the same operating state, and the M+3rd stage gate drive circuit GA(M+3) has the same characteristics as... Figure 3A The second stage t2 is the same working state. Therefore, the Mth stage light emission control signal EM(M) is high level, and the M+1 stage light emission control signal EM(M+1) output by the M+1 stage gate drive circuit GA(M+1) to the M+3 stage light emission control signal EM(M+3) output by the M+3 stage gate drive circuit GA(M+3) are low level.

[0149] During the third time period ti3, the start signal STV(M) corresponding to the M-stage gate drive circuit GA(M) is low, the first clock signal CK1 is high, and the second clock signal CK2 and the partition control signal SEN are low. The M-stage gate drive circuit GA(M) has the same characteristics as... Figure 3A The sixth stage t6 has the same operating state, and the gate drive circuit GA(M+1) of the M+1 stage has the same... Figure 3A The fifth stage t5 has the same operating state, and the gate drive circuit GA(M+2) of the M+2 stage has the same characteristics as... Figure 3A The fourth stage t4 has the same operating state, and the gate drive circuit GA(M+3) of the M+3 stage has the same characteristics as... Figure 3A The third stage t3 is the same working state. Therefore, the Mth stage light emission control signal EM(M) and the M+1th stage light emission control signal EM(M+1) are high level, and the M+2th stage light emission control signal EM(M+2) output by the M+2th stage gate drive circuit GA(M+2) to the M+3th stage light emission control signal EM(M+3) output by the M+3th stage gate drive circuit GA(M+3) are low level.

[0150] In the fourth time period ti4, the start signal STV(M) corresponding to the M-stage gate drive circuit GA(M) is low, the first clock signal CK1 and the partition control signal SEN are low, and the second clock signal CK2 is high. The M-stage gate drive circuit GA(M) has the same characteristics as... Figure 3A The seventh stage t7 has the same operating state, and the gate drive circuit GA(M+1) of the M+1 stage has the same... Figure 3A The sixth stage t6 has the same operating state, and the gate drive circuit GA(M+2) of the M+2 stage has the same characteristics as... Figure 3A The fifth stage t5 has the same operating state, and the gate drive circuit GA(M+3) of the M+3 stage has the same characteristics as... Figure 3A The fourth stage t4 is the same working state. Therefore, the light emission control signals EM(M+1) to EM(M+2) of the M+1 stage are high level, and the light emission control signals EM(M) of the M stage and EM(M+3) of the M+3 stage are low level.

[0151] Similarly, we can also obtain the working principle of the multi-stage gate drive circuit GA cascaded after the M+3 stage gate drive circuit GA(M+3) when the corresponding partition control signal SEN is low.

[0152] At the first transition time tk1, the partition control signal SEN transitions from low to high. Because the first partition transistor Tf1 is turned off in the gate drive circuit GA cascaded before the P-stage gate drive circuit GA(P), the light emission control signal EM output from each gate drive circuit GA cascaded before the P-stage gate drive circuit GA(P) remains low. Meanwhile, in the P-stage gate drive circuit GA(P), the first partition transistor Tf1 and the first selection transistor Tx1 are turned on, thus forming a current path between the signal output terminal EOT of the P-stage gate drive circuit GA(P) and the third power supply terminal VC.

[0153] In the fifth time period ti5, the start signal STV(P-2) corresponding to the P-2 stage gate drive circuit GA(P-2) is low. The start signal STV corresponding to the P-stage gate drive circuit GA(P) is low, the clock signal XCK corresponding to the P-stage gate drive circuit GA(P) is the first clock signal CK1, and the first clock signal CK1 and the partition control signal SEN are high, while the second clock signal CK2 is low. The P-stage gate drive circuit GA(P) has the same... Figure 3B The sixth stage t6 has the same operating state, and the P+1 stage gate drive circuit GA(P+1) has the same... Figure 3B The fifth stage t5 has the same operating state, and the gate drive circuit GA(P-1) of the P-1 stage has the same characteristics as... Figure 3A The seventh stage t7 has the same operating state, and the gate drive circuit GA(P-2) of the P-2 stage has the same characteristics as... Figure 3A The operating state is the same as that in the period following the seventh stage t7. Therefore, the P-th stage light emission control signal EM(P) output by the P-th gate driver to the P+1-th stage light emission control signal EM(P+1) output by the P+1-th stage gate driver are at a high level, and the P-2-th stage light emission control signal EM(P-2) output by the P-2-th stage gate driver circuit GA(P-2) to the P-1-th stage light emission control signal EM(P-1) output by the P-1-th stage gate driver circuit GA(P-1) are at a low level. Where P > 2.

[0154] During the sixth time period ti6, the start signal STV corresponding to the P-stage gate drive circuit GA(P) is low, the second clock signal CK2 and the partition control signal SEN are high, and the first clock signal CK1 is low. The P-stage gate drive circuit GA(P) has the same characteristics as... Figure 3B The seventh stage t7 has the same operating state, and the P+1 stage gate drive circuit GA(P+1) has the same... Figure 3BThe sixth stage t6 is the same working state. Therefore, the P-th stage light emission control signal EM(P) to the P+1 stage light emission control signal EM(P+1) output by the P-th stage gate driver are at a high level, and the P-2 stage light emission control signal EM(P-2) output by the P-2 stage gate driver circuit GA(P-2) to the P-1 stage light emission control signal EM(P-1) output by the P-1 stage gate driver circuit GA(P-1) are at a low level.

[0155] During the seventh time period ti7, the start signal STV corresponding to the P-stage gate drive circuit GA(P) is low, the first clock signal CK1 and the partition control signal SEN are high, and the second clock signal CK2 is low. The P-stage gate drive circuit GA(P) has the same characteristics as... Figure 3B The eighth stage t8 has the same operating state, and the P+1 stage gate drive circuit GA(P+1) has the same... Figure 3B The seventh stage t7 is the same working state. Therefore, the P-th stage light emission control signal EM(P) to the P+1 stage light emission control signal EM(P+1) output by the P-th stage gate driver are at a high level, and the P-2 stage light emission control signal EM(P-2) output by the P-2 stage gate driver circuit GA(P-2) to the P-1 stage light emission control signal EM(P-1) output by the P-1 stage gate driver circuit GA(P-1) are at a low level.

[0156] Similarly, we can also obtain the working principle of the multi-stage gate drive circuit GA cascaded after the P+1 stage gate drive circuit GA(P+1) when the corresponding partition control signal SEN is high.

[0157] At the second transition time tk2, the partition control signal SEN transitions from high to low. Because the first partition transistor Tf1 is turned off in the gate drive circuit GA cascaded before the Q-stage gate drive circuit GA(Q), the light emission control signal EM output from each gate drive circuit GA cascaded before the Q-stage gate drive circuit GA(Q) remains high. Meanwhile, in the Q-stage gate drive circuit GA(Q), the first partition transistor Tf1, the second selection transistor Tx2, and the third selection transistor Tx3 are turned on, thus forming a current path between the signal output terminal EOT of the Q-stage gate drive circuit GA(Q) and the third power supply terminal VC.

[0158] During the eighth time period ti8, the start signal STV(Q-2) of the Q-2 stage gate drive circuit GA(Q-2) is low, the start signal STV of the Q stage gate drive circuit GA(Q) is low, the clock signal XCK of the Q stage gate drive circuit GA(Q) is the first clock signal CK1, and the second clock signal CK2 and the partition control signal SEN are low, while the first clock signal CK1 is high. The Q stage gate drive circuit GA(Q) has the same characteristics as... Figure 3A The sixth stage t6 has the same operating state, and the Q+1 stage gate drive circuit GA(Q+1) has the same... Figure 3A The fifth stage t5 has the same operating state, and the gate drive circuit GA(Q-1) of the Q-1 stage has the same characteristics as... Figure 3B The seventh stage t7 has the same operating state, and the gate drive circuit GA(Q-2) of the Q-2 stage has the same characteristics as... Figure 3B The eighth stage t8 operates in the same state. Therefore, the light emission control signal EM(Q-2) output from the gate driver of the (Q-2)th stage to the light emission control signal EM(Q+1) output from the gate driver of the (Q-2)th stage are at a high level. Where Q > 2.

[0159] During the ninth time period ti9, the start signal STV corresponding to the Q-stage gate drive circuit GA(Q) is low, the first clock signal CK1 and the partition control signal SEN are low, and the second clock signal CK2 is low. The Q-stage gate drive circuit GA(Q) has the same characteristics as... Figure 3A The seventh stage t7 has the same operating state, and the Q+1 stage gate drive circuit GA(Q+1) has the same... Figure 3A The sixth stage t6 is the same working state. Therefore, the Q-th stage light emission control signal EM(Q) output by the Q-th stage gate driver is low, the Q+1 stage light emission control signal EM(Q+1) output by the Q+1 stage gate driver is high, and the Q-2 stage light emission control signal EM(Q-2) to the Q-1 stage light emission control signal EM(Q-1) are high.

[0160] During the tenth time period ti10, the start signal STV corresponding to the Q-stage gate drive circuit GA(Q) is low, the second clock signal CK2 and the partition control signal SEN are low, and the first clock signal CK1 is high. The Q+1 stage gate drive circuit GA(Q+1) has the same characteristics as... Figure 3A The seventh stage t7 is the same operating state. Therefore, the Q-th stage light emission control signal EM(Q) to the Q+1-th stage light emission control signal EM(Q+1) output by the Q-th stage gate drive is at a low level, and the Q-2-th stage light emission control signal EM(Q-2) to the Q-1-th stage light emission control signal EM(Q-1) is at a high level.

[0161] Similarly, we can also obtain the working principle of the multi-stage gate drive circuit GA cascaded after the Q+1 stage gate drive circuit GA(Q+1) when the corresponding partition control signal SEN is high.

[0162] It should be noted that, Figure 5C and Figure 5D The diagram illustrates the design of the corresponding gate drive circuit GA, which selects different times as the second transition time tk2 during operation.

[0163] It should be understood that since the gate driver GMC includes any of the aforementioned gate drive circuits GA, the gate driver GMC provided in this application has all the beneficial effects of the aforementioned gate drive circuits GA, which will not be elaborated here.

[0164] This application also provides a display panel including any of the above-described gate drive circuits GA or gate drivers GMC.

[0165] like Figure 6 This is a schematic diagram of the structure of a display panel according to an exemplary embodiment of this disclosure. This application also provides a display panel, which may further include multiple sub-pixels Spx, which are used to implement the display function of the display panel.

[0166] Optionally, the display panel may include multiple pixels arranged in an array. Each pixel may include multiple sub-pixels (Spx). In some embodiments, each pixel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors.

[0167] In some embodiments, the first sub-pixel emits light in red, the second sub-pixel emits light in green, and the third sub-pixel emits light in blue.

[0168] Optionally, at least one sub-pixel Spx may include a first light-emitting device LE1. The first light-emitting device LE1 may be an organic light-emitting diode, a sub-millimeter light-emitting diode, or a micro light-emitting diode.

[0169] Optionally, the sub-pixel Spx, including the first light-emitting device LE1, can be used to implement a privacy display on the display panel.

[0170] In some embodiments, when a sub-pixel Spx including the first light-emitting device LE1 is used to implement a privacy display, the first light-emitting device LE1 can be configured to be in a non-light-emitting state. When a sub-pixel Spx including the first light-emitting device LE1 is used to implement a non-privacy display, the first light-emitting device LE1 can be configured to be in a light-emitting state.

[0171] In other embodiments, when the sub-pixel Spx including the first light-emitting device LE1 is used to implement a privacy display, the first light-emitting device LE1 can be configured to be in an emitting state. When the sub-pixel Spx including the first light-emitting device LE1 is used to implement a non-privacy display, the first light-emitting device LE1 can be configured to be in a non-emitting state.

[0172] Optionally, to achieve light emission control of the first light-emitting device LE1, the sub-pixel Spx of the first light-emitting device LE1 may further include a pixel driving circuit SPD. The pixel driving circuit SPD is electrically connected to the first light-emitting device LE1. The pixel driving circuit SPD is configured to control the on / off of the flow path of the driving current supplied to the first light-emitting device LE1 according to the corresponding light emission control signal EM, so as to control whether the driving current flows through or does not flow through the first light-emitting device LE1, thereby controlling whether the first light-emitting device LE1 emits light or not, and then controlling the sub-pixel Spx of the first light-emitting device LE1 to realize the display switching between non-peeping display and peeping display.

[0173] Optionally, to provide the required light emission control signal EM to the pixel driving circuit SPD, the display panel may further include multiple gate driving circuits GA, which are cascaded together. Multiple sub-pixels Spx are electrically connected to the multiple gate driving circuits GA. The signal output terminal EOT of each gate driving circuit GA is used to output the light emission control signal EM, so as to provide the corresponding light emission control signal EM to the multiple pixel driving circuits SPD through the multiple gate driving circuits GA. Furthermore, since the gate driving circuit GA can adjust the duration of its output signal level under the control of the partition control signal SEN, providing the corresponding light emission control signal EM to the corresponding pixel driving circuit SPD through the gate driving circuit GA allows the sub-pixel Spx applying the light emission control signal EM to control the duration for which the corresponding first light-emitting device LE1 is driven by or not driven by the driving current, thereby making the light emission duration of the first light-emitting device LE1 controllable. This allows the sub-pixel Spx including the first light-emitting device LE1 to switch between privacy protection display and non-privacy protection display, which is beneficial for supporting the display panel to achieve partition privacy protection selection control.

[0174] It should be noted that the cascaded design of multiple gate drive circuits (GA) can be obtained by referring to the relevant description of the gate driver (GMC) mentioned above, and will not be repeated here.

[0175] In some embodiments, the aforementioned start signal STF may be a frame start signal.

[0176] Optionally, to control the light emission duration of at least one first light-emitting device LE1, the partition control signal SEN can be made to switch between a first level and a second level within at least one frame, thereby configuring the partition circuit 20 in at least one gate drive circuit GA to connect the current path between the first power supply terminal VA and the third node No3 according to the signal of the second node No2 and the second level of the partition control signal SEN, and the output circuit 30 is configured to connect the current path between the third power supply terminal VC and the signal output terminal EOT according to the signal of the third node No3.

[0177] As in some embodiments, combined with Figures 5A-5D The timing sequence shown, with the first level being low and the second level being high, is as follows: Within a frame, at the first transition time tk1, the control signal SEN of the control zone changes from the first level to the second level. Correspondingly, the P-level gate drive circuit GA(P) and the gate drive circuits cascaded after GA(P) (referred to as the first type of gate drive circuit) continuously output a high-level light-emitting control signal EM within that frame. This causes the first light-emitting device LE1, included in the sub-pixel Spx electrically connected to the first type of gate drive circuit GA, to not emit light for at least a portion of the time within that frame. If the time period between the start of the fifth stage t5 and the start of the seventh stage t7 corresponding to each gate drive circuit GA is denoted as the first sub-time period, then the first type of gate drive circuit GA can turn on the second selection transistor Tx2 and the third selection transistor Tx3 during the first sub-time period when the corresponding control signal SEN is low, thereby causing the output light-emitting control signal EM to become low at the end of the first sub-time period.

[0178] Optionally, during a time period corresponding to a frame, the partitioning circuit 20 in at least one gate driving circuit GA is configured to control the formation of a current path between the third node No3 and the first node No1 according to the signal of the second node No2 and the partitioning control signal SEN. The output circuit 30 is configured to control the signal output terminal EOT to form a current path between the second power supply terminal VB and the third power supply terminal VC according to the signal of the third node No3, so that the first light-emitting device LE1 included in the sub-pixel Spx electrically connected to the partial gate driving circuit emits light during at least a portion of the time period in that frame.

[0179] Optionally, the partition control signal SEN transitions from a first level to a second level at the first transition time tk1, and the partition control signal SEN transitions from a second level to a first level at the second transition time tk2; wherein the first transition time tk1 and the second transition time tk2 may be located in the same frame or different frames.

[0180] Optionally, in order to control whether the driving current flows through or not through the first light-emitting device LE1 by means of the light-emitting control signal EM, a driving sub-circuit 401 and a first switching sub-circuit 402 can be provided in the sub-pixel Spx including the first light-emitting device LE1.

[0181] like Figure 7 This is a schematic block diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure. Figure 7 The pixel driving circuit SPD of sub-pixel Spx is illustrated by example.

[0182] In a pixel driving circuit SPD comprising a sub-pixel Spx of a first light-emitting device LE1, a driving sub-circuit 401 and a first switching sub-circuit 402 may be included. The driving sub-circuit 401 is electrically connected to the first light-emitting device LE1 and is configured to generate a driving current supplied to the first light-emitting device LE1. The driving sub-circuit 401, the first switching sub-circuit 402, and the corresponding first light-emitting device LE1 are electrically connected between a first voltage terminal Vdd and a second voltage terminal Vss. The first switching sub-circuit 402 is configured to control the on / off state of the path for the driving current to flow between the first voltage terminal Vdd and the second voltage terminal Vss according to a corresponding light-emitting control signal EM.

[0183] In some embodiments, the first switching sub-circuit 402 includes a first light-emitting control sub-circuit 4021, which is electrically connected between the driving sub-circuit 401 and the light-emitting device. The first light-emitting control sub-circuit 4021 is configured to control the on / off state of the driving current flow path between the driving sub-circuit 401 and the first light-emitting device LE1 according to the corresponding light-emitting control signal EM.

[0184] In some embodiments, the first switching sub-circuit 402 includes a second light-emitting control sub-circuit 4022, which is electrically connected between the driving sub-circuit 401 and the first voltage terminal Vdd. The second light-emitting control sub-circuit 4022 is configured to control the on / off state of the current flow path between the driving sub-circuit 401 and the first voltage terminal Vdd according to the corresponding light-emitting control signal EM.

[0185] It should be noted that, Figure 7 The diagram only shows the case where the first switching sub-circuit 402 includes both the first light-emitting control sub-circuit 4021 and the second light-emitting control sub-circuit 4022. However, in practical applications, the first switching sub-circuit 402 may include at least one of the first light-emitting control sub-circuit 4021 and the second light-emitting control sub-circuit 4022. Figure 7 The sub-circuits, signals, and devices shown in dashed lines can be selectively configured; that is, in some embodiments, at least one of the sub-circuits, signals, and devices shown in dashed lines can be omitted or not omitted.

[0186] To achieve controllable brightness of the first light-emitting device LE1, the pixel driving circuit SPD may include a data writing sub-circuit 403. The data writing sub-circuit 403 is electrically connected to the driving sub-circuit 401. The data writing sub-circuit 403 is configured to transmit the corresponding data signal to the driving sub-circuit 401 according to the corresponding first scan signal Scan1, so that the driving sub-circuit 401 generates a driving current according to the corresponding data signal.

[0187] Optionally, the driving sub-circuit 401, the first switching sub-circuit 402, and the data writing sub-circuit 403 can be implemented with switching devices or other components.

[0188] like Figure 8 This is a circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In some embodiments, the driving sub-circuit 401 includes a driving transistor Tdr, the data writing sub-circuit 403 includes a data transistor Tda, and the first switching sub-circuit 402 includes at least one light-emitting control transistor.

[0189] The control terminal of the driving transistor Tdr is configured to receive the corresponding data signal Vda. The first source-drain terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd, and the second source-drain terminal of the driving transistor Tdr is electrically connected to the first light-emitting device LE1.

[0190] The data transistor Tda includes a control terminal configured to receive a corresponding first scan signal Scan1, a first source-drain terminal electrically connected to a corresponding data line, and a second source-drain terminal electrically connected to one of the control terminal of the driving transistor Tdr, the first source-drain terminal of the driving transistor Tdr, and the second source-drain terminal of the driving transistor Tdr.

[0191] It should be noted that, Figure 8 This embodiment only shows an implementation where the data transistor Tda and the driving transistor Tdr are electrically connected to their first source-drain terminals. However, in some embodiments, the second source-drain terminal of the data transistor Tda may be electrically connected to either the control terminal of the driving transistor Tdr or the second source-drain terminal of the driving transistor Tdr.

[0192] When the first switching sub-circuit 402 includes the first light-emitting control sub-circuit 4021, the first light-emitting control sub-circuit 4021 includes the first light-emitting control transistor Ta1. The first light-emitting control transistor Ta1 includes a control terminal configured to receive the corresponding light-emitting control signal EM, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the anode of the first light-emitting device LE1.

[0193] When the first switching sub-circuit 402 includes the second light-emitting control sub-circuit 4022, the second light-emitting control sub-circuit 4022 includes the second light-emitting control transistor Ta2. The second light-emitting control transistor Ta2 includes a control terminal configured to receive the corresponding light-emitting control signal EM, a first source-drain terminal electrically connected to the first voltage terminal Vdd, and a second source-drain terminal electrically connected to the first source-drain terminal of the driving transistor Tdr.

[0194] In some embodiments, in the same sub-pixel Spx, the control terminal of the first light-emitting control transistor Ta1 and the control terminal of the second light-emitting control transistor Ta2 receive the same light-emitting control signal EM.

[0195] Optionally, the pixel driving circuit SPD may further include a first storage sub-circuit 407, such as Figure 7 As shown, the first storage sub-circuit 407 is electrically connected to the control terminal of the driving transistor Tdr, and the first storage sub-circuit 407 is configured to maintain the potential of the control terminal of the driving transistor Tdr.

[0196] In some embodiments, the first storage sub-circuit 407 includes a first storage capacitor Cst, such as Figure 8 As shown, the first storage capacitor Cst is electrically connected between the control terminal of the driving transistor Tdr and the first voltage terminal Vdd.

[0197] Optionally, when the second source-drain terminal of the data transistor Tda is electrically connected to the first source-drain terminal of the driving transistor Tdr, the pixel driving circuit SPD may further include a second storage capacitor Cbt, which is electrically connected between the control terminal of the data transistor Tda and the control terminal of the driving transistor Tdr.

[0198] Optionally, to reduce the impact of the threshold voltage of the driving transistor Tdr on the driving current, the pixel driving circuit SPD can also include a compensation sub-circuit 404, such as... Figure 7 As shown, the compensation sub-circuit 404 is electrically connected to the driving transistor Tdr, and the compensation sub-circuit 404 is configured to compensate the threshold voltage of the driving transistor Tdr according to the corresponding second scan signal Scan2.

[0199] In some embodiments, the compensation sub-circuit 404 includes a compensation transistor Tc, such as Figure 8 As shown, the compensation transistor Tc includes a control terminal configured to receive the corresponding second scan signal Scan2, a first source-drain terminal electrically connected to one of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the control terminal of the driving transistor Tdr.

[0200] In some embodiments, the second source-drain terminal of the data transistor Tda is electrically connected to one of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr, and the second source-drain terminal of the compensation transistor Tc is electrically connected to the other of the first source-drain terminal and the second source-drain terminal of the driving transistor Tdr.

[0201] Optionally, to reduce the impact of residual charge at the control terminal of the driving transistor Tdr on the driving current, the pixel driving circuit SPD may further include a first initialization sub-circuit 405, such as... Figure 7 As shown, the first initialization sub-circuit 405 is electrically connected to the driving transistor Tdr. The first initialization sub-circuit 405 is configured to reset the potential of the control terminal of the driving transistor Tdr according to the corresponding third scan signal Scan3.

[0202] In some embodiments, the first initialization sub-circuit 405 includes a first initial transistor Ti1, such as Figure 8 As shown, the first initial transistor Ti1 includes a control terminal configured to receive the corresponding third scan signal Scan3, a first source-drain terminal electrically connected to the control terminal of the driving transistor Tdr, and a second source-drain terminal configured to receive the first initial signal Vi1.

[0203] Optionally, to reduce the impact of residual charge on the anode of the first light-emitting device LE1 on the brightness of the first light-emitting device LE1, the pixel driving circuit SPD may include a second initialization sub-circuit 406, such as... Figure 7 As shown, the second initialization sub-circuit 406 is electrically connected to the anode of the first light-emitting device LE1, and the second initialization sub-circuit 406 is configured to reset the potential of the anode of the first light-emitting device LE1 according to the corresponding fourth scan signal Scan4.

[0204] In some embodiments, the second initialization sub-circuit 406 includes a second initial transistor Ti2, such as Figure 8 As shown, the second initial transistor Ti2 includes a control terminal configured to receive the corresponding fourth scan signal Scan4, a first source-drain terminal electrically connected to the anode of the first light-emitting device LE1, and a second source-drain terminal configured to receive the second initial signal Vi2.

[0205] Optionally, to enable switching between privacy and non-privacy display modes on the display panel, the display panel may also include multiple second light-emitting devices LE2. The second light-emitting devices LE2 may be organic light-emitting diodes, sub-millimeter light-emitting diodes, or micro light-emitting diodes.

[0206] Optionally, the characteristic parameters of each second light-emitting device LE2 may be the same as or different from those of any other second light-emitting device LE2. The characteristic parameters include at least one of the following: luminous efficiency, light-emitting area, light-emitting aperture, light-emitting material, and viewing angle.

[0207] In some embodiments, the same sub-pixel Spx may simultaneously include a first light-emitting device LE1 and a second light-emitting device LE2. In other embodiments, a first type of sub-pixel includes the first light-emitting device LE1, and a second type of sub-pixel includes the second light-emitting device LE2, so that the first light-emitting device LE1 and the second light-emitting device LE2 are included in different sub-pixels Spx.

[0208] In some embodiments, when the sub-pixel Spx including the second light-emitting device LE2 is used to implement both privacy and non-privacy displays, the second light-emitting device LE2 can be configured to be in an emitting state. In other embodiments, when the sub-pixel Spx including the second light-emitting device LE2 is used to implement a privacy display, the second light-emitting device LE2 can be configured to be in a non-emitting state. When the sub-pixel Spx including the second light-emitting device LE2 is used to implement a non-privacy display, the second light-emitting device LE2 can be configured to be in an emitting state.

[0209] To facilitate understanding of the operating states of the first light-emitting device LE1 and the second light-emitting device LE2 in this application, corresponding to both privacy and non-privacy display modes, an example is provided where a sub-pixel Sp includes both the first light-emitting device LE1 and the second light-emitting device LE2. However, it should be noted that the first light-emitting device LE1 and the second light-emitting device LE2 can also be disposed in different sub-pixels Sp.

[0210] In some embodiments, a first privacy protection design is employed. That is, when the sub-pixel Spx, including the first light-emitting device LE1 and the second light-emitting device LE2, is used to achieve a privacy display, the first light-emitting device LE1 does not emit light, while the second light-emitting device LE2 emits light. When the sub-pixel Spx, including the first light-emitting device LE1 and the second light-emitting device LE2, is used to achieve a non-privacy display, both the first light-emitting device LE1 and the second light-emitting device LE2 emit light. The luminous efficiency, luminous area, light-emitting aperture, and luminous material of the first light-emitting device LE1 and the second light-emitting device LE2 may be the same or different.

[0211] In other embodiments, a second privacy protection design is employed. That is, when the sub-pixel Spx, including the first light-emitting device LE1 and the second light-emitting device LE2, is used to achieve a privacy display, the first light-emitting device LE1 emits light, while the second light-emitting device LE2 does not emit light. When the sub-pixel Spx, including the first light-emitting device LE1 and the second light-emitting device LE2, is used to achieve a non-privacy display, the first light-emitting device LE1 does not emit light, while the second light-emitting device LE2 emits light. At least one of the luminous efficiency, luminous area, light-emitting aperture, and luminous material of the first light-emitting device LE1 and the second light-emitting device LE2 may be different. Optionally, the light-emitting aperture of the first light-emitting device LE1 is smaller than the light-emitting aperture of the second light-emitting device LE2.

[0212] Optionally, within the same sub-pixel Spx, the emission color of the first light-emitting device LE1 is the same as the emission color of the second light-emitting device LE2.

[0213] Optionally, within the same sub-pixel Spx, a separate pixel driving circuit SPD can be provided for the second light-emitting device LE2 to control whether the second light-emitting device LE2 emits light or not. The pixel driving circuit SPD corresponding to the second light-emitting device LE2 can be designed with reference to the pixel driving circuit SPD corresponding to the first light-emitting device LE1, and will not be described in detail here.

[0214] Optionally, to facilitate high-resolution design of the display panel, reduce power consumption, and save costs, the first light-emitting device LE1 and the second light-emitting device LE2 of the same sub-pixel Spx can share a pixel driving circuit SPD.

[0215] In some embodiments, the second light-emitting device LE2 is electrically connected between the driving sub-circuit 401 of the corresponding pixel driving circuit SPD and the second voltage terminal Vss. The driving current generated by the driving sub-circuit 401 of the pixel driving circuit SPD is also configured to drive the second light-emitting device LE2 to emit light. By allowing the first light-emitting device LE1 and the second light-emitting device LE2 to share the pixel driving circuit SPD, the number of transistors and capacitors included in the display panel is reduced, thereby facilitating the high-resolution design of the display panel, reducing power consumption, and saving costs.

[0216] Optionally, to reduce the impact of residual charge on the anode of the second light-emitting device LE2 on the brightness of the second light-emitting device LE2, the pixel driving circuit SPD may include a third initialization sub-circuit 410, such as... Figure 7 As shown, the third initialization sub-circuit 410 is electrically connected to the anode of the second light-emitting device LE2, and the third initialization sub-circuit 410 is configured to reset the potential of the anode of the second light-emitting device LE2 according to the corresponding fourth scan signal Scan4.

[0217] In some embodiments, the third initialization sub-circuit 410 includes a third initial transistor Ti3, such as Figure 8 As shown, the third initial transistor Ti3 includes a control terminal configured to receive the corresponding fourth scan signal Scan4, a first source-drain terminal electrically connected to the anode of the second light-emitting device LE2, and a second source-drain terminal configured to receive the third initial signal Vi3.

[0218] Optionally, the pixel driving circuit SPD may also include a second switching sub-circuit 408, such as Figure 7 As shown, the second switch sub-circuit 408 is electrically connected between the driver sub-circuit 401 and the first voltage terminal Vdd. The second switch sub-circuit 408 is configured to control the on / off state of the current flow path between the driver sub-circuit 401 and the first voltage terminal Vdd according to the corresponding switch control signal EMa. By setting the second switch sub-circuit 408, when the first light-emitting device LE1 and the second light-emitting device LE2 share the pixel driver circuit SPD, the light emission control of the second light-emitting device LE2 can be made independent of the light emission control of the first light-emitting device LE1.

[0219] In some embodiments, the second switching sub-circuit 408 includes a third light-emitting control transistor Ta3, such as Figure 8 As shown, the third light-emitting control transistor Ta3 includes a control terminal configured to receive the corresponding switch control signal EMA, a first source-drain terminal electrically connected to the first voltage terminal Vdd, and a second source-drain terminal electrically connected to the first source-drain terminal of the driving transistor Tdr.

[0220] Optionally, a switching sub-circuit can also be provided between the driving sub-circuit 401 and the second light-emitting device LE2 to control the driving current to drive or not drive the second light-emitting device LE2. In some embodiments, the pixel driving circuit SPD may also include a third switching sub-circuit 409, such as... Figure 7 As shown, the third switch sub-circuit 409 is electrically connected between the driver sub-circuit 401 and the second light-emitting device LE2. The third switch sub-circuit 409 is configured to control the on / off state of the current flow path between the driver sub-circuit 401 and the second light-emitting device LE2 according to the corresponding switch control signal EMa.

[0221] In some embodiments, the third switching sub-circuit 409 includes a fourth light-emitting control transistor Ta4, such as Figure 8 As shown, the fourth light-emitting control transistor Ta4 includes a control terminal configured to receive the corresponding switch control signal EMA, a first source-drain terminal electrically connected to the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected to the anode of the second light-emitting device LE2.

[0222] Optionally, to reduce the probability of flickering and other problems, the pixel driving circuit SPD may also include a fourth initialization sub-circuit 411. The fourth initialization sub-circuit 411 is electrically connected to the first source-drain terminal of the driving transistor Tdr. The fourth initialization sub-circuit 411 is configured to control the transmission of the fourth initial signal Vi4 to the first source-drain terminal of the driving transistor Tdr according to the corresponding fourth scan signal Scan4.

[0223] In some embodiments, the fourth initialization sub-circuit 411 includes a fourth initialization transistor Ti4, such as Figure 8 As shown, the fourth initial transistor Ti4 includes a control terminal configured to receive the corresponding fourth scan signal Scan4, a first source-drain terminal electrically connected to the first source-drain terminal of the driving transistor Tdr, and a second source-drain terminal configured to receive the fourth initial signal Vi4.

[0224] It should be noted that the transistors included in the pixel driving circuit SPD can be P-type transistors or N-type transistors, and the transistors can be silicon transistors or oxide transistors. The potential of the first voltage terminal Vdd can be higher than the potential of the second voltage terminal Vss.

[0225] It should be understood that, Figure 8 The pixel driving circuit SPD shown is merely an example to facilitate understanding of this application. In practical applications, those skilled in the art will modify the specific implementation of each sub-circuit in the pixel driving circuit SPD according to different actual needs.

[0226] Figures 9A-9B This is a timing diagram corresponding to the pixel driving circuit of an exemplary embodiment of this disclosure. To facilitate understanding of the design of the pixel driving circuit SPD for implementing a privacy display in this application, we will first use... Figure 8 Taking the pixel driving circuit SPD shown as an example, the first type of privacy protection design corresponding to the pixel driving circuit SPD will be explained. Specifically, the first initial transistor Ti1 and the compensation transistor Tc in the pixel driving circuit SPD are N-type transistors, while the remaining transistors are P-type transistors.

[0227] When a privacy display is implemented for a sub-pixel Spx, which includes a first light-emitting device LE1 and a second light-emitting device LE2, the operating timing of the pixel driving circuit SPD includes a first initial stage tb1, a second initial stage tb2, a data writing stage tw, a third initial stage tb3, and a light-emitting stage tl. The first scan signal Scan1 corresponding to the sub-pixel Spx is one of the m-th level first scan signal Scan(m) and the (m+1)-th level first scan signal Scan(m+1), where m ≥ 1.

[0228] Please continue reading. Figure 8 and Figure 9A In the first initial stage (tb1), the second scan signal Scan2 is at a low level, while the light emission control signal EM, the switch control signal EMa, the first scan signal Scan1, the third scan signal Scan3, and the fourth scan signal Scan4 are at a high level. The first initial transistor Ti1 is turned on to reset the control terminal potential of the driving transistor Tdr.

[0229] In the second initial stage tb2, the light emission control signal EM, the switch control signal EMa, the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 are at high levels. The first initial transistor Ti1 and the compensation transistor Tc are turned on to reset the potentials of the control terminal, the first source-drain terminal, and the second source-drain terminal of the driving transistor Tdr.

[0230] During the data writing phase (tw): the first scan signal Scan1 and the third scan signal Scan3 are at low level, while the light emission control signal EM, the switch control signal EMa, the second scan signal Scan2, and the fourth scan signal Scan4 are at high level. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal and the threshold voltage of the drive transistor Tdr are stored at the control terminal of the drive transistor Tdr.

[0231] In the third initial stage tb3, the second scan signal Scan2, the third scan signal Scan3, and the fourth scan signal Scan4 are at low levels, while the light emission control signal EM, the switch control signal EMa, and the first scan signal Scan1 are at high levels. The second initial transistor Ti2 to the fourth initial transistor Ti4 are turned on to reset the potentials of the first source-drain terminal of the driving transistor Tdr, the anode of the first light-emitting device LE1, and the anode of the second light-emitting device LE2.

[0232] During the light-emitting stage tl, the switch control signal EMa, the second scan signal Scan2, and the third scan signal Scan3 are at low levels, while the light-emitting control signal EM, the first scan signal Scan1, and the fourth scan signal Scan4 are at high levels. The third light-emitting control transistor Ta3 and the fourth light-emitting control transistor Ta4 are turned on, while the first light-emitting control transistor Ta1 and the second light-emitting control transistor Ta2 are turned off. The first light-emitting device LE1 does not emit light, while the second light-emitting device LE2 emits light.

[0233] When a sub-pixel Spx, including a first light-emitting device LE1 and a second light-emitting device LE2, is implemented as a non-peeping display, the operating timing of the pixel driving circuit SPD can still include a first initial stage tb1, a second initial stage tb2, a data writing stage tw, a third initial stage tb3, and a light-emitting stage tl. However, when the sub-pixel Spx is implemented as a non-peeping display, the light-emitting control signal EM is low during the light-emitting stage tl to control the first light-emitting device LE1 to be driven by the driving current to emit light.

[0234] Please continue reading. Figure 8 and Figure 9B During the light-emitting stage tl, the light-emitting control signal EM, the switch control signal EMa, the second scan signal Scan2, and the third scan signal Scan3 are at low levels, while the first scan signal Scan1 and the fourth scan signal Scan4 are at high levels. The first light-emitting control transistor Ta1 to the fourth light-emitting control transistor Ta4 are turned on, and both the first light-emitting device LE1 and the second light-emitting device LE2 emit light.

[0235] Therefore, by controlling the level of the light emission control signal EM, the working state of the first light-emitting device LE1 can be controlled, thereby realizing the switching control between privacy display and non-privacy display.

[0236] When implementing the second type of privacy protection design using a pixel driver circuit (SPD), the SPD can still include a first initial stage (tb1) to a second initial stage (tb2), a data writing stage (tw), a third initial stage (tb3), and an emission stage (tl). However, the level settings of the emission control signal EM and the switch control signal EMa corresponding to the emission stage (tl) are different. Figures 9A-9B The difference lies in the implementation. Specifically, when a sub-pixel Spx, including the first light-emitting device LE1 and the second light-emitting device LE2, is used to implement a privacy display, the light-emitting control signal EM can be set to a low level during the light-emitting phase tl, while the switch control signal EMa is set to a high level. This turns on the first light-emitting control transistor Ta1 and the second light-emitting control transistor Ta2, causing the first light-emitting device LE1 to emit light; the third light-emitting control transistor Ta3 and the fourth light-emitting control transistor Ta4 are turned off, and the second light-emitting device LE2 does not emit light. Conversely, when a sub-pixel Spx, including the first light-emitting device LE1 and the second light-emitting device LE2, is used to implement a non-privacy display, the light-emitting control signal EM can be set to a high level during the light-emitting phase tl, while the switch control signal EMa is set to a low level. This turns off the first light-emitting control transistor Ta1 and the second light-emitting control transistor Ta2, causing the first light-emitting device LE1 to not emit light; the third light-emitting control transistor Ta3 and the fourth light-emitting control transistor Ta4 are turned on, and the second light-emitting device LE2 emits light.

[0237] It should be understood that, by referring to the working principle of the pixel driving circuit SPD corresponding to different privacy protection designs, it can be similarly obtained that when the first light-emitting control transistor Ta1 and the second light-emitting control transistor Ta2 in the pixel driving circuit SPD are N-type transistors, the sub-pixel Spx, together with the gate driving circuit GA, realizes the design of privacy protection and non-privacy protection display. This will not be elaborated further here.

[0238] Alternatively, to reduce the number of gate drive circuits GA included in the gate driver GMC, each gate drive circuit GA can be electrically connected to multiple sub-pixels Spx.

[0239] In some embodiments, such as the Nth-level gate drive circuit GA(N), a plurality of sub-pixels Spx located in row 2N-1 and a plurality of sub-pixels Spx located in row 2N are electrically connected.

[0240] Optionally, in order to provide the required scanning signal and switching control signal EMa to each sub-pixel Spx, the display panel may also include multiple gating drivers. The design of the gating drivers can be obtained with reference to the gate driver GMC or related technologies, and will not be described in detail here.

[0241] In some embodiments, the plurality of gating drivers includes a first gating driver, which includes a plurality of cascaded gating driver circuits. Each gating driver circuit generates a switch control signal EMA. The gating driver circuit may have the same circuit topology as the gate driver circuit GA, and the partition control signal SEN applied by the gating driver circuit and the partition control signal SEN applied by the gate driver circuit GA are independent of each other, so as to realize the second privacy protection design described above by using the first gating driver in conjunction with the gate driver GMC. It should be understood that when the gating driver circuit and the gate driver circuit GA have the same circuit topology, referring to the working principle of the gate driver GMC and the light emission control signal EM controlling the first light-emitting device LE1 to emit or not emit light, the working principle of the first gating driver and the switch control signal EMA controlling the second light-emitting device LE2 to emit or not emit light can be obtained accordingly, which will not be elaborated here.

[0242] In some embodiments, in the H frame, when the second light-emitting device LE2 included in the plurality of sub-pixels Spx located in the i-th row is configured to emit light according to the corresponding driving current, the first switching sub-circuit 402 is configured to control the flow path of the driving current supplied to the first light-emitting device LE1 to be disconnected according to the corresponding light-emitting control signal EM; when the second light-emitting device LE2 of the plurality of sub-pixels Spx located in the j-th row is configured to emit light according to the corresponding driving current, the first switching sub-circuit 402 is configured to control the flow path of the driving current supplied to the first light-emitting device LE1 to be connected according to the corresponding light-emitting control signal EM; wherein, H≥1, i≥1, j≥1, i≠j, the plurality of sub-pixels Spx located in the i-th row and the plurality of sub-pixels Spx located in the j-th row are electrically connected to gate driving circuits GA of different levels, so that in the H frame, the display panel simultaneously has privacy protection display and privacy protection display.

[0243] In some embodiments, the first gating driver includes multiple cascaded gating driving circuits, the circuit topology of which is the same as that of the gate driving circuit GA. Corresponding to the H-th frame, when the second light-emitting device LE2 of multiple sub-pixels Spx located in the i-th row is configured to emit light according to the corresponding driving current, the first switching sub-circuit 402 is configured to control the disconnection of the path of the driving current supplied to the first light-emitting device LE1 according to the corresponding light-emitting control signal EM; when the first light-emitting device LE1 of multiple sub-pixels Spx located in the j-th row is configured to emit light according to the corresponding driving current, the third switching sub-circuit 409 is configured to control the disconnection of the path of the driving current supplied to the second light-emitting device LE2 according to the corresponding switching control signal EMa. Wherein, H≥1, i≥1, j≥1, i≠j, and the multiple sub-pixels located in the i-th row and the multiple sub-pixels located in the j-th row are electrically connected to gate driving circuits GA of different levels, and the multiple sub-pixels located in the i-th row and the multiple sub-pixels located in the j-th row are electrically connected to gating driving circuits of different levels.

[0244] For ease of understanding this application, it will still be referred to as Figures 5A-5D Taking the timing sequence as an example, this paper explains how to implement multi-zone privacy or non-privacy display on a display panel.

[0245] Please continue reading. Figures 5A-5D , Figure 8 and Figure 9AIn frame H, the M-th level gate drive circuit GA(M) to the (P-1)-th level gate drive circuit GA(P-1), under the action of the partition control signal SEN corresponding to the gate driver GMC being low, control the M-th level light emission control signal EM(M) to the (P-1)-th level light emission control signal EM(P-1) to sequentially output high levels, and correspondingly switch from high levels to low levels, so that the first light emission device LE1 of the multiple sub-pixels Spx in the first pixel group emits light in the corresponding light emission stage tl. The first pixel group includes pixel rows electrically connected to the M-th level gate drive circuit GA(M) to the (P-1)-th level gate drive circuit GA(P-1), and each pixel row includes multiple sub-pixels Spx.

[0246] Corresponding to the first privacy protection design, the M-level gating drive circuit to the P-1-level gating drive circuit control the M-level switch control signal to the P-1-level switch control signal to output high level in sequence, and switch from high level to low level in sequence, so that the second light-emitting device LE2 of the multiple sub-pixels Spx in the first pixel group emits light in the corresponding light-emitting stage tl, thereby enabling the multiple sub-pixels Spx in the first pixel group to achieve non-privacy display.

[0247] For the second type of privacy protection design, the gating drive circuit and the gate driver GMC have the same circuit topology. Under the action of the partition control signal SEN corresponding to the first gating driver being high, the M-th to P-1-th level gating drive circuits continuously output high levels of the M-th to P-1-th level switch control signals. This causes the second light-emitting devices LE2 of the multiple sub-pixels Spx in the first pixel group to not emit light during the corresponding light-emitting stage tl, thereby enabling the multiple sub-pixels Spx in the first pixel group to achieve privacy protection display.

[0248] Corresponding to frame H, the P-level gate driving circuit GA(P) to the Q-1-level gate driving circuit GA(Q-1), under the action of the partition control signal SEN corresponding to the gate driver GMC being at a high level, control the P-level light emission control signal EM(P) to the Q-1-level light emission control signal EM(Q-1) to continuously output a high level, causing the first light-emitting device LE1 of the multiple sub-pixels Spx in the second pixel group to not emit light during the corresponding light emission stage tl. The second pixel group includes pixel rows electrically connected to the P-level gate driving circuit GA(P) to the Q-1-level gate driving circuit GA(Q-1), and each pixel row includes multiple sub-pixels Spx.

[0249] Corresponding to the first privacy protection design, the P-level switch control signal to the Q-1-level switch control signal output by the P-level gating drive circuit to the Q-1-level gating drive circuit are sequentially output at high level, and are sequentially switched from high level to low level, so that the second light-emitting device LE2 of the multiple sub-pixels Spx in the second pixel group emits light in the corresponding light-emitting stage tl, thereby enabling the multiple sub-pixels Spx in the two pixel group to achieve privacy protection display.

[0250] For the second type of privacy protection design, the gating drive circuit and the gate driver GMC have the same circuit topology. Under the action of the partition control signal SEN corresponding to the first gating driver being low, the P-level gating drive circuit to the Q-1-level gating drive circuit sequentially output high levels and correspondingly switch from high to low levels, causing the second light-emitting devices LE2 of the multiple sub-pixels Spx in the second pixel group to emit light in the corresponding light-emitting stage tl, thus enabling the multiple sub-pixels Spx in the second pixel group to achieve non-privacy display.

[0251] It should be noted that when multiple sub-pixels Spx in the first pixel group adopt the first privacy protection design, multiple sub-pixels Spx in the second pixel group can also adopt the first privacy protection design. Similarly, when multiple sub-pixels Spx in the first pixel group adopt the second privacy protection design, multiple sub-pixels Spx in the second pixel group can also adopt the second privacy protection design. In the above embodiments, the first light-emitting control transistor Ta1 and the second light-emitting control transistor Ta2 are P-type transistors as examples, along with the corresponding light-emitting control signal EM. However, in practical applications, the first light-emitting control transistor Ta1 and the second light-emitting control transistor Ta2 can also be N-type transistors. Correspondingly, the gate driving circuit GA is used to achieve controllable design of the low-level duration of the light-emitting control signal EM under the action of the partition control signal SEN.

[0252] It should be understood that by controlling the level of the partition control signal SEN, the privacy display area can be arbitrarily changed. Therefore, the boundary between privacy display and non-privacy display is not limited to a two-pixel partition privacy. Moreover, a sub-pixel Spx that implements privacy display in one frame can switch to non-privacy display in another frame. The display panel can also have multiple privacy and non-privacy display areas corresponding to the same frame.

[0253] It should be noted that the above embodiments only illustrate the privacy-protecting partitioned display of this application using two privacy-protecting designs as examples. However, in practical applications, it is not limited to the above two privacy-protecting designs. For example, in one embodiment, one of the first light-emitting device LE1 and the second light-emitting device LE2 can also be used as an interference source to achieve privacy protection. In privacy-protecting display mode, both the first light-emitting device LE1 and the second light-emitting device LE2 emit light, and the light emitted by the first light-emitting device LE1 is used to interfere with the light emitted by the second light-emitting device LE2 to achieve privacy protection. In non-privacy-protecting display mode, the first light-emitting device LE1 does not emit light, and the second light-emitting device LE2 emits light. Combining the relevant descriptions of the above two privacy-protecting designs, it is similar to obtain a design in which one of the first light-emitting device LE1 and the second light-emitting device LE2 is used as an interference source to achieve partitioned privacy protection, which will not be elaborated here.

[0254] Furthermore, since the display panel of this application includes any of the aforementioned gate drive circuits GA or gate drivers GMC, the display panel has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0255] Figure 10 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure. This application also provides a display device including any of the above-described display panels.

[0256] In some embodiments, the display device may further include a timing controller electrically connected to a plurality of gate drives, the timing controller being configured to output a partition control signal SEN to a plurality of gate drive circuits GA.

[0257] In some embodiments, the display device may further include a source controller, a source driver electrically connected to multiple data lines in the display panel, and the source driver being configured to provide the required data signals to the display panel.

[0258] Optionally, the display panel may also include components not shown, such as a graphics processor and a power management chip.

[0259] Since the display device of this application includes any of the above-mentioned display panels, the display device has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0260] It should be noted that the gate drive circuit GA of this application can also be used to control multiple sub-pixels Spx to have different display frequencies.

[0261] In some embodiments, the light emission control signal EM generated by the gate drive circuit GA can be provided to the control terminal of the compensation transistor Tc or the control terminal of the first initial transistor Ti1 to control the frequency at which the sub-pixel Spx receives the corresponding data signal, thereby controlling the display refresh frequency of the sub-pixel Spx.

[0262] When the gate drive circuit GA is applied in the display panel, multiple gate drive circuits GA can still be cascaded to form a gate driver GMC, but multiple gate driver GMCs are not cascaded with each other.

[0263] In some embodiments, the display panel may include two gate drivers, namely a first gate driver and a second gate driver. Each gate driving circuit GA in the first gate driver is electrically connected to the control terminal of the compensation transistor Tc of a plurality of sub-pixels Spx in at least one pixel row, and each gate driving circuit GA in the second gate driver is electrically connected to the control terminal of the first initial transistor Ti1 of a plurality of sub-pixels Spx in at least one pixel row.

[0264] To facilitate understanding of the gate driving circuit GA provided in this embodiment, the light emission control signal EM output by each gate driving circuit GA in the first gate driver GMC to the compensation transistor Tc is abbreviated as the first control signal, and the light emission control signal EM output by each gate driving circuit GA in the second gate driver GMC to the first initial transistor Ti1 is abbreviated as the second control signal. When controlling multiple sub-pixels Spx to have different display frequencies, a display cycle may include multiple frames. In the first frame of the multiple frames, the pixel driving circuit SPD of each sub-pixel Spx sequentially goes through the stages of resetting the control terminal of the driving transistor Tdr (as described in the first initial stage tb1 above), writing data signals (as described in the data writing stage tw above), and driving the light-emitting device to emit light. Within at least one frame following the first frame in a display cycle, the first and second control signals corresponding to multiple sub-pixels Spx located in rows F to G can be deactivated, thus preventing these sub-pixels Spx from undergoing the reset and data writing phase of the driving transistor Tdr. This allows the sub-pixels Spx in rows F to G to maintain the same display content as in the first frame. Conversely, by ensuring that the first and second control signals corresponding to multiple sub-pixels Spx in rows G and later have valid pulses, these sub-pixels Spx in rows G and later again undergo the reset and data writing phase of the driving transistor Tdr. This refreshes the content displayed by the sub-pixels Spx in rows G and later, enabling the design of multiple sub-pixels Spx having different display frequencies. Where F ≥ 1, G > F.

[0265] It should be noted that when the compensation transistor Tc is an N-type transistor, the effective pulse of the first control signal corresponds to the design when the first control signal is at a high level, and the invalid pulse of the first control signal corresponds to the design when the first control signal is at a low level. When the compensation transistor Tc is a P-type transistor, the effective pulse of the first control signal corresponds to the design when the first control signal is at a low level, and the invalid pulse of the first control signal corresponds to the design when the first control signal is at a high level. Similarly, the designs for the effective and invalid pulses of the second control signal can also be obtained. Therefore, since the gate drive circuit GA can control the duration of the output light emission control signal EM using the partition control signal SEN, when the light emission control signal EM is used as the first or second control signal, the operating duration of the compensation transistor Tc and the first initial transistor Ti1 can be controlled, thereby achieving frequency control of the data signal received by the sub-pixel Spx.

[0266] Therefore, depending on the object to be controlled corresponding to the light emission control signal EM generated by the gate driving circuit GA, the gate driving circuit GA provided in this application can be used to support the display panel to realize multi-area privacy selection control, and can also support the display panel to realize multi-area display frequency control.

[0267] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, include: A cascade circuit, electrically connected to the first node and the second node, is configured to control the signal of the first node to be in phase with the signal of the second node according to a start signal and a clock signal; A partitioning circuit, electrically connected to the first node, the second node, and the third node, is configured to control one of the first node and the first power supply terminal to form a current path with the third node based on the signal from the second node and the partitioning control signal. The output circuit, electrically connected to the third node, is configured to control one of the second power supply terminal and the third power supply terminal to form a current path between the signal output terminal of the gate drive circuit according to the signal of the third node. Wherein, when the partitioning circuit is configured to control the formation of a current path between the first power supply terminal and the third node, the output circuit is configured to control the formation of a current path between the third power supply terminal and the signal output terminal according to the signal of the third node.

2. The gate driving circuit according to claim 1, characterized in that, The voltage of the first power signal supplied by the first power supply terminal is different from the voltage of the second power signal supplied by the second power supply terminal, and the voltage of the first power signal is the same as the voltage of the third power signal supplied by the third power supply terminal.

3. The gate driving circuit according to claim 1, characterized in that, The partitioning circuit includes: A partition control sub-circuit, electrically connected to the second node and the fourth node, is configured to control the signal of the fourth node according to the signal of the second node and the partition control signal; The partition selection sub-circuit, electrically connected to the fourth node, is configured to control, based on a signal from the fourth node, one of the first node and the first power supply terminal to form a current path between the third node and the first node.

4. The gate driving circuit according to claim 3, characterized in that, When the partition control subcircuit is configured to control the signal of the fourth node to the second level according to the signal of the second node and the first level of the partition control signal, the partition selection subcircuit is configured to connect the current path between the first node and the third node according to the signal of the fourth node; When the partition control subcircuit is configured to control the signal of the fourth node to the first level according to the signal of the second node and the second level of the partition control signal, the partition selection subcircuit is configured to connect the current path between the first power supply terminal and the third node according to the signal of the fourth node; Wherein, the first level is one of a high level and a low level, and the second level is the other of a high level and a low level.

5. The gate driving circuit according to claim 3, characterized in that, The partition control sub-circuit includes: A node control sub-circuit, electrically connected to the second node and electrically connected to the fourth node through the fifth node, is configured to control the signal transmission between the partition control line transmitting the partition control signal and the fifth node according to the signal from the second node. During the period when the node control subcircuit connects the current path between the partition control line and the fifth node according to the signal of the second node, the partition selection subcircuit controls the formation of a current path between the third node and the first node or the first power supply terminal, and the output circuit is configured to control the formation of a current path between the third power supply terminal and the signal output terminal according to the signal of the third node. During the period when the node control subcircuit disconnects the current path between the partition control line and the fifth node according to the signal of the second node, and the partition selection subcircuit is configured to control the formation of a current path between the first node and the third node, the output circuit is configured to control the formation of a current path between the second power supply terminal and the signal output terminal according to the signal of the third node.

6. The gate driving circuit according to claim 5, characterized in that, A first inverting sub-circuit, electrically connected between the fourth node and the fifth node, is configured to control the signal of the fourth node to be inverted with the signal of the fifth node; as well as A storage sub-circuit, electrically connected to the fifth node, is configured to maintain the potential of the fifth node.

7. The gate driving circuit according to claim 6, characterized in that, The node control sub-circuit includes a first partition transistor, which includes a control terminal electrically connected to the second node, a first source-drain terminal electrically connected to the partition control line, and a second source-drain terminal electrically connected to the fifth node. The first inverting sub-circuit includes a second partition transistor and a third partition transistor. The control terminals of the second partition transistor and the third partition transistor are electrically connected to the fifth node. The first source-drain terminal of the second partition transistor is electrically connected to the first power supply terminal. The first source-drain terminal of the third partition transistor is electrically connected to the fourth power supply terminal. The second source-drain terminal of the second partition transistor and the second source-drain terminal of the third partition transistor are electrically connected to the fourth node. The storage sub-circuit includes a first capacitor, which is electrically connected between the fourth power supply terminal and the fifth node; The majority carrier type of the second partition transistor is different from that of the third partition transistor.

8. The gate driving circuit according to claim 7, characterized in that, The first partition transistor is an N-type oxide transistor, and the threshold voltage of the first partition transistor is greater than 0.

9. The gate driving circuit according to claim 3, characterized in that, The partition selection sub-circuit includes: A first selection sub-circuit, electrically connected between the first power supply terminal and the third node, is configured to control signal transmission between the first power supply terminal and the third node based on a signal from the fourth node; and The second selector circuit, electrically connected between the first node and the third node, is configured to control the signal transmission between the first node and the third node based on the signal from the fourth node.

10. The gate driving circuit according to claim 9, characterized in that, The second selection sub-circuit includes: A second inverting sub-circuit, electrically connected between the fourth node and the sixth node, is configured to control the signal of the sixth node to be inverted compared to the signal of the fourth node; and A transmission gate circuit, electrically connected between the first node and the third node, is configured to control signal transmission between the first node and the third node based on signals from the fourth node and the sixth node.

11. The gate driving circuit according to claim 10, characterized in that, The first selection sub-circuit includes a first selection transistor, which includes a control terminal electrically connected to the fourth node, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the third node. The transmission gate circuit includes a second selection transistor and a third selection transistor. The second selection transistor includes a control terminal electrically connected to the fourth node, a first source-drain terminal electrically connected to the first node, and a second source-drain terminal electrically connected to the third node. The third selection transistor includes a control terminal electrically connected to the sixth node, a first source-drain terminal electrically connected to the first node, and a second source-drain terminal electrically connected to the third node. The second inverting sub-circuit includes a fourth selection transistor and a fifth selection transistor. The control terminals of the fourth and fifth selection transistors are electrically connected to the fourth node. The first source-drain terminal of the fourth selection transistor is electrically connected to the first power supply terminal. The first source-drain terminal of the fifth selection transistor is electrically connected to the fourth power supply terminal. The second source-drain terminals of the fourth and fifth selection transistors are electrically connected to the sixth node. The majority carrier type of the first selection transistor is the same as that of the third selection transistor, and the majority carrier type of the first selection transistor is different from that of the second selection transistor.

12. The gate driving circuit according to claim 11, characterized in that, During the period when the first selection transistor is configured to be on according to the signal of the fourth node, the second selection transistor is configured to be off according to the signal of the fourth node, the third selection transistor is configured to be off according to the signal of the sixth node, and the fourth selection transistor is configured to be on according to the signal of the fourth node; During the period when the first selection transistor is configured to be off according to the signal of the fourth node, the second selection transistor is configured to be on according to the signal of the fourth node, the third selection transistor is configured to be on according to the signal of the sixth node, and the fifth selection transistor is configured to be on according to the signal of the fourth node.

13. The gate driving circuit according to claim 11, characterized in that, The voltage of the first power signal supplied by the first power supply terminal is greater than the voltage of the fourth power signal supplied by the fourth power supply terminal. Wherein, the first selection transistor and the third selection transistor are both P-type transistors, and the second selection transistor is an N-type transistor.

14. The gate driving circuit according to claim 5 or 6, characterized in that, The transmission circuit includes: The first sub-circuit, electrically connected to the first node via the seventh node, is configured to control the signals of the seventh node and the first node according to the start signal and the clock signal; The second sub-circuit, electrically connected to the second node and the seventh node, is configured to control the signal of the second node to be in phase with the signal of the first node based on the signal of the seventh node; The third sub-circuit, electrically connected to the second sub-circuit at the eighth node and electrically connected to the seventh node, is configured to control the signal transmission between the fourth power supply terminal and the seventh node according to the signal from the eighth node, and is also configured to control the signal transmission between the first power supply terminal and the seventh node according to the signal from the eighth node and the clock signal.

15. The gate driving circuit according to claim 14, characterized in that, The second sub-circuit is configured to control the signal transmission between the second node and the first power supply terminal and the fourth power supply terminal according to the signal of the seventh node; Specifically, during the period when the second sub-circuit is configured to connect the current path between the first power supply terminal and the second node, the node control sub-circuit is configured to connect the current path between the partition control line and the fifth node; during the period when the second sub-circuit is configured to connect the current path between the fourth power supply terminal and the second node, the node control sub-circuit is configured to disconnect the current path between the partition control line and the fifth node.

16. The gate driving circuit according to claim 14, characterized in that, The first sub-circuit includes: A start control sub-circuit, electrically connected to the seventh node, is configured to control the signal transmission between the seventh node and the first power supply terminal and the fourth power supply terminal according to the start signal and the clock signal; The third inverting sub-circuit, electrically connected between the seventh node and the first node, is configured to control the signal of the first node to be inverted with the signal of the seventh node; The second node and the eighth node are the same node.

17. The gate driving circuit according to claim 14, characterized in that, The second sub-circuit includes: A fourth inverting sub-circuit, electrically connected between the seventh node and the eighth node, is configured to control the signal at the eighth node to be inverted compared to the signal at the seventh node; and The fifth inverting sub-circuit, electrically connected between the second node and the eighth node, is configured to control the signal of the second node to be inverted with the signal of the eighth node; Wherein, the first node and the seventh node are the same node, and the first sub-circuit is configured to control the signal transmission between the start signal line transmitting the start signal and the seventh node according to the clock signal.

18. The gate driving circuit according to claim 14, characterized in that, The transmission circuit also includes: A reset sub-circuit, electrically connected to the seventh node, is configured to reset the potential of the seventh node according to a reset control signal.

19. The gate driving circuit according to claim 5 or 6, characterized in that, The output circuit includes: An output control sub-circuit, electrically connected between the third node and the ninth node, is configured to control the signal of the ninth node to be inverted compared to the signal of the third node; and... The gate output sub-circuit, electrically connected between the ninth node and the signal output terminal, is configured to control, according to the signal from the ninth node, one of the second power supply terminal and the third power supply terminal to form a current path between the signal output terminal and the signal output terminal.

20. The gate driving circuit according to claim 19, characterized in that, During the period when the node control subcircuit connects the current path between the partition control line and the fifth node according to the signal of the second node, the output control subcircuit is configured to connect the current path between the second power supply terminal and the ninth node according to the signal of the third node, and the gate output subcircuit is configured to connect the current path between the third power supply terminal and the signal output terminal according to the signal of the ninth node. During the period when the node control subcircuit disconnects the current path between the partition control line and the fifth node according to the signal of the second node, and the partition selection subcircuit is configured to control the formation of a current path between the first node and the third node, the output control subcircuit is configured to connect the current path between the third power supply terminal and the ninth node according to the signal of the third node, and the gate output subcircuit is configured to connect the current path between the second power supply terminal and the signal output terminal according to the signal of the ninth node.

21. The gate driving circuit according to claim 20, characterized in that, The output control sub-circuit includes a first output transistor and a second output transistor. The control terminals of the first output transistor and the second output transistor are electrically connected to the third node. The first source-drain terminal of the first output transistor is electrically connected to the third power supply terminal. The first source-drain terminal of the second output transistor is electrically connected to the second power supply terminal. The second source-drain terminal of the first output transistor and the second source-drain terminal of the second output transistor are electrically connected to the ninth node. The gate output sub-circuit includes a third output transistor and a fourth output transistor. The control terminals of the third output transistor and the fourth output transistor are electrically connected to the ninth node. The first source-drain terminal of the third output transistor is electrically connected to the third power supply terminal. The first source-drain terminal of the fourth output transistor is electrically connected to the second power supply terminal. The second source-drain terminals of the third and fourth output transistors are electrically connected to the signal output terminal. The majority carrier type of the first output transistor is different from that of the second output transistor, the majority carrier type of the third output transistor is different from that of the fourth output transistor, and the majority carrier type of the first output transistor is the same as that of the third output transistor.

22. A display panel, characterized in that, include: A plurality of gate driving circuits as described in any one of claims 1 to 21, wherein the plurality of gate driving circuits are cascaded, and the signal output terminal of each gate driving circuit is used to output a light emission control signal; Multiple sub-pixels are electrically connected to multiple gate driving circuits. Each sub-pixel includes a pixel driving circuit and a first light-emitting device. The pixel driving circuit is configured to control the on / off state of the flow path of the driving current supplied to the first light-emitting device according to the light-emitting control signal output by the corresponding gate driving circuit.

23. The display panel according to claim 22, characterized in that, Within at least one frame, the partition control signal has a transition between a first level and a second level; In at least one of the gate driving circuits, the partitioning circuit is configured to connect the current path between the first power supply terminal and the third node according to the signal of the second node and the second level of the partitioning control signal, and the output circuit is configured to connect the current path between the third power supply terminal and the signal output terminal according to the signal of the third node.

24. The display panel according to claim 23, characterized in that, During a time period corresponding to a frame, at least one of the gate driving circuits is configured to control the formation of a current path between the third node and the first node according to the signal of the second node and the partition control signal, and the output circuit is configured to control the formation of a current path between the signal output terminal and the second power supply terminal and the third power supply terminal in a time-division manner according to the signal of the third node.

25. The display panel according to claim 22, characterized in that, Each pixel driving circuit includes a driving sub-circuit and a first switching sub-circuit, wherein the driving sub-circuit, the first switching sub-circuit, and the corresponding first light-emitting device are electrically connected between a first voltage terminal and a second voltage terminal. The driving sub-circuit is configured to generate the driving current, and the first switching sub-circuit is configured to control the opening and closing of the path for the driving current to flow between the first voltage terminal and the second voltage terminal according to the corresponding light emission control signal.

26. The display panel according to claim 22, characterized in that, It also includes multiple secondary light-emitting devices; The characteristic parameters of each of the second light-emitting devices are different from those of any of the first light-emitting devices, and the characteristic parameters include at least one of luminous efficiency, luminous area and light emission angle.

27. A display device, characterized in that, include: The display panel as described in any one of claims 22 to 26; as well as A timing controller, electrically connected to a plurality of the gate drive circuits, is configured to output the partition control signal to the plurality of the gate drive circuits.

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