Display device

Abstract

Disclosed are display devices. The display device includes a display panel including a plurality of gate lines and a plurality of data lines, and at least one data driving integrated circuit configured to supply a data signal to each of the plurality of data lines. In the plurality of data lines driven by one data driving integrated circuit, some data lines disposed in a center area are directly connected to the data driving integrated circuit, and the remaining data lines disposed on the left and right are not directly connected to the data driving integrated circuit, but are electrically connected to the data lines directly connected to the data driving integrated circuit via a plurality of connection lines within a display area.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2025-0057090, filed on April 30, 2025, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to display devices, and more particularly to display devices capable of achieving narrow bezels. Background Technology

[0003] Image display devices that reproduce various information on a screen are a core technology of the information and communication age, and are being developed to be thinner, lighter, more portable, and have higher performance. Therefore, display devices that can be manufactured in a lightweight and thin form are attracting attention.

[0004] Representative examples of display devices include, but are not limited to, liquid crystal display (LCD) devices, quantum dot display (QD) devices, field emission display (FED) devices, and organic light-emitting diode (OLED) display devices.

[0005] OLED displays are self-emissive display devices. Therefore, OLED displays are advantageous in terms of power consumption due to their low-voltage driving characteristics, and also offer excellent color performance, high response speed, wide viewing angle, and high contrast ratio (CR). Consequently, OLED displays are currently being developed as the next generation of display devices.

[0006] Research is underway in this type of OLED display device to increase the display area while reducing the bezel area, which serves as the non-display area.

[0007] In recent OLED display devices, the number of data driver ICs driving the data lines has been reduced to maintain price competitiveness. As the number of data driver ICs decreases, the number of data lines driven by each IC increases, inevitably increasing the width of the wiring area connecting the pads of the data driver ICs to the data lines. Therefore, a reduction in the number of data driver ICs may result in an increase in the bezel area. Summary of the Invention

[0008] Therefore, this disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0009] One aspect of this disclosure is to provide a display device that can achieve a narrow bezel even when the number of data-driven integrated circuits is reduced to ensure price competitiveness.

[0010] The aspects to be achieved by this disclosure are not limited to those mentioned above. Other aspects not mentioned herein will be clearly understood by those skilled in the art through the following description.

[0011] Additional advantages, aspects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon reviewing the following, or may be learned from practice of this disclosure. Aspects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description of this disclosure, its claims, and the accompanying drawings.

[0012] A display device according to an embodiment of the present disclosure includes: a display panel including a plurality of gate lines and a plurality of data lines; and at least one data driver integrated circuit configured to supply a data signal to each of the plurality of data lines. Among the plurality of data lines driven by the data driver integrated circuit, some data lines located in the central region are directly connected to the data driver integrated circuit, while the remaining data lines located on the left and right sides are not directly connected to the data driver integrated circuit, but are electrically connected within the display area via a plurality of connecting lines to the data lines directly connected to the data driver integrated circuit.

[0013] Multiple connecting lines can have the same length.

[0014] Multiple connection lines can be placed at the center of the longitudinal direction of multiple data lines.

[0015] Each of the multiple connecting lines can be connected to each other to achieve the same color data lines.

[0016] Some data lines set in the central area can correspond to half of multiple data lines, and the remaining data lines set on the left and right sides can correspond to the remaining half of multiple data lines.

[0017] The direct connection of multiple data lines to the data driver integrated circuit can be divided into data lines located in region B-1 and data lines located in region B-2. Furthermore, data lines located on one side and the opposite side of regions B-1 and B-2 can be divided into data lines located in region A-1 and data lines located in region A-2. Data lines located in region A-1 can be electrically connected to data lines located in region B-1 via some of the multiple connecting lines, and data lines located in region A-2 can be electrically connected to data lines located in region B-2 via the remaining connecting lines.

[0018] The number of data lines set in area A-1, the number of data lines set in area A-2, the number of data lines set in area B-1, and the number of data lines set in area B-2 can be the same.

[0019] The data input time for data lines set in areas A-1 and A-2 can be longer than the data input time for data lines set in areas B-1 and B-2.

[0020] Multiple sub-pixels can be set between the (4k-3)th gate line and the (4k-2)th gate line, and between the (4k-1)th gate line and the 4kth gate line, and no sub-pixels can be set between the (4k-2)th gate line and the (4k-1)th gate line, and between the 4kth gate line and the (4k+1)th gate line.

[0021] Two subpixels can be set between one pair of data lines and another pair of data lines, and no subpixels can be set between this pair of data lines and between this pair of data lines.

[0022] Subpixels in regions A-1 and A-2 can be driven by even-numbered gate lines, and subpixels in regions B-1 and B-2 can be driven by odd-numbered gate lines.

[0023] Subpixels in regions A-1 and A-2 can be driven by odd-numbered gate lines, and subpixels in regions B-1 and B-2 can be driven by even-numbered gate lines.

[0024] The display device may also include a reference voltage line disposed between two sub-pixels disposed between one pair of data lines and another pair of data lines.

[0025] Multiple sub-pixels can be set between corresponding gate lines in a plurality of gate lines. A sub-pixel can be set between the (4k-3)th and (4k-2)th data lines and between their corresponding gate lines in a plurality of data lines, and a sub-pixel can be set between the (4k-1)th and 4kth data lines and between their corresponding gate lines. No sub-pixels can be set between the (4k-2)th and (4k-1)th data lines and between the 4kth and (4k+1)th data lines.

[0026] The display device may also include a reference voltage line disposed between the (4k-2) data line and the (4k-1) data line and between the 4k data line and the (4k+1) data line.

[0027] Multiple interconnect lines can be formed from the same material as multiple gate lines.

[0028] It should be understood that both the foregoing general description of this disclosure and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings:

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0031] Figure 2 This is a circuit diagram of pixels included in a display device according to an embodiment of the present disclosure.

[0032] Figure 3 This is a cross-sectional view of one of the sub-pixels disposed in the display area of ​​the display panel according to an embodiment of the present disclosure;

[0033] Figure 4A This is a plan view illustrating data lines and a plurality of data-driven integrated circuits according to embodiments of the present disclosure;

[0034] Figure 4B This is a plan view illustrating data lines and a plurality of data-driven integrated circuits according to another embodiment of the present disclosure;

[0035] Figure 5A This is a plan view illustrating multiple data lines driven by a data driver integrated circuit according to an embodiment of the present disclosure;

[0036] Figure 5B This is a plan view illustrating multiple data lines driven by a data driver integrated circuit according to another embodiment of the present disclosure;

[0037] Figure 6 It is a plan view showing the RC delay variation of multiple data lines driven by a data driver integrated circuit according to an embodiment of the present disclosure in a second (e.g., vertical) direction and a first (e.g., horizontal) direction.

[0038] Figure 7 This is a view showing the data input time and data charging rate of the data lines in regions A and B according to an embodiment of the present disclosure;

[0039] Figure 8A This is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to an embodiment of the present disclosure;

[0040] Figure 8BThis is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to another embodiment of the present disclosure;

[0041] Figure 9 It is along Figure 8A The schematic cross-sectional view of the connecting line shown;

[0042] Figure 10A This is a view illustrating the layout of gate lines, data lines, and sub-pixels in regions A-1 and B-1 according to yet another embodiment of the present disclosure; and

[0043] Figure 10B This is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to another embodiment of the present disclosure. Detailed Implementation

[0044] Exemplary embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Throughout the specification, the same or similar elements are indicated by the same reference numerals.

[0045] In the following description of embodiments of this disclosure, detailed descriptions of known functions and configurations contained herein will be omitted where such descriptions might make the subject matter of this disclosure rather unclear. Furthermore, the names of elements used in the following description of embodiments of this disclosure have been chosen for ease of preparation of the specification and may therefore differ from the names of components in an actual product.

[0046] The shapes, dimensions, ratios, angles, and numbers of the elements shown in the accompanying drawings for describing embodiments of the present disclosure are merely exemplary, and therefore the present disclosure is not limited to the details shown.

[0047] In the following description of the embodiments, the terms “comprising,” “including,” “containing,” and “having” will be interpreted as indicating the presence of one or more other features, numbers, steps, operations, elements, or components or combinations thereof stated in this specification, and the possibility of the presence or addition of other features, numbers, steps, operations, elements, components, or combinations thereof is not excluded unless terms such as “only” or “merely” are used. It will be understood that, unless otherwise stated, singular expressions of elements include plural expressions.

[0048] In interpreting the elements included in the various embodiments of this disclosure, unless otherwise stated, it should be interpreted that a quantitative description of the characteristics of the elements includes ranges of error or tolerance.

[0049] In the following description of the implementation, it will be understood that when expressing positional relationships, for example, when an element is referred to as being “above,” “on,” “above,” “below,” “under,” “near,” or “next to” another element, the two elements may be in direct contact with each other, or one or more other elements may be inserted between the two elements unless the terms “exactly” or “directly” are used.

[0050] In the following description of the implementation, it should be understood that when expressing temporal relationships, for example, when using terms that express the order of events, such as “after,” “following,” “next,” and “before,” the terms include both sequential and discontinuous relationships between events, unless the terms “exactly” or “directly” are used.

[0051] In the following description of the embodiments, it will be understood that when the terms "first," "second," etc., are used to describe various elements, these terms are only used to distinguish the same or similar elements. Therefore, without departing from the technical scope of this disclosure, the first element described below may be referred to as the second element.

[0052] In the following description of the implementation, the terms "pixel" and "subpixel" may be used interchangeably.

[0053] The various features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may be interlocked or driven in various technical ways. The various embodiments may be implemented independently of each other or may be implemented together through the connection between them.

[0054] In the following description, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0055] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0056] Figure 2 This is a circuit diagram of pixels included in a display device according to an embodiment of the present disclosure.

[0057] like Figure 1As shown, the display device 10 according to an embodiment of the present disclosure may include: a display panel 100 including a plurality of sub-pixels P; a controller 200; a gate driving circuit 300 configured to supply gate signals to the plurality of sub-pixels P; a data driving circuit 400 configured to supply data signals to the plurality of sub-pixels P; a power supply 500 configured to supply power required to drive the plurality of sub-pixels P; a level shifter 600 configured to adjust the potential of the gate signals applied to the gate driving circuit 300; and a sensing unit (not shown) configured to sense degradation of the plurality of sub-pixels P. In this case, the controller 200, the gate driving circuit 300, the data driving circuit 400, and the sensing unit may be collectively referred to as the controller.

[0058] The display panel 100 may include a display area in which a plurality of sub-pixels P are disposed, and a non-display area disposed around the display area. The gate driving circuit 300 and the data driving circuit 400 may be disposed in the non-display area. Alternatively, the gate driving circuit 300 may be disposed in the display area.

[0059] In the display panel 100, multiple gate lines SCL and EML, as well as multiple data lines DL, intersect each other, and each of the multiple sub-pixels P is connected to the gate lines SCL and EML and the data lines DL. Specifically, a sub-pixel P receives a gate signal from the gate driving circuit 300 through the gate lines SCL and EML, receives a data signal from the data driving circuit 400 through the data lines DL, and receives a high-level driving voltage EVDD and a low-level driving voltage EVSS from the power supply 500 through the driving voltage line PL.

[0060] In this configuration, the gate lines SCL and EML may, according to various implementations, comprise multiple scan lines SCL configured to supply scan signals SC and multiple light emission control lines EML configured to supply light emission control signals EM, respectively. The data line DL supplies the data voltage Vdata. Furthermore, the multiple sub-pixels P may also include power lines VL for receiving a reference voltage Vref or an initialization voltage Vini.

[0061] The thin-film transistor (TFT) constituting the sub-pixel P can be implemented as an oxide TFT including an oxide semiconductor layer. Considering electron mobility and process variations, oxide TFTs can be advantageous for increasing the area of ​​the display panel 100. This disclosure is not limited thereto, and the semiconductor layer of the TFT can be formed, for example, amorphous silicon or polycrystalline silicon.

[0062] Furthermore, each of the sub-pixels P may include pixel circuitry configured to control the driving of the OLED light-emitting device. In this case, the OLED may include an anode (ANO), a cathode (CAT), and a light-emitting layer (EL) disposed between the anode (ANO) and the cathode (CAT) (see [link to relevant documentation]). Figure 3 ).

[0063] like Figure 2 As shown, each sub-pixel P may include a switching transistor ST, a driving transistor DT, a compensation circuit CC, a light-emitting device OLED, and a storage capacitor Cst.

[0064] The light-emitting device OLED can be operated to emit light according to the driving current generated by the driving transistor DT.

[0065] The switching transistor ST can perform a switching operation, causing the data signal supplied via the data line DL in response to the scan signal supplied via the scan line SCL to be stored as a data voltage in the storage capacitor Cst. The storage capacitor Cst can maintain the data voltage for one frame.

[0066] The driving transistor DT can be operated such that a constant driving current flows between the high-potential power line EVDD and the low-potential power line EVSS in response to the data voltage stored in the storage capacitor Cst.

[0067] The compensation circuit CC is used to compensate for the threshold voltage of the driving transistor DT. The compensation circuit CC may include one or more thin-film transistors and capacitors. The configuration of the compensation circuit CC can vary widely depending on the compensation method.

[0068] For example, Figure 2 The sub-pixel P shown has a 2T1C (two transistors and one capacitor) structure, including a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and a light-emitting device OLED. When a compensation circuit CC is additionally included, the sub-pixel P can be configured in various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, or 8T1C.

[0069] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and objects in the background are visible. The display panel 100 can be manufactured as a flexible display panel. A flexible display panel can be implemented as an organic light-emitting diode display panel using a substrate made of a flexible material such as plastic.

[0070] Each of the sub-pixels P can be divided into red, green, and blue pixels for color implementation. Each of the sub-pixels P may also include a white pixel. However, the embodiments of this disclosure are not limited thereto. For example, each of the sub-pixels P may include pixels of other colors from other color systems, such as cyan, magenta, yellow, etc. Each of the sub-pixels P includes pixel circuitry.

[0071] A touch sensor can be provided on the display panel 100. Touch input can be sensed using a separate touch sensor or by a sub-pixel P. The touch sensor can be provided on the screen of the display panel in an on-cell or add-on manner, or it can be implemented as an in-cell touch sensor embedded in the display panel 100.

[0072] The controller 200 processes RGB image data input from an external source to suit the size and resolution of the display panel 100, and supplies the processed image data to the data driving circuit 400. The controller 200 uses timing signals CS (e.g., dot clock signal CLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from an external source to generate a gate control signal GCS and a data control signal DCS. The controller 200 controls the gate driving circuit 300 and the data driving circuit 400 by supplying the generated gate control signal GCS and the generated data control signal DCS to the gate driving circuit 300 and the data driving circuit 400, respectively.

[0073] Depending on the device on which the controller 200 is installed, the controller 200 can be combined with various processors (e.g., microprocessors, mobile processors, or application processors).

[0074] The host system can be any of, but is not limited to, a television (TV) system, a laptop, a tablet, a laptop computer, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, a vehicle system, and a vehicle display system.

[0075] The controller 200 can multiply the input frame rate by i (where i is a positive integer greater than 0) to control the operating timing of the display panel driving unit at a frame rate of “input frame rate × i”. The input frame rate is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase Inverter (PAL) scheme.

[0076] Controller 200 generates signals that cause sub-pixel P to be driven at various refresh rates. That is, controller 200 generates signals associated with the driving of sub-pixel P, causing sub-pixel P to be driven in a variable refresh rate (VRR) mode or to be driven to switch between a first refresh rate and a second refresh rate. For example, controller 200 can drive sub-pixel P at various refresh rates by changing the speed of a clock signal, generating a synchronization signal to create horizontal or vertical blanking, or driving the gate drive circuit 300 with a mask scheme.

[0077] The controller 200 generates a gate control signal GCS for controlling the operating timing of the gate drive circuit 300 and a data control signal DCS for controlling the operating timing of the data drive circuit 400 based on the timing signal CS received from the host system. The controller 200 controls the operating timing of the display panel drive unit to synchronize the gate drive circuit 300 and the data drive circuit 400.

[0078] The data driving circuit 400 receives image data DATA and a data control signal DCS from the controller 200. In response to the data control signal DCS from the controller 200, the data driving circuit 400 converts the image data DATA into a gamma-compensated voltage to generate a data voltage Vdata and supplies the data voltage Vdata synchronously with the scan signal SC to the data line DL of the display panel 100. The data driving circuit 400 can be connected to the data line of the display panel 100 via a chip-on-glass (COG) process or a tape-on-brush (TAB) process. Although not shown in the figures, the data driving circuit 400 may include at least one data driving integrated circuit D-IC. For example, the data driving circuit 400 may include one or more data driving integrated circuits D-IC.

[0079] The gate drive circuit 300 operates according to the gate control signal GCS input from the level shifter 600 to generate a gate signal and sequentially supplies the gate signal to the gate lines. The gate drive circuit 300 can be directly formed on the lower substrate of the display panel 100 using an in-panel gate driver (GIP) scheme. The gate drive circuit 300 can be formed in the display area of ​​the displayed image on the display panel 100, or it can be formed in a non-display area outside the display area. The non-display area may include a bezel area, or it may be the same as the bezel area. In the GIP scheme, the level shifter 600 can be mounted on a printed circuit board (PCB) together with the controller 200.

[0080] Power supply 500 uses a DC-DC converter to generate the direct current (DC) power required to drive the pixel array and display panel driving unit of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, or boost converter, etc. Power supply 500 can receive a DC input voltage applied from a host system (not shown) and can generate DC voltages such as gate low voltage VGL and emitter low voltage VEL, gate high voltage VGH and emitter high voltage VEH, high-level drive voltage EVDD, and low-level drive voltage EVSS. Gate low voltage VGL and emitter low voltage VEL, as well as gate high voltage VGH and emitter high voltage VEH, are supplied to a level shifter (not shown) and gate driving unit 300. High-level drive voltage EVDD and low-level drive voltage EVSS are jointly supplied to sub-pixel P.

[0081] The level shifter 600 boosts the transistor-to-transistor logic (TTL) level voltage of the gate control signal GCS input from the controller 200 to a gate high voltage VGH and a gate low voltage VGL capable of driving the TFTs formed in the display panel 100, and supplies the boosted voltage to the gate drive circuit 300. The gate control signal GCS may include a start signal and a clock signal. The plurality of sub-pixels P of the display panel 100 may include at least a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel may emit light of different colors. For example, the first sub-pixel may be a red pixel, the second sub-pixel may be a green pixel, and the third sub-pixel may be a blue pixel. However, the embodiments of this disclosure are not limited thereto.

[0082] Multiple subpixels P can have the same size as each other, or they can have different sizes. Considering, for example, the lifetime or color balance of the light-emitting device OLED included in each of the first, second, and third subpixels, the sizes of the first, second, and third subpixels can be designed to be different from each other.

[0083] The display panel 100 may include an organic light-emitting diode display panel as a self-emissive display panel.

[0084] Figure 3 This is a cross-sectional view of one of the sub-pixels disposed in the display area of ​​the display panel according to an embodiment of the present disclosure.

[0085] like Figure 3 As shown, multiple pixels are arranged in the display panel 100. In each pixel area, a light-emitting device (OLED), transistors TFT1 and TFT2 for driving the light-emitting device, a capacitor CST, and an encapsulation layer 120 can be provided.

[0086] Transistors TFT1 and TFT2 may include silicon thin-film transistors containing polycrystalline semiconductor materials and oxide thin-film transistors containing oxide semiconductor materials. In this case, the thin-film transistor containing polycrystalline semiconductor materials may be referred to as polycrystalline thin-film transistor TFT1, and the thin-film transistor containing oxide semiconductor materials may be referred to as oxide thin-film transistor TFT2. For example, polycrystalline thin-film transistor TFT1 may be a transistor connected to a light-emitting device OLED, and oxide thin-film transistor TFT2 may be a transistor connected to a capacitor CST.

[0087] In another embodiment, the thin-film transistor comprising a polycrystalline semiconductor material may be referred to as a polycrystalline thin-film transistor TFT2, and the thin-film transistor comprising an oxide semiconductor material may be referred to as an oxide thin-film transistor TFT1. For example, the polycrystalline thin-film transistor TFT2 may be a transistor connected to a capacitor CST, and the oxide thin-film transistor TFT1 may be a transistor connected to a light-emitting device OLED.

[0088] In the following text, a thin-film transistor containing polycrystalline semiconductor material will be referred to as polycrystalline thin-film transistor TFT1, and a thin-film transistor containing oxide semiconductor material will be referred to as oxide thin-film transistor TFT2.

[0089] The substrate 111 can be a glass substrate or a flexible substrate. When the substrate 111 is a flexible substrate, it can be implemented as a multilayer structure with alternating organic and inorganic layers. For example, the substrate 111 can be implemented by alternating layers of organic layers, such as polyimide, epoxy resin, phenolic resin, or siloxane, and inorganic layers, such as silicon oxide (SiO2). x It is formed by an inorganic layer (such as silicon dioxide (SiO2)), silicon nitride (SiNx) or silicon oxynitride (SiOxNy).

[0090] A lower buffer layer 112a can be formed on the substrate 111. The lower buffer layer 112a is used to block moisture and other substances from penetrating from the external environment, and can be formed by stacking multiple layers, such as silicon oxide (SiO2). x This can be formed by stacking multiple layers, such as silicon dioxide (SiO2), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). An auxiliary buffer layer 112b can also be disposed on the lower buffer layer 112a to protect the device from moisture penetration. The auxiliary buffer layer 112b can be formed by stacking multiple layers, such as silicon oxide (SiO2) layers. x (e.g., silicon dioxide (SiO2)) layer, silicon nitride (SiNx) layer or silicon oxide nitride (SiOxNy) layer, and may be formed of a material different from the lower buffer layer 112a.

[0091] A polycrystalline thin-film transistor (TFT) 1 can be formed on substrate 111. The TFT 1 can use a polycrystalline semiconductor as its active layer. The TFT 1 may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes can move. A first gate insulating layer 113 can be disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 113 can be formed as a single inorganic layer, such as silicon oxide (SiO2). xIt can be formed by stacking inorganic layers multiple times, such as silicon nitride (SiNx) or silicon oxynitride (SiOxNy) layers.

[0092] The first active layer ACT1 may include a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the opposite side of the first channel region. The first source region and the first drain region are conductive regions formed by doping the intrinsic polycrystalline semiconductor material with group V impurity ions (e.g., phosphorus (P)) or group III impurity ions (e.g., boron (B)) at a predetermined concentration. The first channel region is used to maintain the polycrystalline semiconductor material in its intrinsic state and can provide a path for electrons or holes to move through.

[0093] According to an embodiment, the polycrystalline thin-film transistor TFT1 can be implemented as a top-gate structure with a first gate electrode GE1 disposed above the first active layer ACT1. Therefore, the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the oxide thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. By forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS via a single mask process, the number of mask processes can be reduced.

[0094] The first gate electrode GE1 may be formed of a metal. For example, the first gate electrode GE1 may have a single-layer structure or a multi-layer structure, each layer being formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W), and alloys thereof. However, this disclosure is not limited thereto.

[0095] A first interlayer insulating layer 114 may be disposed on the first gate electrode GE1. The first interlayer insulating layer 114 may be made of, for example, silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)), silicon nitride (SiNx) or silicon oxynitride (SiOxNy) are formed.

[0096] Each sub-pixel P in the display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on a first interlayer insulating layer 114. Each of the upper buffer layer 115 and the second interlayer insulating layer 117 may be made of, for example, silicon oxide (SiO2). x (e.g., SiO2), silicon nitride (SiNx) or silicon oxynitride (SiOxNy) are formed, but not limited thereto.

[0097] The first source electrode SD1 and the first drain electrode SD2 of the polycrystalline thin-film transistor TFT1 can be formed on the second interlayer insulating layer 117. The first source electrode SD1 and the first drain electrode SD2 of the polycrystalline thin-film transistor TFT1 can be connected to the first source region and the first drain region of the first active layer ACT1, respectively, through contact holes penetrating the first gate insulating layer 113, the first interlayer insulating layer 114, the upper buffer layer 115, the second gate insulating layer 116, and the second interlayer insulating layer 117.

[0098] The upper buffer layer 115 can separate the second active layer ACT2 of the oxide thin film transistor TFT2 formed of oxide semiconductor material from the first active layer ACT1 formed of polycrystalline semiconductor material, and can provide a substrate on which the second active layer ACT2 is formed.

[0099] The oxide thin-film transistor TFT2 can be formed on the upper buffer layer 115. The oxide thin-film transistor TFT2 may include a second active layer ACT2 formed of oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116, a second source electrode SD3 disposed on the second interlayer insulating layer 117, and a second drain electrode SD4 disposed on the second interlayer insulating layer 117.

[0100] The second active layer ACT2 may be formed of an oxide semiconductor material and may include an intrinsic second channel region that is undoped and may include a second source region and a second drain region that are doped and thus become conductive.

[0101] The oxide thin-film transistor TFT2 may further include a light-shielding layer LS disposed below the upper buffer layer 115 and overlapping with the second active layer ACT2. The light-shielding layer LS can block light incident through the substrate 111, thereby ensuring the reliability of the oxide thin-film transistor TFT2. The light-shielding layer LS may be formed of the same material as the first gate electrode GE1 and may be disposed on the upper surface of the first gate insulating layer 113. The light-shielding layer LS may be electrically connected to the second gate electrode GE2 to form a dual-gate structure.

[0102] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously on the second interlayer insulating layer 117 from the same material as the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of mask processes.

[0103] The second gate insulating layer 116 can cover the second active layer ACT2 of the oxide thin-film transistor TFT2. Since the second gate insulating layer 116 is formed on the second active layer ACT2, which is formed of an oxide semiconductor material, the second gate insulating layer 116 can be implemented as an inorganic layer. The second gate insulating layer 116 can be made of, for example, silicon oxide (SiO2). x(e.g., silicon dioxide (SiO2)), silicon nitride (SiNx) or silicon oxynitride (SiOxNy) are formed.

[0104] The second gate electrode GE2 can be formed of metal. For example, the second gate electrode GE2 can have a single-layer structure or a multi-layer structure, each layer being formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W), and alloys thereof. However, this disclosure is not limited thereto.

[0105] A first electrode CST1 can be disposed on the first gate insulating layer 113, and a second electrode CST2 can be disposed on the first interlayer insulating layer 114 to overlap with the first electrode CST1, thereby realizing a capacitor CST. The first electrode CST1 can be formed of the same material as the light-shielding layer LS and the first gate electrode GE1.

[0106] For example, the second electrode CST2 can have a single-layer structure or a multi-layer structure, each layer being formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W), and their alloys.

[0107] The capacitor CST can be used to store the data voltage applied through the data line DL for a predetermined time period. The capacitor CST may include two corresponding electrodes and a dielectric disposed between the two electrodes. A first interlayer insulating layer 114 may be disposed between the first electrode CST1 and the second electrode CST2.

[0108] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin-film transistor TFT2. However, this disclosure is not limited thereto. The connection relationship of the capacitor CST can be changed according to the sub-pixel driving circuit.

[0109] A first planarization layer 118 and a second planarization layer 119 for surface planarization can be sequentially disposed on the polycrystalline thin-film transistor TFT1, the oxide thin-film transistor TFT2, and the capacitor CST. The first planarization layer 118 and the second planarization layer 119 can be organic layers formed of, for example, polyimide or acrylic resin. A light-emitting device OLED can be formed on the second planarization layer 119.

[0110] An OLED (Optical Display Panel) may include an anode (ANO), a cathode (CAT), and an emitting layer (EL) disposed between the ANO and the CAT. When the sub-pixel driving circuitry is implemented to share a low-potential power supply voltage connected to the cathode (CAT), the ANO is configured as a separate electrode for each sub-pixel. Alternatively, when the sub-pixel driving circuitry is implemented to share a high-potential power supply voltage, the cathode (CAT) may be configured as a separate electrode for each sub-pixel.

[0111] The light-emitting device OLED can be electrically connected to the driving element via an intermediate electrode CNE disposed on the first planarization layer 118. For example, the anode ANO of the light-emitting device OLED and the first source electrode SD1 of the polycrystalline thin-film transistor TFT1 can be connected to each other via the intermediate electrode CNE.

[0112] The anode ANO can be connected to the portion of the intermediate electrode CNE exposed through a contact hole penetrating the second planarization layer 119. The intermediate electrode CNE can be connected to the portion of the first source electrode SD1 exposed through a contact hole penetrating the first planarization layer 118.

[0113] The intermediate electrode CNE can be used as an intermediary to connect the first source electrode SD1 to the anode ANO. The intermediate electrode CNE can be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), titanium (Ti), or tungsten (W).

[0114] The second planarization layer 119 and the intermediate electrode CNE can be omitted. When the second planarization layer 119 and the intermediate electrode CNE are omitted, the anode ANO can be directly electrically connected to the portion of the first source electrode SD1 exposed through the contact hole penetrating the first planarization layer 118.

[0115] When applied to top-emitting organic light-emitting diode (OLED) display devices, the anode (ANO) can be formed as a multilayer structure comprising a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can be formed of a material with a relatively high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO). The opaque conductive layer can have a single-layer or multilayer structure, with each layer comprising a material selected from the group consisting of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), tungsten (W), and their alloys. For example, the anode (ANO) can be formed in a structure where transparent conductive layers, opaque conductive layers, and transparent conductive layers are stacked sequentially, or in a structure where transparent conductive layers and opaque conductive layers are stacked sequentially.

[0116] The dam layer (BNK) can be a subpixel-defining layer that exposes the anode (ANO) of each subpixel. The dam layer (BNK) can be formed of an opaque material (e.g., black) to prevent optical interference between adjacent subpixels. In this case, the dam layer (BNK) can include, but is not limited to, a light-shielding material, which includes, but is not limited to, a color pigment, organic black, or carbon black.

[0117] The light-emitting layer (EL) can be stacked on the anode (ANO) in either the order of a hole-dependent layer including a hole injection layer (HIL) and a hole transport layer (HTL), an organic light-emitting layer including a light-emitting layer (EM), and an electron-dependent layer including an electron transport layer (ETL) and an electron injection layer (EIL), or in the reverse order. Figure 7 Only the hole transport layer (HTL), the light-emitting layer (EM), and the electron transport layer (ETL) are shown in the diagram, but this disclosure is not limited thereto.

[0118] The cathode (CAT) can face the anode (ANO), with the light-emitting layer (EL) placed between them, and the cathode (CAT) can be formed on the upper and side surfaces of the light-emitting layer (EL). The cathode (CAT) can be integrally formed to cover the entire display area. When applied to top-emitting organic light-emitting diode (OLED) display devices, the cathode (CAT) can be implemented as a transparent conductive layer formed of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO). When applied to bottom-emitting organic light-emitting diode (OLED) display devices, the cathode (CAT) can be implemented as an opaque conductive layer with a single-layer or multi-layer structure, each layer comprising a material selected from the group consisting of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), tungsten (W), and their alloys. Alternatively, the cathode (CAT) can be implemented as a semi-transparent conductive layer with a single-layer or multi-layer structure, each layer comprising a material selected from the group consisting of aluminum (Al), magnesium (Mg), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), tungsten (W), and their alloys.

[0119] An encapsulation layer 120 for suppressing moisture penetration can be additionally disposed on the cathode CAT. The encapsulation layer 120 can block foreign substances such as external moisture or oxygen from penetrating towards the light-emitting layer EL, which is susceptible to the effects of such foreign substances. For this purpose, the encapsulation layer 120 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. However, this disclosure is not limited thereto. The encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 stacked sequentially.

[0120] The first encapsulation layer 121 and the third encapsulation layer 123 can be formed of an inorganic insulating material capable of low-temperature deposition (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), or aluminum oxide (Al2O3)). Because the first encapsulation layer 121 and the third encapsulation layer 123 are deposited in a low-temperature atmosphere, damage to the light-emitting layer EL, which is susceptible to high-temperature atmospheres, can be prevented during the deposition of the first encapsulation layer 121 and the third encapsulation layer 123.

[0121] The second encapsulation layer 122 can serve as a buffer to alleviate interlayer stress caused by bending of the display device 10 and to flatten interlayer steps. The second encapsulation layer 122 can be disposed on a substrate 111 on which the first encapsulation layer 121 is formed, and is formed of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, benzocyclobutene, unsaturated polyester resin, polyethylene, or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacrylic acid. However, this disclosure is not limited thereto.

[0122] Although not shown in the accompanying drawings, a touch sensor may be additionally disposed on the encapsulation layer 120.

[0123] Figure 4A This is a plan view illustrating data lines and a plurality of data-driven integrated circuits according to embodiments of the present disclosure. Figure 4B This is a plan view illustrating data lines and a plurality of data-driven integrated circuits according to another embodiment of the present disclosure.

[0124] exist Figure 4A and Figure 4B In this context, the display panel 100 may include a plurality of gate lines disposed along a first (e.g., horizontal) direction. Figure 4A and Figure 4B (not shown in the image) (see reference) Figure 1 The gate lines (SCL and EML) and multiple data lines DL1 to DLm are arranged along a second (e.g., vertical) direction different from the first direction. Multiple sub-pixels can be arranged at the intersections between the multiple gate lines and the multiple data lines DL1 to DLm.

[0125] Multiple data lines DL1 to DLm can be driven by at least one data driver integrated circuit D-IC (also known as a "data driver"). When the display panel 100 is a large display panel, multiple data lines DL1 to DLm can be driven by multiple data driver integrated circuits D-IC.

[0126] In a network of multiple data lines driven by a single data driver integrated circuit (D-IC), a first portion (e.g., half) of the data lines located in the central region of the network can be directly connected to the D-IC. The remaining portions (e.g., half) of the data lines located on the left and right sides of the central region can be connected to the data lines directly connected to the D-IC within the display area of ​​the display panel, rather than being directly connected to the D-IC.

[0127] This will be described in detail below.

[0128] Figure 5A This is a plan view illustrating multiple data lines driven by a data driver integrated circuit (D-IC) according to an embodiment of the present disclosure. Figure 5B This is a plan view illustrating multiple data lines driven by a data driver integrated circuit (D-IC) according to another embodiment of the present disclosure.

[0129] Multiple data lines driven by a single data driver integrated circuit (D-IC) can be divided into regions A (A-1 and A-2) and regions B (B-1 and B-2). Region B (B-1 and B-2) can include the data lines located in the central region of the multiple data lines driven by the single data driver integrated circuit (D-IC), and region A (A-1 and A-2) can include the data lines located on both sides of region B (B-1 and B-2). The number of data lines in region A (A-1 and A-2) and the number of data lines in region B (B-1 and B-2) can be equal. For example, the number of data lines in region A (A-1 and A-2) can be greater than or less than the number of data lines in region B (B-1 and B-2).

[0130] The data lines located in areas B (B-1 and B-2) can be directly connected to the data driver integrated circuit (D-IC). The data lines located in areas A (A-1 and A-2) do not need to be directly connected to the D-IC; instead, they can be connected within the display area to the data lines located in areas B (B-1 and B-2). The data lines located in areas A (A-1 and A-2) can be connected to the data lines located in areas B (B-1 and B-2) in a one-to-one correspondence, for example, via multiple connecting lines CL1 to CLn (e.g., CL60).

[0131] To minimize the RC delay variation of the data lines located in regions A (A-1 and A-2), multiple connecting lines CL1 to CLn (e.g., CL60) can be used to connect the data lines in regions A (A-1 and A-2) one-to-one to the data lines located in regions B (B-1 and B-2) at the middle section of the data lines. The multiple connecting lines CL1 to CLn (e.g., CL60) can have the same length.

[0132] This will be described in more detail below.

[0133] For ease of description, Figures 5A-5B The description will be based on the assumption that the number of data lines driven by a single data driver integrated circuit is 120.

[0134] Region A (A-1 and A-2) can be divided into region A-1 (A-1) and region A-2 (A-2), and region B (B-1 and B-2) can be divided into region B-1 (B-1) and region B-2 (B-2). The same number of data lines can be set in region A-1 (A-1), region A-2 (A-2), region B-1 (B-1), and region B-2 (B-2).

[0135] Therefore, among the 120 data lines DL1 to DL120 driven by a data driver integrated circuit, the 30 data lines DL1 to DL30 from the 1st data line DL1 to the 30th data line DL30 correspond to region A-1 (A-1), the 30 data lines DL31 to DL60 from the 31st data line DL31 to the 60th data line DL60 correspond to region B-1 (B-1), the 30 data lines DL61 to DL90 from the 61st data line DL61 to the 90th data line DL90 correspond to region B-2 (B-2), and the 30 data lines DL91 to DL120 from the 91st data line DL91 to the 120th data line DL120 correspond to region A-2 (A-2).

[0136] The 30 data lines DL31 to DL60 in region B-1 (B-1) from data line 31 to data line DL60 and the 30 data lines DL61 to DL90 in region B-2 (B-2) from data line 61 to data line DL90 are directly connected to the data driver integrated circuit D-IC.

[0137] The 30 data lines DL1 to DL30 in region A-1 (A-1) and the 30 data lines DL91 to DL120 in region A-2 (A-2) are not directly connected to the data driver integrated circuit D-IC.

[0138] Instead, the 30 data lines DL1 to DL30 in region A-1 (A-1) are electrically connected one-to-one via connecting lines CL1 to CL30 to the 30 data lines DL31 to DL60 in region B-1 (B-1) from data line DL31 to data line DL60.

[0139] In region A-2 (A-2), the 30 data lines DL91 to DL120 (from data line 91 to data line 120) are electrically connected one-to-one via connecting lines CL31 to CL60 to the 30 data lines DL61 to DL90 (from data line 61 to data line 90) in region B-2 (B-2).

[0140] For example, the first data line DL1 in region A-1 (A-1) is electrically connected to the 31st data line DL31 in region B-1 (B-1) via the connecting line CL30; the second data line DL2 in region A-1 (A-1) is electrically connected to the 32nd data line DL32 in region B-1 (B-1) via the connecting line CL29; the 29th data line DL29 in region A-1 (A-1) is electrically connected to the 59th data line DL59 in region B-1 (B-1) via the connecting line CL2; and the 30th data line DL30 in region A-1 (A-1) is electrically connected to the 60th data line DL60 in region B-1 (B-1) via the connecting line CL1.

[0141] In this manner, the 30 data lines DL1 to DL30 in area A-1 (A-1) are connected one-to-one with the 30 data lines DL31 to DL60 in area B-1 (B-1) via connecting lines CL1 to CL30. For example, in Figure 5A In the plan view shown, the connection points of data line DL1 and connecting line CL30, data line DL2 and connecting line CL29, ..., and data line DL30 and connecting line CL1 can form a first line, and the connection points of data line DL31 and connecting line CL30, data line DL32 and connecting line CL29, ..., and data line DL60 and connecting line CL1 can form a second line. The first line can be parallel to the second line. The first line, the second line, connecting line CL1, and connecting line CL30 can form a first parallelogram.

[0142] Data line DL91 in area A-2 (A-2) is electrically connected to data line DL61 in area B-2 (B-2) via connecting line CL31. Data line DL92 in area A-2 (A-2) is electrically connected to data line DL62 in area B-2 (B-2) via connecting line CL32. Data line DL119 in area A-2 (A-2) is electrically connected to data line DL89 in area B-2 (B-2) via connecting line CL59. Data line DL120 in area A-2 (A-2) is electrically connected to data line DL90 in area B-2 (B-2) via connecting line CL60.

[0143] In this manner, the 30 data lines DL91 to DL120 in area A-2 (A-2) are connected one-to-one with the 30 data lines DL61 to DL90 in area B-2 (B-2) via connecting lines CL31 to CL60. For example, in Figure 5A In the plan view shown, the connection points of data line DL61 and connecting line CL31, data line DL62 and connecting line CL32, ..., and data line DL90 and connecting line CL60 can form a third line, and the connection points of data line DL91 and connecting line CL31, data line DL92 and connecting line CL32, ..., and data line DL120 and connecting line CL60 can form a fourth line. The third line can be parallel to the fourth line. The third line, the fourth line, connecting line CL31, and connecting line CL60 can form a second parallelogram.

[0144] The first parallelogram and the second parallelogram can be symmetrical about the center of the plurality of data lines in the first (e.g., horizontal) direction.

[0145] Alternative locations, such as Figure 5B As shown, data lines DL1 to DL30 can be connected to data lines DL31 to DL60 via connecting lines CL1 to CL30 in such a way that the first parallelogram is flipped in the second (e.g., vertical) direction, and data lines DL61 to DL90 can be connected to data lines DL91 to DL120 via connecting lines CL31 to CL60 in such a way that the second parallelogram is flipped in the second (e.g., vertical) direction.

[0146] Since the 60 data lines in regions A (A-1 and A-2) are connected one-to-one to the 60 data lines in regions B (B-1 and B-2) via 60 connecting lines CL1 to CL60 using the method described above, all 60 connecting lines CL1 to CL60 have the same length. Furthermore, the 60 connecting lines CL1 to CL60 are positioned at the center of the data lines. Therefore, the RC delay variation caused by the 60 connecting lines CL1 to CL60 can be minimized.

[0147] Figure 6 This is a plan view illustrating the RC delay variation in a second (e.g., vertical) direction and a first (e.g., horizontal) direction for multiple data lines driven by a data driver integrated circuit D-IC according to an embodiment of the present disclosure.

[0148] RC delay variation can be based on reference Figures 5A-5B The described connection lines CL1 to CL60 connect data lines DL1 to DL30 and DL91 to DL120 located in area A (A-1 and A-2) to data lines DL31 to DL90 located in area B (B-1 and B-2) in different locations.

[0149] For example, such as Figure 6 As shown, when viewed in the second (e.g., vertical) direction of the display panel, if the connecting lines CL1 to CL60, which connect the data lines DL1 to DL30 and DL91 to DL120 in regions A (A-1 and A-2) to the data lines DL31 to DL90 in regions B (B-1 and B-2), are located at the top or bottom of the display panel, the RC delay change increases compared to when the connecting lines CL1 to CL60 are located at the center of the display panel.

[0150] Furthermore, when viewed in the first (e.g., horizontal) direction of the display panel, in region A-1 (A-1), the number of intersections between the connecting lines and data lines gradually increases towards the right, thus increasing the RC delay. Conversely, in region B-1 (B-1), the number of intersections between the connecting lines and data lines gradually decreases towards the right, thus decreasing the RC delay. Furthermore, regions A-2 (A-2) and B-2 (B-2) exhibit trends opposite to those of regions A-1 (A-1) and B-1 (B-1). Therefore, due to the variation in RC delay, the boundary between regions A (A-1 and A-2) and regions B (B-1 and B-2) can be visually identified. Therefore, it is advantageous that 60 connecting lines CL1 to CL60 are positioned at the center portion of the data lines DL1 to DL120 in the first (e.g., horizontal) direction.

[0151] Even when, as in reference Figures 4A-4B As described, to minimize the RC delay variation of the data lines, regions B (B-1 and B-2) directly connected to the data driver integrated circuit D-IC are located in the central region of the multiple data lines. Furthermore, when the connection lines CL1 to CL60, which connect data lines DL1 to DL30 and DL91 to DL120 in regions A (A-1 and A-2) to data lines DL31 to DL90 in regions B (B-1 and B-2), are located at the center of the data lines, RC delay variation between the data lines in regions A (A-1 and A-2) and regions B (B-1 and B-2) can still occur. For example, the RC delay of the data lines in regions A (A-1 and A-2) may be greater than the RC delay of the data lines in regions B (B-1 and B-2).

[0152] The RC delay variation between the data lines in region A (A-1 and A-2) and the data lines in region B (B-1 and B-2) affects the charging rate of the data voltage, and thus causes a change in brightness in the display panel.

[0153] Figure 7 This is a view showing the data input time and data charging rate of the data lines in regions A and B according to an embodiment of the present disclosure.

[0154] To prevent brightness variations in the display panel due to RC delay changes between the data lines in areas A (A-1 and A-2) and areas B (B-1 and B-2), such as... Figure 7 As shown, the source output enable (SOE) signal used to output data signals from the data driver integrated circuit D-IC is adjusted so that the data input time of the data lines in region A (A-1 and A-2) is longer than the data input time of the data lines in region B (B-1 and B-2).

[0155] like Figure 7 As shown, when the data input time of the data lines in region A (A-1 and A-2) is the same as that of the data lines in region B (B-1 and B-2) ("before SOE signal adjustment"), a discontinuous change in the data charging rate occurs between the data lines at the boundary of region A-1 (A-1) and region B-1 (B-1), and a discontinuous change in the data charging rate occurs between the data lines at the boundary of region A-2 (A-2) and region B-2 (B-2), which may result in brightness variations in the display panel.

[0156] However, when the data input time of the data lines in regions A-1 (A-1) and A-2 (A-2) is set to be longer than that of the data lines in regions B-1 (B-1) and B-2 (B-2) ("after SOE signal adjustment"), the data charging rate varies smoothly across the entire display panel, and the brightness change of the display panel is not visually perceptible.

[0157] Figure 8A This is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to an embodiment of the present disclosure. Figure 8B This is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to another embodiment of the present disclosure.

[0158] Multiple gate lines Scan(n) to Scan(n+7) can be arranged along a first direction across regions A-1 (A-1) and B-1 (B-1). Multiple data lines D_R, D_G, D_W, and D_B can be arranged in each of regions A-1 and B-1 along a second direction different from the first direction. Multiple sub-pixels can be arranged at the intersections between the multiple gate lines Scan(n) to Scan(n+7) and the multiple data lines D_R, D_G, D_W, and D_B. In this case, n is a positive integer.

[0159] Furthermore, multiple sub-pixels can be positioned between the (4k-3)th and (4k-2)th gate lines and between the (4k-1)th and 4kth gate lines. No sub-pixels are positioned between the (4k-2)th and (4k-1)th gate lines and between the 4kth and (4k+1)th gate lines. In this case, k is a positive integer.

[0160] For example, multiple sub-pixels can be placed between gate lines Scan(n) and Scan(n+1), and between gate lines Scan(n+2) and Scan(n+3) in multiple gate lines Scan(n) to Scan(n+7). No sub-pixels are placed between gate lines Scan(n+1) and Scan(n+2), and between gate lines Scan(n+3) and Scan(n+4). In this case, n is a positive integer.

[0161] In the first (e.g., horizontal) direction, two sub-pixels can be set between a pair of data lines D_R and D_G and a pair of data lines D_W and D_B. No sub-pixels are set between a pair of data lines D_R and D_G or between a pair of data lines D_W and D_B.

[0162] A reference voltage line Ref can be set between two sub-pixels positioned between a pair of data lines D_R and D_G and a pair of data lines D_W and D_B. The reference voltage line Ref can be set parallel to the data lines D_R, D_G, D_W, and D_B.

[0163] Each sub-pixel in region A-1 (A-1) can be driven by odd-numbered gate lines Scan(n), Scan(n+2), Scan(n+4), ..., and each sub-pixel in region B-1 (B-1) can be driven by even-numbered gate lines Scan(n+1), Scan(n+3), Scan(n+5), ... However, this disclosure is not limited thereto. Each sub-pixel in region A-1 (A-1) can be driven by even-numbered gate lines Scan(n+1), Scan(n+3), Scan(n+5), ..., and each sub-pixel in region B-1 (B-1) can be driven by odd-numbered gate lines Scan(n), Scan(n+2), Scan(n+4), ...

[0164] Each of the connecting lines CL(n) to CL(n+3) can electrically connect a data line in region A-1 (A-1) to a data line in region B-1 (B-1) of the same color as the data line in region A-1 (A-1). For example, connecting lines CL(n) to CL(n+3) can electrically connect the red data line D_R in region A-1 (A-1) to the red data line D_R in region B-1 (B-1), the green data line D_G in region A-1 (A-1) to the green data line D_G in region B-1 (B-1), the white data line D_W in region A-1 (A-1) to the white data line D_W in region B-1 (B-1), and the blue data line D_B in region A-1 (A-1) to the blue data line D_B in region B-1 (B-1). In this case, n is a positive integer.

[0165] Due to the aforementioned connection structure of connecting lines CL(n) to CL(n+3), connecting lines CL(n) to CL(n+3) can be positioned at different locations in a second (e.g., vertical) direction, with each connecting line offset by one pixel relative to its adjacent connecting line. However, this disclosure is not limited thereto. For example, each connecting line can be offset by more than one pixel relative to its adjacent connecting line.

[0166] Figure 8A and Figure 8BEach of the following configurations is shown: a connecting line (one of CL(n) to CL(n+3)) is provided between gate lines Scan(n+1) and Scan(n+2), between gate lines Scan(n+3) and Scan(n+4), between gate lines Scan(n+5) and Scan(n+6), and between gate lines Scan(n+7) and Scan(n+8). However, this disclosure is not limited thereto. For example, a connecting line CL(n) may be provided between gate lines Scan(n+1) and Scan(n+2), no connecting line may be provided between gate lines Scan(n+3) and Scan(n+4), a connecting line CL(n+1) may be provided between gate lines Scan(n+5) and Scan(n+6), and no connecting line may be provided between gate lines Scan(n+7) and Scan(n+8). In this case, n is a positive integer.

[0167] Figure 9 It is along Figure 8A The schematic cross-sectional view is shown by the connecting line CL(n).

[0168] like Figure 9 As shown, a first insulating layer 140 may be disposed on the substrate 111. The first insulating layer 140 may include reference... Figure 3 At least one of the described lower buffer layer 112a, auxiliary buffer layer 112b, or first gate insulating layer 113.

[0169] The connecting line CL(n) can be disposed on the first insulating layer 140. The connecting line CL(n) can be made from a reference. Figure 3 The first gate electrode GE1 is formed of the same material. In this case, n is a positive integer.

[0170] A second insulating layer 130 may be disposed on a first insulating layer 140 including the connecting line CL(n). The second insulating layer 130 may include a reference. Figure 3 At least one of the first interlayer insulating layer 114, the upper buffer layer 115, the second gate insulating layer 116, or the second interlayer insulating layer 117 described.

[0171] Multiple data lines D_R, D_G, D_W, and D_B, as well as a reference voltage line Ref, can be provided on the second insulating layer 130 in a direction perpendicular to the connection line CL(n).

[0172] Contact holes can be formed in the second insulating layer 130, allowing the two ends of the connecting line CL(n) to be exposed through the contact holes. The blue data line D_B in region A-1 (A-1) and the blue data line D_B in region B-1 (B-1) can be electrically connected to the corresponding ends of the connecting line CL(n) through the contact holes.

[0173] In this way, each of the connecting lines CL(n) to CL(n+3) can be obtained by referring to... Figure 3 The first gate electrode GE1 or gate line described is formed of the same material. However, the connection lines CL(n) to CL(n+3) according to this disclosure are not limited thereto. The connection lines CL(n) to CL(n+3) according to this disclosure may be formed of a material different from the material of the data lines D_R, D_G, D_W, and D_B. For example, the connection lines CL(n) to CL(n+3) may be formed of a material similar to that of the referenced material. Figure 3 The intermediate electrode CNE, anode ANO, and cathode CAT are all made of the same material. In this case, n is a positive integer.

[0174] Figures 8A-8B The arrangement of gate lines, data lines, and sub-pixels in regions A-1 and B-1 is shown. The arrangement of gate lines, data lines, and sub-pixels in regions A-2 and B-2 is shown in reference. Figures 8A-8B The arrangements described are the same. For example, the arrangement of elements in region A-2 can be the same as the arrangement of elements in region A-1, and the arrangement of elements in region B-2 can be the same as the arrangement of elements in region B-1.

[0175] Figure 10A This is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to yet another embodiment of the present disclosure. Figure 10B This is a view showing the layout of gate lines, data lines and sub-pixels in regions A-1 and B-1 according to another embodiment of the present disclosure.

[0176] Multiple gate lines Scan(n) to Scan(n+7) can be arranged along a first direction across regions A-1 (A-1) and B-1 (B-1). Multiple data lines D_R, D_G, D_W, and D_B can be arranged in each of regions A-1 and B-1 along a second direction different from the first direction. Multiple sub-pixels can be arranged at the intersections between the multiple gate lines Scan(n) to Scan(n+7) and the multiple data lines D_R, D_G, D_W, and D_B. In this case, n is a positive integer.

[0177] Furthermore, multiple sub-pixels can be arranged between corresponding gate lines in the plurality of gate lines Scan(n) to Scan(n+7). In this case, n is a positive integer. A red sub-pixel and a green sub-pixel can be arranged between the (2k-1)th gate line and the 2kth gate line, and a white sub-pixel and a blue sub-pixel can be arranged between the 2kth gate line and the (2k+1)th gate line. In this case, k is a positive integer. Alternatively, a white sub-pixel and a blue sub-pixel can be arranged between the (2k-1)th gate line and the 2kth gate line, and a red sub-pixel and a green sub-pixel can be arranged between the 2kth gate line and the (2k+1)th gate line. However, this disclosure is not limited thereto. The arrangement of the sub-pixels can be modified in various ways.

[0178] For example, red and green sub-pixels can be set between gate lines Scan(n) and Scan(n+1), between gate lines Scan(n+2) and Scan(n+3), between gate lines Scan(n+4) and Scan(n+5), and between gate lines Scan(n+6) and Scan(n+7) in multiple gate lines Scan(n) to Scan(n+7). Furthermore, white and blue sub-pixels can be set between gate lines Scan(n+1) and Scan(n+2), between gate lines Scan(n+3) and Scan(n+4), and between gate lines Scan(n+5) and Scan(n+6). In this case, n is a positive integer.

[0179] In the first (e.g., horizontal) direction, a sub-pixel can be set between the (4k-3)th data line D_R and the (4k-2)th data line D_W, and between the corresponding gate lines in Scan(n) to Scan(n+7). A sub-pixel can also be set between the (4k-1)th data line D_G and the 4kth data line D_B, and between the corresponding gate lines in Scan(n) to Scan(n+7). No sub-pixels are set between the (4k-2)th data line D_W and the (4k-1)th data line D_G, or between the 4kth data line D_B and the (4k+1)th data line D_R. In this case, n is a positive integer.

[0180] A reference voltage line Ref can be set between the (4k-2)th data line D_W and the (4k-1)th data line D_G, and between the 4kth data line D_B and the (4k+1)th data line D_R. The reference voltage line Ref can be set in parallel with the data lines D_R, D_G, D_W, and D_B. In this case, k is a positive integer.

[0181] Each sub-pixel in region A-1 (A-1) can be driven by even-numbered gate lines Scan(n+1), Scan(n+3), Scan(n+5), ..., and each sub-pixel in region B-1 (B-1) can be driven by odd-numbered gate lines Scan(n), Scan(n+2), Scan(n+4), ... However, this disclosure is not limited thereto. Each sub-pixel in region A-1 (A-1) can be driven by odd-numbered gate lines Scan(n), Scan(n+2), Scan(n+4), ..., and each sub-pixel in region B-1 (B-1) can be driven by even-numbered gate lines Scan(n+1), Scan(n+3), Scan(n+5), ...

[0182] Each of the connecting lines CL(n) to CL(n+3) can electrically connect a data line in region A-1 (A-1) to a data line in region B-1 (B-1) of the same color as the data line in region A-1 (A-1). For example, connecting lines CL(n) to CL(n+3) can electrically connect the red data line D_R in region A-1 (A-1) to the red data line D_R in region B-1 (B-1), the green data line D_G in region A-1 (A-1) to the green data line D_G in region B-1 (B-1), the white data line D_W in region A-1 (A-1) to the white data line D_W in region B-1 (B-1), and the blue data line D_B in region A-1 (A-1) to the blue data line D_B in region B-1 (B-1). In this case, n is a positive integer.

[0183] Figures 10A-10B The arrangement of gate lines, data lines, and sub-pixels in regions A-1 and B-1 is shown. The arrangement of gate lines, data lines, and sub-pixels in regions A-2 and B-2 is the same as that described with reference to FIG10. For example, the arrangement of elements in region A-2 can be the same as the arrangement of elements in region A-1, and the arrangement of elements in region B-2 can be the same as the arrangement of elements in region B-1.

[0184] Reference Figures 10A-10B The cross-sectional structure of each of the described connecting lines CL(n) to CL(n+3) can be compared with the reference. Figure 9 The descriptions are the same.

[0185] As described above, according to embodiments of this disclosure, among multiple data lines driven by a single data driver integrated circuit, half of the data lines located in the central region are directly connected to the data driver integrated circuit. The remaining half of the data lines located on the left and right sides are not directly connected to the data driver integrated circuit, but are electrically connected to the data lines directly connected to the data driver integrated circuit. Therefore, a narrow bezel can be achieved.

[0186] Furthermore, the data input time of sub-pixels connected to data lines directly connected to the data driver IC is set to be shorter than the data input time of sub-pixels connected to the remaining data lines not directly connected to the data driver IC. Therefore, visual recognition of brightness variations between data lines directly connected to the data driver IC and the remaining data lines not directly connected to the data driver IC can be prevented.

[0187] As is evident from the above description, according to this disclosure, among multiple data lines driven by a data driver integrated circuit, some data lines located in the central region are directly connected to the data driver integrated circuit. The remaining data lines located on the left and right sides are not directly connected to the data driver integrated circuit, but are electrically connected to the data lines directly connected to the data driver integrated circuit.

[0188] Therefore, narrow bezels can be achieved.

[0189] Furthermore, the data input time of sub-pixels connected to data lines directly connected to the data driver IC is set to be shorter than the data input time of sub-pixels connected to the remaining data lines not directly connected to the data driver IC.

[0190] Therefore, it is possible to prevent the brightness variation between the data lines directly connected to the data driver IC and the remaining data lines not directly connected to the data driver IC from being visually identified.

[0191] The effects achievable through this disclosure are not limited to those mentioned above, and various other effects may be disclosed directly or implicitly in the above detailed description of this disclosure.

[0192] Although this disclosure has been described above, it is not limited to the above-described embodiments and drawings, and it will be apparent to those skilled in the art that various changes, modifications and alterations can be made without departing from the technical spirit of this disclosure.

Claims

1. A display device, comprising: The display panel includes multiple gate lines and multiple data lines; as well as At least one data driver integrated circuit, the at least one data driver integrated circuit being configured to supply a data signal to each of the plurality of data lines. Among the multiple data lines driven by a data driver integrated circuit, some data lines located in the central region of the multiple first data lines are directly connected to the data driver integrated circuit. Among them, the remaining data lines located on the left and right sides of the central region are not directly connected to the data driver integrated circuit, but are electrically connected to the data line directly connected to the data driver integrated circuit via multiple connecting lines.

2. The display device according to claim 1, wherein, The multiple connecting lines have the same length.

3. The display device according to claim 1, wherein, The plurality of connecting lines are located at the center portion of the plurality of first data lines in the direction in which the data lines extend.

4. The display device according to claim 1, wherein, Each of the multiple connecting lines will connect to each other using data lines of the same color.

5. The display device according to claim 1, wherein, The data lines arranged in the central area correspond to half of the plurality of first data lines, and the remaining data lines arranged on the left and right sides correspond to the remaining half of the plurality of first data lines.

6. The display device according to claim 5, wherein, The direct connection of the plurality of first data lines to the half of the data driver integrated circuit is divided into data lines disposed in region B-1 and data lines disposed in region B-2. Specifically, the data lines located on one side of region B-1 and on the opposite side of region B-2 are divided into data lines located in region A-1 and data lines located in region A-2. The data line located in region A-1 is electrically connected to the data line located in region B-1 via some of the multiple connecting lines, and The data line located in region A-2 is electrically connected to the data line located in region B-2 via the remaining connecting lines among the plurality of connecting lines.

7. The display device according to claim 6, wherein, The number of data lines set in area A-1, the number of data lines set in area A-2, the number of data lines set in area B-1, and the number of data lines set in area B-2 are the same.

8. The display device according to claim 6, wherein, The data input time for the data lines located in regions A-1 and A-2 is longer than the data input time for the data lines located in regions B-1 and B-2.

9. The display device according to claim 6, wherein, Multiple sub-pixels are disposed between the (4k-3)th gate line and the (4k-2)th gate line, and between the (4k-1)th gate line and the 4kth gate line, and In this context, no sub-pixels are provided between the (4k-2)th gate line and the (4k-1)th gate line, and between the 4kth gate line and the (4k+1)th gate line, where k is a positive integer.

10. The display device according to claim 9, wherein, Two sub-pixels are set between one pair of data lines and another pair of data lines, and No sub-pixels are set between the pair of data lines and between the other pair of data lines.

11. The display device according to claim 10, wherein, The sub-pixels in regions A-1 and A-2 are driven by even-numbered gate lines, and In this context, the sub-pixels in regions B-1 and B-2 are driven by odd-numbered gate lines.

12. The display device according to claim 10, wherein, The sub-pixels in regions A-1 and A-2 are driven by odd-numbered gate lines, and In this context, the sub-pixels in regions B-1 and B-2 are driven by even-numbered gate lines.

13. The display device according to claim 10, further comprising a reference voltage line disposed between the two sub-pixels.

14. The display device according to claim 6, wherein, Multiple sub-pixels are disposed between corresponding gate lines among the plurality of gate lines. Specifically, a sub-pixel is disposed between the (4k-3)th data line and the (4k-2)th data line, and between their respective gate lines; and a sub-pixel is disposed between the (4k-1)th data line and the 4kth data line, and between their respective gate lines. In this context, no sub-pixels are set between the (4k-2)th data line and the (4k-1)th data line, and between the 4kth data line and the (4k+1)th data line, where k is a positive integer.

15. The display device according to claim 14, wherein, The sub-pixels in regions A-1 and A-2 are driven by even-numbered gate lines, and In this context, the sub-pixels in regions B-1 and B-2 are driven by odd-numbered gate lines.

16. The display device according to claim 14, wherein, The sub-pixels in regions A-1 and A-2 are driven by odd-numbered gate lines, and In this context, the sub-pixels in regions B-1 and B-2 are driven by even-numbered gate lines.

17. The display device according to claim 14, further comprising a plurality of reference voltage lines, the plurality of reference voltage lines being disposed between the (4k-2)th data line and the (4k-1)th data line and between the 4kth data line and the (4k+1)th data line, wherein, k is a positive integer.

18. The display device according to claim 1, wherein, The plurality of connecting lines are formed of the same material as the plurality of gate lines.

19. A display device, comprising: Display panel, the display panel having multiple data lines; as well as Multiple data drivers are disposed in the non-display area of ​​the display panel. Specifically, for each data driver in at least a portion of the plurality of drivers, a first portion of the plurality of data lines is directly connected to the data driver, and a second portion of the plurality of data lines is not directly connected to the data driver, but is connected to the first portion of the plurality of data lines. The data lines in the second part are configured to surround the data lines in the first part.

20. The display device according to claim 19, wherein, The data lines of the second part are connected to the data lines of the first part via multiple connecting lines.

21. The display device according to claim 19, wherein, The data input time of the second part of the data line is longer than that of the first part of the data line.

22. The display device according to claim 20, wherein, The multiple connecting lines are made of a different material than the multiple data lines.

23. The display device according to claim 19, further comprising a plurality of gate lines, in, The sub-pixels connected to the data lines of the first part are driven by gate lines with a first parity number, and the sub-pixels connected to the data lines of the second part are driven by gate lines with a parity number opposite to the first parity.

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