Display device and display control method

Abstract

Embodiments of the present disclosure provide a display device and a display control method. The display device comprises: a display module configured to map output data according to a first arrangement order and / or a second arrangement order, the first arrangement order being opposite to the second arrangement order; a detection unit configured to detect whether a viewer exists on a first face and / or a second face of the display module; and a control unit electrically connected to the display module and the detection unit respectively, and configured to generate a driving control signal according to a detection result. When only the first face has the viewer, the display module outputs data according to the first arrangement order; when only the second face has the viewer, the display module outputs data according to the second arrangement order; and when both the first face and the second face have the viewer, the first display area outputs data according to the first arrangement order and the second display area outputs data according to the second arrangement order. The display device realizes hardware-level bidirectional adaptive display and reduces display delay.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and a display control method. Background Technology

[0002] Transparent displays, as an emerging display technology, have broad application prospects in retail windows, interactive booths, translation devices, and other fields. They allow users to see the real objects behind the screen while viewing the content, achieving a fusion of virtual information and real-world scenarios and greatly increasing interactivity.

[0003] However, most transparent displays have a fixed data transmission direction during manufacturing (usually sequentially from one side to the other), resulting in them only displaying the correct image in one direction (defined as the "front"). When a user views from the back of the screen, the image is mirrored horizontally due to the fixed image, severely impacting the viewing experience for users on the back. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display device, comprising: a display module, a detection unit, and a control unit; the display module is configured to map output data according to a first arrangement order and / or a second arrangement order, wherein the first arrangement order is the reverse of the second arrangement order; the detection unit is configured to detect whether a viewer exists on a first side and / or a second side of the display module; the control unit is electrically connected to the display module and the detection unit respectively, and is configured to generate a drive control signal based on the detection result of the detection unit; the control unit is further configured to: in response to the detection unit detecting that a viewer exists only on the first side, control the display module to enter a first display mode based on the drive control signal, wherein the first display mode... The system may instruct the output data to be mapped according to a first arrangement order corresponding to the first surface; or, in response to the detection unit detecting that only the second surface has a viewer, the system controls the display module to enter a second display mode based on a drive control signal, the second display mode indicating that the output data is mapped according to a second arrangement order corresponding to the second surface; or, in response to the detection unit detecting that both the first and second surfaces have viewers, the system controls the display module to enter a third display mode based on a drive control signal, the third display mode indicating that the first display area in the display module is mapped and output data according to the first arrangement order corresponding to the first surface, and indicating that the second display area in the display module is mapped and output data according to the second arrangement order corresponding to the second surface.

[0005] For example, in a display device provided in at least one embodiment of this disclosure, the driving control signal includes a display mode control signal and a data transmission direction control signal. The display module includes an electrically connected display panel, a timing control unit, and a source driving unit. The timing control unit has a display mode control pin and is configured to receive and output a corresponding scan start pulse signal and a clock signal to the display panel based on the display mode control signal. The timing control unit is also configured to transmit data to the source driving unit. The source driving unit has a data transmission direction control pin and is configured to receive and output data according to a first arrangement order and / or a second arrangement order based on the data transmission direction control signal.

[0006] For example, in a display device provided in at least one embodiment of this disclosure, the display panel includes a first gate array driving circuit and a second gate array driving circuit. The first gate array driving circuit and the second gate array driving circuit are respectively disposed on opposite sides of the display panel. The first gate array driving circuit is configured to drive each gate line in a first display area, and the second gate array driving circuit is configured to drive each gate line in a second display area.

[0007] For example, in the display device provided in at least one embodiment of this disclosure, the first gate array driving circuit and the second gate array driving circuit are cascaded. In the first display mode or the second display mode, the timing control unit outputs a full-screen scanning start pulse signal. The first gate array driving circuit and the second gate array driving circuit are cascaded and cooperate to sequentially complete the full-screen continuous scanning of the display panel.

[0008] For example, in a display device provided in at least one embodiment of this disclosure, a first gate array driving circuit is disposed on the left side of the display panel and is used to drive all gate lines in the first display area and the second display area; a second gate array driving circuit is disposed on the right side of the display panel and is used to drive all gate lines in the first display area and the second display area.

[0009] For example, in the display device provided in at least one embodiment of this disclosure, a first gate array driving circuit is disposed on the left side of the display panel, a second gate array driving circuit is disposed on the right side of the display panel, a first display area is the upper half of the display module, and a second display area is the lower half of the display module; the first gate array driving circuit drives each gate line in the upper half of the display panel, the second gate array driving circuit drives each gate line in the lower half of the display panel, and there is no gate array driving circuit on the left side of the lower half of the display panel.

[0010] For example, in a display device provided in at least one embodiment of this disclosure, the execution steps of the third display mode include: during odd-numbered frame periods, a timing control unit outputs a first scan start pulse signal and a first clock signal to enable a first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controls the source driving unit to map and output data in a first arrangement order; during even-numbered frame periods, a timing control unit outputs a second scan start pulse signal and a second clock signal to enable a second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controls the source driving unit to map and output data in a second arrangement order; wherein the second row sequence is the opposite of the first row sequence.

[0011] For example, in a display device provided in at least one embodiment of this disclosure, the display module further includes a level conversion unit electrically connected to a timing control unit. The level conversion unit is configured to receive and convert a first scan start pulse signal and a second scan start pulse signal into a first voltage, the first voltage being the turn-on voltage of each gate line in the first display area and each gate line in the second display area.

[0012] For example, in the display device provided in at least one embodiment of this disclosure, the control unit is further configured to: control the display module to enter a first display mode in response to a display mode control signal being low and a data transmission direction control signal being high; or, control the display module to enter a second display mode in response to a display mode control signal being low and a data transmission direction control signal being low; or, control the level of the data transmission direction control signal to alternately switch in an odd-even frame manner in response to a display mode control signal being high, so that the display module enters a third display mode.

[0013] For example, in a display device provided in at least one embodiment of this disclosure, the driving control signal includes a display mode control signal, and the display module includes an electrically connected display panel, a timing control unit, a first source driving unit, and a second source driving unit. Each column of pixels on the display panel is correspondingly connected to a first data line and a second data line. The timing control unit has a display mode control pin and is configured to receive and output a corresponding scan start pulse signal and a clock signal to the display panel based on the display mode control signal. The timing control unit is also configured to transmit data to the first source driving unit and the second source driving unit. The first source driving unit is disposed on a first side of the display panel, and the output pins of the first source driving unit are connected to the first data lines of each column of pixels in a first arrangement order. The second source driving unit is disposed on a second side of the display panel, and the output pins of the second source driving unit are connected to the second data lines of each column of pixels in a second arrangement order.

[0014] For example, in a display device provided in at least one embodiment of this disclosure, the display panel includes a first gate array driving circuit and a second gate array driving circuit. The first gate array driving circuit is configured to drive each gate line in a first display area, and the second gate array driving circuit is configured to drive each gate line in a second display area. The execution steps of the third display mode include: during odd-numbered frame periods, a timing control unit outputs a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controls the first source driving unit to output data through the first data line in a first arrangement order; during even-numbered frame periods, the timing control unit outputs a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controls the second source driving unit to output data through the second data line in a second arrangement order; wherein the second row sequence is the opposite of the first row sequence.

[0015] For example, in the display device provided in at least one embodiment of this disclosure, the control unit is further configured to: control the display module to enter a first display mode or a second display mode in response to a low level display mode control signal; or, control the display module to enter a third display mode in response to a high level display mode control signal.

[0016] For example, in the display device provided in at least one embodiment of this disclosure, after the timing control unit outputs the first scan start pulse signal and before the first gate array driving circuit turns on the effective gate line, a first virtual scan period is provided, during which the first gate array driving circuit performs a pre-charge scan on the virtual gate line; after the timing control unit outputs the second scan start pulse signal and before the second gate array driving circuit turns on the effective gate line, a second virtual scan period is provided, during which the second gate array driving circuit performs a pre-charge scan on the virtual gate line.

[0017] For example, in a display device provided in at least one embodiment of this disclosure, the detection unit includes a first image acquisition unit and a second image acquisition unit. The first image acquisition unit is disposed on a first side of the display module and is configured to acquire a first image of the first side. The second image acquisition unit is disposed on a second side of the display module and is configured to acquire a second image of the second side. The control unit includes a processor, which identifies the location of the viewer based on the first image and the second image.

[0018] For example, in at least one embodiment of the display device provided in this disclosure, the display module includes a transparent liquid crystal display.

[0019] For example, in a display device provided in at least one embodiment of this disclosure, the first arrangement order is that each data in a row of data is arranged in column order from left to right, and the second arrangement order is that each data in a row of data is arranged in column order from right to left.

[0020] At least one embodiment of this disclosure also provides a display control method for the display device of any of the above embodiments. The display control method includes: acquiring a detection result of a detection unit; generating a drive control signal based on the detection result; in response to a detection result indicating that only a viewer exists on a first side of the display module, controlling the display module to enter a first display mode based on the drive control signal, wherein the first display mode indicates that data is mapped and output according to a first arrangement order corresponding to the first side; in response to a detection result indicating that only a viewer exists on a second side of the display module, controlling the display module to enter a second display mode based on the drive control signal, wherein the second display mode indicates that data is mapped and output according to a second arrangement order corresponding to the second side, wherein the first arrangement order and the second arrangement order are reversed; in response to a detection result indicating that both the first and second sides have viewers, controlling the display module to enter a third display mode based on the drive control signal, wherein the third display mode indicates that a first display area in the display module is mapped and output according to the first arrangement order corresponding to the first side, and indicates that a second display area in the display module is mapped and output according to the second arrangement order corresponding to the second side.

[0021] For example, in a display control method provided in at least one embodiment of this disclosure, the driving control signal includes a display mode control signal and a data transmission direction control signal, the display module includes a timing control unit and a source driving unit, and the display control method further includes: the timing control unit outputs a scan start pulse signal and a clock signal according to the display mode control signal; the source driving unit maps and outputs data according to the data transmission direction control signal in a first arrangement order and / or a second arrangement order.

[0022] For example, in the display control method provided in at least one embodiment of this disclosure, the display module further includes a first gate array driving circuit and a second gate array driving circuit, which are respectively disposed on opposite sides of the display panel; the first gate array driving circuit is used to drive each gate line in the first display area, and the second gate array driving circuit is used to drive each gate line in the second display area.

[0023] For example, in the display control method provided in at least one embodiment of this disclosure, the execution process of the third display mode includes: during odd-numbered frame periods, outputting a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controlling the source driving unit to map and output data in a first arrangement order; during even-numbered frame periods, outputting a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controlling the source driving unit to map and output data in a second arrangement order; wherein, the second row sequence is the opposite of the first row sequence.

[0024] For example, in the display control method provided in at least one embodiment of this disclosure, before the odd-numbered frame period or the even-numbered frame period, the display control method further includes: performing level conversion on the first scan start pulse signal and / or the second scan start pulse signal and then outputting it to the corresponding gate line.

[0025] For example, at least one embodiment of the display control method provided in this disclosure further includes: controlling the display module to enter a first display mode in response to a display mode control signal being low and a data transmission direction control signal being high; or, controlling the display module to enter a second display mode in response to a display mode control signal being low and a data transmission direction control signal being low; or, controlling the level of the data transmission direction control signal to alternately switch in an odd-even frame manner in response to a display mode control signal being high, so that the display module enters a third display mode.

[0026] For example, in the display control method provided in at least one embodiment of this disclosure, the driving control signal includes a display mode control signal, the display module includes a first source driving unit and a second source driving unit, each column of pixels on the display panel is connected to a first data line and a second data line, and the display control method further includes: controlling a timing control unit to select the first source driving unit and / or the second source driving unit based on the display mode control signal; the first source driving unit outputs data in a first arrangement order through the first data line; and the second source driving unit outputs data in a second arrangement order through the second data line.

[0027] For example, in the display control method provided in at least one embodiment of this disclosure, the execution process of the third display mode includes: during odd-numbered frame periods, outputting a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controlling the first source driving unit to output data through the first data line in a first arrangement order; during even-numbered frame periods, outputting a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controlling the second source driving unit to output data through the second data line in a second arrangement order; wherein, the second row sequence is the opposite of the first row sequence.

[0028] For example, in a display control method provided in at least one embodiment of this disclosure, after outputting a first scan start pulse signal and before turning on an effective gate line, the display control method further includes: performing a first virtual scan step to pre-charge scan the virtual gate line; after outputting a second scan start pulse signal and before turning on an effective gate line, the display control method further includes: performing a second virtual scan step to pre-charge scan the virtual gate line. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0030] Figure 1 A schematic structural block diagram of a display device provided in at least one embodiment of this disclosure;

[0031] Figure 2 This is a schematic structural block diagram of a display module provided in at least one embodiment of the present disclosure;

[0032] Figure 3 A driving architecture diagram of a display panel with a resolution of 960×540 is provided for at least one embodiment of this disclosure;

[0033] Figure 4 A timing diagram of GOA driver in full-screen display mode is provided for at least one embodiment of this disclosure;

[0034] Figure 5 A timing diagram for GOA driving in an alternating odd-even frame split-screen display mode is provided in at least one embodiment of this disclosure;

[0035] Figure 6 A schematic structural block diagram of a display module provided in at least one embodiment of this disclosure;

[0036] Figure 7A schematic diagram of a positive unified display mode system provided in at least one embodiment of this disclosure;

[0037] Figure 8 A schematic diagram of an alternating odd-even frame split-screen display system provided for at least one embodiment of this disclosure;

[0038] Figure 9 A schematic structural block diagram of another display module provided in at least one embodiment of this disclosure;

[0039] Figure 10 A schematic diagram of a dual-source drive unit split-screen display system provided in at least one embodiment of this disclosure;

[0040] Figure 11 A schematic diagram of a reverse unified display system provided for at least one embodiment of this disclosure; and

[0041] Figure 12 This is a flowchart illustrating a display control method provided in at least one embodiment of the present disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components are omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is indicated by the same or similar reference numerals in each drawing.

[0045] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of the technical features in the embodiments of this disclosure; however, these terms may vary according to the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0046] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0047] To address the mirroring problem of transparent displays in the background technology, related technologies typically rely on the operating system or application software layer to pre-mirrorize the output image, or use a method of virtually dividing the screen into two logical areas at the system layer, rendering two sets of images separately, and then compositing them for output. However, these solutions fail to utilize the physical characteristics of the display driving circuit itself and cannot achieve true hardware-level screen splitting.

[0048] In view of the above problems, at least one embodiment of this disclosure provides a display device, including a display module, a detection unit, and a control unit; the display module is configured to map output data according to a first arrangement order and / or a second arrangement order, wherein the first arrangement order is the reverse of the second arrangement order; the detection unit is configured to detect whether a viewer exists on a first side and / or a second side of the display module; the control unit is electrically connected to the display module and the detection unit respectively, and is configured to generate a drive control signal based on the detection result of the detection unit; the control unit is further configured to: in response to the detection unit detecting that a viewer exists only on the first side, control the display module to enter a first display mode based on the drive control signal, wherein the first display mode... The system may instruct the output data to be mapped according to a first arrangement order corresponding to the first surface; or, in response to the detection unit detecting that only the second surface has a viewer, the system controls the display module to enter a second display mode based on a drive control signal, the second display mode indicating that the output data is mapped according to a second arrangement order corresponding to the second surface; or, in response to the detection unit detecting that both the first and second surfaces have viewers, the system controls the display module to enter a third display mode based on a drive control signal, the third display mode indicating that the first display area in the display module is mapped and output data according to the first arrangement order corresponding to the first surface, and indicating that the second display area in the display module is mapped and output data according to the second arrangement order corresponding to the second surface.

[0049] Accordingly, at least one embodiment of this disclosure also provides a display control method corresponding to the above-described display device.

[0050] The display device in at least one embodiment of this disclosure does not require image flipping or compositing rendering operations at the software level. Instead, it achieves automatic adjustment of the display module's display direction based on the viewer's position by switching the data arrangement order at the hardware level, under the premise of low latency and low system resource consumption. When there are viewers on both the front and back sides, it can also enable both sides to see the front image simultaneously through hardware split-screen, thereby overcoming the back mirroring problem caused by the fixed data transmission direction of traditional transparent display modules, as well as the inefficiency and inability to split the screen at the hardware level caused by software processing.

[0051] The display device of this disclosure will now be described through specific embodiments.

[0052] Figure 1 A schematic structural block diagram of a display device provided for at least one embodiment of the present disclosure.

[0053] like Figure 1As shown, the display device 100 includes a detection unit 110, a control unit 120, and a display module 130. The detection unit 110 is configured to detect the presence of a viewer on a first and / or second surface of the display module 130 and output the detection result to the control unit 120. The control unit 120 is electrically connected to both the detection unit 110 and the display module 130, and is configured to generate a drive control signal based on the detection result from the detection unit 110. The display module 130 is configured to map output data according to a first arrangement order and / or a second arrangement order, wherein the first arrangement order is the reverse of the second arrangement order.

[0054] Specifically, the control unit 120 is further configured to: when the detection unit 110 detects that only the first side (e.g., the front) of the display module 130 is occupied by a viewer, the control unit 120 controls the display module 130 to enter a first display mode, that is, to map and output data according to a first arrangement order corresponding to the first side, so that the viewer on the first side can see a frontal image; when the detection unit 110 detects that only the second side (e.g., the back) of the display module 130 is occupied by a viewer, the control unit 120 controls the display module 130 to enter a second display mode, that is, to map and output data according to a second arrangement order corresponding to the second side, so that the viewer on the second side can see a frontal image; when the detection unit 110 detects that both the first side and the second side are occupied by a viewer, the control unit 120 controls the display module 130 to enter a third display mode, that is, to map and output data in the first display area of ​​the display module 130 according to the first arrangement order and the second display area according to the second arrangement order, so that the viewer on the first side can see a frontal image through the first display area and the viewer on the second side can see a frontal image through the second display area.

[0055] It should be noted that the "arrangement order" mentioned above refers to the mapping relationship between each data point in a row of image data and each column of pixels within the source drive unit (see below). It is a horizontal column order arrangement, not the chronological order of serial output. The first arrangement order is the reverse of the second arrangement order in the horizontal direction. In addition, in reverse scan mode, the timing control unit (see below) also reverses the output order of each row of image data (i.e., rearranges the data vertically) so that the row data received when each gate line is turned on matches the current scan row number. The row order reversal and the column order reversal work together to ensure that the viewer can still see an upright and correct image during reverse scan.

[0056] Therefore, the display device 100 does not need to perform image flipping or compositing rendering operations at the software level. Instead, it can automatically adjust the display direction according to the viewer's position by switching the data arrangement order at the hardware level, with low latency and low system resource consumption. When there are viewers on both the front and back sides, it can also use hardware split-screen to allow both sides to see the front image at the same time. This overcomes the back mirroring problem caused by the fixed data transmission direction in related technologies, as well as the inefficiency and inability to split the screen at the hardware level caused by software processing.

[0057] For example, in one possible implementation, the drive control signal includes a display mode control signal and a data transmission direction control signal. The display module includes an electrically connected display panel, a timing control unit, and a source drive unit. The timing control unit has a display mode control pin and is configured to receive and output a corresponding scan start pulse signal and clock signal to the display panel based on the display mode control signal. The timing control unit is also configured to transmit data to the source drive unit. The source drive unit has a data transmission direction control pin and is configured to receive and output data according to a first arrangement order and / or a second arrangement order based on the data transmission direction control signal.

[0058] Figure 2 This is a schematic structural block diagram of a display module provided in at least one embodiment of the present disclosure.

[0059] like Figure 2 As shown, the display module 130 includes a timing control unit 1301, a source drive unit 1302, and a display panel 1303. The drive control signals include display mode control signals and data transmission direction control signals. The timing control unit 1301 has a display mode control pin (CTRL_Pin), which is configured to receive the display mode control signal. The timing control unit 1301 is configured to output a corresponding scan start pulse signal (STV) and clock signal (CLK) to the display panel 1303 based on the display mode control signal. Simultaneously, the timing control unit 1301 is also configured to transmit the image data to be displayed to the source drive unit 1302. The source drive unit 1302 has a data transmission direction control pin (SHL pin), which is configured to receive the data transmission direction control signal. The source drive unit 1302 is configured to map the output data according to a first arrangement order and / or a second arrangement order when outputting image data based on the data transmission direction control signal. It should be noted that the SHL pin may be named DIR, SL or SHIFT in different models of source driver unit 1302, but its essential function is the same as that of a hardware-level data direction control pin. The embodiments disclosed herein do not limit this.

[0060] Thus, by using different level combinations of the two hardware pins, the display mode control pin (CTRL_Pin) and the data transmission direction control pin (SHL pin), hardware-level control of the scanning mode and data arrangement direction of the display panel 1303 is achieved without the need for timing control unit register configuration or software intervention, thereby completing the display mode switching with extremely low latency.

[0061] The following is combined with Figures 3-5 Further explanation of the workflow of display panel 1303.

[0062] For example, in one possible implementation, the display panel includes a first gate array driving circuit and a second gate array driving circuit, which are respectively disposed on opposite sides of the display panel. The first gate array driving circuit is configured to drive each gate line in a first display area, and the second gate array driving circuit is configured to drive each gate line in a second display area.

[0063] Figure 3 This is a driving architecture diagram of a display panel with a resolution of 960×540, provided for at least one embodiment of the present disclosure.

[0064] Combination Figure 2 and Figure 3 As shown, the display panel 1303 includes a first gate-on-array (GOA) driving circuit and a second gate-on-array driving circuit. The first gate-on-array driving circuit and the second gate-on-array driving circuit are respectively disposed on opposite sides of the display panel 1303.

[0065] In this embodiment, a display panel with a resolution of 960×540 is used as an example: the first gate array driving circuit is located on the left side of the display panel, and the second gate array driving circuit is located on the right side of the display panel. The first display area is the upper half of the display module, corresponding to 270 gate lines from Gate 1 to Gate 270; the second display area is the lower half of the display module, corresponding to 270 gate lines from Gate 271 to Gate 540. The first gate array driving circuit is configured to drive each gate line in the upper half of the screen (Gate 1 to Gate 270), and the second gate array driving circuit is configured to drive each gate line in the lower half of the screen (Gate 271 to Gate 540). In other words, the left GOA is connected to each gate line of the upper half of the screen, and the right GOA is connected to each gate line of the lower half of the screen.

[0066] like Figure 3As shown, the left and right GOAs receive the STV signal (scan start pulse) and the four-phase clock signal CLK1-CLK4 from the timing control unit, respectively, and both GOAs respond to the four-phase clock CLK1-CLK4. Through this partitioned layout, the gate scanning of the first and second display areas is independently controlled by the two GOAs, providing a hardware foundation for subsequent full-screen cascaded scanning and split-screen independent scanning modes. It should be noted that the left GOA... Figure 3 The extension extends to the entire height of the display panel, meaning it can also be extended to drive all gate lines (Gate 1 to Gate 540), and the specific operation of this variant will be described below.

[0067] For example, in one possible implementation, a first gate array driving circuit is disposed on the left side of the display panel for driving all gate lines in the first display area and the second display area; a second gate array driving circuit is disposed on the right side of the display panel for driving all gate lines in the first display area and the second display area.

[0068] For example, still refer to Figure 3 The first gate array driving circuit (left GOA) is located on the left side of the display panel and is used to drive all gate lines (Gate 1 to Gate 540). The second gate array driving circuit (right GOA) is located on the right side of the display panel and can also be used to drive all gate lines (Gate 1 to Gate 540). However, in this case, the second gate array driving circuit (right GOA) also has GOA units corresponding to Gate 1-Gate 270 (not shown in the figure). In the first display mode (only the front viewer is present) or the second display mode (only the back viewer is present), the timing control unit 1301 outputs a full-screen scan start pulse signal (STV) to the left GOA. The left GOA independently completes the full-screen continuous scan of the display panel 1303 under the drive of the four-phase clock CLK1-CLK4.

[0069] Figure 4 This disclosure provides a timing diagram for GOA driving in full-screen display mode, which is provided in at least one embodiment of the present disclosure.

[0070] like Figure 4As shown, at the beginning of a display frame (e.g., frame N), the STV1 signal is injected from the top into the start stage of the left GOA. After the STV1 signal is triggered but before the effective gate line Gate 1 is officially turned on, the first virtual scan period (i.e., the pre-charge phase) is entered. In this phase, the timing control unit 1301 first outputs the DUMMY clock pulses (i.e., virtual clock cycles) of CLK3 and CLK4 to pre-charge the start stage node of the internal shift register of the GOA, so that it reaches a stable voltage amplitude. Since this DUMMY pre-charge phase occurs first on CLK3 and CLK4, the effective turn-on sequence of the gate line in this frame is not the standard CLK1→CLK2→CLK3→CLK4, but CLK3→CLK4→CLK1→CLK2—that is, the DUMMY pre-charge of CLK3 and CLK4 is completed first, and then the normal CLK1→CLK2→CLK3→CLK4 cycle is entered for effective row scanning.

[0071] It should be noted that if the DUMMY precharge phase is set on CLK1 and CLK2 (i.e., the precharge phase occurs first on CLK1 and CLK2), the effective turn-on sequence of the gate lines is still CLK1→CLK2→CLK3→CLK4. In this embodiment, the DUMMY precharge phase occurs first on CLK3 and CLK4, making the effective turn-on sequence CLK3→CLK4→CLK1→CLK2. After the precharge phase ends, the four-phase clocks of CLK1-CLK4 cyclically output high levels in the order of CLK3→CLK4→CLK1→CLK2→CLK3→CLK4→…, driving Gate 1 to Gate 540 to turn on line by line, with the left GOA independently completing full-screen continuous scanning. During this process, the right GOA does not work (e.g., it is in a closed or standby state), thereby reducing system power consumption.

[0072] It should also be noted that in the end-of-frame phase, after scanning to Gate 540 (i.e., the last line of valid gate lines) and before the arrival of the next frame's STV signal, a frame end reset phase is set. For example... Figure 4As shown, in this stage, the timing control unit 1301 continues to output DUMMY clock pulses for CLK1 and CLK2 after Gate 540 scanning is completed. The function of this frame-end DUMMY differs from the frame-beginning DUMMY—the frame-beginning DUMMY is used for pre-charging (establishing the startup stage voltage), while the frame-end DUMMY is used for reset (discharging residual charge). Specifically, the frame-end DUMMY pulses for CLK1 and CLK2 are used to discharge the residual high-level charge in the shift register nodes of each stage within the GOA to a low level (VGL), ensuring that the internal nodes of all valid gate lines are completely cleared, preventing false triggering by residual charge when the next frame (e.g., frame N+1) arrives. After the frame-end DUMMY ends, the timing control unit 1301 stops outputting all CLK signals and enters the blanking time. The GOA completes a full reset, preparing for the arrival of the next frame STV. For example, the clock cycle of the blanking time occupies a clock width of "16H".

[0073] Furthermore, in Figure 4 In the timing diagram, "H" represents the display time of one row (one gate line), i.e., the scan cycle of one row of pixels; "Duty" represents the duty cycle of the clock signal, i.e., the proportion of high level within one clock cycle. In some embodiments of this disclosure, Duty is approximately 50%, meaning the duration of the high level and the duration of the low level of the CLK signal within one cycle are roughly equal. Thus, a complete clock pulse cycle is approximately "2H"—that is, one CLK cycle corresponds to two rows of display time, and the duration of both the high and low levels of the CLK signal is approximately 1H. Under this timing configuration, the four-phase clocks CLK1-CLK4 sequentially drive the GOA shift register, and the high level of each phase clock sequentially triggers the gate line of the corresponding row to turn on, with a scan interval of 1H between adjacent rows.

[0074] In addition, Figure 4In this code, "VDS" represents the forward scan control signal, and "VSD" represents the reverse scan control signal. In full-screen display mode, VDS and VSD control the data arrangement direction: when VDS is high and VSD is low, the source drive units output data in a first arrangement order (e.g., from left to right), suitable for front-viewing; when VDS is low and VSD is high, the source drive units output data in a second arrangement order (e.g., from right to left), suitable for back-viewing. In full-screen mode, regardless of the VDS / VSD level combination, the GOA scan row order is from Gate 1 to Gate 540 (from top to bottom); VDS / VSD only controls the data arrangement order of the source drive units, not the GOA scan row order. "VGH" represents the gate turn-on voltage (high level, e.g., +20V to +30V), and "VGL" represents the gate turn-off voltage (low level, e.g., -5V to -8V). After receiving the STV and CLK signals, the GOA circuit outputs VGH to the corresponding gate line step by step to turn on the thin-film transistors of that row of pixels. During non-scanning periods, it outputs VGL to the gate line to keep the thin-film transistors off. Figure 4 As shown, since this embodiment is a full-screen display mode, VDS and VSD maintain a constant level throughout the entire frame. Depending on the viewer's position, VDS is high and VSD is low when viewed from the front, and VDS is low and VSD is high when viewed from the back. This controls the data arrangement direction to select either the first or second arrangement order accordingly.

[0075] Therefore, in the aforementioned full-screen display mode, since the left-side GOA independently completes the scanning of all gate lines, the timing control of the entire full-screen display (front side) process is relatively simple, and only one-sided GOA needs to be enabled, which helps reduce power consumption. Similarly, the entire full-screen display (reverse side) process can also be achieved through the right-side GOA, which will not be elaborated here.

[0076] For example, in one possible implementation, the first gate array driving circuit and the second gate array driving circuit are cascaded together. In the first display mode or the second display mode, the timing control unit outputs a full-screen scanning start pulse signal. The first gate array driving circuit and the second gate array driving circuit are cascaded together to complete the full-screen continuous scanning of the display panel in sequence.

[0077] For example, the first gate array driving circuit and the second gate array driving circuit can be cascaded—that is, a cascaded trace is provided between the final stage output terminal of the first gate array driving circuit and the first stage input terminal of the second gate array driving circuit, used to transmit the scan enable signal from the final stage of the first gate array driving circuit to the first stage of the second gate array driving circuit. In the first display mode (only the front viewer is present) or the second display mode (only the back viewer is present), the timing control unit 1301 outputs a full-screen scan start pulse signal (STV). This STV signal is first injected into the start stage of the first gate array driving circuit. Driven by the four-phase clock CLK1-CLK4, the first gate array driving circuit sequentially turns on Gate 1 to Gate 270 in a top-to-bottom order. When scanning reaches Gate 270 (i.e., the last row of the first display area), the final stage output signal of the first gate array driving circuit is transmitted to the first stage of the second gate array driving circuit through the cascaded trace, triggering the second gate array driving circuit to start working. Subsequently, the second gate array driving circuit, also driven by the four-phase clock of CLK1-CLK4, continues to turn on Gate 271 to Gate 540 in a top-to-bottom order, thereby completing the full-screen continuous scan of the display panel 1303. This cascaded solution does not require gate lines covering the entire screen on the left side of the GOA, and the GOA circuit layout is more compact, making it suitable for narrow bezel designs.

[0078] For example, in one possible implementation, the first gate array driving circuit is disposed on the left side of the display panel, the second gate array driving circuit is disposed on the right side of the display panel, the first display area is the upper half of the display module, and the second display area is the lower half of the display module; the first gate array driving circuit drives each gate line in the upper half of the display panel, the second gate array driving circuit drives each gate line in the lower half of the display panel, and there is no gate array driving circuit on the left side of the lower half of the display panel.

[0079] For example, a first gate array driving circuit is located on the left side of the display panel, and a second gate array driving circuit is located on the right side of the display panel. The first display area is the upper half of the display module, and the second display area is the lower half of the display module. The first gate array driving circuit drives each gate line (Gate 1 to Gate 270) in the upper half of the screen, and the second gate array driving circuit drives each gate line (Gate 271 to Gate 540) in the lower half of the screen. Figure 3 The difference in the architecture shown is that in this embodiment, there is no gate array driving circuit on the left side of the lower half of the screen—that is, the lower half of the screen is driven only by the right GOA, and the left GOA only covers the upper half of the screen (Gate 1 to Gate 270) and does not extend to the lower half of the screen. This asymmetrical layout simplifies the circuit layout on the lower left side of the panel, saves wiring space and the number of GOA circuits, and is especially suitable for smaller or cost-sensitive products.

[0080] For example, in one possible implementation, the execution steps of the third display mode include: during odd-numbered frame periods, the timing control unit outputs a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controls the source driving unit to map and output data in a first arrangement order; during even-numbered frame periods, the timing control unit outputs a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controls the source driving unit to map and output data in a second arrangement order; wherein the second row sequence is the opposite of the first row sequence.

[0081] Figure 5 This is a timing diagram of GOA driving in an alternating odd and even frame split-screen display mode, provided in at least one embodiment of the present disclosure.

[0082] Combination Figure 3 and Figure 5 As shown, the execution steps of the third display mode (dual-sided split-screen display mode) include: during odd-numbered frame periods (e.g., frames 1, 3, 5, etc.), the timing control unit 1301 outputs a first scan start pulse signal (STV1) to the first gate array drive circuit and outputs a four-phase clock CLK1-CLK4. After receiving STV1, the first gate array drive circuit starts scanning each gate line in the first display area according to the first row sequence (from Gate 1 to Gate 270, i.e., from top to bottom). At the same time, the source drive unit 1302 maps and outputs data (VDS high, VSD low) in the first arrangement order, so that the viewer on the first side can see the front image through the first display area.

[0083] During even-numbered frame periods (e.g., frames 2, 4, 6, etc.), the timing control unit 1301 outputs a second scan start pulse signal (STV2) to the second gate array drive circuit and continues to output the four-phase clock CLK1-CLK4. Upon receiving STV2, the second gate array drive circuit initiates scanning of each gate line in the second display area according to the second row sequence (from Gate 540 to Gate 271, i.e., from bottom to top). Simultaneously, the source drive unit 1302 maps and outputs data in the second arrangement order (VDS low, VSD high). At this time, the timing control unit 1301 provides the image data of each row within a frame to the source drive unit 1302 line by line in the reverse order of the scanning sequence—that is, data originally corresponding to Gate 540 is output when Gate 540 is turned on, data originally corresponding to Gate 539 is output when Gate 539 is turned on, and so on. Thus, although the gates are physically scanned from bottom to top, because the row sequence of the data is synchronously reversed, the viewer on the back sees an upright image, not an inverted image.

[0084] Unlike full-screen mode, in split-screen display mode, VDS and VSD alternate between high and low positions every frame – odd-numbered frames correspond to high VDS and low VSD, and even-numbered frames correspond to low VDS and high VSD. Simultaneously, during even-numbered frames, the GOA scan row order itself changes to bottom-to-top (i.e., the second row order), and the timing control unit 1301 synchronously reverses the row order of the image data. Thus, the reversed gate scan row order and the reversed data row order cancel each other out, allowing the viewer on the second side (relative to the first side's viewing angle) to see an upright image vertically; the data arrangement direction, from right to left (the second arrangement order), is restored to left-to-right from the second side's viewing angle, allowing the second side's viewer to see a forward-facing image horizontally. Ultimately, the viewer on the second side sees a completely upright image through the second display area. The second row order is the opposite of the first row order.

[0085] It should be noted that in split-screen display mode, the VDS / VSD switching not only controls the alternation of data arrangement direction between odd and even frames, but also links to the GOA row order scanning direction: odd-numbered frames have row order from top to bottom with data in ascending order; even-numbered frames have row order from bottom to top with data in descending order. In full-screen display mode, however, the GOA row order is always from top to bottom, and VDS / VSD is only used to control the data arrangement direction.

[0086] By alternating between odd and even frames, and utilizing properties such as the retention characteristics of liquid crystals and the persistence of vision in the human eye, the viewer on the first side stably perceives the forward content of the first display area, and the viewer on the second side stably perceives the forward content of the second display area, thus achieving independent forward display on both sides of the same physical screen. Figure 5 As shown, a blanking time is set between odd and even frames. During this period, the timing control unit 1301 stops outputting STV and CLK signals, and both the left and right GOAs complete the internal node reset to prevent signal crosstalk from occurring when the left and right GOAs switch.

[0087] In other embodiments, a forward scanning method can also be used to implement the third display mode in even-numbered frames. Specifically, during odd-numbered frames, the timing control unit 1301 outputs a first scan start pulse signal (STV1) to the first gate array driving circuit, enabling the first gate array driving circuit to start scanning of each gate line in the first display area in a top-to-bottom order (Gate 1 to Gate 270). The source driving unit 1302 maps and outputs data in a first arrangement order, causing the first display area to refresh and display the front content. During even-numbered frames, the timing control unit 1301 outputs a second scan start pulse signal (STV2) to the second gate array driving circuit, enabling the second gate array driving circuit to start scanning of each gate line in the second display area in a top-to-bottom order (Gate 271 to Gate 540). The source driving unit 1302 maps and outputs data in a second arrangement order, causing the second display area to refresh and display the back content. In other words, in this embodiment, both odd and even frames are scanned in the forward direction (from top to bottom), rather than alternating between forward and reverse. Therefore, the image data can be output in the normal row order without the need for row order reversal processing. The source drive unit only needs to output the image data of each row to the corresponding gate line in the normal row order, making the timing control logic simpler. Thus, by alternating the partial refresh of odd and even frames, it is possible for both front and back viewers to see the forward image, and only half of the display area needs to be refreshed per frame, which helps to reduce power consumption. This embodiment is applicable, for example, to display panels that do not support GOA bidirectional scanning, lowering the hardware threshold. It should be noted that the voltage amplitude of the STV signal is a logic level (e.g., 3.3V or 1.8V), which cannot directly drive the pixel TFT to turn on. Therefore, the display module of at least one embodiment of this disclosure further includes a level conversion unit electrically connected to the timing control unit. The level conversion unit is configured to receive and convert the first scan start pulse signal and the second scan start pulse signal into a first voltage, which is the turn-on voltage of each gate line in the first display area and each gate line in the second display area.

[0088] Figure 6 This is a schematic structural block diagram of a display module provided for at least one embodiment of the present disclosure.

[0089] like Figure 6As shown, the display module 130 includes a timing control unit 1301, a source drive unit 1302, a level conversion unit 1304, and a display panel 1303. The timing control unit 1301 is electrically connected to the source drive unit 1302, the level conversion unit 1304, and the display panel 1303. The level conversion unit 1304 is electrically connected to the timing control unit 1301 and is configured to receive the scan start pulse signal (STV) and clock signal (CLK) output by the timing control unit 1301, and convert the voltage amplitude of the scan start pulse signal (and the enable signal corresponding to each gate) from a logic level (e.g., 3.3V or 1.8V) to a first voltage (VGH, e.g., +20V to +30V). This first voltage is the turn-on voltage for each gate line in the first display area and each gate line in the second display area. The VGH signal, boosted by the level conversion unit 1304, is output to the GOA circuit of the display panel 1303. Driven by the CLK signal, the GOA circuit sequentially transmits VGH to the corresponding gate lines to turn on the thin-film transistors of that row of pixels. Simultaneously, the level conversion unit 1304 is also configured to provide a gate turn-off voltage (VGL, e.g., -5V to -8V) to the GOA circuit, outputting VGL to the gate lines during non-scanning periods to keep the thin-film transistors off. Through the boosting process of the level conversion unit 1304, the gate drive voltage output by the GOA circuit is ensured to have sufficient amplitude to turn on the pixel thin-film transistors, thereby achieving stable and reliable display driving.

[0090] Figure 7 This is a schematic diagram of a forward unified display mode system provided for at least one embodiment of the present disclosure.

[0091] In the Figure 7 Before explaining the following examples, it's important to clarify that the "arrangement order" refers to the mapping relationship between each data point in a row of image data and each column of pixels within the source driver unit. The first arrangement order and the second arrangement order are reversed in the horizontal direction. For example, as shown... Figure 7 As shown, the first arrangement order is that the data is mapped to the pixels in each column from left to right (i.e., "forward data transmission"); as Figure 8 As shown, the second arrangement order is that the data is mapped to each column pixel according to the column order from right to left (i.e., "data reverse transmission"). In the embodiments of this disclosure, unless otherwise specified below, "data forward transmission" means that the data is mapped and output according to the first arrangement order, and "data reverse transmission" means that the data is mapped and output according to the second arrangement order.

[0092] like Figure 7As shown, in the first display mode (where viewers are present only on the first side), the control unit 120 (MCU) controls the display mode control signal to a low level (CTRL_Pin is at a low level), and simultaneously controls the data transmission direction control signal to a high level (the SHL pin is at a high level), so that the display module 130 enters the forward unified display mode. In this mode, the entire screen of the display module 130 maps output data according to the first arrangement order (i.e., Figure 7 the schematically marked "forward data transmission" — image data is output from the source drive unit Source drive 1 to the pixels of each column in the left-to-right column order). As shown in Figure 7 , the upper half screen (area 1) displays "Hello" and "Hello", and the lower half screen (area 2) displays "Do you need help?" and "May I help you?", all the content on the full screen is displayed in the forward direction, and the viewer on the first side can read all the content in the forward direction when viewing from the front of the screen. In this mode, the SHL pin remains at a fixed high level, the data transmission direction does not switch alternately, and the screen works in a conventional manner.

[0093] Figure 8 is a schematic diagram of an odd-even frame alternate split-screen display system provided by at least one embodiment of the present disclosure.

[0094] As shown in Figure 8 , in the third display mode (where viewers are present on both the first side and the second side), the control unit 120 (MCU) controls the display mode control signal to a high level (CTRL_Pin is at a high level), and simultaneously controls the level of the data transmission direction control signal to switch alternately in the form of odd and even frames, so that the display module 130 enters the odd-even frame alternate split-screen display mode. In this mode, the display area of the display module 130 is divided into area 1 (for example, the upper half screen) and area 2 (for example, the lower half screen). Wherein, area 1 maps output data according to the first arrangement order in odd frames (i.e., Figure 8 the schematically marked "forward data transmission"), as shown by "Hello" and "Hello" schematically displayed in area 1 in Figure 8 , so that the viewer on the first side sees a forward image through area 1. Area 2 maps output data according to the second arrangement order in even frames (i.e., Figure 8 the schematically marked "reverse data transmission"), as shown in Figure 8The schematically displayed "ollɘH" shown in region 2 is a mirror image of "Hello". During the even frame period, the second gate array driving circuit turns on scanning of each gate line in region 2 according to the second row sequence (from Gate 540 to Gate 271, that is, from bottom to top), and the timing control unit provides the image data of each row corresponding to region 2 to the source driving unit row by row in the order opposite to the scanning sequence. As a result, the reverse gate scanning row sequence and the reverse data row sequence cancel each other out, so that the viewer on the second side sees an upright picture in the vertical direction; the data arrangement direction from right to left is restored to from left to right for the viewing angle of the viewer on the second side, so that the viewer on the second side sees a normal-direction picture in the horizontal direction. Finally, when the viewer on the second side views region 2 from the second side of the screen, the mirrored "ollɘH" is restored to the normal-direction "Hello", and a normal-direction image is seen. Specifically, region 1 updates and displays during the odd frame period, and region 2 updates and displays during the even frame period, and independent dual-sided normal-direction display is achieved through continuous alternation.

[0095] In other embodiments, a normal-direction scanning manner may also be adopted in even frames to implement the third display mode. Specifically, during the odd frame period, the timing control unit 1301 enables the first gate array driving circuit to turn on scanning of each gate line in the first display region in the order from top to bottom (Gate 1 to Gate 270), the data is output in the normal row sequence, and the source driving unit 1302 maps and outputs the data in the first arrangement order, so that the first display region refreshes and displays the front content (e.g. Figure 8 the "Hello" and Chinese characters "您好" schematically shown in region 1). During the even frame period, the timing control unit 1301 enables the second gate array driving circuit to turn on scanning of each gate line in the second display region in the order from top to bottom (Gate 271 to Gate 540), the data is output in the normal row sequence, and the source driving unit 1302 maps and outputs the data in the second arrangement order, so that the second display region refreshes and displays the back content (e.g. Figure 8The “ollɘH” symbolically displayed in area 2 is a mirror image of “Hello”, which reverts to the forward “Hello” when viewed from the back. In other words, in this embodiment, both odd and even frames use forward scanning (from top to bottom), refreshing only one display area per frame (i.e., only the display area that needs updating is scanned and pixels are written), while the other display area retains the image from the previous frame. Therefore, there is no need to reverse the data row order, reducing the complexity of timing control. Thus, by alternating between partial refreshes in odd and even frames, it is possible for both front and back viewers to see the forward image, and only half of the display area needs to be refreshed per frame, which helps reduce power consumption. In this embodiment, the third display mode does not rely on the reverse scanning capability of GOA, and is applicable to display panels that do not support reverse scanning. Those skilled in the art can flexibly choose a reverse scanning split-screen scheme or a forward scanning split-screen scheme according to the panel hardware capabilities (whether it supports GOA bidirectional scanning) and product design requirements.

[0096] Therefore, by using different combinations of voltage levels on two hardware pins (CTRL_Pin and SHL pin), three display modes can be quickly switched: when CTRL_Pin is low and SHL pin is high, it is the first display mode (positive unified display mode, such as...). Figure 7 As shown, the second display mode is when CTRL_Pin is low and the SHL pin is low (reverse unified display mode, full-screen reverse display, viewed from the back as normal); the third display mode is when CTRL_Pin is high (alternating odd and even frame split-screen display mode, such as...). Figure 8 As shown, each side has its own area (viewed from the front and back). The entire switching process requires no timing control unit register configuration or software intervention, resulting in extremely low latency.

[0097] For example, in one possible implementation, the drive control signal includes a display mode control signal. The display module includes an electrically connected display panel, a timing control unit, a first source drive unit, and a second source drive unit. Each column of pixels on the display panel is connected to a first data line and a second data line. The timing control unit has a display mode control pin and is configured to receive and output a corresponding scan start pulse signal and clock signal to the display panel based on the display mode control signal. The timing control unit is also configured to transmit data to the first source drive unit and the second source drive unit. The first source drive unit is disposed on a first side of the display panel, and the output pins of the first source drive unit are connected to the first data lines of each column of pixels in a first arrangement order. The second source drive unit is disposed on a second side of the display panel, and the output pins of the second source drive unit are connected to the second data lines of each column of pixels in a second arrangement order.

[0098] Figure 9This is a schematic structural block diagram of another display module provided in at least one embodiment of the present disclosure.

[0099] like Figure 9 As shown, the display module 130 includes a timing control unit 1301, a first source drive unit 1302-1, a second source drive unit 1302-2, and a display panel 1303. The drive control signals include display mode control signals. The timing control unit 1301 has a display mode control pin (CTRL_Pin), configured to receive and output corresponding scan start pulse (STV) and clock signals (CLK) to the display panel 1303 based on the display mode control signals. The timing control unit 1301 is also configured to transmit image data to the first source drive unit 1302-1 and the second source drive unit 1302-2.

[0100] Each column of pixels in the display panel 1303 is connected to a first data line and a second data line. A first source driver unit 1302-1 is located on the first side (e.g., the lower side) of the display panel 1303. The output pins of the first source driver unit 1302-1 are connected to the first data lines of each column of pixels in a first arrangement order (e.g., from left to right, i.e., OUT1→OUT2→…→OUTn corresponding to first data line_1→first data line_2→…→first data line_n). A second source driver unit 1302-2 is located on the second side (e.g., the upper side) of the display panel 1303. The output pins of the second source driver unit 1302-2 are connected to the second data lines of each column of pixels in a second arrangement order (e.g., from right to left, i.e., OUT1→OUT2→…→OUTn corresponding to second data line_n→second data line_(n-1)→…→second data line_1). In other words, the first source driver unit 1302-1 is connected to the pixel array with a forward physical trace, and the second source driver unit 1302-2 is connected to the pixel array with a reverse physical trace.

[0101] In the dual-source drive unit architecture, the timing control unit 1301 selects the first source drive unit 1302-1 and / or the second source drive unit 1302-2 according to the display mode control signal. When the display mode control signal is low (CTRL_Pin is low), the timing control unit 1301 selects only one of the first source drive unit 1302-1 or the second source drive unit 1302-2 to work, causing the display module 130 to enter the first display mode or the second display mode. When the display mode control signal is high (CTRL_Pin is high), the timing control unit 1301 selects the first source drive unit 1302-1 and the second source drive unit 1302-2 in an alternating odd and even frame manner—selecting the first source drive unit 1302-1 in odd frames and selecting the second source drive unit 1302-2 in even frames—causing the display module 130 to enter the third display mode. Therefore, through the hardware architecture of symmetrical reverse wiring of dual-source drive units, forward and reverse data streams are directly generated at the physical level without the need for dynamic direction switching of the source drive units, making the control logic simpler.

[0102] Figure 10 This is a schematic diagram of a dual-source drive unit split-screen display system provided in at least one embodiment of the present disclosure.

[0103] Combination Figure 9 and Figure 10 As shown, in the third display mode (where viewers are present on both the first and second sides), the control unit 120 (MCU) controls the display mode control signal to be high (CTRL_Pin is high), causing the display module 130 to enter the dual-source drive unit split-screen display mode. In this mode, the timing control unit 1301 (Tcon) selects the first source drive unit 1302-1 and the second source drive unit 1302-2 (Source drive 2) in an alternating odd-even frame manner. The scan start pulse signal (STV) output by the timing control unit 1301 (Tcon) is first boosted to the gate turn-on voltage (VGH) by the level shift unit, and then sent to the GOA circuit to drive the gate scan.

[0104] Specifically, during the odd frame period, the timing control unit 1301 (Tcon) outputs a first scan start pulse signal (STV1) to the first gate array drive circuit (left-side GOA). After being boosted by the level shift unit (Level shift), STV1 enables the left-side GOA to turn on the scanning of each gate line in the first display area (upper half screen, area 1) in the top-to-bottom order (the first row sequence). Meanwhile, the timing control unit 1301 (Tcon) selects the first source drive unit 1302-1 (Source drive 1) and turns off the second source drive unit 1302-2 (Source drive 2). The first source drive unit 1302-1 (Source drive 1) maps and outputs data through the first data line (Data line A) in the first arrangement sequence (i.e. Figure 10 the "forward data transmission" schematically marked in — data is output to the pixels of each column in the left-to-right column order). As shown in Figure 10 , the upper half screen (area 1) displays "Ni Hao" and "Hello", this content is output in the first arrangement sequence (from left to right), and a viewer on the first side can read "Ni Hao" and "Hello" in the normal direction when viewing from the front of the screen. At this time, the second display area (lower half screen, area 2) is not refreshed and maintains the previous frame image.

[0105] During the even frame period, the timing control unit 1301 (Tcon) outputs a second scan start pulse signal (STV2) to the second gate array drive circuit (right-side GOA). After being boosted by the level shift unit (Level shift), STV2 enables the right-side GOA to turn on the scanning of each gate line in the second display area (lower half screen, area 2) in the bottom-to-top order (the second row sequence, Gate 540→Gate 271). Meanwhile, the timing control unit 1301 (Tcon) selects the second source drive unit 1302-2 and turns off the first source drive unit 1302-1. At this time, the timing control unit 1301 (Tcon) provides the image data of each row corresponding to the second display area to the second source drive unit 1302-2 row by row in the order opposite to the scanning order (that is, the data originally corresponding to Gate 540 is output when Gate 540 is turned on, the data originally corresponding to Gate 539 is output when Gate 539 is turned on, and so on). The second source drive unit 1302-2 (Source drive 2) maps and outputs data through the second data line (Data line B) in the second arrangement sequence (i.e. Figure 10 the "reverse data transmission" schematically marked in — data is output to the pixels of each column in the right-to-left column order, and the data is arranged in a left-right mirrored manner relative to the viewer on the first side). As shown in Figure 10As shown, the lower half of the screen (area 2) displays, for example, “؟uoy plɘh I yaM” (a mirror image of “May I help you?”), which is output according to the second arrangement order (from right to left). Thus, the reversed gate scan row order cancels out the reversed data row order, allowing the viewer on the back to see an upright image in the vertical direction; the data arrangement direction, from right to left, is restored to left to right relative to the second-side viewing angle, allowing the second-side viewer to see a forward-facing image in the horizontal direction. Finally, when the viewer on the second side views area 2 from the second side of the screen, the mirrored text is restored to the forward-facing “May I help you?”, and the second-side viewer sees a forward-facing image through the second display area. At this time, the first display area (upper half of the screen, area 1) does not refresh, maintaining the previous frame.

[0106] In other embodiments, the third display mode can also be implemented by forward scanning in even-numbered frames. Specifically, during odd-numbered frame periods, the timing control unit 1301 outputs a first scan start pulse signal (STV1) to the first gate array driving circuit, enabling the first gate array driving circuit to start scanning of each gate line in the first display area in a top-to-bottom order (Gate 1 to Gate 270). At the same time, the timing control unit 1301 selects the first source drive unit 1302-1 and turns off the second source drive unit 1302-2. The first source drive unit 1302-1 outputs data through the first data line (Data line A) in a first arrangement order, so that the first display area refreshes and displays the front content. During even-numbered frames, the timing control unit 1301 outputs a second scan start pulse signal (STV2) to the second gate array drive circuit, enabling the second gate array drive circuit to scan each gate line in the second display area in a top-to-bottom order (Gate 271 to Gate 540). Simultaneously, the timing control unit 1301 selects the second source drive unit 1302-2 and disables the first source drive unit 1302-1. The second source drive unit 1302-2 outputs data via the second data line (Data line B) in a second arrangement order, causing the second display area to refresh and display the back content. In other words, in this embodiment, both odd and even-numbered frames use forward scanning (from top to bottom), rather than alternating forward and reverse scanning. Therefore, the image data can be output in normal line order without the need for line order reversal processing, resulting in simpler timing control logic.

[0107] Through continuous alternation of odd frames and even frames, using for example the holding characteristic of liquid crystals and the visual persistence effect of the human eye, the viewer on the first side stably perceives "Hello" and "Hello" on the upper half screen, and the viewer on the second side stably perceives "Need help?" and "May I help you?" on the lower half screen, thereby realizing double-sided independent forward display on the same physical screen.

[0108] Figure 11 is a schematic diagram of a reverse unified display system provided by at least one embodiment of the present disclosure.

[0109] as Figure 11 shown, in the second display mode (where there are viewers only on the second side), the control unit 120 (MCU) controls the display mode control signal to a low level (CTRL_Pin is at a low level), so that the display module 130 enters the reverse unified display mode. In this mode, the timing control unit 1301 (Tcon) selects the second source driving unit 1302-2 (Source drive 2), turns off the first source driving unit 1302-1 (Source drive 1), and disconnects the power supply voltage of the first source driving unit 1302-1 (Source drive 1). The timing control unit 1301 (Tcon) outputs the scan start pulse signal (STV) and the clock signal (CLK) according to the normal timing. The STV signal is first boosted by the level shift unit (Level shift) to the gate turn-on voltage (VGH, for example, +20V to +30V), and then sent to the GOA circuit to drive the GOA to perform full-screen gate sequential scanning (from Gate 1 to Gate 540). At the same time, the second source driving unit 1302-2 (Source drive 2) fills data for the full-screen pixels through the second data line (Data line B) in the second arrangement order (i.e. Figure 11 the "reverse data transmission" schematically marked in — data is output to each column of pixels in the column order from right to left).

[0110] as Figure 11As shown, because the output pins of the second source drive unit 1302-2 are connected to the second data lines (Data line B) of each column of pixels in reverse physical routing (i.e., the second arrangement order), the data is mapped from right to left at the physical column level. Therefore, when viewed from the front, the entire screen content displayed in regions 1 and 2 appears as a mirror image. For example, the "ollɘH" (i.e., the mirror image of "Hello") schematically displayed in region 1 is flipped horizontally because the data arrangement direction is from right to left (i.e., data is transmitted in reverse). When viewed from the second side (back), the mirrored "ollɘH" returns to the upright "Hello", and the rest of the content also returns to the upright arrangement when viewed from the back. Thus, the viewer from the back sees a full-screen upright image.

[0111] It should be noted that in the dual-source driver unit scheme, the switching between the first and second arrangement orders is achieved by selecting different source driver units, without relying on the data transmission direction control pin (SHL pin) inside the source driver unit for dynamic switching. In this embodiment, the SHL pin can be fixed at any level or kept floating.

[0112] For example, in one possible implementation, the detection unit includes a first image acquisition unit and a second image acquisition unit. The first image acquisition unit is disposed on a first side of the display module and configured to acquire a first image of the first side. The second image acquisition unit is disposed on a second side of the display module and configured to acquire a second image of the second side. The control unit includes a processor that identifies the viewer's location based on the first and second images.

[0113] For example, the detection unit includes a first image acquisition unit and a second image acquisition unit. The first image acquisition unit is located on the first side (e.g., the front) of the display module and is configured to acquire a first image of the first side; the second image acquisition unit is located on the second side (e.g., the back) of the display module and is configured to acquire a second image of the second side. The first and second image acquisition units can be cameras (such as binocular cameras) or other optical sensors with image acquisition capabilities. The control unit includes a processor that runs, for example, an eye detection and localization algorithm. This algorithm can employ, for example, Haar feature extraction, an Adaboost cascade classifier, or a deep learning-based face / eye detection model. Based on the first image acquired by the first image acquisition unit and the second image acquired by the second image acquisition unit, the processor detects whether an eye (i.e., a viewer) exists on the first and second sides, respectively, and identifies the viewer's location (only on the front, only on the back, or both). By combining binocular vision with an eye-tracking algorithm, accurate real-time perception of the viewer's location is achieved, providing a reliable perceptual basis for adaptive display control.

[0114] It should be noted that the specific implementation of the detection unit described above is merely an example. In other embodiments, the detection unit may also employ other types of sensing elements such as infrared pyroelectric sensor arrays, ultrasonic sensors, or capacitive proximity sensing matrices, as long as it can detect whether a viewer is present on the first and / or second sides of the display module. Those skilled in the art can select appropriate sensing solutions based on actual application scenarios (such as detection distance, ambient light, cost requirements, etc.), and these alternative solutions all fall within the protection scope of this disclosure.

[0115] For example, the display module in the above embodiments includes a transparent liquid crystal display. The transparent liquid crystal display employs a side-lit backlight and a transparent light guide plate design, allowing viewers to see the objects behind the screen while it displays images. By applying the bidirectional adaptive display control scheme of this disclosure to a transparent liquid crystal display, bidirectional interactive functionality is achieved while maintaining the screen's transparency—viewers on both the front and back can see the frontal image content (in a two-sided viewing scenario, the front viewer sees the upper half of the screen's frontal content, and the back viewer sees the lower half of the screen's frontal content). This expands the application prospects of transparent displays in scenarios such as retail windows (two-sided viewing inside and outside the window), interactive booths (two-way explanation of exhibits), translation machines (split-screen viewing for both parties in a conversation), and double-sided advertising machines (synchronous or independent playback on both sides).

[0116] In addition, the display module can also employ other types of transparent display technologies, such as transparent OLED displays or transparent displays based on polymer network liquid crystals (PNLC), as long as they possess the transparent characteristics for bidirectional viewing and the ability to be driven in sections. Those skilled in the art can select appropriate transparent display technology solutions according to actual product requirements, and these alternative solutions all fall within the protection scope of this disclosure.

[0117] The display device in at least one embodiment of this disclosure does not require image flipping or compositing rendering operations at the software level. Instead, it achieves automatic adjustment of the display module's display direction based on the viewer's position by switching the data arrangement order at the hardware level, under the premise of low latency and low system resource consumption. When there are viewers on both the front and back sides, it can also enable both sides to see the front image simultaneously through hardware split-screen, thereby overcoming the back mirroring problem caused by the fixed data transmission direction of traditional transparent display modules, as well as the inefficiency and inability to split the screen at the hardware level caused by software processing.

[0118] Based on the same inventive concept, at least one embodiment of this disclosure also provides a display control method for the display device of any of the above embodiments. The display control method includes: acquiring a detection result of a detection unit; generating a drive control signal based on the detection result; in response to a detection result indicating that only a viewer exists on a first side of the display module, controlling the display module to enter a first display mode based on the drive control signal, wherein the first display mode indicates that data is mapped and output according to a first arrangement order corresponding to the first side; in response to a detection result indicating that only a viewer exists on a second side of the display module, controlling the display module to enter a second display mode based on the drive control signal, wherein the second display mode indicates that data is mapped and output according to a second arrangement order corresponding to the second side, wherein the first arrangement order and the second arrangement order are reversed; in response to a detection result indicating that both the first and second sides have viewers, controlling the display module to enter a third display mode based on the drive control signal, wherein the third display mode indicates that a first display area in the display module is mapped and output according to the first arrangement order corresponding to the first side, and indicates that a second display area in the display module is mapped and output according to the second arrangement order corresponding to the second side.

[0119] Figure 12 This is a schematic flowchart illustrating a display control method provided in at least one embodiment of this disclosure. Figure 12 As shown, the display control method includes steps S200-S240.

[0120] Step S200: Obtain the detection results of the detection unit.

[0121] Step S210: Generate a drive control signal based on the detection result.

[0122] Step S220: In response to the detection result indicating that only the first side of the display module has a viewer, the display module is controlled to enter the first display mode based on the drive control signal. The first display mode indicates that the output data is mapped according to the first arrangement order corresponding to the first side.

[0123] Step S230: In response to the detection result indicating that only the second side of the display module has a viewer, the display module is controlled to enter the second display mode based on the drive control signal. The second display mode indicates that the output data is mapped according to the second arrangement order corresponding to the second side, and the first arrangement order and the second arrangement order are reversed.

[0124] Step S240: In response to the detection result indicating that there are viewers on both the first and second sides, the display module is controlled to enter a third display mode based on the drive control signal. The third display mode indicates that the first display area in the display module maps and outputs data according to the first arrangement order corresponding to the first side, and indicates that the second display area in the display module maps and outputs data according to the second arrangement order corresponding to the second side.

[0125] For details on the specific execution process corresponding to step S200, please refer to the above description of the detection unit, which will not be repeated here.

[0126] For details on the specific execution process corresponding to steps S210-S240, please refer to the above description of the control unit, which will not be repeated here.

[0127] For example, in one possible implementation, the drive control signal includes a display mode control signal and a data transmission direction control signal. The display module includes a timing control unit and a source drive unit. The display control method further includes: the timing control unit outputting a scan start pulse signal and a clock signal according to the display mode control signal; and the source drive unit mapping and outputting data according to a first arrangement order and / or a second arrangement order according to the data transmission direction control signal. For specific level combination logic, please refer to the above regarding... Figure 7 , Figure 8 The explanation will not be repeated here.

[0128] For example, in one possible implementation, the display module further includes a first gate array driving circuit and a second gate array driving circuit, which are respectively disposed on opposite sides of the display panel; the first gate array driving circuit is used to drive each gate line in the first display area, and the second gate array driving circuit is used to drive each gate line in the second display area. For specific GOA layout details, please refer to the above information regarding... Figure 3 The explanation will not be repeated here.

[0129] For example, in one possible implementation, the execution process of the third display mode includes: during odd-numbered frame periods, outputting a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controlling the source driving unit to map and output data in a first arrangement order; during even-numbered frame periods, outputting a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controlling the source driving unit to map and output data in a second arrangement order; wherein the second row sequence is the opposite of the first row sequence. For specific timing details, please refer to the above regarding... Figure 5 The explanation will not be repeated here.

[0130] For example, in one possible implementation, before the odd-numbered frame period or the even-numbered frame period, the method further includes: performing a level shift on the first scan start pulse signal and / or the second scan start pulse signal and then outputting it to the corresponding gate line. For the specific level shifting process, please refer to the above description. Figure 6 The explanation will not be repeated here.

[0131] For example, in one possible implementation, the method further includes: controlling the display module to enter a first display mode in response to a low level display mode control signal and a high level data transmission direction control signal; controlling the display module to enter a second display mode in response to a low level display mode control signal and a low level data transmission direction control signal; and controlling the level of the data transmission direction control signal to alternately switch in an odd-even frame manner in response to a high level display mode control signal, thereby causing the display module to enter a third display mode. For specific level combinations and switching logic, please refer to the above description. Figure 7 , Figure 8 The explanation will not be repeated here.

[0132] For example, in one possible implementation, the drive control signal includes a display mode control signal, the display module includes a first source drive unit and a second source drive unit, and each column of pixels on the display panel is connected to a first data line and a second data line. The method further includes: controlling a timing control unit to select the first source drive unit and / or the second source drive unit based on the display mode control signal. When the display mode control signal is low, only one of the first source drive unit or the second source drive unit is selected to implement a first display mode or a second display mode; when the display mode control signal is high, the first source drive unit and the second source drive unit are selected in an alternating odd-even frame manner to implement a third display mode. The first source drive unit outputs data through the first data line in a first arrangement order, and the second source drive unit outputs data through the second data line in a second arrangement order. For the specific dual-source drive unit architecture and selection method, please refer to the above-mentioned... Figures 9-11 The explanation will not be repeated here.

[0133] For example, in one possible implementation, the execution process of the third display mode includes: during odd-numbered frame periods, outputting a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to a first row sequence, and controlling the first source driving unit to output data through the first data line in a first arrangement order; during even-numbered frame periods, outputting a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to a second row sequence, and controlling the second source driving unit to output data through the second data line in a second arrangement order; wherein, the second row sequence is the opposite of the first row sequence. For specific dual-source split-screen timing, please refer to the above regarding... Figure 10 The explanation will not be repeated here.

[0134] For example, in one possible implementation, after outputting the first scan start pulse signal and before enabling the effective gate line, the method further includes: performing a first virtual scan step to pre-charge the virtual gate line; after outputting the second scan start pulse signal and before enabling the effective gate line, the method further includes: performing a second virtual scan step to pre-charge the virtual gate line. The setting of the virtual scan period ensures that the startup node of the GOA's internal shift register obtains a stable pre-charge level before officially enabling the effective gate line, effectively eliminating transient interference during the startup phase. For specific dummy timing details, please refer to the above regarding... Figure 4 , Figure 5 The explanation will not be repeated here.

[0135] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0136] The following points should be noted regarding this disclosure:

[0137] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0138] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0139] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0140] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A display device, comprising: The display module is configured to map output data according to a first arrangement order and / or a second arrangement order, wherein the first arrangement order is the reverse of the second arrangement order; The detection unit is configured to detect whether a viewer is present on the first and / or second sides of the display module; The control unit, electrically connected to both the display module and the detection unit, is configured to generate drive control signals based on the detection results from the detection unit. The control unit is further configured to: In response to the detection unit detecting that the viewer exists only on the first face, the display module is controlled to enter a first display mode based on the drive control signal. The first display mode indicates that data is mapped and output according to the first arrangement order corresponding to the first face. or, In response to the detection unit detecting that the viewer exists only on the second side, the display module is controlled to enter a second display mode based on the drive control signal. The second display mode indicates that data is mapped and output according to the second arrangement order corresponding to the second side. or, In response to the detection unit detecting the presence of viewers on both the first and second surfaces, the display module is controlled to enter a third display mode based on the drive control signal. The third display mode instructs the first display area in the display module to map and output data according to the first arrangement order corresponding to the first surface, and instructs the second display area in the display module to map and output data according to the second arrangement order corresponding to the second surface.

2. The display device according to claim 1, wherein, The display module includes an electrically connected display panel, a timing control unit, and a source drive unit. The display panel includes a first gate array driving circuit and a second gate array driving circuit, which are respectively disposed on opposite sides of the display panel. The first gate array driving circuit is configured to drive each gate line in the first display area, and the second gate array driving circuit is configured to drive each gate line in the second display area.

3. The display device according to claim 2, wherein, The first gate array driving circuit and the second gate array driving circuit are cascaded together. In either the first display mode or the second display mode, the timing control unit outputs a full-screen scan start pulse signal, and the first gate array driving circuit and the second gate array driving circuit are cascaded together to sequentially complete the full-screen continuous scan of the display panel.

4. The display device according to claim 2, wherein, The first gate array driving circuit is disposed on the left side of the display panel and is used to drive all gate lines in the first display area and the second display area; The second gate array driving circuit is located on the right side of the display panel and is used to drive all gate lines in the first display area and the second display area.

5. The display device according to claim 2, wherein, The first gate array driving circuit is disposed on the left side of the display panel, the second gate array driving circuit is disposed on the right side of the display panel, the first display area is the upper half of the display module, and the second display area is the lower half of the display module; The first gate array driving circuit drives each gate line in the upper half of the screen, and the second gate array driving circuit drives each gate line in the lower half of the screen. There is no gate array driving circuit on the left side of the lower half of the screen.

6. The display device according to claim 2, wherein, The execution steps of the third display mode include: During odd-numbered frame periods, the timing control unit outputs a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to the first row sequence, and controls the source driving unit to map and output data in the first arrangement order; and, During even-numbered frame periods, the timing control unit outputs a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to the second row sequence, and controls the source driving unit to map and output data in the second arrangement order; The second row order is the reverse of the first row order.

7. The display device according to claim 2, wherein, The drive control signals include display mode control signals and data transmission direction control signals. The timing control unit has a display mode control pin and is configured to receive and output a corresponding scan start pulse signal and clock signal to the display panel based on the display mode control signal. The timing control unit is also configured to transmit data to the source drive unit. The source drive unit has a data transmission direction control pin, configured to receive and map output data according to the first arrangement order and / or the second arrangement order based on the data transmission direction control signal.

8. The display device according to claim 7, wherein, The display module also includes: A level conversion unit is electrically connected to the timing control unit. The level conversion unit is configured to receive and convert the first scan start pulse signal and the second scan start pulse signal into a first voltage, the first voltage being the turn-on voltage of each gate line in the first display area and each gate line in the second display area.

9. The display device according to claim 7, wherein, The control unit is further configured to: In response to the display mode control signal being low and the data transmission direction control signal being high, the display module is controlled to enter the first display mode; or... In response to the display mode control signal being low and the data transmission direction control signal being low, the display module is controlled to enter the second display mode; or... In response to the display mode control signal being high, the level of the data transmission direction control signal is switched alternately in an odd-even frame manner so that the display module enters the third display mode.

10. The display device according to claim 1, wherein, The drive control signal includes a display mode control signal. The display module includes an electrically connected display panel, a timing control unit, a first source drive unit, and a second source drive unit. Each column of pixels on the display panel is connected to a first data line and a second data line. The timing control unit has a display mode control pin and is configured to receive and output a corresponding scan start pulse signal and clock signal to the display panel based on the display mode control signal. The timing control unit is also configured to transmit data to the first source drive unit and the second source drive unit. The first source driving unit is disposed on the first side of the display panel, and the output pins of the first source driving unit are connected to the first data lines of each column of pixels in the first arrangement order; The second source driving unit is disposed on the second side of the display panel, and the output pins of the second source driving unit are connected to the second data lines of each column of pixels in the second arrangement order.

11. The display device according to claim 10, wherein, The display panel includes a first gate array driving circuit and a second gate array driving circuit. The first gate array driving circuit is configured to drive each gate line in the first display area, and the second gate array driving circuit is configured to drive each gate line in the second display area. The execution steps of the third display mode include: During odd-numbered frame periods, the timing control unit outputs a first scan start pulse signal and a first clock signal to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to the first row sequence, and controls the first source driving unit to map and output data through the first data line in the first arrangement order; and, During even-numbered frame periods, the timing control unit outputs a second scan start pulse signal and a second clock signal to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to the second row sequence, and controls the second source driving unit to map and output data through the second data line in the second arrangement order; The second row order is the reverse of the first row order.

12. The display device according to claim 10, wherein, The control unit is further configured to: In response to the display mode control signal being low, the display module is controlled to enter either the first display mode or the second display mode; or, In response to the display mode control signal being high, the display module is controlled to enter the third display mode.

13. The display device according to claim 6 or 11, wherein, After the timing control unit outputs the first scan start pulse signal and before the first gate array driving circuit turns on the effective gate line, a first virtual scan period is set, during which the first gate array driving circuit performs a pre-charge scan on the virtual gate line. After the timing control unit outputs the second scan start pulse signal and before the second gate array drive circuit turns on the effective gate line, a second virtual scan period is set, during which the second gate array drive circuit performs a pre-charge scan on the virtual gate line.

14. The display device according to any one of claims 1-12, wherein, The detection unit includes: A first image acquisition unit is disposed on the first surface of the display module and is configured to acquire a first image of the first surface. The second image acquisition unit is disposed on the second surface of the display module and is configured to acquire a second image of the second surface. The control unit includes a processor that identifies the viewer's location based on the first image and the second image.

15. The display device according to any one of claims 1-12, wherein, The display module includes a transparent liquid crystal display.

16. The display device according to any one of claims 1-12, wherein, The first arrangement order is that the data in a row are arranged in column order from left to right, and the second arrangement order is that the data in a row are arranged in column order from right to left.

17. A display control method for a display device according to any one of claims 1-16, comprising: Obtain the detection results from the detection unit; A drive control signal is generated based on the detection results; In response to the detection result indicating that only the first side of the display module has a viewer, the display module is controlled to enter a first display mode based on the drive control signal. The first display mode indicates that data is mapped and output according to a first arrangement order corresponding to the first side. In response to the detection result indicating that the viewer exists only on the second side of the display module, the display module is controlled to enter a second display mode based on the drive control signal. The second display mode indicates that data is mapped and output according to a second arrangement order corresponding to the second side, and the first arrangement order is the opposite of the second arrangement order. In response to the detection result indicating that the viewer is present on both the first and second surfaces, the display module is controlled to enter a third display mode based on the drive control signal. The third display mode indicates that the first display area in the display module maps and outputs data according to the first arrangement order corresponding to the first surface, and indicates that the second display area in the display module maps and outputs data according to the second arrangement order corresponding to the second surface.

18. The display control method according to claim 17, wherein, The display module includes an electrically connected display panel, a timing control unit, and a source drive unit. The display module further includes a first gate array driving circuit and a second gate array driving circuit, which are respectively disposed on opposite sides of the display panel. The first gate array driving circuit is used to drive each gate line in the first display area, and the second gate array driving circuit is used to drive each gate line in the second display area.

19. The display control method according to claim 18, wherein, The execution process of the third display mode includes: During odd-numbered frame periods, a first scan start pulse signal and a first clock signal are output to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to the first row sequence, and control the source driving unit to map and output data in the first arrangement order; During even-numbered frame periods, a second scan start pulse signal and a second clock signal are output to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to the second row sequence, and control the source driving unit to map and output data in the second arrangement order; The second row order is the reverse of the first row order.

20. The display control method according to claim 19, wherein, Before the odd-numbered frame period or the even-numbered frame period, the method further includes: The first scan start pulse signal and / or the second scan start pulse signal are level-converted and then output to the corresponding gate line.

21. The display control method according to claim 18, wherein, The drive control signal includes a display mode control signal and a data transmission direction control signal, and the method further includes: The timing control unit outputs a scan start pulse signal and a clock signal according to the display mode control signal; The source drive unit maps and outputs data according to the data transmission direction control signal, in accordance with the first arrangement order and / or the second arrangement order.

22. The display control method according to claim 21, further comprising: In response to the display mode control signal being low and the data transmission direction control signal being high, the display module is controlled to enter the first display mode; or... In response to the display mode control signal being low and the data transmission direction control signal being low, the display module is controlled to enter the second display mode; or... In response to the display mode control signal being high, the level of the data transmission direction control signal is switched alternately in an odd-even frame manner so that the display module enters the third display mode.

23. The display control method according to claim 17, wherein, The driving control signal includes a display mode control signal; the display module includes a first source driving unit and a second source driving unit; each column of pixels on the display panel is correspondingly connected to a first data line and a second data line; the method further includes: Based on the display mode control signal, the timing control unit is controlled to select the first source drive unit and / or the second source drive unit; The first source drive unit outputs data through the first data line in the first arrangement order; The second source drive unit outputs data through the second data line in the second arrangement order.

24. The display control method according to claim 23, wherein, The execution process of the third display mode includes: During odd-numbered frame periods, a first scan start pulse signal and a first clock signal are output to enable the first gate array driving circuit to start scanning of each gate line in the first display area according to the first row sequence, and control the first source driving unit to output data through the first data line in the first arrangement order; During even-numbered frame periods, a second scan start pulse signal and a second clock signal are output to enable the second gate array driving circuit to start scanning of each gate line in the second display area according to the second row sequence, and control the second source driving unit to output data through the second data line in the second arrangement order; The second row order is the reverse of the first row order.

25. The display control method according to claim 19 or 24, wherein, After outputting the first scan start pulse signal and before turning on the active gate line, the method further includes: Perform the first virtual scan step to pre-charge scan the virtual gate lines; After outputting the second scan start pulse signal and before turning on the active gate line, the method further includes: Perform the second virtual scan step to pre-charge scan the virtual gate lines.

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