Driving circuit and display device

Abstract

The application provides a driving circuit and a display device. The driving circuit comprises a timing controller and a vertical blanking period detection circuit. The timing controller obtains a data enable signal based on source image data; the vertical blanking period detection circuit obtains a frame synchronization pulse according to the data enable signal, and outputs a first control signal when the (n+1)th frame synchronization pulse is not detected within a preset threshold time after the end of the nth frame synchronization pulse, and outputs a second control signal when the (n+1)th frame synchronization pulse is detected within the preset threshold time after the end of the nth frame synchronization pulse; the timing controller controls the polarity inversion of a data voltage in a first polarity inversion mode in response to the first control signal and controls the polarity inversion of the data voltage in a second polarity inversion mode in response to the second control signal; and the polarity inversion frequency in the first polarity inversion mode is higher than the polarity inversion frequency in the second polarity inversion mode. The driving circuit can improve the flicker problem of the display.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving circuit and a display device. Background Technology

[0002] With the continuous evolution of Liquid Crystal Display (LCD) technology, the market demand for ultra-high refresh rates has been growing, gradually increasing from the traditional 60Hz to 300Hz, 400Hz, 500Hz, and even over 1000Hz. High refresh rates can significantly reduce motion blur, improving the smoothness of dynamic images and the visual experience. However, simply increasing a fixed refresh rate cannot completely solve the screen tearing and stuttering problems caused by the asynchrony between the graphics card's output frame rate and the monitor's refresh rate in games or dynamic scenes. To address this, Variable Refresh Rate (VRR) technology has emerged, with typical implementations including FreeSync (adaptive synchronization) and G-Sync (global synchronization). VRR allows the monitor to dynamically adjust its refresh rate based on the instantaneous frame rate output by the graphics card, keeping the two synchronized, thereby completely eliminating tearing and reducing input lag. In practical applications, VRR's operating frequency range often spans a wide range, from 48Hz to 500Hz or even higher, covering the entire spectrum from low to extremely high frame rates.

[0003] However, in VRR mode, brightness flicker becomes apparent. Since the brightness characteristics of an LCD panel are closely related to the driving voltage, pixel response time, and backlight modulation method, when the refresh rate changes rapidly over a wide range, pixel charging time, capacitor leakage, and the nonlinearity of the gamma curve will cause fluctuations in the actual brightness of each frame. The human eye can perceive these as periodic or random changes in brightness, which seriously affects the user experience.

[0004] The most common suppression method used in the industry is a brightness compensation mechanism based on gamma lookup tables. However, this method still suffers from limited brightness compensation and uneven brightness transitions due to limitations in the number of tables stored. Summary of the Invention

[0005] In view of this, the main objective of this application is to propose a driving circuit and display device that aims to solve the brightness flicker problem of existing high refresh rate LCDs in VRR mode.

[0006] To achieve the above objectives, a first aspect of this application provides a driving circuit for driving a display panel to display, the driving circuit including a timing controller and a vertical blanking period detection circuit. The system includes a timing controller for receiving source image data and obtaining a data enable signal based on the source image data; a vertical blanking period detection circuit electrically connected to the timing controller for receiving the data enable signal output by the timing controller, processing the data enable signal, obtaining a frame synchronization pulse based on the vertical blanking period in the data enable signal, and outputting a first control signal when no (n+1)th frame synchronization pulse is detected within a preset threshold time after the end of the nth frame synchronization pulse, and outputting a second control signal when the (n+1)th frame synchronization pulse is detected within a preset threshold time after the end of the nth frame synchronization pulse; wherein n≥1; wherein the timing controller responds to the first control signal by using a first polarity reversal mode to control the data voltage to perform polarity reversal, and responds to the second control signal by using a second polarity reversal mode to control the data voltage to perform polarity reversal; wherein the number of display frames between two adjacent polarity reversals in the first polarity reversal mode is less than the number of display frames between two adjacent polarity reversals in the second polarity reversal mode.

[0007] The driving circuit provided in this application determines the refresh rate corresponding to the nth frame period based on the time interval between the nth frame synchronization pulse and the (n+1)th frame synchronization pulse through the vertical blanking period detection circuit, and outputs the corresponding toggle mode control signal to the timing controller according to the refresh rate corresponding to the nth frame period, so as to control the source driver to switch the polarity toggle mode in real time. It can realize the adaptive adjustment of the polarity toggle interval according to the refresh rate, so that the actual time frequency of polarity toggle can be maintained at a better balance point at both high and low refresh rates, thereby avoiding the problem of screen flickering caused by the mismatch between the polarity toggle interval and the refresh rate.

[0008] In some embodiments, the timing controller is further configured to generate a frame start signal, and the timing controller is configured to control the data voltage to perform polarity reversal using the first polarity reversal mode when receiving the first control signal at a preset time before the effective level pulse of the frame start signal, and to control the data voltage to perform polarity reversal using the second polarity reversal mode when receiving the second control signal at a preset time before the effective level pulse of the frame start signal.

[0009] In some embodiments, the vertical blanking period detection circuit includes an envelope extraction circuit, a pulse generation circuit, and a timing comparison circuit. The circuit includes an envelope extraction circuit electrically connected to the timing controller. It receives the data enable signal output by the timing controller and performs asymmetric integral filtering on the data enable signal to filter out high-frequency components generated by the periodic switching between the row valid data segment and the row blanking segment. It also extracts the vertical blanking period envelope signal to characterize the vertical blanking period. A pulse generation circuit electrically connected to the envelope extraction circuit receives the vertical blanking period envelope signal output by the envelope extraction circuit. It generates a square wave signal based on the relationship between the vertical blanking period envelope signal and a first preset reference voltage, and differentiates the edges of the square wave signal to obtain the frame synchronization pulse. A timing comparison circuit receives the frame synchronization pulse and times the time interval between two adjacent frame synchronization pulses. It outputs the first control signal when no (n+1)th frame synchronization pulse is detected within a preset threshold time after the end of the nth frame synchronization pulse, and outputs the second control signal when the (n+1)th frame synchronization pulse is detected within the preset threshold time after the end of the nth frame synchronization pulse.

[0010] In some embodiments, the pulse generation circuit includes a hysteresis comparison circuit and a differentiating circuit. The hysteresis comparison circuit is electrically connected to the envelope extraction circuit, and the differentiating circuit is electrically connected between the hysteresis comparison circuit and the timing comparison circuit. The hysteresis comparison circuit has a rising edge trigger threshold and a falling edge trigger threshold, which are set based on a first preset reference voltage. The hysteresis comparison circuit performs a hysteresis comparison between the vertical blanking period envelope signal and the rising edge trigger threshold and the falling edge trigger threshold to obtain a square wave signal. The differentiating circuit performs differential processing on the edges of the square wave signal to obtain the frame synchronization pulse.

[0011] In some embodiments, the envelope extraction circuit includes a diode, a first resistor, and a first capacitor. The anode of the diode is electrically connected to the timing controller for receiving the data enable signal output by the timing controller, and the cathode of the diode is electrically connected to the pulse generation circuit. The first capacitor is connected in parallel with the first resistor between the cathode of the diode and ground. The diode, the first resistor, and the first capacitor constitute a filter circuit to perform asymmetric integral filtering on the data enable signal to filter out high-frequency components generated by the periodic switching between the row valid data segment and the row blanking segment, and output the vertical blanking period envelope signal to the pulse generation circuit.

[0012] In some embodiments, the hysteresis comparator circuit includes a first comparator, a first voltage divider resistor, a second voltage divider resistor, and a hysteresis resistor. The inverting input of the first comparator is electrically connected to the envelope extraction circuit, and the output of the first comparator is electrically connected to the differentiating circuit. The first voltage divider resistor is electrically connected between a voltage source and the non-inverting input of the first comparator. The second voltage divider resistor is electrically connected between the non-inverting input of the first comparator and ground. The hysteresis resistor is electrically connected between the non-inverting input and the output of the first comparator.

[0013] In some embodiments, the differentiating circuit includes a second capacitor and a second resistor. A first terminal of the second capacitor is electrically connected to the hysteresis comparator circuit, and a second terminal of the second capacitor is electrically connected to the timing comparator circuit; the second resistor is electrically connected between the second terminal of the second capacitor and ground.

[0014] In some embodiments, the timing comparison circuit includes a switching transistor, a reference voltage generation circuit, a second comparator, a timing capacitor, and a timing resistor. The control terminal of the switching transistor is electrically connected to the pulse generation circuit and is used to receive the frame synchronization pulse output by the pulse generation circuit; the first connection terminal of the switching transistor is grounded. The reference voltage generation circuit is used to generate a second preset reference voltage; the second preset reference voltage corresponds to the preset threshold time. The inverting input terminal of the second comparator is electrically connected to the second connection terminal of the switching transistor, and the non-inverting input terminal of the second comparator is electrically connected to the reference voltage generation circuit, used to receive the second preset reference voltage output by the reference voltage generation circuit. The first terminal of the timing capacitor is electrically connected to the second connection terminal of the switching transistor, and the second terminal of the timing capacitor is grounded. The timing resistor is electrically connected between the voltage source and the second connection terminal of the switching transistor.

[0015] In some embodiments, the switching transistor is a high-level on switching transistor; when the switching transistor receives the nth frame synchronization pulse, the switching transistor connects the inverting input terminal of the second comparator to ground, causing the second comparator to output the second control signal; when the nth frame synchronization pulse ends, the switching transistor disconnects the inverting input terminal of the second comparator from ground, causing the voltage source to charge the timing capacitor through the timing resistor; when the switching transistor receives the (n+1)th frame synchronization pulse within the preset threshold time after the nth frame synchronization pulse ends, the voltage at the inverting input terminal of the second comparator is lower than the second preset reference voltage, thereby the second comparator continues to output the second control signal; when the switching transistor does not receive the (n+1)th frame synchronization pulse within the preset threshold time after the nth frame synchronization pulse ends, the voltage at the inverting input terminal of the second comparator is charged to a level higher than the second preset reference voltage, thereby causing the second comparator to output the first control signal.

[0016] A second aspect of this application provides a display device, the display device including a display panel and a driving circuit as described in the first aspect above, the driving circuit being used to drive the display panel to perform a display.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the display device provided in the embodiments of this application; Figure 2 for Figure 1 A schematic diagram of the vertical blanking period detection circuit in the image; Figure 3 for Figure 2 The circuit diagram of the vertical blanking period detection circuit is shown. Figure 4 for Figure 3 The timing diagram of each signal in the diagram.

[0019] The annotations in the attached figures are explained as follows: Display device 1; driving circuit 10; display panel 20; timing controller 11; vertical blanking period detection circuit 12; source driver 13; data enable signal DE; frame synchronization pulse PS; flip mode control signal TTL; frame start signal STV; envelope extraction circuit 121; vertical blanking period envelope signal EDS; pulse generation circuit 122; square wave signal EDS_ws; timing comparator circuit 123; hysteresis comparator circuit 1221; differentiating circuit 1222; diode D1; first resistor R1; first capacitor C1; first comparator A1; first voltage divider resistor R_H; second voltage divider resistor R_L; third voltage divider resistor R_H2; fourth voltage divider resistor R_L2; hysteresis resistor R_fb; second capacitor C2; second resistor R2; switching transistor Q1; reference voltage generation circuit 1231; second comparator A2; timing capacitor C_T; timing resistor R_T.

[0020] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] Furthermore, the terms "first," "second," etc., used in this specification are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0024] With the continuous evolution of LCD technology, the market demand for ultra-high refresh rates is growing, currently increasing from the traditional 60Hz to 300Hz, 400Hz, 500Hz, and even above 1000Hz. High refresh rates can significantly reduce motion blur, improving the smoothness of dynamic images and the overall visual experience. However, simply increasing a fixed refresh rate cannot completely solve the screen tearing and stuttering problems caused by the asynchrony between the graphics card's output frame rate and the monitor's refresh rate in games or dynamic scenes.

[0025] To address this, variable refresh rate (VRR) technology emerged, with typical implementations including FreeSync (Adaptive Sync) and G-Sync (Global Sync). VRR allows the monitor to dynamically adjust its refresh rate based on the instantaneous frame rate output by the graphics card, keeping the two synchronized, thereby completely eliminating screen tearing and reducing input lag. In practical applications, VRR often operates over a wide range of frequencies, from 48Hz to 500Hz or even higher, covering the entire spectrum from low to extremely high frame rates.

[0026] However, in VRR mode, brightness flickering becomes apparent. Since the brightness characteristics of an LCD panel are closely related to the driving voltage, pixel response time, and backlight modulation method, when the refresh rate changes rapidly over a wide range, pixel charging time, capacitor leakage, and the nonlinearity of the gamma curve will cause fluctuations in the actual brightness of each frame. The human eye can perceive these as periodic or random changes in brightness, which seriously impairs the user experience.

[0027] Currently, the commonly used brightness compensation schemes in the industry mainly fall into two categories: one is the brightness compensation mechanism based on a gamma look-up table (Gamma LUT), and the other is liquid crystal overdrive technology. The Gamma LUT scheme pre-stores multiple sets of gamma correction parameters corresponding to different refresh rates in memory, and attempts to maintain constant brightness by real-time detection of the current refresh rate and looking up the table to switch compensation values. Overdrive technology, on the other hand, accelerates pixel response by applying a driving voltage higher than the target grayscale to the liquid crystal, thereby reducing transient brightness deviations caused by refresh rate changes.

[0028] However, all of the above solutions have inherent limitations. Gamma LUT compensation is essentially a digital adjustment in the digital domain, meaning it corrects brightness by modifying the grayscale data in the digital video signal. But when the refresh rate exceeds 300Hz, the polarity reversal cycle of the LCD panel shortens drastically, and the time loss required for polarity switching accounts for a significantly larger proportion of the effective driving time of each frame, resulting in a substantial decrease in the compensation effect. Especially when the monitor suddenly switches from an ultra-high refresh rate (e.g., 500Hz) to a lower refresh rate (e.g., 48Hz), the drastic change in polarity switching mode introduces additional brightness differences, thus failing to effectively eliminate flicker.

[0029] In addition, the Gamma LUT scheme is limited by the storage capacity of the lookup table and can only cover a limited number of refresh rate points discretely. For continuously changing VRR intervals, the interpolation accuracy is insufficient, and the switching of compensation parameters between different refresh rates lacks a smooth transition mechanism, which can easily cause sudden changes in brightness.

[0030] Therefore, there is an urgent need for a driving circuit that can overcome the bottleneck of digital domain compensation, adapt to a wide VRR range, and achieve continuous and smooth brightness compensation in order to solve the brightness flicker problem of high refresh rate LCDs in VRR mode.

[0031] In view of this, this application provides a driving circuit 10 for driving a display panel 20 to display.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 1 As shown, the driving circuit 10 includes a timing controller 11, a vertical blanking period detection circuit 12, and a source driver 13.

[0033] The timing controller 11 is used to receive source image data and obtain a data enable signal DE based on the source image data. The source image data includes video data and timing information, etc. The timing controller 11 includes a high-speed receiver decoder (not shown in the figure), which receives the source image data, performs low-level protocol decoding on the source image data, reconstructs the data enable signal DE in real time, and synchronously outputs the data enable signal DE to the vertical blanking period detection circuit 12 through its pin interface.

[0034] The vertical blanking period detection circuit 12 is electrically connected to the timing controller 11 and is used to receive the data enable signal DE output by the timing controller 11, process the data enable signal DE, and obtain the frame synchronization pulse PS based on the vertical blanking period in the data enable signal DE. The frame synchronization pulse PS is used to characterize the start feature of the vertical blanking period of each frame. That is, each frame period corresponds to one frame synchronization pulse PS, and the time interval between two adjacent frame synchronization pulses PS is positively correlated with the duration of the vertical blanking period in the frame period. Specifically, the nth frame period corresponds to the nth frame synchronization pulse PS, the (n+1)th frame period corresponds to the (n+1)th frame synchronization pulse PS, and the time interval between the nth frame synchronization pulse PS and the (n+1)th frame synchronization pulse PS is positively correlated with the duration of the vertical blanking period in the nth frame period.

[0035] The vertical blanking period detection circuit 12 is used to determine the refresh rate corresponding to the nth frame period based on the time interval between the nth frame synchronization pulse PS and the (n+1)th frame synchronization pulse PS, and outputs a corresponding toggle mode control signal TTL to the timing controller 11 according to the refresh rate corresponding to the nth frame period, so as to control the source driver 13 to switch the polarity toggle mode in real time. Specifically, the toggle mode control signal TTL includes a first control signal and a second control signal. For example, the first control signal is a low-level signal and the second control signal is a high-level signal.

[0036] The vertical blanking period detection circuit 12 outputs the first control signal when no (n+1)th frame synchronization pulse PS is detected within a preset threshold time after the end of the nth frame synchronization pulse PS, and outputs the second control signal when the (n+1)th frame synchronization pulse PS is detected within the preset threshold time after the end of the nth frame synchronization pulse PS. Where n≥1, the first control signal indicates a low refresh rate state, and the second control signal indicates a high refresh rate state.

[0037] The preset threshold time can be determined based on a frame period of the switching threshold between high refresh rate and low refresh rate (e.g., 144Hz, 240Hz).

[0038] It should be noted that when the time interval between the current moment and the end of the nth frame synchronization pulse PS is less than the preset threshold time, the vertical blanking period detection circuit 12 continuously outputs the second control signal. If the vertical blanking period detection circuit 12 continuously outputs the second control signal during the time interval between the nth frame synchronization pulse PS, it indicates that the refresh rate corresponding to the nth frame period is a high refresh rate. When the time interval between the current moment and the end of the nth frame synchronization pulse PS is greater than the preset threshold time, and no (n+1)th frame synchronization pulse PS is detected during this period, the vertical blanking period detection circuit 12 outputs the first control signal, indicating that the refresh rate corresponding to the nth frame period is a low refresh rate.

[0039] The timing controller 11 responds to the first control signal by using a first polarity reversal mode to control the data voltage to reverse polarity, and responds to the second control signal by using a second polarity reversal mode to control the data voltage to reverse polarity. In the first polarity reversal mode, the number of display frames between two adjacent polarity reversals is less than the number of display frames between two adjacent polarity reversals in the second polarity reversal mode.

[0040] The source driver 13 is electrically connected to the timing controller 11, and the source driver 13 is used to output data voltage to the display panel 20 according to the polarity inversion mode set by the timing controller 11. For example, in the first polarity inversion mode, the polarity of the data voltage output by the source driver 13 is inverted once per frame. In the second polarity inversion mode, the polarity of the data voltage output by the source driver 13 is inverted once every two frames.

[0041] It should be noted that the main reasons for flickering in LCD monitors caused by VRR mode are as follows: 1. At low refresh rates, prolonged exposure to the same polarity can lead to the accumulation of ionic impurities, forming a DC bias that causes image retention and brightness drift; 2. At high refresh rates, short charging times and frequent switching can easily lead to asymmetric charging of positive and negative polarities.

[0042] The driving circuit 10 provided in this application determines the refresh rate corresponding to the nth frame period based on the time interval between the nth frame synchronization pulse PS and the (n+1)th frame synchronization pulse PS through the vertical blanking period detection circuit 12, and outputs the corresponding toggle mode control signal TTL to the timing controller 11 according to the refresh rate corresponding to the nth frame period, so as to control the source driver 13 to switch the polarity toggle mode in real time. This can realize the adaptive adjustment of the polarity toggle interval according to the refresh rate, so that the actual time frequency of polarity toggle can be kept at a better balance point at both high and low refresh rates, thereby avoiding the problem of screen flickering caused by the mismatch between the polarity toggle interval and the refresh rate.

[0043] Specifically, at lower refresh rates, the frame period is longer. If the flip interval is too large, prolonged use of the same polarity will exacerbate ion accumulation. Therefore, a smaller flip interval is needed to allow rapid alternation of positive and negative polarities, which can disrupt directional ion migration. At higher refresh rates, the frame period is extremely short. If the flip interval is too small, the number of flips per unit time will surge, leading to insufficient charging time and potentially causing positive-negative asymmetry, which will worsen flicker. Therefore, a larger flip interval is needed to maintain a sufficient polarity alternation rate to prevent DC accumulation, while also allowing the same polarity to persist for multiple frames to compensate for insufficient charging time.

[0044] In some embodiments of this application, the timing controller 11 is further configured to generate a frame start signal STV. The timing controller 11 is configured to control the data voltage to perform polarity reversal using the first polarity reversal mode when it receives the first control signal at a preset time before the effective level pulse of the frame start signal STV, and to control the data voltage to perform polarity reversal using the second polarity reversal mode when it receives the second control signal at a preset time before the effective level pulse of the frame start signal STV.

[0045] The preset time interval between the effective level pulse of the frame start signal STV can be on the order of microseconds. In this way, the refresh rate determination and polarity reversal mode determination can be completed before the arrival of the new effective level pulse of the frame start signal STV, and the real-time performance of polarity reversal mode switching is improved.

[0046] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the vertical blanking period detection circuit is shown. In some embodiments of this application, the vertical blanking period detection circuit 12 includes an envelope extraction circuit 121, a pulse generation circuit 122, and a timing comparison circuit 123.

[0047] The envelope extraction circuit 121 is electrically connected to the timing controller 11. The envelope extraction circuit 121 is used to receive the data enable signal DE output by the timing controller 11, and perform asymmetric integral filtering on the data enable signal DE to filter out the high-frequency components generated by the periodic switching between the row valid data segment and the row blanking segment in the data enable signal DE, and extract the vertical blanking period envelope signal EDS used to characterize the timing of the vertical blanking period.

[0048] The "line active data segment" refers to the period during which the data enable signal DE is high within a single line scan cycle. During this period, the source driver 13 writes the data voltage for that line to the sub-pixels in the display panel. The "line blanking segment" refers to the period during which the data enable signal DE is low within a single line scan cycle. Located after the end of a single line active data segment and before the start of the next line active data segment, it provides line buffer time. The "vertical blanking period" refers to the period after the end of one frame cycle and before the start of the next frame cycle during which the data enable signal DE remains low. No active pixel data is transmitted during this period, providing buffer time for the liquid crystal molecules to respond.

[0049] For example, taking a QHD (Quad High Definition) 48Hz-540Hz display panel as an example, the vertical active rows (V_active) are 1440, the vertical blanking rows (V_blank) are 40, and the vertical total rows (V_total) are 1480. The horizontal active pixels (H_active) are 2560 pixels, the horizontal blanking pixels (H_blank) are 80 pixels, and the horizontal total pixels (H_total) are 2640 pixels. At a refresh rate of 540Hz, the frame time is 1 / 540Hz = 1.85ms = 1850us, the line scan time (TH) is 1850us / 1480H = 1.25us, and the line blanking time is 80 / 2640 × 1.25us = 0.038us = 38ns. At a refresh rate of 48Hz, the horizontal blanking time (TH_blank) is as follows: In VRR mode, the horizontal frequency remains unchanged, and only the vertical blanking line count (V_blank) is increased. That is, the duration of the vertical blanking period at a refresh rate of 48Hz is (1 / 48Hz) - (1440 × 1.125us) = 19ms.

[0050] The pulse generation circuit 122 is electrically connected to the envelope extraction circuit 121 and is used to receive the vertical blanking period envelope signal EDS output by the envelope extraction circuit 121, generate a square wave signal EDS_ws based on the relationship between the vertical blanking period envelope signal EDS and the first preset reference voltage, and perform differential processing on the edge of the square wave signal EDS_ws to obtain the frame synchronization pulse PS.

[0051] The timing comparison circuit 123 is used to receive the frame synchronization pulse PS, and to time the time interval between two adjacent frame synchronization pulses PS. When no frame synchronization pulse PS is detected within a preset threshold time after the end of the nth frame synchronization pulse PS, the circuit outputs the first control signal. When the frame synchronization pulse PS is detected within the preset threshold time after the end of the nth frame synchronization pulse PS, the circuit resets the timing and outputs the second control signal.

[0052] In some embodiments of this application, the pulse generation circuit 122 includes a hysteresis comparison circuit 1221 and a differentiating circuit 1222. The hysteresis comparison circuit 1221 is electrically connected to the envelope extraction circuit 121, and the differentiating circuit 1222 is electrically connected between the hysteresis comparison circuit 1221 and the timing comparison circuit 123.

[0053] The hysteresis comparison circuit 1221 is provided with a rising edge trigger threshold and a falling edge trigger threshold. The rising edge trigger threshold and the falling edge trigger threshold are set based on the first preset reference voltage. The hysteresis comparison circuit 1221 is used to perform a hysteresis comparison between the vertical blanking period envelope signal EDS and the rising edge trigger threshold and the falling edge trigger threshold to obtain a square wave signal EDS_ws.

[0054] The differentiating circuit 1222 is used to differentiate the edge of the square wave signal EDS_ws to obtain the frame synchronization pulse PS.

[0055] The rising edge trigger threshold, also known as the upper threshold voltage, refers to the input voltage value corresponding to a transition (e.g., from high to low) in the comparator output state when the input signal (i.e., the vertical blanking envelope signal EDS) gradually rises from a low level. The falling edge trigger threshold, also known as the lower threshold voltage, refers to the input voltage value corresponding to a transition (e.g., from low to high) in the comparator output state when the input signal gradually decreases from a high level. The rising edge trigger threshold is greater than the falling edge trigger threshold.

[0056] Please refer to the following: Figures 3-4 , Figure 3 for Figure 2 The circuit diagram of the vertical blanking period detection circuit is shown. Figure 4 for Figure 3 The timing diagram of each signal in the diagram.

[0057] like Figure 3 As shown, the envelope extraction circuit 121 includes a diode D1, a first resistor R1, and a first capacitor C1.

[0058] The anode of diode D1 is electrically connected to the timing controller 11 to receive the data enable signal DE output by the timing controller 11, and the cathode of diode D1 is electrically connected to the hysteresis comparator circuit 1221 in the pulse generation circuit 122.

[0059] The first capacitor C1 and the first resistor R1 are connected in parallel between the cathode of the diode D1 and ground.

[0060] The diode D1, the first resistor R1, and the first capacitor C1 constitute a filter circuit to perform asymmetric integral filtering on the data enable signal DE, thereby filtering out the high-frequency components generated by the periodic switching between the row valid data segment and the row blanking segment in the data enable signal DE, and outputting the vertical blanking envelope signal EDS to the pulse generation circuit 122.

[0061] Specifically, taking a QHD (Quad High Definition) 48Hz-540Hz display panel as an example, the working principle of the envelope extraction circuit 121 is as follows: During the active data segment, the data enable signal DE is high. At this time, the diode D1 is forward-biased, and the first capacitor C1 receives the data enable signal DE, performs rapid charging and voltage boosting, and maintains a high level. The driving circuit 10 enters the row blanking segment after scanning each row.

[0062] During the horizontal blanking phase, the data enable signal DE will have a low level time of 38ns. At this time, the diode D1 will be reverse cut off, cutting off the return path of the first capacitor C1. The first capacitor C1 can only discharge slowly through the first resistor R1. That is to say, the diode D1 makes the first capacitor C1 have the asymmetric characteristics of fast charging and slow discharging. Since the horizontal blanking phase is extremely short, the voltage of the first capacitor C1 will hardly drop. In this way, the high-frequency components in the data enable signal DE can be filtered out to obtain the DC envelope signal.

[0063] After the driving circuit 10 completes scanning 1440 vertical effective lines of one frame, it enters the vertical blanking period. During the vertical blanking period, the data enable signal DE will remain at a low level for 40 lines (40 × 1.25 = 50 μs). At this time, the diode D1 is in the off state, and the first capacitor C1 will be deeply and effectively discharged through the first resistor R1, thereby keeping the first capacitor C1 at a low level.

[0064] Thus, through the above three circuit operation stages, the envelope extraction circuit 121 can filter out the high-frequency components in the data enable signal DE, thereby extracting the high-frequency components such as... Figure 4 The vertical blanking period envelope signal EDS is shown.

[0065] In some embodiments of this application, the hysteresis comparator circuit 1221 includes a first comparator A1, a first voltage divider resistor R_H, a second voltage divider resistor R_L, and a hysteresis resistor R_fb.

[0066] The inverting input of the first comparator A1 is electrically connected to the cathode of the diode D1 in the envelope extraction circuit 121, and is used to receive the vertical blanking envelope signal EDS output by the hysteresis comparator circuit 1221. The output of the first comparator A1 is electrically connected to the differentiating circuit 1222, and is used to output the square wave signal EDS_ws to the differentiating circuit 1222.

[0067] The first voltage divider resistor R_H is electrically connected between the voltage source (e.g., 3.3V) and the non-inverting input of the first comparator A1.

[0068] The second voltage divider resistor R_L is electrically connected between the non-inverting input of the first comparator A1 and ground.

[0069] The hysteresis resistor R_fb is electrically connected between the non-inverting input and the output of the first comparator A1.

[0070] The hysteresis comparator circuit 1221 utilizes an inverting comparator topology with a positive feedback network to invert the signal logic of the vertical blanking envelope signal EDS, transforming the falling edge of the vertical blanking envelope signal EDS into a steep positive trigger edge. The hysteresis comparator circuit 1221 further achieves hysteresis comparison by setting the hysteresis resistor R_fb and introducing rising edge trigger thresholds and falling edge trigger thresholds based on the first preset reference voltage, thus obtaining the square wave signal EDS_ws. This eliminates the level oscillation problem caused by signal noise floor in high-frequency complex display systems, providing a clean timing foundation for subsequent differential processing.

[0071] The rising edge trigger threshold and the falling edge trigger threshold are described below using R_H=20kΩ, R_L=10kΩ, and R_fb=470kΩ as examples. The first preset reference voltage = 3.3V×R_L / (R_L+R_H) = 1.1V.

[0072] When the first comparator A1 outputs a low level (i.e., 0V), the hysteresis resistor R_fb is equivalent to being connected in parallel with the second voltage divider resistor R_L between the non-inverting input terminal of the first comparator A1 and ground. The equivalent resistance of the two is R_Leq = R_L × R_fb / (R_L + R_fb) = 9.79kΩ. Then, the formula for calculating the falling edge trigger threshold Vth- is: Vth- = 3.3V × R_Leq / (R_H + R_Leq) = 1.084V.

[0073] When the first comparator A1 outputs a high level (i.e., 3.3V), the hysteresis resistor R_fb is equivalent to being connected in parallel with the first voltage divider resistor R_H between the voltage source and the non-inverting input of the first comparator A1. The equivalent resistance of the two is R_Heq. Then, the formula for calculating the rising edge trigger threshold Vth+ is: Vth+=3.3V×R_L / (R_L+R_Heq)=1.131V.

[0074] Therefore, the hysteresis resistor R_fb introduces a hysteresis threshold ΔVth=(Vth+)-(Vth-)=0.047V. Thus, by dynamically changing the reference threshold at the moment the output state flips (e.g., jumping from 1.084V to 1.131V), a hardware hysteresis window with tolerance is constructed, which can effectively handle the level oscillation problem caused by signal noise in high-frequency complex display systems.

[0075] The working principle of the hysteresis comparator circuit 1221 is as follows: During the row valid data segment and the row blanking segment, the vertical blanking envelope signal EDS is at a high level. At this time, the voltage at the inverting input terminal of the first comparator A1 is higher than the voltage at the non-inverting input terminal, so the first comparator A1 outputs a low level.

[0076] During the vertical blanking period, the vertical blanking envelope signal EDS decreases slowly. As long as it does not fall below the falling edge trigger threshold of the first comparator A1, the first comparator A1 maintains a low output level. When it falls to or below the falling edge trigger threshold of the first comparator A1, the first comparator A1 will momentarily output a high level.

[0077] In some embodiments of this application, the differentiating circuit 1222 includes a second capacitor C2 and a second resistor R2.

[0078] The first end of the second capacitor C2 is electrically connected to the hysteresis comparator circuit 1221 to receive the square wave signal EDS_ws output by the hysteresis comparator circuit 1221, and the second end of the second capacitor C2 is electrically connected to the timing comparator circuit 123.

[0079] The second resistor R2 is electrically connected between the second terminal of the second capacitor C2 and ground.

[0080] It should be noted that since the high level of the square wave signal EDS_ws output by the hysteresis comparator circuit 1221 lasts for almost the entire vertical blanking period, if this wide square wave is directly used to drive the switch Q1 in the subsequent timing comparator circuit 123, the switch Q1 will be clamped in the on state for a long time, causing the timing capacitor C_T in the timing comparator circuit 123 to be unable to start the next round of charging timing for a long time, which will introduce serious system errors.

[0081] The differentiating circuit 1222 utilizes the physical characteristic that the voltage across a capacitor cannot change instantaneously to clip the rising edge of the square wave signal EDS_ws from the previous stage into an extremely short nanosecond / microsecond spike pulse, enabling true "zero-delay check-in" and instantaneous bus release. The working principle of the differentiating circuit 1222 is described below using the second capacitor C2=1nF and the second capacitor C2=1kΩ as an example: At the instant of the rising edge of the square wave signal EDS_ws, the voltage of the square wave signal EDS_ws rises from 0V to 3.3V, and the rise time Tr is extremely short (signal dV / dT is extremely large). According to the definition of physics, the voltage across a capacitor cannot change abruptly. At this time, in this extremely short period of time, the second capacitor C2 is equivalent to a fully conductive short circuit. The 3.3V voltage from the previous stage will be applied to the second resistor R2, so the voltage at the second terminal of the second capacitor C2 will jump from 0V to 3.3V, that is, the differentiating circuit 1222 outputs the frame synchronization pulse PS.

[0082] During the flat-top phase of the square wave signal EDS_ws, after the front-end voltage stabilizes at 3.3V, the square wave signal EDS_ws will charge the second capacitor C2 through the second resistor R2. As the charge in the second capacitor C2 accumulates, the voltage across the second resistor R2 will decrease.

[0083] When the second capacitor C2 is fully charged, no current will flow through the circuit, the voltage of the second resistor R2 will return to zero, and the voltage at the second terminal of the second capacitor C2 will return to 0V, that is, the output frame synchronization pulse PS of the differentiating circuit 1222 will end.

[0084] Thus, after operating through the aforementioned stages, the differentiating circuit 1222 responds to the rising edge of the square wave signal EDS_ws from the preceding stage, converting it into a signal such as... Figure 4 The frame synchronization pulse PS with a positive, extremely narrow spike is shown.

[0085] In some embodiments of this application, the timing comparison circuit 123 includes a switching transistor Q1, a reference voltage generation circuit 1231, a second comparator A2, a timing capacitor C_T, and a timing resistor R_T.

[0086] The control terminal of the switch Q1 is electrically connected to the differentiating circuit 1222 in the pulse generation circuit 122. The control terminal of the switch Q1 is used to receive the frame synchronization pulse PS output by the pulse generation circuit 122. The first connection terminal of the switch Q1 is grounded.

[0087] The reference voltage generation circuit 1231 is used to generate a second preset reference voltage, which corresponds to the preset threshold time. Specifically, the reference voltage generation circuit 1231 includes a third voltage divider resistor R_H2 and a fourth voltage divider resistor R_L2. The third voltage divider resistor R_H2 is electrically connected between its non-inverting input terminal and the voltage source, and the fourth voltage divider resistor R_L2 is electrically connected between its non-inverting input terminal and ground. The third voltage divider resistor R_H2 and the fourth voltage divider resistor R_L2 are used to divide the power supply voltage provided by the voltage source to obtain the second preset reference voltage.

[0088] The inverting input of the second comparator A2 is electrically connected to the second connection terminal of the switching transistor Q1, and the non-inverting input of the second comparator A2 is electrically connected to the reference voltage generation circuit 1231. The non-inverting input of the second comparator A2 is used to receive the second preset reference voltage output by the reference voltage generation circuit 1231, and the output of the second comparator A2 is used to output the flip mode control signal TTL (i.e. the aforementioned).

[0089] The first terminal of the timing capacitor C_T is electrically connected to the second terminal of the switching transistor Q1, and the second terminal of the timing capacitor C_T is grounded.

[0090] The timing resistor R_T is electrically connected between the voltage source and the second connection terminal of the switching transistor Q1.

[0091] In some embodiments of this application, the switch Q1 is a high-level on switch (e.g., an NMOS transistor). When the switch Q1 receives the nth frame synchronization pulse PS, the switch Q1 connects the inverting input of the second comparator A2 to ground, causing the second comparator A2 to output the second control signal.

[0092] At the end of the nth frame synchronization pulse PS, the switch Q1 disconnects the electrical connection between the inverting input of the second comparator A2 and ground, allowing the voltage source to charge the timing capacitor C_T through the timing resistor R_T. When the switch Q1 receives the (n+1)th frame synchronization pulse PS within the preset threshold time after the end of the nth frame synchronization pulse PS, the voltage at the inverting input of the second comparator A2 is lower than the second preset reference voltage, thus the second comparator continues to output the second control signal.

[0093] When the switch Q1 does not receive the (n+1)th frame synchronization pulse PS within the preset threshold time after the end of the nth frame synchronization pulse PS, the voltage at the inverting input of the second comparator A2 is charged to a level higher than the second preset reference voltage, thereby causing the second comparator A2 to output the first control signal.

[0094] The switching between high and low refresh rates is limited by the physical contradiction between the leakage rate and charging rate of the liquid crystal. The industry generally defines the switching threshold between high and low refresh rates as 144Hz and 240Hz. The frame period corresponding to the 240Hz refresh rate is 1000ms / 240 = 4.16ms, and the frame period corresponding to the 1440Hz refresh rate is 1000ms / 144 = 6.94ms. In order to balance the high frequency without misjudgment and the low frequency with fast response, the preset threshold time T_out = 5.1ms can be set.

[0095] The working principle of the timing comparator circuit 123 will be described in detail below, taking the timing resistor R_T=100kΩ and the timing capacitor C_T=0.1uF as an example: The time parameter τ = R_T × C_T = 10ms. According to the DC RC charging formula: V_D(t) = VCC × (1 - e^(-t / τ)), substituting t = 5.1ms, VCC = 3.3V, and τ = 10ms, we can obtain the threshold voltage V_Dth = V_D(5.1ms) = 1.32V corresponding to the preset threshold time. That is to say, when the charging time is 5.1ms, the voltage V_D at the first end of the timing capacitor C_T (i.e., the voltage at the inverting input of the second comparator A2) will reach 1.32V.

[0096] The values ​​of the third voltage divider resistor R_H2 and the fourth voltage divider resistor R_L2 can be determined by V_D (5.1ms) = 1.32V. Specifically, 1.32V / 3.3V = R_L2 / (R_H2+R_L2), and R_L2 can be taken as 10kΩ and R_H2 as 15kΩ.

[0097] When the switch Q1 receives the frame synchronization pulse PS, it turns on instantaneously, short-circuiting and clearing the timing capacitor C_T to zero. Because the high-level interval of the frame synchronization pulse PS is extremely short, the timing capacitor C_T does not have time to charge to reach the threshold voltage V_Dth. In other words, the voltage at the inverting input terminal of the second comparator A2 will be less than the voltage at the non-inverting input terminal. As a result, the second comparator A2 will output the second control signal.

[0098] When the time interval between two adjacent frame synchronization pulses PS is greater than the preset threshold time, the switch Q1 is continuously turned off, and the timing capacitor C_T will be continuously charged through the timing resistor R_T until the voltage V_D at the first end of the timing capacitor C_T is greater than the threshold voltage V_Dth. As a result, the second comparator A2 will output the first control signal.

[0099] It should be noted that traditional timing controllers typically rely on a digital clock to count the interval between two vertical synchronization signals (Vsync) to detect the display's refresh rate. However, the digital counting logic requires waiting for the entire duration of a frame to be determined before the exact length of the previous frame can be calculated, thus determining whether it is a high or low refresh rate state. In other words, the timing controller will have a lag of at least one frame when performing compensation. In contrast, the driving circuit 10 provided in this application, by setting a vertical blanking period detection circuit 12 and utilizing the RC charging characteristics for physical time timing, can complete refresh rate identification without waiting for the end of a frame, enabling refresh rate detection and polarity inversion mode switching at the sub-frame level.

[0100] Based on the same concept, this application also provides a display device 1, which includes a display panel 20 and a driving circuit 10 as described in any of the preceding embodiments, wherein the driving circuit 10 is used to drive the display panel 20 to perform display.

[0101] It is understood that the above is only an example, and adjustments can be made as needed in actual applications, without any limitations.

[0102] In summary, this application possesses the aforementioned superior characteristics, enabling it to achieve unprecedented performance in use and thus become a highly practical product.

[0103] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A driving circuit, said driving circuit being used to drive a display panel to display, characterized in that, The driving circuit includes: A timing controller, configured to receive source image data and obtain a data enable signal based on the source image data; and A vertical blanking period detection circuit, electrically connected to the timing controller, is used to receive the data enable signal output by the timing controller, process the data enable signal, obtain a frame synchronization pulse based on the vertical blanking period in the data enable signal, and output a first control signal when no frame synchronization pulse (n+1) is detected within a preset threshold time after the end of the nth frame synchronization pulse, and output a second control signal when the frame synchronization pulse (n+1) is detected within the preset threshold time after the end of the nth frame synchronization pulse; wherein, n≥1; The timing controller responds to the first control signal by using a first polarity reversal mode to control the data voltage to reverse polarity, and responds to the second control signal by using a second polarity reversal mode to control the data voltage to reverse polarity; wherein the number of display frames between two adjacent polarity reversals in the first polarity reversal mode is less than the number of display frames between two adjacent polarity reversals in the second polarity reversal mode.

2. The driving circuit as described in claim 1, characterized in that, The timing controller is also used to generate a frame start signal. When the timing controller receives the first control signal at a preset time before the effective level pulse of the frame start signal, it uses the first polarity reversal mode to control the polarity reversal of the data voltage. When the timing controller receives the second control signal at a preset time before the effective level pulse of the frame start signal, it uses the second polarity reversal mode to control the polarity reversal of the data voltage.

3. The driving circuit as described in claim 1, characterized in that, The vertical blanking period detection circuit includes: Envelope extraction circuit, electrically connected to the timing controller, is used to receive the data enable signal output by the timing controller, and perform asymmetric integral filtering on the data enable signal to filter out the high-frequency components generated by the periodic switching between the row valid data segment and the row blanking segment in the data enable signal, and extract the vertical blanking period envelope signal used to characterize the vertical blanking period. A pulse generation circuit, electrically connected to the envelope extraction circuit, is used to receive the vertical blanking period envelope signal output by the envelope extraction circuit, generate a square wave signal based on the relationship between the vertical blanking period envelope signal and a first preset reference voltage, and differentiate the edges of the square wave signal to obtain the frame synchronization pulse; and A timing comparison circuit is used to receive the frame synchronization pulse, time the time interval between two adjacent frame synchronization pulses, output the first control signal when no (n+1)th frame synchronization pulse is detected within a preset threshold time after the end of the nth frame synchronization pulse, and output the second control signal when the (n+1)th frame synchronization pulse is detected within a preset threshold time after the end of the nth frame synchronization pulse.

4. The driving circuit as described in claim 3, characterized in that, The pulse generation circuit includes a hysteresis comparator circuit and a differentiator circuit. The hysteresis comparator circuit is electrically connected to the envelope extraction circuit, and the differentiator circuit is electrically connected between the hysteresis comparator circuit and the timing comparator circuit. The hysteresis comparison circuit is provided with a rising edge trigger threshold and a falling edge trigger threshold. The rising edge trigger threshold and the falling edge trigger threshold are set based on the first preset reference voltage. The hysteresis comparison circuit is used to perform a hysteresis comparison between the vertical blanking period envelope signal and the rising edge trigger threshold and the falling edge trigger threshold to obtain a square wave signal. The differentiating circuit is used to differentiate the edges of the square wave signal to obtain the frame synchronization pulse.

5. The driving circuit as described in claim 3, characterized in that, The envelope extraction circuit includes: A diode, wherein the anode of the diode is electrically connected to the timing controller for receiving the data enable signal output by the timing controller, and the cathode of the diode is electrically connected to the pulse generation circuit; First resistor; and The first capacitor is connected in parallel with the first resistor between the cathode of the diode and ground; The diode, the first resistor, and the first capacitor constitute a filter circuit to perform asymmetric integral filtering on the data enable signal, thereby filtering out high-frequency components generated by the periodic switching between the row valid data segment and the row blanking segment in the data enable signal, and outputting the vertical blanking envelope signal to the pulse generation circuit.

6. The driving circuit as described in claim 4, characterized in that, The hysteresis comparator circuit includes: A first comparator, wherein the inverting input terminal of the first comparator is electrically connected to the envelope extraction circuit, and the output terminal of the first comparator is electrically connected to the differentiating circuit; The first voltage divider resistor is electrically connected between the voltage source and the non-inverting input terminal of the first comparator; The second voltage divider resistor is electrically connected between the non-inverting input of the first comparator and ground; and The hysteresis resistor is electrically connected between the non-inverting input and the output of the first comparator.

7. The driving circuit as described in claim 4, characterized in that, The differentiating circuit includes: A second capacitor, the first terminal of which is electrically connected to the hysteresis comparator circuit, and the second terminal of which is electrically connected to the timing comparator circuit; and The second resistor is electrically connected between the second terminal of the second capacitor and ground.

8. The driving circuit as described in claim 3, characterized in that, The timing comparison circuit includes: A switching transistor, the control terminal of which is electrically connected to the pulse generation circuit, is used to receive the frame synchronization pulse output by the pulse generation circuit, and the first connection terminal of the switching transistor is grounded; A reference voltage generation circuit is used to generate a second preset reference voltage; the second preset reference voltage corresponds to the preset threshold time. The second comparator has its inverting input terminal electrically connected to the second connection terminal of the switching transistor, and its non-inverting input terminal electrically connected to the reference voltage generation circuit, for receiving the second preset reference voltage output by the reference voltage generation circuit; A timing capacitor, wherein the first terminal of the timing capacitor is electrically connected to the second terminal of the switching transistor, and the second terminal of the timing capacitor is grounded; and The timing resistor is electrically connected between the voltage source and the second connection terminal of the switching transistor.

9. The driving circuit as described in claim 8, characterized in that, The switching transistor is a high-level conducting switching transistor; when the switching transistor receives the nth frame synchronization pulse, the switching transistor conducts the electrical connection between the inverting input terminal of the second comparator and ground, so that the second comparator outputs the second control signal; At the end of the nth frame synchronization pulse, the switching transistor disconnects the electrical connection between the inverting input terminal of the second comparator and ground, allowing the voltage source to charge the timing capacitor through the timing resistor. When the switching transistor receives the (n+1)th frame synchronization pulse within the preset threshold time after the end of the nth frame synchronization pulse, the voltage at the inverting input terminal of the second comparator is lower than the second preset reference voltage, thus the second comparator continues to output the second control signal. When the switching transistor does not receive the (n+1)th frame synchronization pulse within the preset threshold time after the end of the nth frame synchronization pulse, the voltage at the inverting input terminal of the second comparator is charged to a level higher than the second preset reference voltage, thus causing the second comparator to output the first control signal.

10. A display device, characterized in that, The display device includes: Display panel; and The driving circuit according to any one of claims 1 to 9 is used to drive the display panel to display.

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