A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a plurality of data lines and a display driving circuit, and the plurality of data lines comprises a first data line. The working process of the display panel comprises a plurality of display frames. In a first display frame, the display driving circuit provides a first data voltage for the first data line in a data refreshing stage, and the display driving circuit provides a first compensation voltage for the first data line in a display blank stage. In a second display frame, the display driving circuit provides a second data voltage for the first data line in the data refreshing stage, and the display driving circuit provides a second compensation voltage for the first data line in the display blank stage. The first data voltage is greater than a common electrode voltage, the second data voltage is less than the common electrode voltage, and the absolute value of the difference between the first compensation voltage and the common electrode voltage is not equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage. In the application, the flicker can be inhibited, and the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, consumers have increasingly higher requirements for display panels. For example, for the same display panel, there are requirements for good display brightness in different display scenarios, and different refresh rates in different display scenarios, etc.

[0003] However, current display panels suffer from issues such as flickering, which affects the display quality. Summary of the Invention

[0004] This application provides a display panel and a display device to solve the problem of screen flickering.

[0005] According to one aspect of this application, a display panel is provided, comprising: Multiple data lines and a display driver circuit, wherein the multiple data lines include a first data line; The operation of the display panel includes multiple display frames, each display frame including a data refresh phase and a display blank phase, and the multiple display frames include a first display frame and a second display frame; In the first display frame, the display driving circuit provides a first data voltage to the first data line during the data refresh phase, and the display driving circuit provides a first compensation voltage to the first data line during the display blank phase; In the second display frame, the display driving circuit provides a second data voltage to the first data line during the data refresh phase, and the display driving circuit provides a second compensation voltage to the first data line during the display blank phase; The first data voltage is greater than the common electrode voltage, the second data voltage is less than the common electrode voltage, and the absolute value of the difference between the first compensation voltage and the common electrode voltage is not equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage.

[0006] According to another aspect of this application, a display device is provided, comprising: a display panel as described above.

[0007] In this application, the display frame of the display panel includes a data refresh phase and a display blank phase; in the first display frame, a first data voltage is provided to the first data line during the data refresh phase and a first compensation voltage is provided to the first data line during the display blank phase; in the second display frame, a second data voltage is provided to the first data line during the data refresh phase and a second compensation voltage is provided to the first data line during the display blank phase; the absolute value of the difference between the first compensation voltage and the common electrode voltage is not equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage. In this application, due to the presence of parasitic capacitance in the pixel circuit, there is a difference between the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit when it is not compensated. The absolute value of the difference between the first compensation voltage and the common electrode voltage is designed not to be equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage. By compensating the first display frame and the second display frame separately, the influence of parasitic capacitance on the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit can be reduced, thereby reducing the difference between the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit, reducing the brightness difference of sub-pixels in positive and negative frames, suppressing flicker, reducing screen jitter during positive and negative frames, which is beneficial to reducing screen flicker. It is also applicable to improving the screen flicker caused by dynamic refresh rate switching in variable refresh rate screens, and improving the display effect of the display panel.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of the data signals in the first data line; Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another type of data signal in the first data line; Figure 5 This is a schematic diagram of another type of data signal in the first data line; Figure 6 This is a schematic diagram of another display panel provided in an embodiment of this application; Figure 7 This is a timing diagram of the display panel; Figure 8 This is a timing diagram for another type of display panel; Figure 9 This is a timing diagram for yet another type of display panel; Figure 10 This is a timing diagram for yet another type of display panel; Figure 11 This is a schematic diagram of yet another display panel provided in an embodiment of this application; Figure 12 This is a schematic diagram of yet another display panel provided in an embodiment of this application; Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of the data signals in the first data line, for reference. Figure 1 and Figure 2The display panel 100 provided in this application embodiment includes: multiple data lines 101 and a display driving circuit 102. The multiple data lines 101 include a first data line DLA. The operation of the display panel 100 includes multiple display frames Fr. The display frame Fr includes a data refresh phase Fs and a display blank phase Fb. The multiple display frames Fr include a first display frame Fr1 and a second display frame Fr2. In the first display frame Fr1, the display driving circuit 102 provides a first data voltage Vd1 to the first data line DLA during the data refresh phase Fs1, and the display driving circuit 102 provides a first data voltage Vd1 to the first data line DLA during the display blank phase Fb1. The first data line DLA is provided with a first compensation voltage Vp1; in the second display frame Fr2, the display driving circuit 102 provides a second data voltage Vd2 to the first data line DLA during the data refresh phase Fs2, and provides a second compensation voltage Vp2 to the first data line DLA during the display blank phase Fb2; the first data voltage Vd1 is greater than the common electrode voltage Vcom, the second data voltage Vd2 is less than the common electrode voltage Vcom, and the absolute value of the difference between the first compensation voltage Vp1 and the common electrode voltage Vcom is not equal to the absolute value of the difference between the second compensation voltage Vp2 and the common electrode voltage Vcom.

[0014] In this embodiment, the display panel 100 includes a plurality of pixel circuits 103. Exemplarily, the plurality of pixel circuits 103 are arranged in an array, but are not limited thereto. Specifically, the plurality of pixel circuits 103 are arranged in a row along a first direction X, multiple rows of pixel circuits 103 are arranged along a second direction Y, the plurality of pixel circuits 103 are arranged in a column along the second direction Y, and multiple columns of pixel circuits 103 are arranged along the first direction X, where the first direction X and the second direction Y intersect, wherein the first direction X is the row direction and the second direction Y is the column direction. Alternatively, in some embodiments, the first direction can be designed as the column direction and the second direction as the row direction.

[0015] The display panel 100 includes multiple data lines 101 and multiple scan lines 104. The data lines 101 extend along a second direction Y, and the multiple data lines 101 are arranged along a first direction X. Each data line 101 is electrically connected to at least one column of pixel circuits 103. The scan lines 104 extend along the first direction X, and the multiple scan lines 104 are arranged along the second direction Y. Each scan line 104 is electrically connected to at least one row of pixel circuits 103. For example, one scan line GL1 of the multiple scan lines 104 is electrically connected to multiple pixel circuits 103 in row PX1, one scan line GL2 of the multiple scan lines 104 is electrically connected to multiple pixel circuits 103 in row PX2, one scan line GL3 of the multiple scan lines 104 is electrically connected to multiple pixel circuits 103 in row PX3, and so on. A scan line 104 transmits a scan signal to each pixel circuit 103 in the corresponding electrically connected pixel circuit row, and a data line 101 transmits a data signal Vdata to each corresponding electrically connected pixel circuit 103. The scan line 104 controls whether the data signal Vdata on the data line 101 is written into the pixel circuit 103 in the pixel circuit row corresponding to the scan line 104. When the scan signal transmitted by the scan line 104 is at an on level, the data signal Vdata transmitted by the data line 101 is written into the pixel circuit 103; conversely, when the scan signal transmitted by the scan line 104 is at an off level, the data signal Vdata transmitted by the data line 101 cannot be written into the pixel circuit 103.

[0016] Specifically, the pixel circuit 103 includes a data writing transistor Mx. A data line 101 is electrically connected to the first terminal of the data writing transistor Mx in the pixel circuit 103, and a scan line 104 is electrically connected to the gate of the data writing transistor Mx in the pixel circuit 103. The scan line 104 transmits a scan signal to control the data writing transistor Mx in the pixel circuit 103 to be turned on or off. If the scan line 104 transmits a scan signal at an on level, it can control the corresponding data writing transistor Mx in the pixel circuit 103 to be turned on, and the data signal Vdata on the data line 101 can be written to the pixel circuit 103; conversely, if the scan line 104 transmits a scan signal at an off level, it can control the corresponding data writing transistor Mx in the pixel circuit 103 to be turned off, and the data signal Vdata on the data line 101 cannot be written to the pixel circuit 103.

[0017] The display panel 100 includes a display driving circuit 102, which is electrically connected to a data line 101 and provides a data signal Vdata to the data line 101.

[0018] The operation of the display panel 100 includes multiple display frames Fr. If the display panel 100 has a low refresh rate, such as a refresh rate of 30Hz, then the display panel 100 refreshes its image 30 times per second. In other words, the operation of the display panel 100 in one second includes 30 display frames Fr. If the display panel 100 has a high refresh rate, such as a refresh rate of 120Hz, then the display panel 100 refreshes its image 120 times per second. In other words, the operation of the display panel 100 in one second includes 120 display frames Fr.

[0019] A display frame Fr of the display panel 100 may include a data refresh phase Fs and a display blank phase Fb. The data signal Vdata includes the data voltage Vd.

[0020] During the data refresh phase Fs, scan line 104 transmits a scan signal, and display driver circuit 102 applies a data voltage Vd to data line 101, causing each pixel circuit 103 in display panel 100 to write the data voltage Vd. For example, display panel 100 performs line-by-line scanning. Specifically, scan line GL1 transmits a scan signal with an on-level signal, and display driver circuit 102 applies the data voltage Vd corresponding to the pixel circuit 103 in pixel circuit row PX1 to data line 101. Thus, pixel circuit 103 in pixel circuit row PX1 is written with the corresponding data voltage Vd, achieving the writing of the corresponding data voltage to each pixel circuit 103 in pixel circuit row PX1. Sequentially, scan line GL2 transmits a scan signal with an on-level signal, and display driver circuit 102 applies the data voltage Vd corresponding to the pixel circuit 103 in pixel circuit row PX2 to data line 101. Thus, pixel circuit row PX2... In row PX2, the pixel circuit 103 is written with the corresponding data voltage Vd, thus writing the corresponding data voltage to each pixel circuit 103 in the pixel circuit row PX2. Sequentially, the scan line GL3 transmits a scan signal with a conduction level, and the display driving circuit 102 loads the data line 101 with the corresponding data voltage Vd of the pixel circuit 103 in the pixel circuit row PX3. Thus, the pixel circuit 103 in the pixel circuit row PX3 is written with the corresponding data voltage Vd, thus writing the corresponding data voltage to each pixel circuit 103 in the pixel circuit row PX3. The remaining pixel circuit rows are processed in the same way, and the display panel 100 realizes the screen refresh and display of one display frame Fr.

[0021] During the blank display phase Fb, the scan line 104 transmits a scan signal at the off level. Then, the data writing transistor Mx of each pixel circuit 103 in the corresponding pixel circuit row is turned off, and the data signal Vdata on the data line 101 cannot be written to the pixel circuit 103.

[0022] In this embodiment, the multiple data lines 101 include a first data line DLA. The first data line DLA can be any one of the multiple data lines 101. The multiple data lines 101 can include at least one first data line DLA, or all of the multiple data lines 101 can be the first data line DLA. Figure 1 Only one first data line, DLA, is shown. The operation of the display panel 100 includes multiple display frames Fr, which include a first display frame Fr1 and a second display frame Fr2, wherein, reference... Figure 2 The first display frame Fr1 and the second display frame Fr2 can be two adjacent display frames Fr. In either the first display frame Fr1 or the second display frame Fr2, during the display blank phase Fb, the scan line 104 transmits a scan signal at the off level, and the display driving circuit 102 also applies a compensation voltage Vp to the first data line DLA.

[0023] For the first display frame Fr1, the display panel 100 includes a data refresh phase Fs1 and a display blank phase Fb1. During the data refresh phase Fs1, when the scan line 104 transmits a scan signal at the on level, the display driving circuit 102 applies the data voltage Vd of the corresponding pixel circuit 103 to the data line 101. Specifically, the display driving circuit 102 applies the first data voltage Vd1 of the corresponding pixel circuit 103 to the first data line DLA. During the display blank phase Fb1, when the scan line 104 transmits a scan signal at the off level, the display driving circuit 102 applies the first compensation voltage Vp1 to the first data line DLA.

[0024] For the second display frame Fr2, the display panel 100 includes a data refresh phase Fs2 and a display blank phase Fb2. During the data refresh phase Fs2, when the scan line 104 transmits a scan signal at the on level, the display driving circuit 102 applies the data voltage Vd corresponding to the pixel circuit 103 to the data line 101. Specifically, the display driving circuit 102 applies the second data voltage Vd2 corresponding to the pixel circuit 103 to the first data line DLA. During the display blank phase Fb2, when the scan line 104 transmits a scan signal at the off level, the display driving circuit 102 applies the second compensation voltage Vp2 to the first data line DLA.

[0025] In other words, for the same pixel circuit 103 electrically connected to the first data line DLA, pixel circuit 103A is used as an example here; during the data refresh phase of the first display frame Fr1, the pixel circuit 103A is written with the corresponding first data voltage Vd1, and during the display blank phase of the first display frame Fr1, the pixel circuit 103A is written with the corresponding first compensation voltage Vp1; during the data refresh phase of the second display frame Fr2, the pixel circuit 103A is written with the corresponding second data voltage Vd2, and during the display blank phase of the second display frame Fr2, the pixel circuit 103A is written with the corresponding second compensation voltage Vp2.

[0026] It is understandable that, depending on the display status of the display panel, the data voltage Vd of any two pixel circuits 103 in the same display frame Fr may be different or the same, and the compensation voltage Vp of any two pixel circuits 103 in the same display frame Fr may be different or the same. Furthermore, if only a portion of the multiple data lines 101 are the first data line DLA, then during the display blanking phase Fb of either the first display frame Fr1 or the second display frame Fr2, the display driving circuit 102 applies a compensation voltage Vp to the first data line DLA, while the other data lines 101 remain in a floating state.

[0027] In this embodiment, the first data voltage Vd1 is greater than the common electrode voltage Vcom, and the second data voltage Vd2 is less than the common electrode voltage Vcom. The polarity of the data voltage Vd greater than the common electrode voltage Vcom can be considered positive, and correspondingly, the data voltage Vd greater than the common electrode voltage Vcom can be defined as a positive frame voltage; similarly, the polarity of the data voltage Vd less than the common electrode voltage Vcom can be considered negative, and correspondingly, the data voltage Vd less than the common electrode voltage Vcom can be defined as a negative frame voltage. Based on this, the first display frame Fr1 can be defined as a positive frame, and the second display frame Fr2 can be defined as a negative frame.

[0028] In this application, the display panel 100 can be a liquid crystal display panel. During normal operation, the polarity of the data voltage Vd of the pixel circuit 103 dynamically changes, preventing liquid crystal aging or inertia. This avoids the situation where the data voltage Vd of the pixel circuit 103 remains at the same polarity for a long time, leading to liquid crystal inertia and stagnation, thus improving the display effect. Taking the same pixel circuit 103A electrically connected to the first data line DLA as an example, during the data refresh phase of the first display frame Fr1, the pixel circuit 103A is written with the corresponding first data voltage Vd1 (positive frame voltage) for Fs1. During the data refresh phase of the second display frame Fr2, the pixel circuit 103A is written with the corresponding second data voltage Vd2 (negative frame voltage) for Fs2. Therefore, during the operation of the display panel 100, the data voltage Vd of the pixel circuit 103A in different display frames Fr will continuously alternate between positive and negative frame voltages. Thus, the pixel circuit 103A will not experience the problem of liquid crystal inertia and stagnation caused by its data voltage Vd remaining at the same polarity for a long time, which is beneficial to improving the display effect of the display panel 100.

[0029] It is understandable that parasitic capacitance exists in the pixel circuit 103. Let's take a liquid crystal display panel as an example. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of this application, see reference. Figure 3 The pixel circuit 103C is used in a liquid crystal display panel. The pixel circuit 103C includes a pixel switch 103C1 and a pixel electrode 103C2. The pixel switch 103C1 includes a single-gate transistor or a dual-gate transistor, but is not limited thereto. The pixel switch 103C1 includes a gate, a source, and a drain. The gate of the pixel switch 103C1 is electrically connected to the scan line 104, the first electrode of the pixel switch 103C1 is electrically connected to the data line 101, and the second electrode of the pixel switch 103C1 is electrically connected to the pixel electrode 103C2. According to the product design, the first electrode of the pixel switch 103C1 is the drain and the second electrode is the source, or the first electrode of the pixel switch 103C1 is the source and the second electrode is the drain.

[0030] As the resolution of liquid crystal display panels increases, the size of pixel switch 103C1 becomes smaller and smaller during actual manufacturing. The gate, source, and drain of pixel switch 103C1 inevitably overlap, resulting in a parasitic capacitance between the gate and the second electrode of pixel switch 103C1. In this embodiment, the parasitic capacitance in pixel circuit 103 includes the parasitic capacitance of pixel switch 103C1.

[0031] When the liquid crystal display panel is operating, the scan line 104 transmits a gate drive signal to the gate of the pixel switch 103C1. This gate drive signal undergoes high-low voltage transitions to control the pixel switch 103C1 to turn on or off. During the transition from a high to a low level, the parasitic capacitance within the pixel switch 103C1 couples to the potential of its second electrode, which in turn couples to the pixel electrode 103C2, causing the potential of the pixel electrode 103C2 to drop. Similarly, during the transition from a low to a high level, the parasitic capacitance within the pixel switch 103C1 couples to the potential of its second electrode, which in turn couples to the pixel electrode 103C2, causing the potential of the pixel electrode 103C2 to rise. The voltage of the pixel electrode in the pixel circuit 103 is the pixel voltage of the pixel circuit 103.

[0032] Based on this, when the first data voltage Vd1 (positive frame voltage) is written to the pixel circuit 103A via the first data line DLA, there may be a voltage difference between the actual pixel voltage in the pixel circuit 103A and the first data voltage Vd1. Similarly, when the second data voltage Vd2 (negative frame voltage) is written to the pixel circuit 103A via the first data line DLA, there may be a voltage difference between the actual pixel voltage in the pixel circuit 103A and the second data voltage Vd2. This will cause the positive frame voltage difference of the same pixel circuit 103A in the positive frame to be different from the negative frame voltage difference in the negative frame. Here, the positive frame voltage difference is the voltage difference between the positive frame voltage and the common electrode voltage Vcom, and the negative frame voltage difference is the voltage difference between the negative frame voltage and the common electrode voltage Vcom. Since the change of the data voltage Vd of the pixel circuit 103 in the display panel 100 will affect the brightness of the corresponding sub-pixel, the difference between the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit 103 will lead to a large difference in the brightness of the sub-pixel in the positive frame and the negative frame, which may result in flicker.

[0033] Based on this, in this embodiment, the display driving circuit 102 provides a compensation voltage Vp to at least one data line 101 during the display blank stage Fb, which can compensate for the data voltage Vd in the pixel circuit 103, reduce the influence of parasitic capacitance on the data voltage Vd in the pixel circuit 103, thereby reducing the difference between the positive frame voltage difference and the negative frame voltage difference in the same pixel circuit 103 and improving the flicker situation.

[0034] For the first display frame Fr1, during the data refresh phase Fs1, the pixel circuit 103A is written with the corresponding first data voltage Vd1, i.e., the positive frame voltage. However, the parasitic capacitance of the pixel circuit 103A causes a difference between the amplitude of the positive frame voltage in the pixel circuit 103A and the first data voltage Vd1 transmitted by the data line 101. In this embodiment, during the display blank phase Fb1 of the first display frame Fr1, the pixel circuit 103A is written with the first compensation voltage Vp1. This compensates for the positive frame voltage in the pixel circuit 103A, thereby reducing the impact of parasitic capacitance on the positive frame voltage difference of the pixel circuit 103A, reducing the impact of parasitic capacitance on sub-pixel brightness, improving flicker, and ultimately reducing screen flicker and improving display performance.

[0035] For the second display frame Fr2, during the data refresh phase Fs2, the pixel circuit 103A is written with the corresponding second data voltage Vd2, i.e., the negative frame voltage. In reality, the parasitic capacitance of the pixel circuit 103A causes a difference between the amplitude of the negative frame voltage in the pixel circuit 103A and the second data voltage Vd2 transmitted by the data line 101. In this embodiment, during the display blank phase Fb2 of the second display frame Fr2, the pixel circuit 103A is written with the second compensation voltage Vp2. This compensates for the negative frame voltage in the pixel circuit 103A, thereby reducing the impact of parasitic capacitance on the negative frame voltage difference of the pixel circuit 103A, reducing the impact of parasitic capacitance on sub-pixel brightness, improving flicker, and ultimately reducing screen flicker and improving display performance.

[0036] As described above, for different display frames Fr, the amplitude of the first data voltage Vd1 written to the pixel circuit 103A by Fs1 during the data refresh phase of the first display frame Fr1 is different from the amplitude of the second data voltage Vd2 written to the same pixel circuit 103A by Fs2 during the data refresh phase of the second display frame Fr2. Based on this, by reasonably designing the absolute value of the difference between the first compensation voltage Vp1 and the common electrode voltage Vcom to be equal to the absolute value of the difference between the second compensation voltage Vp2 and the common electrode voltage Vcom, the difference between the positive and negative frame voltage differences of the same pixel circuit 103A is reduced by separately compensating for positive and negative frames. This also reduces the different effects of parasitic capacitance on the positive and negative frame voltage differences of the pixel circuit 103A, ultimately improving the brightness of sub-pixels and reducing screen flicker, which is beneficial to improving the display effect.

[0037] In this application, the display frame of the display panel includes a data refresh phase and a display blank phase; in the first display frame, a first data voltage is provided to the first data line during the data refresh phase and a first compensation voltage is provided to the first data line during the display blank phase; in the second display frame, a second data voltage is provided to the first data line during the data refresh phase and a second compensation voltage is provided to the first data line during the display blank phase; the absolute value of the difference between the first compensation voltage and the common electrode voltage is not equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage. In this application, due to the presence of parasitic capacitance in the pixel circuit, there is a difference between the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit when it is not compensated. The absolute value of the difference between the first compensation voltage and the common electrode voltage is designed not to be equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage. By compensating the first display frame and the second display frame separately, the influence of parasitic capacitance on the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit can be reduced, thereby reducing the difference between the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit, reducing the brightness difference of sub-pixels in positive and negative frames, suppressing flicker, reducing screen jitter during positive and negative frames, which is beneficial to reducing screen flicker. It is also applicable to improving the screen flicker caused by dynamic refresh rate switching in variable refresh rate screens, and improving the display effect of the display panel.

[0038] In some embodiments, the plurality of display frames includes a third display frame; in the third display frame, the display driving circuit provides data voltage to the first data line during the data refresh phase, and the transmission path between the display driving circuit and the first data line is disconnected during the display blank phase. In some embodiments, at least one third display frame is provided between two adjacent first display frames; or, at least one third display frame is provided between two adjacent second display frames.

[0039] Here, the first and second display frames can be two non-adjacent display frames, separated by at least one third display frame; or, two first display frames can be separated by at least one third display frame; or, two second display frames can be separated by at least one third display frame. The third display frame is different from the first display frame, and also different from the second display frame. Specifically, the blank display phase of the third display frame is different from the blank display phase of the first display frame, and also different from the blank display phase of the second display frame; the specific difference is that, in the blank display phase of the third display frame, the display driving circuit does not apply electrical signals to the data lines, that is, the data lines are in a floating state during the blank display phase of the third display frame.

[0040] Figure 4 This is a schematic diagram of data signals in another type of first data line. (Reference) Figure 4The third display frame Fr3(1) is a negative frame. During the data refresh phase Fs, the display driver circuit 102 applies a negative frame voltage to the first data line DLA. During the display blank phase Fb, the scan line 104 transmits a scan signal at the off level. The display driver circuit 102 does not apply an electrical signal to the first data line DLA, so the first data line DLA is in a floating state.

[0041] Figure 5 This is a schematic diagram of another type of data signal in the first data line. (Reference) Figure 5 The third display frame Fr3(2) is a positive frame. During the data refresh phase Fs, the display driver circuit 102 applies a positive frame voltage to the first data line DLA. During the display blank phase Fb, the scan line 104 transmits a scan signal at the off level. The display driver circuit 102 does not apply an electrical signal to the first data line DLA, so the first data line DLA is in a floating state.

[0042] In some embodiments, the first compensation voltage is greater than the common electrode voltage, and the second compensation voltage is less than the common electrode voltage. In some embodiments, the first data voltage is greater than the first compensation voltage. In some embodiments, the second data voltage is less than the second compensation voltage.

[0043] Parasitic capacitance exists in pixel circuit 103. This parasitic capacitance affects the positive frame voltage difference of pixel circuit 103 in the first display frame Fr1 (positive frame) and the negative frame voltage difference in the second display frame Fr2 (negative frame), causing the positive frame voltage difference of the same pixel circuit 103 to differ from the negative frame voltage difference. Furthermore, during the display blank phase Fb of display frame Fr, the data writing transistor Mx in pixel circuit 103 is turned off. The turned-off data writing transistor Mx has leakage current. The leakage current of the turned-off data writing transistor Mx may flow from pixel circuit 103 to data line 101 or from data line 101 to pixel circuit 103. This causes a change in the data voltage Vd of pixel circuit 103, further exacerbating the difference between the positive and negative frame voltage differences of the same pixel circuit 103, resulting in a large brightness difference between sub-pixels in the positive and negative frames, and consequently, flickering.

[0044] refer to Figure 2In this embodiment, the first compensation voltage Vp1 is greater than the common electrode voltage Vcom, and the first data voltage Vd1 is greater than the first compensation voltage Vp1. Specifically, since there is parasitic capacitance in the pixel circuit 103A, during the data refresh phase Fs1 of the positive frame, i.e., the first display frame Fr1, the actual data voltage in the pixel circuit 103A may be lower than the first data voltage Vd1 transmitted by the first data line DLA. Sequentially, during the display blank phase Fb1 of the first display frame Fr1, the data writing transistor Mx in the pixel circuit 103A is turned off, and the leakage current of the turned-off data writing transistor Mx flows from the pixel circuit 103A to the first data line DLA, further reducing the data voltage in the pixel circuit 103A. Therefore, during the blank display phase Fb1 of the first display frame Fr1, a first compensation voltage Vp1 is transmitted to the pixel circuit 103A through the first data line DLA. The first data voltage Vd1 is greater than the first compensation voltage Vp1, and the first compensation voltage Vp1 is greater than the common electrode voltage Vcom. The first compensation voltage Vp1 can compensate for the positive frame voltage in the pixel circuit 103A, reduce the influence of parasitic capacitance and leakage on the positive frame voltage difference of the pixel circuit 103A, improve the brightness of the sub-pixels, and help improve the display effect.

[0045] refer to Figure 2 In this embodiment, the second compensation voltage Vp2 is less than the common electrode voltage Vcom, and the second data voltage Vd2 is less than the second compensation voltage Vp2. Specifically, since there is a parasitic capacitance in the pixel circuit 103A, during the data refresh phase Fs2 of the negative frame, i.e., the second display frame Fr2, the data voltage in the pixel circuit 103A is actually different from the second data voltage Vd2 transmitted by the first data line DLA. Sequentially, during the display blank phase Fb2 of the second display frame Fr2, the data writing transistor Mx in the pixel circuit 103A is turned off, and the leakage current of the turned-off data writing transistor Mx flows from the first data line DLA to the pixel circuit 103A, further increasing the data voltage in the pixel circuit 103A. Therefore, during the blank display phase Fb2 of the second display frame Fr2, a second compensation voltage Vp2 is transmitted to the pixel circuit 103A through the first data line DLA. The second data voltage Vd2 is less than the second compensation voltage Vp2, and the second compensation voltage Vp2 is less than the common electrode voltage Vcom. The second compensation voltage Vp2 can compensate for the negative frame voltage in the pixel circuit 103A, reduce the influence of parasitic capacitance and leakage on the negative frame voltage difference of the pixel circuit 103A, improve the brightness of the sub-pixels, and help improve the display effect.

[0046] It is understandable that if the first data voltage Vd1 is less than the first compensation voltage Vp1, and / or the second compensation voltage Vp2 is less than the second data voltage Vd2, it may lead to excessive power consumption of the display panel 100, affecting its lifespan and battery life. Therefore, to balance the working performance of the display panel 100, the first data voltage Vd1 can be designed to be greater than the first compensation voltage Vp1, and the second compensation voltage Vp2 can be greater than the second data voltage Vd2. However, the actual situation is not limited to this. To meet different product requirements, there may be any of the following situations: the first compensation voltage Vp1 is less than the common electrode voltage Vcom, the first data voltage Vd1 is less than the first compensation voltage Vp1, the second compensation voltage Vp2 is greater than the common electrode voltage Vcom, and the second data voltage Vd2 is greater than the second compensation voltage Vp2.

[0047] In this embodiment, the absolute value of the difference between the first compensation voltage Vp1 and the common electrode voltage Vcom is not equal to the absolute value of the difference between the second compensation voltage Vp2 and the common electrode voltage Vcom. The first compensation voltage Vp1 is greater than the common electrode voltage Vcom, the first data voltage Vd1 is greater than the first compensation voltage Vp1, the second compensation voltage Vp2 is less than the common electrode voltage Vcom, and the second data voltage Vd2 is less than the second compensation voltage Vp2. By compensating the first display frame and the second display frame separately, it is beneficial to reduce the influence of the parasitic capacitance and leakage current of the pixel circuit 103A in different display frames Fr on the data voltage of the pixel circuit 103A. Finally, by compensating the positive and negative frames separately, the difference between the positive frame voltage difference and the negative frame voltage difference of the same pixel circuit 103A is reduced, the flickering situation is improved, and the display effect is improved.

[0048] Figure 6 This is a schematic diagram of another display panel provided in an embodiment of this application. Figure 7 This is a timing diagram of the display panel. Figure 8 This is a timing diagram for another type of display panel. Figure 9 This is a timing diagram for yet another type of display panel. In some embodiments, refer to Figure 6 The display driving circuit 102 includes a threshold current circuit 106 and a source driving circuit 105. The threshold current circuit 106 includes a plurality of threshold current switches, and the source driving circuit 105 is electrically connected to a data line 101 through a threshold current switch. In the display frame Fr, the threshold current switch is turned on during the data refresh phase Fs. In some embodiments, reference is made to... Figure 6 The display driving circuit 102 further includes a level conversion circuit 107, which is electrically connected to the control terminal of the threshold current switch. In some embodiments, refer to... Figures 2 to 9 In the first display frame Fr1, the threshold current switch is activated in Fb1 during the display blank phase. In some embodiments, refer to Figures 2 to 9In the second display frame Fr2, the threshold current switch is activated during the blank display phase of Fb2. In some embodiments, refer to Figure 8 and Figure 9 Multiple display frames Fr include a third display frame Fr3; in the third display frame Fr3, the threshold current switch Fb is turned off during the display blank phase.

[0049] In this embodiment, the threshold current switch may include switching transistors, which are sequentially labeled M1, M2, M3, ... The gate of the threshold current switch is electrically connected to a level conversion circuit 107, the first terminal of the threshold current switch is electrically connected to a source drive circuit 105, and the second terminal of the threshold current switch is electrically connected to a data line 101. The source drive circuit 105 is used to transmit data signals to the data line 101 through the threshold current switch.

[0050] If all the switching transistors are NMOS, then one signal terminal of the level shifting circuit 107 can be electrically connected to the gates of multiple switching transistors. The level shifting circuit 107 provides a high turn-on level and a low turn-off level for the switching transistors. Alternatively, if all the switching transistors are PMOS, then one signal terminal of the level shifting circuit 107 can be electrically connected to the gates of multiple switching transistors. The level shifting circuit 107 provides a low turn-on level and a high turn-off level for the switching transistors. The source drive circuit 105 is used to transmit data signals to the data line 101 through a threshold current switch. Alternatively, if at least one switching transistor is an NMOS and at least one switching transistor is a PMOS, then the level shifting circuit 107 has two signal terminals. One signal terminal is electrically connected to each NMOS switching transistor to control the corresponding NMOS switching transistor to be simultaneously turned on or off, and the other signal terminal is electrically connected to each PMOS switching transistor to control the corresponding PMOS switching transistor to be simultaneously turned on or off.

[0051] In the display driving circuit 102, the threshold current circuit 106 and the source driving circuit 105 can be two independent circuits; or, in some embodiments, the threshold current circuit can be integrated inside the source driving circuit. In the display driving circuit 102, the level conversion circuit 107 and the source driving circuit 105 can be two independent circuits; or, in some embodiments, the level conversion circuit can be integrated inside the source driving circuit; or, in some embodiments, the level conversion circuit can be integrated inside other circuits or devices.

[0052] Taking a switching transistor M1 electrically connected to the first data line DLA and M1 being an NMOS as an example, the gate of switching transistor M1 (labeled M1_Gate in the figure) is electrically connected to the level shifting circuit 107, the first terminal of switching transistor M1 is electrically connected to the source drive circuit 105, and the second terminal of switching transistor M1 is electrically connected to the first data line DLA. The level shifting circuit 107 provides an on-level vgh or an off-level vgl to the gate of switching transistor M1. During the data refresh phase Fs of display frame Fr, the level shifting circuit 107 provides an on-level to the gate of switching transistor M1 to turn on switching transistor M1.

[0053] refer to Figure 2 and Figure 7 In the first display frame Fr1, during the data refresh phase Fs1, the level conversion circuit 107 provides an on-level vgh to the gate M1_Gate of the switching transistor M1, and the source drive circuit 105 provides a first data voltage Vd1 to the first data line DLA through the turned-on switching transistor M1. Sequentially, during the display blank phase Fb1, the display drive circuit 102 needs to provide a first compensation voltage Vp1 to the first data line DLA. Therefore, during this phase, the level conversion circuit 107 provides an on-level vgh to the gate M1_Gate of the switching transistor M1 to turn on the switching transistor M1, and the source drive circuit 105 provides a first compensation voltage Vp1 to the first data line DLA through the turned-on switching transistor M1. Similarly, in the second display frame Fr2, during the data refresh phase Fs2, the level conversion circuit 107 provides an on-level vgh to the gate M1_Gate of the switching transistor M1, and the source drive circuit 105 provides a second data voltage Vd2 to the first data line DLA through the turned-on switching transistor M1. Sequentially, during the display blank phase Fb2, the display drive circuit 102 needs to provide a second compensation voltage Vp2 to the first data line DLA. Therefore, in this phase, the level conversion circuit 107 provides an on-level vgh to the gate M1_Gate of the switching transistor M1 to turn on the switching transistor M1, and the source drive circuit 105 provides a second compensation voltage Vp2 to the first data line DLA through the turned-on switching transistor M1.

[0054] Figure 4 Including the third display frame Fr3, which is different Figure 2 In this context Figure 4 and Figure 8The timing of the third display frame Fr3(1) is described only. In the third display frame Fr3(1), during the data refresh phase Fs, the level conversion circuit 107 provides the turn-on level vgh to the gate M1_Gate of the switching transistor M1, and the source drive circuit 105 provides the first data voltage Vd1 to the first data line DLA through the turned-on switching transistor M1. Sequentially, during the display blank phase Fb, the display drive circuit 102 does not load the data signal for the first data line DLA. Therefore, during this phase, the level conversion circuit 107 provides the turn-off level vgl to the gate M1_Gate of the switching transistor M1 to turn off the switching transistor M1. The source drive circuit 105 is disconnected from the first data line DLA, and the first data line DLA is in a floating state.

[0055] Figure 5 Including the third display frame Fr3, which is different Figure 2 In this context Figure 5 and Figure 9 The timing of the third display frame Fr3(2) is described only. In the third display frame Fr3(2), during the data refresh phase Fs, the level conversion circuit 107 provides the turn-on level vgh to the gate M1_Gate of the switching transistor M1, and the source drive circuit 105 provides the first data voltage Vd1 to the first data line DLA through the turned-on switching transistor M1. Sequentially, during the display blank phase Fb, the display drive circuit 102 does not load the data signal for the first data line DLA. Therefore, during this phase, the level conversion circuit 107 provides the turn-off level vgl to the gate M1_Gate of the switching transistor M1 to turn off the switching transistor M1. The source drive circuit 105 is disconnected from the first data line DLA, and the first data line DLA is in a floating state.

[0056] In some embodiments, the display blanking phase in the first display frame includes a first blanking sub-phase and a second blanking sub-phase; the threshold current switch is turned on in the first blanking sub-phase and turned off in the second blanking sub-phase. In some embodiments, the duration of the first blanking sub-phase in the first display frame is greater than or equal to the duration of the second blanking sub-phase.

[0057] Figure 10 This is a timing diagram for yet another type of display panel. Here, we will only use... Figure 10 Describe the timing of the first display frame Fr1, refer to Figure 10 In the first display frame Fr1, the display blank phase Fb1 includes a first blank sub-phase Fb11 and a second blank sub-phase Fb12; in the first blank sub-phase Fb11, the threshold current switch is turned on and in the second blank sub-phase Fb12, the threshold current switch is turned off, and the duration of the first blank sub-phase Fb11 is greater than or equal to the duration of the second blank sub-phase Fb12.

[0058] refer to Figure 10During the data refresh phase Fs1 of the first display frame Fr1, the level conversion circuit 107 provides an on-level vgh to the gate M1_Gate of the switching transistor M1, and the source drive circuit 105 provides a first data voltage Vd1 to the first data line DLA through the turned-on switching transistor M1. During the display blank phase Fb1 of the first display frame Fr1, in the first blank sub-phase Fb11, the level conversion circuit 107 provides an on-level vgh to the gate M1_Gate of the switching transistor M1 to turn on the switching transistor M1, and the source drive circuit 105 provides a first compensation voltage Vp1 to the first data line DLA through the turned-on switching transistor M1. During the display blank phase Fb1 of the first display frame Fr1, in the second blank sub-phase Fb12, the level conversion circuit 107 provides an off-level vgl to the gate M1_Gate of the switching transistor M1 to turn off the switching transistor M1, and the display drive circuit 102 does not load a data signal to the first data line DLA, so the first data line DLA is in a floating state.

[0059] In some embodiments, the display blanking phase in the second display frame includes a first blanking sub-phase and a second blanking sub-phase; the threshold current switch is turned on in the first blanking sub-phase and turned off in the second blanking sub-phase. In some embodiments, the duration of the first blanking sub-phase in the second display frame is greater than or equal to the duration of the second blanking sub-phase. See also... Figure 10 The timing diagram of the first display frame is shown below; the timing diagram of the second display frame will not be described in detail here.

[0060] In this embodiment, the display area AA is equipped with a pixel circuit 103, and the non-display area NA is equipped with a source drive circuit 105, a threshold current circuit 106, and a level conversion circuit 107. The threshold current circuit 106 includes multiple threshold current switches. The control terminal of each threshold current switch is electrically connected to the level conversion circuit 107, the first terminal of each threshold current switch is electrically connected to the source drive circuit 105, and the second terminal of each threshold current switch is electrically connected to the data line 101. The level conversion circuit 107 selectively activates the threshold current switches according to the display timing, enabling separate compensation for the first and second display frames. This helps reduce the difference in positive and negative frame voltage differences within the same pixel circuit 103, improving flicker and enhancing the display effect.

[0061] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of this application. In some embodiments, reference is made to... Figure 2 and 11The display driving circuit 102 includes multiple data connection lines 108 and a source driving circuit 105. The source driving circuit 105 is electrically connected to a data line 101 through a data connection line 108. The data connection line 108 includes a first trace 108A, a second trace 108B, and a third trace 108C. The first trace 108A is electrically connected between the source driving circuit 105 and the third trace 108C, and the second trace 108B is electrically connected to the source driving circuit 101. Between 5 and the third routing section 108C, the third routing section 108C is electrically connected to the data line 101; in the first display frame Fr1, the source drive circuit 105 sequentially provides electrical signals to the corresponding data line 101 through the first routing section 108A and the third routing section 108C in the data connection line 108; in the second display frame Fr2, the source drive circuit 105 sequentially provides electrical signals to the corresponding data line through the second routing section 108B and the third routing section 108C in the data connection line 108.

[0062] In this embodiment, a threshold current circuit is not required. Specifically, the display driving circuit 102 includes a data connection line 108 and a source driving circuit 105. The source driving circuit 105 is electrically connected to a data line 101 through a data connection line 108. The data connection line 108 includes a first trace 108A, a second trace 108B, and a third trace 108C. The source driving circuit 105 is sequentially electrically connected to the data line 101 through the first trace 108A and the third trace 108C of the same data connection line 108. The source driving circuit 105 can transmit positive frame voltage through the first trace 108A. The source driving circuit 105 is sequentially electrically connected to the data line 101 through the second trace 108B and the third trace 108C of the same data connection line 108. The source driving circuit 105 can transmit negative frame voltage through the second trace 108B.

[0063] This example uses the first data line, DLA. (Reference) Figure 2 and Figure 11In the first display frame Fr1, during the data refresh phase Fs1, the source drive circuit 105 provides the first data voltage Vd1 to the first data line DLA through the first trace 108A and the third trace 108C in a data connection line 108. During this time, the source drive circuit 105 disconnects from the second trace 108B in the same data connection line 108, without affecting the normal transmission of the data voltage in the first trace 108A in the same data connection line 108. Sequentially, during the blank display phase Fb1... The display driving circuit 102 needs to provide a first compensation voltage Vp1 to the first data line DLA. Therefore, during this stage, the source driving circuit 105 provides the first compensation voltage Vp1 to the first data line DLA through the first trace 108A and the third trace 108C in a data connection line 108. At this point, the source driving circuit 105 and the second trace 108B in the same data connection line 108 are disconnected, which does not affect the normal transmission of the compensation voltage of the first trace 108A in the same data connection line 108. Therefore, in this embodiment, during the first display frame Fr1, the source driving circuit 105 transmits the data voltage and compensation voltage of the positive frame in a time-division manner through the first trace 108A and the third trace 108C in a data connection line 108, enabling the display of the positive frame. During this process, the second trace 108B is in a floating state.

[0064] Similarly, in the second display frame Fr2, during the data refresh phase Fs2, the source drive circuit 105 provides the second data voltage Vd2 to the first data line DLA through the second trace 108B and the third trace 108C in a data connection line 108. At this point, the source drive circuit 105 is disconnected from the first trace 108A in the same data connection line 108, which does not affect the normal transmission of the data voltage in the second trace 108B in the same data connection line 108; sequentially, during the display blank phase Fb2... The display driving circuit 102 needs to provide a second compensation voltage Vp2 to the first data line DLA. Therefore, during this stage, the source driving circuit 105 provides the second compensation voltage Vp2 to the first data line DLA through the second trace 108B and the third trace 108C in a data connection line 108. When the source driving circuit 105 is disconnected from the first trace 108A in the same data connection line 108, it will not affect the normal transmission of the compensation voltage of the second trace 108B in the same data connection line 108. Therefore, in this embodiment, in the second display frame Fr2, the source driving circuit 105 transmits the data voltage and compensation voltage of the negative frame in a time-division manner through the second trace 108B and the third trace 108C in a data connection line 108, enabling the display of the negative frame. During this process, the first trace 108A is in a floating state.

[0065] As described above, the same data connection line 108 includes a first wiring section 108A, a second wiring section 108B, and a third wiring section 108C, with the first wiring section 108A and the second wiring section 108B respectively electrically connected to the third wiring section 108C.

[0066] and Figure 6 compared to, Figure 11 No threshold current circuit is needed, allowing for a narrow bezel. Additionally, Figure 11 The source drive circuit 105 outputs positive frame data voltage and negative frame data voltage respectively through the first trace 108A and the second trace 108B of the same data connection line 108, enabling independent input control of the positive and negative frame data voltages. Similarly, the source drive circuit 105 outputs positive frame compensation voltage and negative frame compensation voltage respectively through the first trace 108A and the second trace 108B of the same data connection line 108, enabling independent input control of the positive and negative frame compensation voltages. This design allows the absolute value of the difference between the first compensation voltage Vp1 and the common electrode voltage Vcom to be unequal to the absolute value of the difference between the second compensation voltage Vp2 and the common electrode voltage Vcom, which helps improve screen flicker.

[0067] Figure 12 This is a schematic diagram of another display panel provided in an embodiment of this application. In some embodiments, with Figure 11 The difference lies in the reference. Figure 2 and Figure 12 The display driving circuit 102 further includes a threshold current circuit 106, which includes a plurality of threshold current switches. Each threshold current switch includes a first sub-switch Ma and a second sub-switch Mb. The first sub-switch Ma is electrically connected between a first trace portion 108A and a third trace portion 108C, and the second sub-switch Mb is electrically connected between a second trace portion 108B and a third trace portion 108C. In the first display frame Fr1, the first sub-switch Ma is on and the second sub-switch Mb is off. In the second display frame Fr2, the first sub-switch Ma is off and the second sub-switch Mb is on. In some embodiments, refer to... Figure 2 and Figure 12 The display driving circuit 102 further includes a level conversion circuit 107, the first signal terminal of the level conversion circuit 107 being electrically connected to each of the first sub-switches Ma, and the second signal terminal of the level conversion circuit 107 being electrically connected to each of the second sub-switches Mb.

[0068] In this embodiment, the display driving circuit 102 includes a data connection line 108, a threshold current circuit 106, a level conversion circuit 107, and a source driving circuit 105.

[0069] The threshold current circuit 106 includes multiple threshold current switches, each of which includes a first sub-switch Ma and a second sub-switch Mb. In some embodiments, the first sub-switches Ma are all NMOS, or the first sub-switches Ma are all PMOS. The first signal terminal of the level conversion circuit 107 is electrically connected to each of the first sub-switches Ma, which can control the first sub-switches Ma to be turned on or off simultaneously. In some embodiments, the second sub-switches Mb are all NMOS, or the second sub-switches Mb are all PMOS. The second signal terminal of the level conversion circuit 107 is electrically connected to each of the second sub-switches Mb, which can control the second sub-switches Mb to be turned on or off simultaneously.

[0070] In data connection line 108, a first sub-switch Ma is electrically connected between the first trace section 108A and the third trace section 108C. The level conversion circuit 107 controls the first sub-switch Ma to turn on or off, thereby connecting or disconnecting the transmission path between the first trace section 108A and the data line 101. In data connection line 108, a second sub-switch Mb is electrically connected between the second trace section 108B and the third trace section 108C. The level conversion circuit 107 controls the second trace section 108B to turn on or off, thereby connecting or disconnecting the transmission path between the second trace section 108B and the data line 101.

[0071] In the first display frame Fr1, the first sub-switch Ma is on and the second sub-switch Mb is off; in the second display frame Fr2, the first sub-switch Ma is off and the second sub-switch Mb is on. The first data line DLA is used as an example here.

[0072] refer to Figure 2 and Figure 12 In the first display frame Fr1, the level conversion circuit 107 controls the first sub-switch Ma to turn on, and the source drive circuit 105 connects the first data line DLA through the first trace 108A. During the data refresh phase, Fs1 provides the first data voltage Vd1 to the first data line DLA through the first trace 108A, and during the display blank phase, Fb1 provides the first compensation voltage Vp1 to the first data line DLA through the first trace 108A. In the first display frame Fr1, the second sub-switch Mb is turned off, so the first data line DLA will not leak current to the second trace 108B, reducing interference to the floating state of the second trace 108B.

[0073] refer to Figure 2 and Figure 12In the second display frame Fr2, the level conversion circuit 107 controls the second sub-switch Mb to turn on, and the source drive circuit 105 connects the first data line DLA through the second trace 108B. During the data refresh phase, Fs2 provides the second data voltage Vd2 to the first data line DLA through the second trace 108B, and during the display blank phase, Fb2 provides the second compensation voltage Vp2 to the first data line DLA through the second trace 108B. In the second display frame Fr2, the first sub-switch Ma turns off, so the first data line DLA will not leak current to the first trace 108A, reducing interference to the first trace 108A in the floating state.

[0074] and Figure 11 compared to, Figure 12 The level conversion circuit 107 controls the first sub-switch Ma to turn on or off, thus connecting or disconnecting the transmission path between the first trace section 108A and the data line 101. Similarly, the level conversion circuit 107 controls the second sub-switch Mb to turn on or off, thus connecting or disconnecting the transmission path between the second sub-switch Mb and the data line 101. In the first display frame Fr1, the first sub-switch Ma is on and the second sub-switch Mb is off, so the first data line DLA will not leak current to the second trace section 108B. Similarly, in the second display frame Fr2, the first sub-switch Ma is off and the second sub-switch Mb is on, so the first data line DLA will not leak current to the first trace section 108A. This design allows the absolute value of the difference between the first compensation voltage Vp1 and the common electrode voltage Vcom to be unequal to the absolute value of the difference between the second compensation voltage Vp2 and the common electrode voltage Vcom, which helps to improve screen flicker.

[0075] Based on the same concept, embodiments of this application provide a display device. Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application, with reference to... Figure 13 The display device 1 includes: the display panel 100 as described in any embodiment of this application.

[0076] In this embodiment, the display device 1 can be applied to a liquid crystal display device, an organic light-emitting display device, or a micro light-emitting diode display device; there is no specific limitation. (Reference) Figure 13The display device 1 is a smartphone, which includes a display panel 100. This display panel 100 is the same as described in any embodiment of this application, and has display and touch functions. The display device 1 can also be an automotive display product, a mobile display product, or something else. The display device 1 provided in this application embodiment has the corresponding functional modules and beneficial effects of the display panel 100 described in any embodiment of this application. This display device 1 can be applied to terminal devices such as smartphones, automotive displays, tablets, laptops, super mobile personal computers, netbooks, smart wearable devices, and augmented reality (AR) / virtual reality (VR) devices.

[0077] It should be noted that with the application of variable refresh rate screens, especially in IT product lines, dynamic refresh rate switching may cause screen flicker. In this application, by writing compensation voltage to the data lines during the display blank phase of the first display frame and again during the display blank phase of the second display frame, the dynamic flicker level in a variable refresh rate screen can be optimized, thus improving the display effect. However, this method is not limited to variable refresh rate screens.

[0078] Note that the above embodiments of this application are merely illustrative examples for the purpose of clearly illustrating the present application, and are not intended to limit the implementation of the present application, nor do they constitute a limitation on the scope of protection of the present application. For those skilled in the art, various obvious changes, readjustments, and substitutions can be made according to design requirements and other factors without departing from the scope of protection of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present application. It is neither necessary nor possible to exhaustively describe all implementation methods here. The scope of the present application is determined by the scope of the appended claims. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present application should be included within the scope of protection of the claims of the present application.

Claims

1. A display panel, characterized in that, include: Multiple data lines and a display driver circuit, wherein the multiple data lines include a first data line; The operation of the display panel includes multiple display frames, each display frame including a data refresh phase and a display blank phase, and the multiple display frames include a first display frame and a second display frame; In the first display frame, the display driving circuit provides a first data voltage to the first data line during the data refresh phase, and the display driving circuit provides a first compensation voltage to the first data line during the display blank phase; In the second display frame, the display driving circuit provides a second data voltage to the first data line during the data refresh phase, and the display driving circuit provides a second compensation voltage to the first data line during the display blank phase; The first data voltage is greater than the common electrode voltage, the second data voltage is less than the common electrode voltage, and the absolute value of the difference between the first compensation voltage and the common electrode voltage is not equal to the absolute value of the difference between the second compensation voltage and the common electrode voltage.

2. The display panel according to claim 1, characterized in that, The first compensation voltage is greater than the common electrode voltage, and the second compensation voltage is less than the common electrode voltage.

3. The display panel according to claim 1, characterized in that, The first data voltage is greater than the first compensation voltage.

4. The display panel according to claim 1, characterized in that, The second data voltage is less than the second compensation voltage.

5. The display panel according to claim 1, characterized in that, The plurality of display frames includes a third display frame; In the third display frame, the display driving circuit provides data voltage to the first data line during the data refresh phase, and the transmission path between the display driving circuit and the first data line is disconnected during the display blank phase.

6. The display panel according to claim 5, characterized in that, At least one third display frame is provided between two adjacent first display frames; Alternatively, at least one of the third display frames may be provided between two adjacent second display frames.

7. The display panel according to claim 1, characterized in that, The display driving circuit includes a threshold current circuit and a source driving circuit. The threshold current circuit includes multiple threshold current switches, and the source driving circuit is electrically connected to a data line through one of the threshold current switches. During the display frame, the threshold current switch is turned on during the data refresh phase.

8. The display panel according to claim 7, characterized in that, The display driving circuit further includes a level conversion circuit, which is electrically connected to the control terminal of the threshold current switch.

9. The display panel according to claim 7, characterized in that, In the first display frame, the threshold current switch is turned on during the display blank phase.

10. The display panel according to claim 7, characterized in that, In the first display frame, the display blank phase includes a first blank sub-phase and a second blank sub-phase; The threshold current switch is turned on during the first blank sub-stage and turned off during the second blank sub-stage.

11. The display panel according to claim 10, characterized in that, In the first display frame, the duration of the first blank sub-phase is greater than or equal to the duration of the second blank sub-phase.

12. The display panel according to claim 7, characterized in that, In the second display frame, the threshold current switch is turned on during the display blank phase.

13. The display panel according to claim 7, characterized in that, The plurality of display frames includes a third display frame; In the third display frame, the threshold current switch is turned off during the display blank phase.

14. The display panel according to claim 1, characterized in that, The display driving circuit includes: multiple data connection lines and a source driving circuit, wherein the source driving circuit is electrically connected to one of the data lines through one of the data connection lines; The data connection line includes a first trace, a second trace, and a third trace. The first trace is electrically connected between the source drive circuit and the third trace. The second trace is electrically connected between the source drive circuit and the third trace. The third trace is electrically connected to the data line. In the first display frame, the source drive circuit sequentially provides electrical signals to the corresponding data lines through the first trace and the third trace in the data connection line; In the second display frame, the source drive circuit sequentially provides electrical signals to the corresponding data lines through the second and third traces in the data connection lines.

15. The display panel according to claim 14, characterized in that, The display driving circuit further includes a threshold current circuit, which includes a plurality of threshold current switches. The threshold current switches include a first sub-switch and a second sub-switch. The first sub-switch is electrically connected between the first trace and the third trace, and the second sub-switch is electrically connected between the second trace and the third trace. In the first display frame, the first sub-switch is turned on and the second sub-switch is turned off; In the second display frame, the first sub-switch is off and the second sub-switch is on.

16. The display panel according to claim 15, characterized in that, The display driving circuit further includes a level conversion circuit, wherein the first signal terminal of the level conversion circuit is electrically connected to each of the first sub-switches, and the second signal terminal of the level conversion circuit is electrically connected to each of the second sub-switches.

17. A display device, characterized in that, include: The display panel as described in any one of claims 1-16.

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