A liquid crystal screen high-speed refreshing method based on SPI bus

Abstract

The present application relates to the technical field of embedded display control, and particularly relates to a liquid crystal screen high-speed refreshing method based on SPI bus, the present application constructs parallel refreshing operation environment through initializing SPI peripheral, DMA controller, double-buffered display memory, interrupt and GUI program, and takes 10 rows of pixels as a refreshing unit during refreshing, and realizes synchronous pipeline operation of DMA transmission and graphic rendering by alternately switching the double display memory, the DMA takes empty SPI sending register as a trigger source, independently carries the display memory pixels to the liquid crystal screen, the CPU synchronously renders the next group of pixels in the other display memory, triggers the interrupt after completing the single-group data transmission, switches the read-write roles of the two display memories through atomic operation, and starts a new round of transmission after updating the DMA data source address, so that the rendering and transmission are synchronously executed, the screen refreshing time is greatly reduced, and the refreshing rate and display fluency of the liquid crystal screen are improved.

Description

Technical Field

[0001] This invention relates to the field of embedded display control technology, specifically to a high-speed refresh method for LCD screens based on the SPI bus. Background Technology

[0002] Low-cost microcontrollers, due to limited hardware resources (the core is a small internal RAM capacity), often use the SPI bus to drive TFT-LCD liquid crystal displays. This can meet the hardware cost, power consumption, and display smoothness requirements of consumer electronics such as smart bracelets and portable detectors, industrial scenarios such as embedded control panels and sensor display terminals, and smart home products such as small smart touch devices.

[0003] Currently, SPI interface TFT-LCD is the mainstream display solution for low-resource embedded devices. The industry generally adopts the "full-screen video memory allocation + serial processing" technical path adapted to mid-to-high-end microcontrollers with large RAM. It is mainly divided into two implementation methods: one is that the MCU core actively moves video memory data to the SPI peripheral byte by byte to complete the screen transmission; the other is to introduce a single-buffered DMA to replace the MCU in performing data moving. Although it can reduce the core occupation to a certain extent, it still needs to match the full screen resolution to allocate continuous full-screen video memory, and the graphics rendering and data transmission are strictly serial processes.

[0004] The aforementioned traditional solutions have significant drawbacks when applied to low-cost microcontrollers with small RAM: First, RAM resource consumption is too high, with the entire screen's display memory severely encroaching on the memory space for program execution and business data storage, making it difficult to adapt to medium-to-high resolution screens. Replacing the microcontroller with one containing large RAM would directly increase hardware costs. Second, the pure MCU-based transfer solution consumes kernel resources throughout the transmission process, reducing overall system efficiency and increasing device power consumption. Third, under serial processing logic, the rendering and transmission times are superimposed, resulting in a low overall screen refresh rate. Dynamic displays are prone to stuttering and delays, making it difficult to meet interactive display requirements.

[0005] To address the aforementioned shortcomings, a technical solution is provided. Summary of the Invention

[0006] To address the aforementioned shortcomings of existing technologies, this invention provides a high-speed refresh method for LCD screens based on the SPI bus. This method effectively solves the problems of excessive screen memory usage, high hardware costs, high CPU data transfer resource overhead, high device power consumption, and low refresh frame rate and dynamic image stuttering delay caused by the serial execution of rendering and transmission when using a low-cost microcontroller with small RAM to drive a TFT-LCD.

[0007] To achieve the above objectives, the present invention can be implemented through the following technical solutions:

[0008] This invention provides a high-speed refresh method for an LCD screen based on an SPI bus, comprising the following steps:

[0009] S1: By sequentially completing the initialization processes of the SPI peripheral, DMA controller, dual-buffered video memory module, interrupt response module, and GUI application, the basic operating environment for DMA-SPI parallel refresh is established.

[0010] S2: The screen refresh phase uses 10 consecutive rows of pixel data as a single basic refresh unit. Relying on the alternating switching mechanism of the two video memory blocks, it cyclically carries out the synchronous operation of DMA hardware data transfer and background graphics parallel rendering until the drawing output of all pixel content of the entire screen is completed.

[0011] During operation: The DMA controller uses the SPI peripheral transmit register empty event as the trigger source to independently output the pixel data in the currently transferred video memory to the LCD screen via SPI. The data transfer process does not occupy CPU computing resources. While the CPU is performing data transfer in the DMA, it is simultaneously completing the graphics rendering operation of the next set of pixels to be refreshed in the currently rendered video memory. Whenever a set of pixel data is transferred by DMA and an interrupt is triggered, the functional roles of the two video memories are switched through atomic operations. After the DMA controller updates the transfer source address to the new transfer video memory start address, it starts the next set of data transfer, forming a stable pipeline operation in which data transfer and graphics rendering are executed in parallel.

[0012] Furthermore, the specific steps of the initialization process are as follows:

[0013] Configure the communication protocol parameters of the microcontroller's SPI peripheral according to the hardware interface timing requirements of the driven TFT-LCD screen, including communication baud rate, data bit width, clock polarity and clock phase;

[0014] Bind the target DMA channel to the SPI peripheral hardware link, set the DMA transfer trigger source to the SPI transmit register empty event, and configure the transfer direction to be unidirectional transfer from memory to peripheral; disable the CPU's control and intervention over the data transfer link, and let the DMA hardware independently complete the batch transfer of pixel data from memory to the display screen via the SPI peripheral;

[0015] Two physical memory regions with completely independent storage space and mutually isolated physical addresses are divided in the microcontroller's on-chip random access memory, labeled as memory region A and memory region B respectively. The storage capacity of the two memory regions is equal, and the storage capacity of a single memory region strictly matches the complete data storage requirements of 10 rows of pixels on the screen. During the initialization phase, one memory region is designated as the initial external transmission memory, and the other memory region is designated as the initial background rendering memory.

[0016] Enable the DMA controller's transfer completion interrupt and bind the corresponding interrupt service function. The interrupt service function is used to send a transfer completion notification signal to the upper-level GUI application when the DMA transfer is complete, triggering the role swapping of the transfer and rendering functions of the two memory blocks.

[0017] Load the basic display parameters adapted to the TFT-LCD screen, including the screen physical resolution, effective display area, and color format; simultaneously complete the initialization configuration of the underlying graphics rendering engine, uniformly initialize the drawing cache, drawing interface, pixel conversion logic, and coordinate mapping rules required by the rendering engine, and build the graphics drawing runtime environment.

[0018] Furthermore, during the initial startup phase of the pipeline operation, the initial external transmission of video memory is only filled with a preset default background color during the initialization phase. The first round of DMA transmission outputs the default background color as the boot placeholder screen. After the first DMA transmission is completed, triggering an interrupt and completing the video memory role switch, subsequent rounds of DMA transmission output valid screen data that has been pre-rendered in the background, covering the first round of placeholder screen.

[0019] Furthermore, before initiating a single group of 10-row pixel DMA transfer, the DMA transfer parameters are configured according to the fixed data bit width of the SPI: the total number of data bytes transferred for a single group of 10-row pixels is 10×W×BP, where W is the effective pixel width of a single row on the screen, and BP is the number of storage bytes occupied by a single pixel, with BP being 2 in RGB565 format; if the SPI data bit width is 16 bits, the number of DMA transfers is configured to be 10×W; if the SPI data bit width is 8 bits, the number of DMA transfers is configured to be 10×W×2; the DMA channel is configured with the source address automatically incrementing, the target address fixedly pointing to the SPI peripheral transmit data register, and the DMA transfer data width is consistent with the SPI data bit width.

[0020] Furthermore, the parallel operation of DMA transfer and CPU rendering satisfies timing constraints: Let the DMA transfer time for a single group of 10 rows of pixels be... The CPU takes 10 seconds to render a single group of 10 rows of pixels. When the two are executed in parallel, the cycle time of a single job is and The maximum value in the range; during parallel operation, the CPU does not participate in pixel data transfer operations, all computing resources are allocated to the GUI rendering task, and the rendering job progress always stays ahead of the DMA transfer of a set of 10 rows of pixel offsets.

[0021] Furthermore, the interrupt service procedure after the DMA transfer completion interrupt is as follows: when the DMA transfer counter decrements to 0, it is determined that a single group of data transfers is complete, and the hardware triggers the DMA transfer completion interrupt; after entering the interrupt service function, the flag bit clearing operation is performed to clear the DMA transfer completion interrupt flag and the SPI transmission completion flag to avoid repeated interrupt triggering; then the global transfer completion event flag is set, and the transfer completion signal is pushed to the upper GUI layer, and the CPU context is restored.

[0022] Furthermore, after receiving the transmission completion signal, the GUI layer performs a memory role switching operation within the interrupt critical protection zone: it latches the original interrupt state and disables global interrupts to create an execution environment without interruption; then it swaps the roles of the current transmission memory and the current rendering memory, with the original transmission memory switching to the new rendering memory; the original rendering memory switches to the new transmission memory, and its stored rendering completion data serves as the data source for the next round of DMA transmission; after the switch is completed, it updates the global memory status flag, restores interrupt enable according to the latched original interrupt state, and exits the critical protection zone; the DMA controller only updates the source address register to the starting physical address of the new transmission memory, while keeping the other transmission parameters fixed, and enables the DMA channel to start the next set of data transmissions.

[0023] Furthermore, when the CPU performs pixel writing in the rendering memory, it strictly follows the rule of continuous address writing: the pixel data of the corresponding row is filled in the order of the screen row number from smallest to largest, the pixel address within a single row is continuously increased, and the high and low bytes of RGB565 format pixels are written to the corresponding memory unit in the transmission order specified by the screen hardware; after all pixels in a single group are filled, a data ready notification is sent to the DMA controller through a preset callback function.

[0024] Furthermore, the final processing and dynamic loop logic for full-screen refresh are as follows: Let the total number of lines on the screen be... The standard processing unit is 10 rows of pixels. The total number of processing units is the integer value obtained by dividing the total number of screen rows by the number of standard rows in a single group. The actual number of rows in the last unit is the remainder obtained by dividing the total number of screen rows by the number of standard rows in a single group. If the remainder is 0, the last unit is a standard 10-row pixel unit. Otherwise, only the pixel data corresponding to the number of rows of the remaining remainder is rendered and transmitted. When the last group of pixels is rendered and all of them are transmitted to the LCD screen via DMA, the single static image refresh process is considered to be over. If it is a dynamic display scene, the transmission unit counter, rendering unit counter and all video memory status flags are reset, and the process returns to execute the S2 process.

[0025] The technical solution provided by this invention has the following advantages compared with the known prior art:

[0026] 1. This invention, by analyzing the hardware triggering logic of SPI data transmission, completes the hardware link binding between the DMA channel and the SPI peripheral, configures the unidirectional automatic transmission rules from the memory to the peripheral, and replaces the CPU polling status determination mechanism with hardware transmission completion interrupt. This achieves zero CPU intervention in the SPI pixel data transfer process, completely releases kernel resources throughout the transmission process, effectively reduces CPU computing load and device power consumption, and allows the MCU to execute other business logic synchronously during the data transmission phase, significantly improving the overall operating efficiency of the embedded device.

[0027] 2. This invention, by quantifying the on-chip RAM capacity constraints of low-cost microcontrollers, decomposes the entire screen refresh task into small processing units of 10 rows of pixels. It divides the on-chip RAM into two physically isolated, independently configured video memory blocks with capacities strictly matching the storage requirements of a single group of 10 rows of pixels. The analysis and design process for constructing a lightweight dual-cache architecture with dynamically rotating functions achieves a significant reduction in video memory usage. It can drive medium-to-high resolution SPI interface TFT-LCDs without needing to allocate continuous video memory to match the full screen resolution, breaking the screen adaptation video memory bottleneck of low-resource microcontrollers. The display solution can be implemented without upgrading the large RAM main controller, effectively reducing device hardware costs.

[0028] 3. This invention, by deconstructing the timing dependencies of the entire screen refresh process, establishes a pipelined operation mechanism that uses DMA hardware to transfer ready pixels currently being transferred to video memory, while the CPU synchronously renders the next set of pixels to be displayed in the background. Combined with the design process of atomic switching logic for video memory roles within the interrupt critical section, this invention achieves full-process timing overlap between graphics rendering operations and SPI data transmission operations, significantly shortening the total screen refresh cycle, significantly improving the screen refresh frame rate, effectively solving the problems of dynamic image stuttering and display latency, and improving the dynamic interactive display effect of TFT-LCD screens. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating the overall process of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0032] like Figure 1 As shown, a high-speed refresh method for an LCD screen based on an SPI bus includes the following steps:

[0033] S1: After the system is powered on and the hardware reset is completed, the whole machine initialization configuration process is executed first. By sequentially completing the initialization processing of SPI peripherals, DMA controller, dual-buffered video memory module, interrupt response module and GUI application, the basic operating environment of DMA-SPI parallel refresh is built, laying the foundation for subsequent high-speed screen refresh.

[0034] S1-1: The SPI peripheral initialization configuration operation is as follows: According to the hardware interface timing requirements of the driven TFT-LCD screen, configure the communication protocol parameters of the microcontroller's SPI peripheral, including the communication baud rate, data bit width, clock polarity, and clock phase, to ensure that the SPI communication timing strictly matches the screen specifications. Among them, the communication baud rate is selected as a fixed value according to the clock frequency range supported by the screen's SPI interface, and the clock frequency does not exceed the maximum tolerance frequency of the screen hardware. At the same time, the frequency division coefficient of the microcontroller's SPI peripheral is matched to complete the frequency division configuration, ensuring that the actual output clock frequency has no deviation from the nominal value. The data bit width is clearly selected as an 8-bit or 16-bit fixed transmission mode, and the data transmission length of a single frame is unified. Fixed bit width is used for sending and receiving instructions, register addresses, and image pixel data throughout the process, without dynamically switching the bit width format. The clock polarity is set to the static level of the SPI bus SCLK according to the screen idle level requirements, ensuring that the clock pin is in a constant high or low level state when there is no data transmission on the bus. The clock phase is matched with the screen data sampling trigger timing, defining that the data is latched and sampled at the first or second edge of the clock, ensuring that the host and screen data transmission and reception sampling times are completely synchronized.

[0035] S1-2: The DMA controller initialization configuration operation is completed as follows: bind the target DMA channel and the SPI peripheral hardware link, set the DMA transfer trigger source to the SPI transmit register empty (TXE) event, configure the transfer direction to be unidirectional transfer from memory to peripheral; disable the CPU's control and intervention on the data transfer link, and rely on the DMA hardware to independently complete the automatic batch transfer of pixel image data. The pixel data is directly output from memory to the display screen via the SPI peripheral, and the transfer process does not occupy CPU computing resources.

[0036] S1-3: The initialization configuration of the dual-buffered video memory module is as follows: Two physically isolated and completely independent video memory storage areas are divided in the microcontroller's on-chip random access memory, labeled as Video Memory A and Video Memory B respectively; the two video memory storage areas are configured with equal storage capacity, and the size of each video memory storage space strictly matches the storage capacity of 10 lines of complete pixel data on the screen. The storage space can completely accommodate all pixel information under the corresponding number of lines, without capacity redundancy or insufficient storage space; in the initialization phase, the two video memories are assigned fixed functional roles and the initial state allocation is completed: Video Memory A is designated as the initial external transmission video memory, used to output the pixel data to be refreshed to the SPI peripheral; Video Memory B is designated as the initial background rendering video memory, used to carry out drawing operations such as graphics drawing and pixel updates. By dividing the independent storage areas and distinguishing the read and write functional roles, a complete hardware dual-buffered data interaction mechanism is built to realize the parallel execution of rendering operations and screen data transmission operations in separate areas.

[0037] S1-4: The initialization configuration operation of the interrupt response module is as follows: enable the DMA controller's transfer completion interrupt and bind the corresponding interrupt service function. In the interrupt service function, the callback logic is set. Specifically, when the DMA transfer completion interrupt is triggered and the interrupt service process is entered, the callback instruction is automatically executed to send a transfer completion notification signal to the upper-level GUI application, driving the upper-level program to complete the functional role switching of the two memory blocks, realizing the role rotation of rendering memory and transfer memory.

[0038] S1-5: The GUI application initialization configuration operation is as follows: Load the basic display parameters adapted to the current TFT-LCD screen, including the screen physical resolution, effective display area and color format (such as RGB565 format), and simultaneously complete the initialization configuration of the underlying graphics rendering engine. The rendering engine's required drawing cache, drawing interface, pixel conversion logic and coordinate mapping rules are uniformly initialized to build a complete graphics drawing runtime environment and complete all the preparatory work for the system to output and render the first frame of the display screen.

[0039] S2: Using 10 consecutive rows of pixel data as a single basic refresh unit, relying on the alternating mechanism of dual caches A and B, it cyclically performs DMA hardware data transfer and background graphics parallel rendering synchronous operations until the entire screen's pixel content is drawn and output. The complete execution flow is broken down as follows:

[0040] S2-1: The GUI application calls the graphics rendering engine and specifies the initial rendering video memory B as the current drawing buffer. The rendering engine reads the screen configuration parameters: the effective pixel width of a single line of the screen, the pixel color storage format, and the storage bytes occupied by a single pixel; it loads the multi-layer data of the screen to be displayed, including the underlying background layer, the control icon layer, and the text layer, performs layer overlay and blending operations pixel by pixel, and outputs the final display color value of each coordinate point.

[0041] Storage write rules: Fill the pixels of rows 1 to 10 in ascending order of screen row number. The pixel address within a single row increases continuously. The high and low bytes of RGB565 pixels are written to the corresponding video memory unit in the order specified by the hardware. After all 10 rows of pixel data have been filled, the DMA controller is notified through a callback function, indicating that the data in video memory B is ready for subsequent transmission.

[0042] After rendering is complete, the DMA controller configures the DMA channel with the following parameters:

[0043] Transfer source address: Set the DMA source address register to the starting physical address of the initial transfer video memory A. It should be noted that during the initial startup phase, video memory A does not yet contain valid screen data (it is only filled with the default background color, such as all black or all white, by the initialization process).

[0044] Transmission target address: Set the DMA target address register to the physical address of the SPI peripheral's transmit data register, pointing to that peripheral register in a fixed manner.

[0045] Transmission direction and incremental mode: Configured as memory → peripheral, source address increments (automatically points to the next pixel after each data unit is transmitted), and destination address is fixed.

[0046] Transmission data width: Keeps consistent with the SPI data bit width (e.g., 16 bits or 8 bits) to ensure that the number of bytes transferred by each DMA matches the SPI frame format.

[0047] Based on the effective pixel width W of a single row on the screen and the number of storage bytes BP occupied by a single pixel (BP = 2 bytes here), the total number of data bytes required for a single transmission (covering 10 rows of pixels) is... for: .

[0048] The number of DMA transfers (i.e. the number of DMA transfer operations triggered) is further determined based on the data bit width configured in the SPI.

[0049] If the SPI data width is 16 bits (2 bytes), then the number of DMA transfers... The formula for calculating the number of pixels is: .

[0050] If the SPI data width is 8 bits (1 byte), then the formula for calculating the number of DMA transfers is: .

[0051] The calculated number of DMA transfers is written to the DMA data transfer quantity register to determine the termination condition for this transfer.

[0052] After completing the above parameter configuration, the DMA controller enables the DMA channel and enables the DMA send request of SPI through the SPI control register. Thereafter, whenever the SPI transmit data register empty (TXE) event occurs, the DMA controller automatically reads a data unit (pixel or byte) from the current address of video memory A and writes it into the transmit data register of the SPI peripheral. At the same time, the source address increments and the transfer counter decrements. The SPI hardware then serially outputs the data to the TFT-LCD screen according to the configured timing, thereby completing the pixel refresh of the screen area from line 1 to line 10.

[0053] Explanation of the first round of transmission: Since the source data for the first transmission is taken from video memory A (containing only the initial background color), the content displayed in this refresh is a preset placeholder color block, not the actual image of the current frame. After the DMA transmission is completed and an interrupt is triggered, the video memory role will be switched (the original rendering video memory B becomes the source of the next round of transmission, and the original transmission video memory A becomes the target of the next round of rendering). Subsequent rounds can then transfer the latest rendered valid data to achieve continuous image updates.

[0054] S2-2: During the DMA transfer of data to video memory A, the MCU main control unit has no data transfer task and continues to run the GUI application in the background. It then completes the rendering of display data for lines 11-20 on the screen in video memory B, achieving parallel execution of data transfer and data rendering. The specific implementation steps are as follows:

[0055] Set the number of standard processing lines per group ; Time taken to transfer a set of 10 rows of pixels for DMA; Time taken to render a set of 10 rows of pixels for the CPU; For transmission unit counter; For rendering unit counters; Represents the current transfer of video memory. This represents the current rendering video memory.

[0056] Initialize the DMA transfer channel and configure the current transfer memory. Total transmission volume Background data is transferred via DMA hardware, which independently occupies the bus to handle pixel transfers. The CPU does not participate in any data copying operations, thus reducing the CPU's workload. All computing power is allocated to GUI rendering tasks, with a computing power allocation coefficient. Parallel constraints: .

[0057] GUI with For drawing caching, render the starting row of the range. End line Calculation of the number of lines rendered: .

[0058] The DMA hardware transfer action and CPU graphics rendering are performed simultaneously, with the timing of the two tasks completely overlapping. The total time consumed in this stage is... The rendering operation does not increase the system time, and the transmission and rendering are executed in parallel.

[0059] S2-3: When the DMA transfer counter decrements to 0, all 10 lines of background data in video memory A have been sent. The DMA hardware triggers a transfer completion interrupt. The interrupt service function performs a flag clearing operation, clearing the DMA transfer completion interrupt flag and the SPI transmission completion flag to avoid repeated interrupt triggering. Subsequently, the global transfer completion event flag is set, and a transfer completion signal is pushed to the upper GUI layer. The CPU context is restored. The specific implementation steps are as follows:

[0060] Set the initial value of the DMA internal decrement counter. Real-time remaining count value Number of lines transmitted The formula for determining transmission completion is as follows: .

[0061] When the equation is true, it means that all 10 lines of background data in video memory A have been transferred. The hardware triggers a DMA transfer completion interrupt and enters the interrupt service function to perform normalized bitwise operations.

[0062] Flag clearing operation: , Clear the hardware interrupt trigger flag to avoid repeated interrupts.

[0063] Event setting operation: It pushes a transmission completion signal to the upper GUI layer.

[0064] CPU context restoration: Perform a stack pop operation, restore the register context, exit the interrupt, and switch the CPU back to the background GUI task.

[0065] S2-4: After receiving the transmission completion signal, the GUI application layer performs a video memory role switching operation within the interrupt critical protection zone: the original transmission video memory A is switched to the new rendering video memory to carry the next set of data for drawing; the original rendering video memory B is switched to the new transmission video memory, and the first 10 lines of valid data stored in it are used as the source for the next round of transmission; after the switching is completed, the global status flag is updated, and interrupts are immediately enabled to resume system operation; subsequently, the DMA control module only updates the DMA source address register to the starting address of video memory B, while keeping other parameters unchanged, enabling the DMA channel, starting the second round of transmission, and sending the first 10 lines of valid screen data to the screen, covering the previous background placeholder screen. The specific implementation steps are as follows:

[0066] GUI detected The video memory switching process is then executed. To ensure the atomicity of the operation, the original interrupt state is latched first. , This is a temporary cache variable for the interrupt flag. To enable global interrupts, execute the command to disable interrupts. Construct a critical protection zone.

[0067] Formula for swapping video memory roles: ;

[0068] Before switching , Substituting the values, we get: , .

[0069] The physical meaning is: the original transfer memory A is converted into a rendering cache, the original rendering memory B is converted into a transfer cache, and the pixels in rows 1 to 10 of memory B are used as the data source for the next round of transfer.

[0070] After the switch is complete, update the global status flags and perform interrupt recovery. Release the critical protection; the DMA parameter update only modifies the source address register, while the other parameters remain unchanged, enable the DMA channel, start the second round of transfer, and output the valid screen of video memory B to cover the placeholder background of the first round.

[0071] S2-5: During the second round of DMA transfer of data to video memory B, the CPU simultaneously renders pixel data for rows 11-20 in video memory A, with the two times completely overlapping. After the second round of transfer is completed, an interrupt is triggered again, and a video memory switch is executed: video memory A becomes the transfer video memory, sending data for rows 11-20; video memory B becomes the rendering video memory, drawing data for rows 21-30; and so on, forming a stable pipeline operation: in each round of DMA transfer of ready data in the current video memory to the screen, the CPU simultaneously renders the next set of 10 rows of data in another video memory. Except for the first round of placeholder transfer, all effective data units achieve complete parallelism between transfer and rendering, and the unit time is determined by the maximum value of the transfer time and the rendering time. The specific implementation steps are as follows:

[0072] Second round of DMA transfer The inner 10 lines of data are synchronized by the CPU. Rendering 11-20 rows of pixels, with two tasks running in parallel, the cycle time for a single group meets the following requirements: .

[0073] The second round of transmission ends and another interrupt is triggered, repeating the recursive formula for memory swapping: .

[0074] when hour, (Transmit lines 11-20) (Render lines 21-30), repeating in a loop to form a pipeline.

[0075] The schedule constraint identity is (rendering always leads the group, with no waiting delay): .

[0076] It should be noted that the first round Transmission without parallel rendering results in preheating losses. All effective screen units are executed in parallel, significantly improving refresh efficiency.

[0077] S2-6: Once the GUI application has completed rendering the last 10 lines of data on the screen (or the remaining lines if less than 10), and this data has been transferred to the TFT-LCD screen via DMA, the full-screen refresh process ends. For dynamic display scenarios, the process in S2 is repeated to achieve continuous high-speed screen refresh. The specific implementation steps are as follows:

[0078] Let the total number of lines on the screen be The system uses 10 rows of pixels as a single standard processing unit. The total number of processing units is the integer value obtained by dividing the total number of screen rows by the number of standard rows in a single group. The actual number of rows in the last unit is the remainder obtained by dividing the total number of screen rows by the number of standard rows in a single group. If the remainder is 0, the last unit is a standard 10-row pixel unit. Otherwise, only the pixel data corresponding to the number of rows of the remaining remainder is rendered and transmitted. When the last group of pixels is rendered and all of them are transmitted to the LCD screen via DMA, the single static image refresh process is considered to be over. If it is a dynamic display scene, the transmission unit counter, rendering unit counter and all video memory status flags are reset, and the S2 process is returned to achieve continuous high-speed screen refresh.

[0079] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed refresh method for an LCD screen based on an SPI bus, characterized in that, Includes the following steps: S1: By sequentially completing the initialization processes of the SPI peripheral, DMA controller, dual-buffered video memory module, interrupt response module, and GUI application, the basic operating environment for DMA-SPI parallel refresh is established. S2: The screen refresh phase uses 10 consecutive rows of pixel data as a single basic refresh unit. Relying on the alternating switching mechanism of the two video memory blocks, it cyclically carries out the synchronous operation of DMA hardware data transfer and background graphics parallel rendering until the drawing output of all pixel content of the entire screen is completed. During operation: The DMA controller uses the SPI peripheral transmit register empty event as the trigger source to independently output the pixel data in the currently transferred video memory to the LCD screen via SPI. The data transfer process does not occupy CPU computing resources. While the CPU is performing data transfer in the DMA, it simultaneously completes the graphics rendering operation of the next set of pixels to be refreshed in the currently rendered video memory. Whenever a set of pixel data is transferred by DMA and triggers an interrupt, the functional roles of the two video memories are switched through atomic operations. After the DMA controller updates the transfer source address to the new transfer video memory start address, it starts the next set of data transfer, forming a stable pipeline operation in which data transfer and graphics rendering are executed in parallel.

2. The method according to claim 1, characterized in that, The specific steps for initialization are as follows: Configure the communication protocol parameters of the microcontroller's SPI peripheral according to the hardware interface timing requirements of the driven TFT-LCD screen, including communication baud rate, data bit width, clock polarity and clock phase; Bind the target DMA channel to the SPI peripheral hardware link, set the DMA transfer trigger source to the SPI transmit register empty event, and configure the transfer direction to be unidirectional transfer from memory to peripheral; disable the CPU's control and intervention over the data transfer link, and let the DMA hardware independently complete the batch transfer of pixel data from memory to the display screen via the SPI peripheral; Two physical memory regions with completely independent storage space and mutually isolated physical addresses are divided in the microcontroller's on-chip random access memory, labeled as memory region A and memory region B respectively. The storage capacity of the two memory regions is equal, and the storage capacity of a single memory region strictly matches the complete data storage requirements of 10 rows of pixels on the screen. During the initialization phase, one memory region is designated as the initial external transmission memory, and the other memory region is designated as the initial background rendering memory. Enable the DMA controller's transfer completion interrupt and bind the corresponding interrupt service function. The interrupt service function is used to send a transfer completion notification signal to the upper-level GUI application when the DMA transfer is complete, triggering the role swapping of the transfer and rendering functions of the two memory blocks. Load the basic display parameters adapted to the TFT-LCD screen, including the screen physical resolution, effective display area, and color format; simultaneously complete the initialization configuration of the underlying graphics rendering engine, uniformly initialize the drawing cache, drawing interface, pixel conversion logic, and coordinate mapping rules required by the rendering engine, and build the graphics drawing runtime environment.

3. The method according to claim 1, characterized in that, During the initial startup phase of the pipeline operation, the initial external memory transfer is only filled with a preset default background color during the initialization phase, and the first round of DMA transfer outputs the default background color as the boot placeholder screen. After the first DMA transfer is completed and an interrupt is triggered, and the video memory role is switched, subsequent DMA transfers will output valid screen data that has been pre-rendered in the background, covering the placeholder screen of the first round.

4. The method according to claim 2, characterized in that, Before initiating a single 10-row pixel DMA transfer, configure the DMA transfer parameters according to the fixed data bit width of the SPI: the total number of data bytes transferred for a single 10-row pixel group is 10×W×BP, where W is the effective pixel width of a single row on the screen, and BP is the number of storage bytes occupied by a single pixel. In RGB565 format, BP is 2. If the SPI data bit width is 16 bits, the number of DMA transfers is configured to be 10×W; if the SPI data bit width is 8 bits, the number of DMA transfers is configured to be 10×W×2. The DMA channel is configured with the source address automatically incrementing and the target address fixedly pointing to the SPI peripheral transmit data register. The DMA transfer data width is consistent with the SPI data bit width.

5. The method according to claim 1, characterized in that, The parallel processing of DMA transfer and CPU rendering satisfies timing constraints: Assume the DMA transfer time for a single group of 10 rows of pixels is... The CPU takes 10 seconds to render a single group of 10 rows of pixels. When the two are executed in parallel, the cycle time of a single job is and The maximum value in the range; during parallel operation, the CPU does not participate in pixel data transfer operations, all computing resources are allocated to the GUI rendering task, and the rendering job progress always stays ahead of the DMA transfer of a set of 10 rows of pixel offsets.

6. The method according to claim 1, characterized in that, The interrupt service procedure after the DMA transfer completion interrupt is as follows: When the DMA transfer counter decrements to 0, it is determined that a single group of data transfers is complete, and the hardware triggers the DMA transfer completion interrupt; after entering the interrupt service function, the flag bit is cleared to clear the DMA transfer completion interrupt flag and the SPI transmission completion flag to avoid repeated interrupt triggering; then the global transfer completion event flag is set, and the transfer completion signal is pushed to the upper GUI layer, and the CPU context is restored.

7. The method according to claim 1, characterized in that, After receiving the transmission completion signal, the GUI layer performs a video memory role switching operation within the interrupt critical protection zone: latching the original interrupt state and disabling global interrupts to build an execution environment without interruption. Then, the roles of the current transfer memory and the current rendering memory are swapped, and the original transfer memory is switched to the new rendering memory. The original rendering memory is switched to the new transfer memory, and the rendered data already stored therein is used as the data source for the next round of DMA transfer. After the switch is completed, the global video memory status flag is updated, the interrupt enable is restored according to the original interrupt status latched, and the critical protection zone is exited. The DMA controller only updates the source address register to the starting physical address of the new transfer video memory, while the other transfer parameters remain fixed, and enables the DMA channel to start the next set of data transfers.

8. The method according to claim 1, characterized in that, When the CPU performs pixel writing in the rendering memory, it strictly follows the rule of continuous address writing: the pixel data of the corresponding row is filled in the order of the screen row number from small to large, the pixel address within a single row is continuously increased, and the high and low bytes of RGB565 format pixels are written to the corresponding memory unit in the transmission order specified by the screen hardware. Once all pixels in a single group have been filled, a data ready notification is sent to the DMA controller via a preset callback function.

9. The method according to claim 1, characterized in that, The final processing and dynamic loop logic for full-screen refresh are as follows: Let the total number of lines on the screen be... The standard processing unit is 10 rows of pixels. The total number of processing units is the integer value obtained by dividing the total number of rows on the screen by the number of standard rows in a single group. The actual number of rows in the last unit is the remainder obtained by dividing the total number of rows on the screen by the number of standard rows in a single group. If the remainder is 0, the last unit is a standard 10-row pixel unit. Otherwise, only the pixel data corresponding to the number of rows of the remaining remainder is rendered and transmitted. When the last group of pixels is rendered and all of them are transmitted to the LCD screen via DMA, the single static image refresh process is considered to be over. If it is a dynamic display scene, the transmission unit counter, rendering unit counter and all video memory status flags are reset, and the process returns to execute S2.

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