Memory, storage system, and electronic device
Patent Information
- Application Number
- CN202510559010.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2026-10-30
AI Technical Summary
[0012]在存储器(该存储器包括两个相键合的半导体结构)的一个半导体结构中，由电容并联成电荷泵中的电容组，在存储器的另一半导体结构中设置电荷泵中的电压调节电路。由于电容组中的多个电容通过连接至半导体结构(第一半导体结构)中的金属层实现并联，故采用本申请提供的技术方案，可以通过控制连接至金属层的电容的数量控制电容组中并联的电容的数量，从而较为灵活地控制电荷泵中电容组的总电容值。
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Figure CN123017100A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a memory, storage system and electronic device. Background Technology
[0002] A charge pump is a circuit that uses the energy storage characteristics of a capacitor to generate an output voltage, and it has wide applications in memory.
[0003] The performance of a charge pump is directly affected by the charge storage capacity of the capacitor in the charge pump (which can be characterized by the capacitance value). In memory, how to rationally design the capacitor in the charge pump still needs further research. Summary of the Invention
[0004] This application provides a memory, a storage system, and an electronic device. The technical solutions provided by this application are as follows:
[0005] According to one aspect of the embodiments of this application, a memory is provided, the memory including a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded to each other;
[0006] The first semiconductor structure includes a metal layer and a capacitor bank in a charge pump, the capacitor bank including a plurality of capacitors;
[0007] The plurality of capacitors are connected to the metal layer, and the metal layer is used to connect the plurality of capacitors in parallel;
[0008] The second semiconductor structure includes the voltage regulation circuit in the charge pump.
[0009] According to one aspect of the embodiments of this application, a storage system is provided, the storage system including a controller and the aforementioned memory, the controller being coupled to the memory to control the memory to store data.
[0010] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including a host and a storage system coupled to the host, the storage system including a controller and the aforementioned memory, the controller being coupled to the memory to control the memory to store data.
[0011] The technical solutions provided in this application have at least the following beneficial effects:
[0012] In one semiconductor structure of a memory (which comprises two bonded semiconductor structures), capacitors are connected in parallel to form a capacitor bank in a charge pump. A voltage regulation circuit for the charge pump is disposed in the other semiconductor structure of the memory. Since the multiple capacitors in the capacitor bank are connected in parallel through a metal layer in the semiconductor structure (the first semiconductor structure), the number of capacitors connected in parallel in the capacitor bank can be controlled by controlling the number of capacitors connected to the metal layer, thereby allowing for more flexible control of the total capacitance value of the capacitor bank in the charge pump. Attached Figure Description
[0013] Figure 1 This is a structural block diagram of an electronic device provided in one embodiment of this application;
[0014] Figure 2 This is a structural block diagram of an electronic device provided in another embodiment of this application;
[0015] Figure 3 This is a schematic diagram of a solid-state driver provided in one embodiment of this application;
[0016] Figure 4 This is a schematic diagram of memory provided in one embodiment of this application;
[0017] Figure 5 This is a schematic diagram of the composition structure of a memory provided in one embodiment of this application;
[0018] Figure 6 This is a schematic diagram illustrating the connection relationship between word lines, bit lines, and memory cells of a memory according to an embodiment of this application;
[0019] Figure 7 This is a schematic diagram of a memory provided in one embodiment of this application;
[0020] Figure 8 This is a schematic diagram of the three-dimensional structure of a memory provided in one embodiment of this application;
[0021] Figure 9 This is a schematic diagram showing the connection relationship between the capacitor bank and the first and second metal layers according to an embodiment of this application;
[0022] Figure 10 This is a schematic diagram showing the correspondence between the structure in the charge pump provided in one embodiment of this application and the first semiconductor structure and the second semiconductor structure, as well as a capacitor bank in the first capacitor circuit;
[0023] Figure 11 This is a schematic diagram showing the correspondence between the structure in the charge pump provided in one embodiment of this application and the first semiconductor structure and the second semiconductor structure, as well as the two capacitor groups in the first capacitor circuit;
[0024] Figure 12 This is a schematic diagram of the memory region distribution provided in one embodiment of this application;
[0025] Figure 13 This is a schematic diagram of the memory area distribution provided in another embodiment of this application. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0027] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in various orders. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with this application. Rather, they are merely examples consistent with some aspects of this application.
[0028] Figure 1 A structural block diagram of an electronic device according to an embodiment of this application is shown. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, electronic device 1 may include a host 10 and a storage system 20, the storage system 20 including a memory controller 30 and one or more memories 40. The host 10 may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host 10 may be configured to send data to or receive data from the memory 40. The controller 30 is coupled to the memory 40 and the host 10 and is configured to control the memory 40. The controller 30 may manage the data stored in the memory 40 and communicate with the host 10.
[0029] The controller 30 can be configured to control the operation of the memory 40, such as read, erase, write, and refresh operations. In some embodiments, the controller 30 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 40. The controller 30 can also perform any other suitable function, such as formatting the memory 40.
[0030] In some specific embodiments, the controller 30 and one or more memories 40 can be integrated into various types of electronic devices. For example, the controller 30 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memories 40 can be integrated into a memory module. In other words, the storage system 20 can be implemented and packaged into different types of terminal electronic products.
[0031] The controller 30 can send data to / receive data from the host 10, and can send commands (CMD) and addresses (ADDR) to the memory. The controller 30 may include a command generator 31, an address generator 32, a device interface 33, and a host interface 34. The host interface 34 can receive commands and addresses from the host 10, the command generator 31 can generate commands for the memory 40 by decoding the commands received from the host 10, and can provide the corresponding commands to the memory 40 through the device interface 33.
[0032] The address generator 32 in the controller 30 can generate the row and column addresses to be accessed in the memory cell array 41 by decoding the address received from the host interface 34. Furthermore, the address generator 32 can generate the addresses of the memory banks to be accessed when the memory cell array 41 comprises multiple banks.
[0033] Furthermore, the controller 30 can control memory operations such as writing and reading by providing various signals to the memory 40 via the device interface 33. For example, the controller 30 can provide a write command to the memory 40. The write command is used to instruct the memory 40 to perform a write operation to store data in the memory 40.
[0034] In some embodiments, the memory 40 includes a memory cell array 41 and peripheral circuitry 42. The memory cell array 41 includes multiple banks, each bank including multiple blocks, each block including multiple rows and columns of memory cells, each row of memory cells coupled to a corresponding word line, and each column of memory cells coupled to a corresponding bit line. The peripheral circuitry 42 can write data to or read data from the memory cell array 41 based on commands and addresses received from the controller 30, or it can provide control signals to the row decoding circuitry and column decoding circuitry for refreshing the memory cells included in the memory cell array 41. In other words, the peripheral circuitry 42 can perform all operations for processing data in the memory cell array 41. The peripheral circuit 42 may include: control circuits corresponding to each memory block, such as sensing amplifier (SA) circuits and word-line driver (WLD) circuits; control circuits corresponding to each memory bank, such as row decoding circuits and column decoding circuits; and control circuits corresponding to all memory banks, such as command buffers, command decoders, address buffers, data input / output buffers, and mode registers.
[0035] In any embodiment of this application, the memory 40 mentioned can be a volatile memory, such as random access memory (RAM). Exemplarily, the memory 40 may include dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. In the following embodiments, DRAM is used as an example for the memory 40.
[0036] Figure 2A structural block diagram of an electronic device according to another embodiment of this application is shown. In some embodiments, the memory 40 (DRAM) in the electronic device 2 may be a structure outside the storage system 50, which may be directly connected to the host 10 as main memory during the operation of the host 10, or the memory 40 may be embedded in the host 10. In some embodiments, the memory 40 may be a structure outside the storage system 50, which may be connected to the storage system 50 for use as a buffer memory, for example, for storing a mapping table. In some embodiments, the memory 40 as a buffer memory may also be embedded in the controller of the storage system 50. In other embodiments, the memory 40 may also be part of the controller of the storage system 50, for example, the memory 40 as a buffer memory is embedded in the controller. In some embodiments, the controller of the storage system 50 includes a controller for the memory 40 (such as a DRAM controller) and a controller for non-volatile memory (such as flash memory) in the storage system. In other embodiments, a stacked arrangement of multiple memories 40 may be applied to a high-bandwidth memory (HBM) architecture for use as a storage medium.
[0037] Figure 3 A schematic diagram of a solid-state drive (SSD) according to an embodiment of this application is shown. This SSD 60 can be understood as an application example of the storage system 20 or storage system 50 described above. In this example, the memory 40 can be used as a buffer memory.
[0038] like Figure 3As shown, the Solid State Drive (SSD) 60 may include an SSD controller 61, memory 40, and non-volatile memory 62. The SSD controller 61 provides the physical connection between the host and the SSD 60. That is, the SSD controller 61 can provide an interface between the host and the SSD 60 according to the host's bus format. The SSD controller 61 can decode instructions provided by the host. The SSD controller 61 can access the non-volatile memory 62 based on the decoding result. The memory 40 can temporarily store data written by the host or data read from the non-volatile memory 62. When the host issues a read request, if the data present in the non-volatile memory 62 is cached, the memory 40 can support a caching function to directly provide cached data to the host. The data transfer rate through the host's bus format (e.g., SATA (Serial Advanced Technology Attachment) or SAS (Serial Attached Small Computer System Interface)) is much higher than the data transfer rate of the SSD 60's memory channels. That is, when the host interface speed is significantly higher, the performance degradation caused by the speed difference can be minimized by providing a high-capacity memory 40. Additionally, memory 40 can store the address mapping table of non-volatile memory 62. Non-volatile memory 62 can be configured as the storage medium of SSD 61. Non-volatile memory 62 can include, but is not limited to, NAND Flash (Not AND Flash).
[0039] Figure 4 A schematic diagram of memory provided in one embodiment of this application is shown. This memory 70 can be understood as an application example of the storage system 20 or storage system 50 described above. In this example, the memory 40 can be used as a storage medium.
[0040] like Figure 4As shown, memory 70 can be easily attached to or installed in an electronic device or removed from an electronic device via the illustrated interface. Memory 70 may include multiple memories 40 (e.g., DRAM) and a memory controller 71. Memory 70 can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of a computer's processor. In some embodiments, memory controller 71 may communicate with memory 40 using at least one communication protocol or technology standard typically associated with, for example, Dual Inline Memory Modules (DIMMs), Registered DIMMs (RDIMMs), Load-Reduced DIMMs (LRDIMMs), and Unbuffered DIMMs (UDIMMs).
[0041] It should be noted that, Figure 3 and Figure 4 The application scenario of the memory 40 shown is exemplary, and this application does not limit its application scenario.
[0042] Figure 5 A schematic diagram of the composition structure of a memory provided in one embodiment of this application is shown; Figure 6 This diagram illustrates the connection relationship between word lines, bit lines, and memory cells of a memory provided in one embodiment of this application.
[0043] Figure 5 The right side illustrates the structure of the memory cell 401 in the memory 40. The memory 40 includes at least one memory die, each memory die including a memory cell array 41. The memory cell array 41 includes multiple memory cells 401 arranged in an array. Each memory cell 401 includes a transistor 402 and a capacitor structure 403. The main working principle of the memory cell 401 is to use the amount of charge stored in the capacitor structure 403 to represent whether a binary bit is 1 or 0. The memory cells 401 are arranged in an array, which can be considered a typical mesh structure. For details of this mesh structure, please refer to [reference needed]. Figure 6 The memory cell array 41 uses row and column addresses to specify addresses. By specifying the intersection of the row and column (by specifying the row address and column address of the DRAM), the controller can independently access each memory cell 401 in the memory chip and perform read, write, or refresh operations on the data stored therein.
[0044] Figure 5The left side shows the memory cell array 41 in memory 40 and some peripheral circuitry. The row decoding circuit, in response to an address input to it, selects word lines to choose the row of the memory cell to access. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit is used to implement the selection of bit lines. For example... Figure 5 As shown, the peripheral circuitry also includes a voltage generator that can generate and regulate various voltages required within the memory 40. For example, a high voltage (such as VPP) can be provided to the row decoding circuitry to drive the selected word line, a reference voltage can be provided to the sense amplifier to detect and amplify small signals on the bit lines, a switching control voltage (such as VDD or a negative voltage) can be provided to the column decoding circuitry to connect the selected bit line to the data bus, and an interface voltage (such as VDDQ or a high voltage VDDQ+, matched to the external system) can be provided to the data input / output buffer to ensure level compatibility between the memory 40 and the external controller.
[0045] To enable write and refresh operations on the memory cells 401 of the memory 40, a voltage higher than the normal operating voltage is required. The charge pump in the voltage generator can convert a low voltage (such as VDD) into the required high voltage (such as VPP, VDDQ+), thereby providing sufficient charge to the memory cells of the memory 40. The charge pump has many advantages such as low power consumption, high integration, and stability, making it widely used.
[0046] A charge pump is a circuit that uses the energy storage characteristics of a capacitor to generate an output voltage. Therefore, the performance of a charge pump is directly affected by the charge storage capacity of the capacitor in the charge pump (which can be characterized by the capacitance value). In memory, how to rationally design the capacitor in the charge pump still needs further research.
[0047] Please refer to Figure 7 The diagram illustrates a memory provided in one embodiment of this application.
[0048] The memory 40 includes a first semiconductor structure 100 and a second semiconductor structure 200, which are bonded to each other.
[0049] It should be noted that the term "bonding" in the embodiments of this application can refer to any suitable bonding technology, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, and eutectic bonding.
[0050] The first semiconductor structure 100 includes a metal layer 150 and a capacitor bank 101 in a charge pump, the capacitor bank 101 including a plurality of capacitors 102.
[0051] Multiple capacitors 102 are connected to a metal layer 150, which is used to connect the multiple capacitors 102 in parallel.
[0052] The second semiconductor structure 200 includes a voltage regulation circuit 250 in a charge pump.
[0053] In some embodiments, the voltage regulation circuit 250 of the charge pump is connected to the input and output terminals of the charge pump to regulate the input voltage.
[0054] The voltage regulation circuit 250 may include any other device (such as a transistor) in the charge pump besides the capacitor bank 101, and this application does not limit this.
[0055] In some embodiments, capacitor bank 101 is connected to voltage regulation circuit 250.
[0056] In some embodiments, please refer to Figure 8 The first semiconductor structure 100 includes a first bonding structure 110, and the second semiconductor structure 200 includes a second bonding structure 210. The first semiconductor structure 100 and the second semiconductor structure 200 are bonded to each other through the first bonding structure 110 and the second bonding structure 210. The materials of the first bonding structure 110 and the second bonding structure 210 include at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).
[0057] The devices included in the first semiconductor structure 100 and the devices included in the second semiconductor structure 200 can be connected through corresponding conductive structures. For example, the capacitor bank 101 and the voltage regulation circuit 250 can be connected through conductive structures in the first semiconductor structure (such as metal vias, metal layers 150, and first bonding structures 110 in the first semiconductor structure 100) and conductive structures in the second semiconductor structure (such as metal vias, metal layers, and second bonding structures 210 in the second semiconductor structure 200).
[0058] The technical solution provided in this application embodiment includes a capacitor bank 101 in a charge pump, where capacitors 102 are connected in parallel in one semiconductor structure of a memory 40 (which includes two bonded semiconductor structures). A voltage regulation circuit 250 in the charge pump is provided in the other semiconductor structure of the memory. Since the multiple capacitors 102 in the capacitor bank 101 are connected in parallel through a metal layer 150 in the semiconductor structure (first semiconductor structure), the number of capacitors 102 connected in parallel in the capacitor bank 101 can be controlled by controlling the number of capacitors connected to the metal layer 150, thereby allowing for more flexible control of the total capacitance value of the capacitor bank 101 in the charge pump.
[0059] For example, capacitor bank 101 includes M capacitors. Since the M capacitors are arranged in parallel, the total capacitance value of the capacitor bank is the sum of the individual capacitance values of the M capacitors. In other words, the total capacitance value of the capacitor bank can be controlled by controlling the value of M, where M is an integer greater than 1.
[0060] In the following embodiments, the specific connection method between the multiple capacitors 102 and the metal layer 150 will be described in more detail.
[0061] In some embodiments, please refer to Figure 9 The metal layer 150 includes a first metal layer 151 and a second metal layer 152.
[0062] In some embodiments, the first metal layer 151 and the second metal layer 152 are different metal layers in the first semiconductor structure 100.
[0063] Each of the multiple capacitors 102 has its first terminal connected to a first metal layer 151, which is used to connect the first terminals of the multiple capacitors to each other. The first metal layer 151 is used to connect the first terminals of the multiple capacitors to each other, which means that the conductor structure in the first metal layer 151 (such as the metal traces in the first metal layer 151) connects the first terminals of the multiple capacitors 102 to each other.
[0064] In some embodiments, please refer to Figure 9 For each of the multiple capacitors 102, the first end of the capacitor 102 is connected to one end of the first connection structure 103 corresponding to the capacitor, and the other end of the first connection structure 103 corresponding to the capacitor 102 is connected to the first metal layer 151. Different capacitors among the multiple capacitors 102 correspond to different first connection structures 103.
[0065] The first connection structure can be any structure with conductive function, such as a metal through hole.
[0066] In the above embodiment, each of the multiple capacitors 102 is connected to the first metal layer 151 through a corresponding first connection structure 103. Therefore, in the memory 40, the total capacitance value of the capacitor group 101 can be flexibly controlled by controlling the number of first connection structures 103 configured for the capacitor group 101 (such as the number of metal vias).
[0067] Each of the multiple capacitors 102 has its second terminal connected to a second metal layer 152, which is used to connect the second terminals of the multiple capacitors to each other. The second metal layer 152 is used to connect the second terminals of the multiple capacitors to each other by means of the conductor structure in the second metal layer 152 (such as the metal traces in the second metal layer 152).
[0068] In some embodiments, for each of the plurality of capacitors 102, the second end of the capacitor 102 is connected to one end of the second connection structure corresponding to the capacitor, and the other end of the second connection structure corresponding to the capacitor 102 is connected to the second metal layer 152, wherein different capacitors among the plurality of capacitors 102 correspond to different second connection structures.
[0069] In other embodiments, the second terminals of each of the plurality of capacitors 102 are directly connected to the second metal layer 152 without the aid of the second connection structure described above.
[0070] In some embodiments, please refer to Figure 10 or Figure 11 The charge pump includes a first capacitor circuit 120, in which the number of capacitor groups 101 is N, the first metal layer 151 includes N first conductor structures, and the second metal layer 152 includes N second conductor structures, where N is a positive integer.
[0071] The first conductor structure is a conductive structure in the first metal layer 151 (such as a metal trace in the first metal layer 151), and the second conductor structure is a conductive structure in the second metal layer 152 (such as a metal trace in the second metal layer 152).
[0072] In the i-th capacitor group 101 of N capacitor groups 101, the first terminal of each of the multiple capacitors 102 is connected to the i-th first conductor structure of N first conductor structures, and the second terminal of each of the multiple capacitors 102 is connected to the i-th second conductor structure of N second conductor structures, where i is a positive integer less than or equal to N.
[0073] In some embodiments, one end of the first capacitor circuit 120 is connected to the voltage regulation circuit 250, and the second semiconductor structure 200 includes a first clock signal source connected to the other end of the first capacitor circuit 120.
[0074] In some embodiments, please refer to Figure 10 When N equals 1, i.e., the first capacitor circuit 120 includes a capacitor bank 101, the first metal layer 151 includes a first conductor structure, and the second metal layer 152 includes a second conductor structure, the first conductor structure is connected to the voltage regulation circuit 250, and the second conductor structure is connected to the first clock signal source.
[0075] In some embodiments, when N is greater than 1, N capacitor groups 101 can be connected in series by connecting different conductor structures in the same metal layer, as will be described in the following embodiments.
[0076] When N is even, the first of the N first conductor structures is connected to the voltage regulation circuit 250, the j-th second conductor structure is connected to the (j+1)-th second conductor structure, the k-th first conductor structure is connected to the (k+1)-th first conductor structure, and the N-th first conductor structure is connected to the first clock signal source. Here, j is a positive odd number less than N, and k is a positive even number less than N.
[0077] For example, please refer to Figure 11 When N equals 2, the first of the two first conductor structures is connected to the voltage regulation circuit 250, the first of the two second conductor structures is connected to the second of the two second conductor structures, and the second of the two first conductor structures is connected to the first clock signal source. Figure 11 As can be seen, by connecting the two second conductor structures (the first second conductor structure and the second second conductor structure) in the second metal layer 152, the two capacitor groups 101 are connected in series to form the first capacitor circuit 120.
[0078] When N is an odd number greater than 1, the first first conductor structure among the N first conductor structures is connected to the voltage regulation circuit, the j-th second conductor structure among the N second conductor structures is connected to the (j+1)-th second conductor structure among the N second conductor structures, the k-th first conductor structure among the N first conductor structures is connected to the (k+1)-th first conductor structure among the N first conductor structures, and the N-th second conductor structure among the N second conductor structures is connected to the first clock signal source.
[0079] For example, when N equals 3, the first of the three first conductor structures is connected to the voltage regulation circuit 250, the first of the three second conductor structures is connected to the second of the three second conductor structures, the second of the three first conductor structures is connected to the third of the three first conductor structures, and the third of the three second conductor structures is connected to the first clock signal source. In this example, by connecting the two second conductor structures (the first and second second conductor structures) in the second metal layer 152 and the two first conductor structures (the second and third first conductor structures) in the first metal layer 151, the three capacitor groups 101 are connected in series to form the first capacitor circuit 120.
[0080] In some embodiments, when N is greater than 1, at least two of the N capacitor groups have a different number of capacitors. For example, when N equals 2, the first capacitor group may contain 10 capacitors, and the second capacitor group may contain 12 capacitors.
[0081] In the above embodiment, the first capacitor circuit 120, which is connected to the voltage regulation circuit 250 and the first clock signal source respectively, can be composed of multiple capacitor groups 101 in addition to a single capacitor group 101. Furthermore, the number of capacitors included in these multiple capacitor groups 101 can also be different. It can be seen that the configuration of the first capacitor circuit 120 has extremely high flexibility.
[0082] In some embodiments, the first semiconductor structure 100 includes a plurality of capacitor circuits in a charge pump, one end of which is connected to a voltage regulation circuit 250. The capacitor circuit includes at least one capacitor group; if the capacitor circuit includes multiple capacitor groups, the multiple capacitor groups are connected in series.
[0083] The aforementioned multiple capacitor circuits may include the first capacitor circuit 120 described in the above embodiments. In the capacitor circuit, the implementation method of multiple capacitor groups 101 connected in series can be referred to the implementation method of N capacitor groups 101 connected in series in the first capacitor circuit 120 in the above embodiments (when N is greater than 1), which will not be repeated here.
[0084] In some embodiments, the other end of the capacitor circuit is connected to a clock signal source in the second semiconductor structure 200.
[0085] In some embodiments, please refer to Figure 10 or Figure 11 The first semiconductor structure 100 includes P capacitor circuits (C1 to C2) in a charge pump. PThe voltage regulation circuit 250 includes P+1 voltage regulation sub-circuits 251, which are connected in series.
[0086] In some embodiments, the voltage regulation sub-circuit 251 is used to control the charging and discharging process of the capacitor circuit, thereby achieving voltage regulation. The voltage regulation sub-circuit 251 may include various devices such as diodes, metal-oxide-semiconductor field-effect transistors, complementary metal-oxide-semiconductor devices, charge transfer switches, and bipolar transistors. This application does not limit the specific types of devices included in the voltage regulation sub-circuit 251.
[0087] The input terminal of the first voltage regulation sub-circuit in the P+1 voltage regulation sub-circuit 251 is connected to the input terminal of the charge pump, and the output terminal of the P+1 voltage regulation sub-circuit in the P+1 voltage regulation sub-circuit is connected to the output terminal of the charge pump.
[0088] One end of the r-th capacitor in the P capacitor circuits is connected to the output terminal of the r-th voltage regulator circuit and the input terminal of the (r+1)-th voltage regulator circuit in the P+1 voltage regulator circuits, where r is a positive integer less than or equal to P.
[0089] For example, when P=2, the input terminal of the first voltage regulation sub-circuit of the three voltage regulation sub-circuits 251 is connected to the input terminal of the charge pump, and the output terminal of the third voltage regulation sub-circuit is connected to the output terminal of the charge pump. One end of the first capacitor circuit of the two capacitor circuits is connected to the output terminal of the first voltage regulation sub-circuit and the input terminal of the second voltage regulation sub-circuit of the three voltage regulation sub-circuit 251, respectively, and one end of the second capacitor circuit of the two capacitor circuits is connected to the output terminal of the second voltage regulation sub-circuit and the input terminal of the third voltage regulation sub-circuit of the three voltage regulation sub-circuit 251, respectively.
[0090] In some embodiments, among the plurality of capacitor circuits, at least two capacitor circuits include different numbers of capacitor groups.
[0091] For example, please refer to Figure 11 In a series of capacitor circuits, capacitor circuit C1 includes two capacitor banks 101, while capacitor circuit C... P It includes only one capacitor bank, 101.
[0092] In some embodiments, the number of capacitors included in the first capacitor group and the number of capacitors included in the second capacitor group are different, wherein the first capacitor group and the second capacitor group are capacitor groups in different capacitor circuits among multiple capacitor circuits.
[0093] For example, please refer to Figure 10In a series of capacitor circuits, capacitor group 101 in capacitor circuit C1 may include 10 capacitors, while capacitor circuit C... P The capacitor bank 101 may include 10 capacitors, or it may include fewer or more than 10 capacitors.
[0094] In the above embodiments, the number of capacitor groups included in different capacitor circuits may be different, and the number of capacitors included in the capacitor groups in different capacitor circuits may also be different. That is to say, based on the charge pump architecture provided in the embodiments of this application, the structure of the capacitor circuits at each position in the charge pump can be flexibly configured as needed. Therefore, the charge storage capacity of the capacitor circuits at each position can be flexibly configured as needed.
[0095] In some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 are stacked along a first direction, and a plurality of capacitor circuits and voltage regulation circuits 250 at least partially overlap in a view perpendicular to the first direction.
[0096] In some embodiments, the first semiconductor structure 100 further includes a memory cell array 41, which includes a plurality of memory cells 401. Each memory cell 401 includes a capacitor structure 403 and a transistor 402, and the capacitor structure 403 and the transistor 402 are connected.
[0097] In some embodiments, the capacitor structure 403 in the storage unit 401 has the same structure as the capacitor 102 in the capacitor group 101.
[0098] Please refer to Figure 12 This illustrates a schematic diagram of the area distribution of a memory provided in one embodiment of this application.
[0099] In some embodiments, such as Figure 12 As shown, the memory 40 includes a first storage area 601, a first peripheral area 602, and a second storage area 603 arranged along a second direction, with the first peripheral area 602 located between the first storage area 601 and the second storage area 603; a storage cell array 41 is located in the first storage area 601 and the second storage area 603; the second direction is perpendicular to the first direction. Furthermore, any two of the first direction, the second direction, and any third direction in the following embodiments are perpendicular to each other.
[0100] In some embodiments, the first storage area 601 and the second storage area 603 include a first circuit area 605, a second circuit area 606, and a third circuit area 607. The plurality of first circuit areas 605 are arranged in an array along a second direction and a third direction, with each storage cell corresponding to one first circuit area 605 (i.e., each first circuit area 605 contains a Bank). For example, as... Figure 12As shown, the memory 40 includes 16 first circuit regions 605, and the memory cell array 401 includes 16 memory banks Bank0-Bank15, each of which corresponds to one first circuit region 605. It should be noted that the number of first circuit regions 605 shown in the figures is for illustrative purposes only and is not intended to limit the number of first circuit regions 605 in the embodiments of this application.
[0101] like Figure 12 As shown, the second circuit region 606 is adjacent to the first circuit region 605 along the second direction, and the third circuit region 607 is located between the first circuit regions 605 adjacent to it along the third direction. The first circuit region 605 may also contain control circuits for each memory block of the corresponding memory bank, such as a sensing amplifier (SA) circuit and a word-line driver (WLD) circuit; the second circuit region 606 may contain column control circuits for the corresponding memory bank, such as a column decoding circuit; and the third circuit region 607 may contain row control circuits for the corresponding memory bank, such as a row decoding circuit. The first peripheral region 602 may include both a portion of the first semiconductor structure 100 and a portion of the second semiconductor structure 200. For example, the first peripheral region 602 may contain the voltage regulation circuit 250 of the aforementioned multiple capacitor circuits and charge pump circuit. For example, the view perpendicular to the first direction can be understood as parallel to... Figure 12 The views shown are in the second and third directions. That is, the multiple capacitor circuits and voltage regulation circuits 250 are all included in the first peripheral region 602 in the view perpendicular to the first direction, and at least partially overlap.
[0102] In addition to the capacitor circuit and voltage regulation circuit 250 mentioned above, the first peripheral area 602 can also be equipped with control circuits corresponding to all memory banks, such as command buffers, command decoders, address buffers, data input / output buffers, mode registers, etc.
[0103] Please refer to Figure 13 This illustrates a schematic diagram of the area distribution of a memory provided in another embodiment of this application.
[0104] like Figure 13 As shown, in addition to the first storage area 601, the first peripheral area 602, and the second storage area 603 arranged along the second direction, the memory 40 also includes a second peripheral area 604. The first storage area 601, the first peripheral area 602, and the second storage area 603 are located on the same side of the two opposite sides of the second peripheral area 604 along the third direction.
[0105] The second peripheral region 604 may include portions of both the first semiconductor structure 100 and the second semiconductor structure 200. For example, the first peripheral region 604 may contain the voltage regulation circuit 250 of the aforementioned plurality of capacitor circuits and charge pump circuit. Exemplarily, the view perpendicular to the first direction can be understood as parallel to... Figure 13 The views shown are in the second and third directions. That is, the multiple capacitor circuits and voltage regulation circuits 250 are all included in the second peripheral region 604 in the view perpendicular to the first direction, and at least partially overlap.
[0106] In the above embodiment, the multiple capacitor circuits and voltage regulation circuits 250 at least partially overlap in a view perpendicular to the first direction, making full use of the stacked structure of the memory 40 and helping to reduce the memory area. Furthermore, arranging the multiple capacitor circuits and voltage regulation circuits 250 in the same area also helps to save on the metal wiring connecting them.
[0107] In some embodiments, the first semiconductor structure 100 further includes a memory cell array 41, which and a plurality of capacitor circuits do not overlap in a view perpendicular to the first direction.
[0108] For example, please refer to Figure 12 The view perpendicular to the first direction can be understood as parallel to... Figure 12 The second and third views are shown. The memory cell array 41 is contained in the first memory area 601 and the second memory area 603, while the multiple capacitor circuits are contained in the first peripheral area 602. It can be seen that the memory cell array 41 and the multiple capacitor circuits do not overlap in the view perpendicular to the first direction.
[0109] For example, please refer to Figure 13 The view perpendicular to the first direction can be understood as parallel to... Figure 13 The second and third views are shown. The memory cell array 41 is contained in the first memory area 601 and the second memory area 603, while the multiple capacitor circuits are contained in the second peripheral area 604. It can be seen that the memory cell array 41 and the multiple capacitor circuits do not overlap in the view perpendicular to the first direction.
[0110] In summary, the technical solution provided by the embodiments of this application supports the flexible configuration of the charge storage capacity of different parts of the charge pump, thereby making the efficiency and current carrying capacity of the charge pump more balanced, so as to meet the design requirements of the charge pump in various scenarios.
[0111] For example, Table 1 below shows the differences in relevant parameters for three different charge pumps when the input signal and the desired high-voltage output signal are the same.
[0112] Table 1
[0113] Charge Pump 1 Charge Pump 2 Charge Pump 3 Output current 15mA 20mA 25mA effect 40％ 41％ 42％ Ripple 10mV 20mV 40mV
[0114] All three charge pumps mentioned above include the capacitor bank 101 provided in the embodiments of this application, but their specific configurations differ (e.g., the number of capacitors 102 included in the capacitor bank 101 is different). It can be seen that changes in the configuration of the charge pump will cause changes in the output current, efficiency, ripple and other index parameters of the charge pump. Therefore, adopting the technical solution provided in the embodiments of this application is beneficial for technicians to configure the charge pump according to actual needs.
[0115] In some embodiments, a storage system is also provided, which may include a controller and a memory provided in any embodiment of the present application, wherein the controller is coupled to the memory to control the memory to store data.
[0116] In some embodiments, an electronic device is also provided, the electronic device including a host and a storage system coupled to the host, the storage system including a controller and a memory provided in any embodiment of the present application, the controller being coupled to the memory to control the memory to store data.
[0117] A more detailed description of the storage system and electronic devices described here can be found in the description of the storage system and electronic devices in the above embodiments, and will not be repeated here.
[0118] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.
[0119] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the protection scope of this application.
Claims
1. A memory, characterized in that, The memory includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded to each other. The first semiconductor structure includes a metal layer and a capacitor bank in a charge pump, the capacitor bank including a plurality of capacitors; The plurality of capacitors are connected to the metal layer, and the metal layer is used to connect the plurality of capacitors in parallel; The second semiconductor structure includes the voltage regulation circuit in the charge pump.
2. The memory according to claim 1, characterized in that, The metal layer includes a first metal layer and a second metal layer; The first terminal of each of the plurality of capacitors is connected to the first metal layer, and the first metal layer is used to connect the first terminals of the plurality of capacitors to each other. The second terminal of each of the plurality of capacitors is connected to the second metal layer, and the second metal layer is used to connect the second terminals of the plurality of capacitors to each other.
3. The memory according to claim 2, characterized in that, For each of the plurality of capacitors, a first end of the capacitor is connected to one end of a first connection structure corresponding to the capacitor, and the other end of the first connection structure corresponding to the capacitor is connected to the first metal layer, wherein different capacitors among the plurality of capacitors correspond to different first connection structures.
4. The memory according to claim 2, characterized in that, The charge pump includes a first capacitor circuit, in which the number of capacitor groups is N, the first metal layer includes N first conductor structures, and the second metal layer includes N second conductor structures, where N is a positive integer. In the i-th capacitor group among the N capacitor groups, the first terminal of each of the plurality of capacitors is connected to the i-th first conductor structure among the N first conductor structures, and the second terminal of each of the plurality of capacitors is connected to the i-th second conductor structure among the N second conductor structures, where i is a positive integer less than or equal to N.
5. The memory according to claim 4, characterized in that, One end of the first capacitor circuit is connected to the voltage regulation circuit, and the second semiconductor structure includes a first clock signal source connected to the other end of the first capacitor circuit. When N equals 1, the first conductor structure is connected to the voltage regulation circuit, and the second conductor structure is connected to the first clock signal source.
6. The memory according to claim 4, characterized in that, One end of the first capacitor circuit is connected to the voltage regulation circuit, and the second semiconductor structure includes a first clock signal source connected to the other end of the first capacitor circuit. When N is an even number, the first first conductor structure among the N first conductor structures is connected to the voltage regulation circuit, the j-th second conductor structure among the N second conductor structures is connected to the (j+1)-th second conductor structure among the N second conductor structures, the k-th first conductor structure among the N first conductor structures is connected to the (k+1)-th first conductor structure among the N first conductor structures, and the N-th first conductor structure among the N first conductor structures is connected to the first clock signal source; When N is an odd number greater than 1, the first first conductor structure among the N first conductor structures is connected to the voltage regulation circuit, the j-th second conductor structure among the N second conductor structures is connected to the (j+1)-th second conductor structure among the N second conductor structures, the k-th first conductor structure among the N first conductor structures is connected to the (k+1)-th first conductor structure among the N first conductor structures, and the N-th second conductor structure among the N second conductor structures is connected to the first clock signal source; Where j is a positive odd number less than N, and k is a positive even number less than N.
7. The memory according to claim 4, characterized in that, When N is greater than 1, at least two of the N capacitor groups have a different number of capacitors.
8. The memory according to any one of claims 1 to 7, characterized in that, The first semiconductor structure includes a plurality of capacitor circuits in the charge pump, one end of which is connected to the voltage regulation circuit; The capacitor circuit includes at least one capacitor group, and when the capacitor circuit includes multiple capacitor groups, the multiple capacitor groups are connected in series.
9. The memory according to claim 8, characterized in that, The first semiconductor structure includes P capacitor circuits in the charge pump, and the voltage regulation circuit includes P+1 voltage regulation sub-circuits, which are connected in series, where P is an integer greater than 1. The input terminal of the first voltage regulation sub-circuit in the P+1 voltage regulation sub-circuit is connected to the input terminal of the charge pump, and the output terminal of the P+1 voltage regulation sub-circuit in the P+1 voltage regulation sub-circuit is connected to the output terminal of the charge pump. One end of the r-th capacitor circuit in the P capacitor circuits is connected to the output terminal of the r-th voltage regulation sub-circuit and the input terminal of the (r+1)-th voltage regulation sub-circuit in the P+1 voltage regulation sub-circuit, respectively, where r is a positive integer less than or equal to P.
10. The memory according to claim 8, characterized in that, Among the plurality of capacitor circuits, at least two capacitor circuits include a different number of capacitor groups.
11. The memory according to claim 8, characterized in that, The first capacitor group includes a different number of capacitors than the second capacitor group. The first capacitor group and the second capacitor group are capacitor groups in different capacitor circuits among the plurality of capacitor circuits.
12. The memory according to claim 8, characterized in that, The first semiconductor structure and the second semiconductor structure are stacked along a first direction, and the plurality of capacitor circuits and the voltage regulation circuit at least partially overlap in a view perpendicular to the first direction.
13. The memory according to claim 12, characterized in that, The first semiconductor structure further includes a memory cell array, and the memory cell array and the plurality of capacitor circuits do not overlap in a view perpendicular to the first direction.
14. The memory according to claim 13, characterized in that, The memory cell array includes multiple memory cells, each memory cell including a capacitor structure and a transistor, the capacitor structure and the transistor being connected.
15. A storage system, characterized in that, The storage system includes a controller and a memory as described in any one of claims 1 to 14, the controller being coupled to the memory to control the memory to store data.
16. An electronic device, characterized in that, The electronic device includes a host and a storage system coupled to the host, the storage system including a controller and a memory as claimed in any one of claims 1 to 14, the controller being coupled to the memory to control the memory to store data.