Control method, control device, storage system, and electronic device

Abstract

The application provides a control method, a control device, a storage system and an electronic device, and relates to the technical field of semiconductors. The control method is used for reading an output of a storage circuit, the storage circuit comprises a first storage array, and the control method comprises the following steps: controlling a first output end of the first storage array to establish a first output signal in a first time period; and performing first conversion control on the first output signal in a second time period. The first time period comprises a first sub time period and a second sub time period. The step of controlling the first output end of the first storage array to establish the first output signal in the first time period comprises the following steps: controlling initial establishment of a working condition of the first storage array in the first sub time period; and controlling stable establishment of the working condition of the first storage array in the second sub time period. The working condition of the first storage array is used for generating the first output signal at the first output end. The scheme can improve the reading rate of the storage circuit while reducing the hardware cost requirement.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a control method, control device, storage system, and electronic device. Background Technology

[0002] Memory is a common component in electronic devices, and its performance is closely related to the performance of the electronic device. For example, the storage capacity or output rate of memory affects the data storage capability or data retrieval efficiency of the electronic device. Therefore, the demand for storage capacity or output rate of memory is increasing. However, as storage capacity increases, the improvement in output rate leads to greater hardware cost requirements. Summary of the Invention

[0003] This application provides a control method, control device, storage system, and electronic device that can improve the read speed of the storage circuit while reducing hardware cost requirements.

[0004] In a first aspect, a control method is provided for reading the output of a storage circuit, the storage circuit including a first storage array, the control method including: controlling a first output terminal of the first storage array to establish a first output signal in a first time period; and performing a first conversion control on the first output signal in a second time period; wherein the first time period includes a first sub-time period and a second sub-time period, controlling the first output terminal of the first storage array to establish the first output signal in the first time period includes: controlling the initial establishment of the operating conditions of the first storage array in the first sub-time period; and controlling the stable establishment of the operating conditions of the first storage array in the second sub-time period, the operating conditions of the first storage array being used to generate the first output signal at the first output terminal.

[0005] The solution provided in this application's embodiments divides the establishment process of the output signal of the storage circuit into time-segmented processes, providing feasibility for parallel execution of the establishment processes of output signals of different storage arrays, thereby improving the overall data output rate of the storage circuit. For example, in the first sub-time period of the first time period, preparation work is carried out in advance for the establishment of the working conditions of the first storage array, so that the working conditions can be initially established. This initial establishment has low requirements for the stability of the working conditions and can be achieved using simple hardware resources (such as switching circuits). Then, the second sub-time period is used to stabilize the working conditions based on the initial establishment. The hardware resources in the readout circuit used for establishing the output signal are used to stabilize the working conditions in the second sub-time period. In the first sub-time period, these resources can be reused by other storage arrays to stabilize the working conditions. In this way, the hardware resource requirements for establishing the output signal in the readout circuit can be reduced, achieving high-speed data output with lower hardware resource overhead.

[0006] In some implementations of the first aspect, the operating conditions include the voltage of the first output terminal. The initial establishment of the operating conditions of the first memory array is controlled in the first sub-time period, which includes: providing a first voltage to the first output terminal in the first sub-time period, the first voltage being used to generate an initial voltage at the first output terminal. The stable establishment of the operating conditions of the first memory array is controlled in the second sub-time period, which includes: controlling the initial voltage of the first output terminal to stabilize to a second voltage in the second sub-time period, the second voltage being used to generate a first output signal at the first output terminal.

[0007] In this implementation, the operating conditions are established by controlling the voltage at the output terminal of the storage array; for example, the operating conditions include the voltage at the first output terminal, which is simple and easy to implement.

[0008] In some implementations of the first aspect, controlling the initial voltage of the first output terminal to stabilize to a second voltage in the second sub-time period includes: controlling the initial voltage of the first output terminal to stabilize to a second voltage based on a reference voltage, wherein the absolute value of the difference between the first voltage and the reference voltage is less than or equal to a threshold.

[0009] In this implementation, the magnitude of the first voltage can be determined based on a reference voltage. For example, the absolute value of the difference between the first voltage and the reference voltage is less than or equal to a threshold. For instance, the first voltage and the reference voltage can be the same or differ only slightly. Thus, when charging the first output terminal using the first voltage, the voltage of the first output terminal can be pre-charged to a target voltage closer to the reference voltage. Then, when establishing a stable state for the first output terminal using the target voltage and the reference voltage, the voltage of the first output terminal can be stabilized in a shorter time. This application does not limit the magnitude of the threshold; it can be set as needed. Setting the first voltage as the reference voltage can reduce the number of signal sources in the device containing the storage circuit.

[0010] In some implementations of the first aspect, the method further includes: performing a second conversion control on the output of the first conversion of the first output signal during a third time period.

[0011] In this implementation, the result of the first conversion can be controlled to undergo a second conversion for output. For example, the second conversion can convert the analog signal into a digital signal to facilitate the subsequent circuitry to process the output data in the digital domain.

[0012] In some implementations of the first aspect, the storage circuit further includes a second storage array, and the method further includes: controlling a second output terminal of the second storage array to establish a second output signal in a fourth time period, including: controlling the initial establishment of the operating conditions of the second storage array in a first sub-time period of the fourth time period; controlling the stable establishment of the operating conditions of the second storage array in a second sub-time period of the fourth time period, the operating conditions of the second storage array being used to generate a second output signal at the second output terminal, wherein the second sub-time period of the fourth time period and the first sub-time period of the first time period at least partially overlap.

[0013] In this implementation, since the second sub-time period of the fourth time period and the first sub-time period of the first time period overlap at least partially, the readout circuit can simultaneously serve the first storage array and the second storage array during the overlapping time period. For example, the first storage array and the second storage array can reuse the resources of the readout circuit, and when the first storage array uses part of the resources of the circuit in the readout circuit, the second storage array uses another part of the resources of the circuit in the circuit. In this way, a pipeline can be established, improving the resource utilization of the readout circuit and increasing the data output rate of the storage circuit.

[0014] In some implementations of the first aspect, the control of performing a first conversion on the second output signal is also included: within a first sub-time period of the first time period.

[0015] In this implementation, preparations are made in advance for the establishment of the working conditions of the first storage array during the first sub-time period of the first time period. At the same time, during the first sub-time period, the second output signal of the second output terminal of the second storage array is controlled by a first conversion. That is, during the first sub-time period, the readout circuit can serve both the first and second storage arrays simultaneously. For example, when the first storage array uses the resources of the establishment circuit in the readout circuit, the second storage array uses the resources of the first conversion circuit, thereby achieving high-speed data output.

[0016] In some implementations of the first aspect, the method further includes: controlling the second output terminal to establish a third output signal in the fifth time period, including: controlling the initial establishment of the operating conditions of the second storage array in the first sub-time period of the fifth time period; controlling the stable establishment of the operating conditions of the second storage array in the second sub-time period of the fifth time period, wherein the operating conditions of the second storage array are also used to generate a third output signal at the second output terminal, wherein the first sub-time period of the fifth time period and the second sub-time period of the first time period at least partially overlap.

[0017] In this implementation, since the first sub-time period of the fifth time period and the second sub-time period of the first time period overlap at least partially, the readout circuit can simultaneously serve the first storage array and the second storage array during the overlapping time period. For example, the first storage array and the second storage array can reuse the resources of the readout circuit, and when the first storage array uses part of the resources of the readout circuit's establishment circuit, the second storage array uses another part of the resources of the establishment circuit. In this way, a pipeline can be established, improving the resource utilization of the readout circuit and increasing the data output rate of the storage circuit.

[0018] In some implementations of the first aspect, the first sub-time period of the fifth time period overlaps at least partially with the second time period.

[0019] In this implementation, preparations are made in advance for establishing the working conditions of the second storage array during the first sub-time period of the fifth time period, and the first conversion control is performed on the first output signal during the second time period. Since the first sub-time period of the fifth time period and the second time period overlap at least partially, the readout circuit can serve the first storage array and the second storage array simultaneously during the overlapping time period. For example, when the first storage array uses the resources of the first conversion circuit of the readout circuit, the second storage array uses the resources of the establishment circuit of the readout circuit, thereby achieving high-speed data output.

[0020] In some implementations of the first aspect, the method further includes: a third time period in which the output of the first conversion of the first output signal is second converted at least partially overlapping with a second sub-time period of the fifth time period.

[0021] In this implementation, since the second sub-time period of the third time period and the fifth time period overlap at least partially, the readout circuit can simultaneously serve the first storage array and the second storage array during the overlapping time period. For example, the first storage array and the second storage array can reuse the resources of the readout circuit, and when the first storage array uses the resources of the second conversion circuit of the readout circuit, the second storage array uses the resources of the establishment circuit. In this way, a pipeline can be established, improving the resource utilization of the readout circuit and increasing the data output rate of the storage circuit.

[0022] In some implementations of the first aspect, the method further includes: controlling voltage mismatch adjustment during the establishment process of the first output signal in a second sub-time period of the first time period.

[0023] In this implementation, the voltage mismatch adjustment of the first output signal is controlled during the second sub-time period to reduce the duration of the second sub-time period, which further reduces the output duration of the storage circuit, thereby further improving the data output rate of the storage circuit.

[0024] In some implementations of the first aspect, the first sub-time period is longer than the second sub-time period.

[0025] In this implementation, since the first sub-time period is longer than the second sub-time period, a longer pre-establishment sub-stage of one memory array can be utilized to provide parallel possibilities for the establishment sub-stages and / or at least one conversion stage of other memory arrays, further improving the output rate of the memory circuit. Furthermore, the pre-establishment resources in the first sub-time period are less than the establishment resources in the second sub-time period; increasing the duration of the first sub-time period within a cycle can further reduce power consumption. Therefore, it is beneficial to save resources consumed in the overall output signal establishment process and reduce power consumption.

[0026] In a second aspect, a control device is provided, comprising: an interface circuit and a processing circuit, wherein the interface circuit is used to signal connect to a storage circuit, and the processing circuit is used to execute any of the control methods of the first aspect.

[0027] Thirdly, a storage system is provided, comprising: a storage circuit; and a control device for executing any of the control methods of the first aspect.

[0028] In some implementations of the third aspect, the first current signal is used to read out the data stored in the storage circuit or to read out the calculation results.

[0029] Fourthly, an electronic device is provided, comprising: a storage system according to any one of the third aspects.

[0030] Fifthly, a computer program product is provided, the computer program product including instructions that, when executed by a processor, cause any of the control methods of the first aspect above to be executed.

[0031] In a sixth aspect, a computer-readable medium is provided that stores instructions which, when executed by a processor, cause any of the control methods of the first aspect above to be performed. Attached Figure Description

[0032] Figure 1 A schematic diagram of a storage system according to an exemplary embodiment of this application is shown.

[0033] Figure 2 This illustration shows a timing diagram for controlling the output of a storage circuit according to an embodiment of this application.

[0034] Figure 3 This illustration shows a timing diagram for controlling the output of a storage circuit according to an embodiment of this application.

[0035] Figure 4 A schematic diagram of a control method according to an exemplary embodiment of this application is shown.

[0036] Figure 5 This illustration shows a timing diagram for controlling the output of a storage circuit according to an embodiment of this application.

[0037] Figure 6 This illustration shows a timing diagram for controlling the output of a storage circuit according to an embodiment of this application.

[0038] Figure 7 A schematic diagram of a storage system according to an exemplary embodiment of this application is shown.

[0039] Figure 8 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0040] Figure 9 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0042] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0043] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0044] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects can be directly connected through a medium (e.g., wires, wiring, etc.), or indirectly connected through other components, or can be an internal connection. "Coupling" includes signal connection between objects, which can be achieved directly through a medium (e.g., wires, wiring, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components. Signaling in the embodiments of this application can also be referred to as a command.

[0045] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0046] Please refer to Figure 1 This is a schematic diagram of a storage system provided in an embodiment of this application. Figure 1 As shown, the storage system 100 may include a storage circuit 110, a control device 120, and a readout circuit 130. The control device 120 is connected to the storage circuit 110 and the readout circuit 130 to control one or more operations of the storage circuit 110, such as data writing, reading, erasing, and calculation. The storage circuit 110 may include multiple storage arrays, thereby increasing the storage capacity of the storage circuit. The readout circuit 130 is coupled to the output terminal of the storage circuit 110, receives the output signal S of the storage circuit 110, converts it into output data D, and provides it to subsequent circuits (e.g., processing circuits) for processing. This application does not limit the processing content of the subsequent circuits; different processing operations may be performed in different application systems.

[0047] The output of the control device 120 to the storage circuit 110 (including reading out stored data or reading out calculation results) may include the following control processes: establishing an output signal and performing at least one conversion on the output signal; the at least one conversion may include one or more of the following, such as signal type conversion, signal magnitude conversion, current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the readout circuit 130 may perform a first conversion and a second conversion on the output signal S; the first conversion includes current-to-voltage conversion, for example, the output signal S of the storage circuit 110 includes a current signal, and the readout circuit 130 may convert the current signal into a voltage signal; the second conversion includes analog-to-digital conversion, for example, the readout circuit 130 may convert the output of the first conversion into a digital signal. During the first conversion and / or the second conversion, the output signal may be amplified, or the output signal may be amplified after the first conversion or the second conversion; the readout circuit 130, which has the function of amplifying the output signal, may also be called an inductive amplifier circuit.

[0048] The output control of the storage circuit by the control device 120 can be reflected through control timing. The following description uses output control including the establishment of the output signal, a first conversion, and a second conversion as examples. In some embodiments of this application, the first conversion can also be referred to as sampling, and the second conversion can also be referred to as decision-making. For example, sampling can be used to sample the current signal output by the storage circuit as a voltage signal; decision-making can be used to convert the waveform parameters of an analog signal (e.g., a voltage signal) into a digital signal, such as converting the amplitude, pulse width, or area of ​​the analog signal into a digital signal through decision-making. This application does not limit the accuracy of the conversion or decision-making; for example, it can include 1-bit or multi-bit conversion accuracy. In the following control timing, conversion 1 is used to represent the first conversion, and conversion 2 is used to represent the second conversion.

[0049] Please refer to Figure 2 This is a timing diagram for controlling the output of a storage circuit, provided in an embodiment of this application. For example... Figure 2 As shown, the horizontal axis represents time, and a single horizontal row represents the control timing of one output. A cycle can include the establishment of the memory array's output signal and one conversion 1. Conversion 2 can occur simultaneously with the establishment of another memory array in the next cycle; this increases the data output rate. For example, as... Figure 2As shown, T represents the period, and the suffix to T is used to distinguish different periods. Within period T-1, the establishment of the output signal of storage array A1 and conversion 1 of that output signal are performed. Within period T-2, the output signal of storage array A1 has completed conversion 1. At this time, the readout circuit can serve the establishment and conversion 1 of the output signal of storage array A2, and simultaneously serve the conversion 2 of the output signal of storage array A1. This improves the resource utilization of the readout circuit and increases the output rate of the storage circuit, such as the data output rate or computation rate. Similarly, within period T-3, the output signal of storage array A2 has completed conversion 1. At this time, the readout circuit can continue to serve the establishment and conversion 1 of the output signal of storage array A1, and simultaneously serve the conversion 2 of storage array A2. And so on, without further elaboration.

[0050] In some embodiments of this application, hardware resources for establishing the output signal can be added to the readout circuit section. This allows one memory array to establish its signal during the output signal establishment process of another memory array using the added hardware resources, improving the parallelism of signal establishment between memory arrays. This increases the amount of data that the memory circuit can output within the same time frame, thereby increasing the data output rate of the memory circuit. For example, please refer to... Figure 3 This is a control timing diagram for the output of another storage circuit provided in an embodiment of this application. For example... Figure 3 As shown, the horizontal direction represents time, and each horizontal row represents the control timing of one output. Storage arrays A1 and A2 can each utilize independent hardware resources to establish their output signals. After conversion 1 of the output signal of storage array A1 is completed, the establishment of the output signal of storage array A2 can begin directly without considering the establishment of the output signal of storage array A2, allowing the establishment timing of the output signals of storage arrays A1 and A2 to overlap. Similarly, after conversion 1 of the output signal of storage array A2 is completed, the establishment of the output signal of storage array A1 can begin directly without considering the establishment of the output signal of storage array A2, allowing the establishment timing of the output signals of storage arrays A1 and A2 to overlap. For example, within periods T-1, T-2, and T-3, the establishment timing of the output signals of storage arrays A1 and A2 overlaps. (Relative to...) Figure 2 The control timing shown allows for an increase in the amount of data output from the storage circuit within the same time frame, meaning the data readout rate of the storage circuit can be improved. However, this increases the hardware resource requirements of the readout circuit and enlarges the chip area.

[0051] This application provides a control method that, by segmenting the output signal establishment process, enables parallel processing of the output signal establishment processes of different memory arrays. This facilitates improving the overall data output rate of the memory circuit by increasing the parallelism of the output signal establishment processes of different memory arrays. For example, the control method provided in this application is used to control the output of a memory circuit, which includes multiple memory arrays, mainly including... Figure 4 The following steps are shown:

[0052] S410: Control the first output terminal of the first storage array to establish the first output signal in the first time period.

[0053] S420: Perform first conversion control on the first output signal during the second time period.

[0054] The first memory array can be any memory array of the memory circuit. Please refer to the reference. Figure 5 This is a control timing diagram for a single output of a storage array provided in an embodiment of this application. For example... Figure 5 As shown, the horizontal direction represents time, and a single horizontal row represents the control timing of one output of the memory array. In this embodiment, T1 represents a first time period, and T2 represents a second time period. The first time period T1 includes a first sub-time period T11 and a second sub-time period T12. In S410, the initial establishment of the operating conditions of the first memory array is controlled in the first sub-time period T11; the stable establishment of the operating conditions of the first memory array is controlled in the second sub-time period T12, and these operating conditions are used to generate a first output signal at the first output terminal.

[0055] The solution provided in this application's embodiments divides the establishment process of the output signal of the storage circuit into time-segmented processes, providing feasibility for parallel execution of the establishment processes of the output signals of different storage arrays, thereby improving the overall data output rate of the storage circuit. For example, in the first sub-time period of the first time period, preparation work is carried out in advance for the establishment of the working conditions of the first storage array, so that the working conditions can be initially established. This initial establishment has low requirements for the stability of the working conditions and can be achieved using simple hardware resources (such as switching circuits). Then, the second sub-time period is used to stabilize the working conditions based on the initial establishment. The hardware resources in the readout circuit used for establishing the output signal are used to stabilize the working conditions in the second sub-time period. In the first sub-time period, these resources can be reused by other storage arrays to stabilize the working conditions. Thus, compared with the above... Figure 3 The control timing shown reduces the hardware resource requirements for establishing the output signal in the readout circuit, achieving high-speed data output with lower hardware resource overhead. Compared to the above... Figure 2The control timing shown can significantly improve the data output rate of the readout circuit.

[0056] The initial setup process of the above operating conditions can be called the pre-setup sub-stage of the output signal, and the stabilization process of the above operating conditions can be called the setup sub-stage of the output signal. Within the pre-setup sub-stage of one memory array, another memory array can utilize the hardware resources of its readout circuit to stabilize its operating conditions. Figure 3 The control timing shown can reduce the hardware resource requirements for establishing the output signal in the readout circuit, thereby achieving high-speed data output with lower hardware resource overhead.

[0057] For example, please refer to Figure 6 This is a control timing diagram for the output of another storage circuit provided in an embodiment of this application. For example... Figure 6 As shown, the horizontal direction represents time, and a single horizontal row represents the control timing of one output. A period can include a pre-establishment sub-stage, an establishment sub-stage, and a conversion 1 for the output signal of one memory array. During the pre-establishment sub-stage of one memory array, another memory array can perform its establishment sub-stage. Thus, the hardware resources required for establishing the output signal, which have high requirements for operating voltage stability, can still be used in one instance. By simplifying the pre-establishment resources, the hardware resource requirements for the readout circuit are reduced. Furthermore, within the same time frame, this control timing can achieve a higher data output rate, achieving a balance between hardware resources and output rate. For example, within period T-1, memory array A1 is controlled to pre-establish its output signal, and then memory array A1 is controlled to establish its output signal. At this time, the resources used for pre-establishment can be released to serve the pre-establishment of the output signal of memory array A2. The pre-establishment of the output signal of memory array A2 does not affect the establishment of the output signal of memory array A1, and the establishment of the output signal of memory array A1 can be performed in parallel. After the output signal of storage array A1 is established, conversion 1 of the output signal can be performed. After conversion 1 of the output signal of storage array A1 is completed, the pre-establishment process of the output signal of storage array A1 can continue. The other cycles T-2 and T-3 are similar and will not be described in detail.

[0058] Please refer to Table 1, which shows the examples of the methods used. Figure 2 The timing sequence shown is 1. Figure 3 The timing sequence shown is 2 and Figure 6Table 1 shows a comparison of the hardware resource overhead of the readout circuit and the data output rate of the storage circuit in timing sequence 3. Here, "Pre-establishment" represents the hardware overhead of the pre-establishment sub-stage of the output signal; "Establishment" represents the hardware overhead of the establishment sub-stage of the output signal; "Conversion 1" represents the hardware overhead of the conversion 1 stage of the output signal; "Conversion 2" represents the hardware overhead of the conversion 2 stage of the output signal; and "Readout Circuit" represents the total hardware overhead of the relevant parts of the readout circuit. The resources in Table 1 are relative proportions. For example, the "Establishment" resource overhead of timing sequence 1 is 1, the "Establishment" resource overhead of timing sequence 2 is 2, and the "Establishment" resource overhead of timing sequence 3 is 1. As can be seen from Table 1, the control method corresponding to timing sequence 3 can reduce the hardware resource requirements of the readout circuit and achieve a higher data output rate.

[0059] Table 1

[0060] Pre-establishment Establish Conversion 1 Conversion 2 Readout circuit Output rate Timing 1 0 1 1 1 1 1 Time series 2 0 2 1 1 1.6 2 Time series 3 1 1 1 1 1.1 2

[0061] The operating conditions are used to establish the operating state of the memory cells within the first memory array. The operating state of a memory cell can include a computation state or a read state. In the computation state, under the influence of an input signal, the memory cell converts the input signal into an output signal based on the stored weight data. In the read state, under the influence of an input signal (or a drive signal), the memory cell outputs the stored data as an output signal. Taking a transistor-type semiconductor device as an example, the conduction capability of the transistor varies depending on the stored data. In the computation state, when an input signal acts on the transistor, a current signal is output at the transistor's output terminal under the influence of the conduction capability corresponding to the stored weight data. In the read state, when an input signal acts on the transistor, it drives the transistor to output a current signal at its output terminal reflecting its conduction capability. The output terminal of the transistor includes, for example, a drain or a source, and the input signal can act on the source, drain, or gate of the transistor. For example, in NAND flash memory, an input signal can act on the transistor of a memory cell through a switching transistor. This switching transistor can control the input signals of a series of transistors connected to it to act on the selected memory cell. The selection of a memory cell is controlled by word lines connected to the transistor of that memory cell.

[0062] The operating conditions can be achieved by establishing the operating voltage. This application does not limit the location of the operating voltage. For example, the operating voltage can be established at the output terminal. Establishing the operating voltage at the output terminal can simplify the complexity of the peripheral circuit of the storage circuit and the control logic of the operating state of the storage circuit. By controlling the read circuit, the control of the output timing can be simplified.

[0063] In some embodiments of this application, operating conditions are established by controlling the voltage at the output terminal of the memory array; for example, the operating conditions include the voltage at a first output terminal. The initial establishment of the operating conditions of the first memory array in the first sub-time period includes: providing a first voltage to the first output terminal in the first sub-time period, the first voltage being used to generate an initial voltage at the first output terminal. The stable establishment of the operating conditions of the first memory array in the second sub-time period includes: stabilizing the initial voltage at the first output terminal to a second voltage in the second sub-time period, the second voltage being used to generate a first output signal at the first output terminal. The first output terminal can be any output terminal of the first memory array.

[0064] In some embodiments of this application, the initial voltage of the first output terminal can be stabilized to a second voltage based on a reference voltage. For example, a clamping circuit is provided in the readout circuit, which is connected to the output terminal of the memory array to couple with the reference voltage, clamping the voltage at the output terminal to near the reference voltage based on the reference voltage.

[0065] In some embodiments of this application, the magnitude of the first voltage can be determined based on a reference voltage. For example, the absolute value of the difference between the first voltage and the reference voltage is less than or equal to a threshold. For instance, the first voltage and the reference voltage can be the same or differ only slightly. Thus, when charging the first output terminal using the first voltage, the voltage of the first output terminal can be pre-charged to a target voltage closer to the reference voltage. Then, when establishing a stable state for the first output terminal using the target voltage and the reference voltage, the voltage of the first output terminal can be stabilized in a shorter time. This application does not limit the magnitude of the threshold; it can be set as needed. Setting the first voltage as the reference voltage can reduce the number of signal sources in the device containing the storage circuit.

[0066] In some embodiments of this application, the memory array may include one or more output terminals, and the first output terminal may be any output terminal of the first memory array. The output signal of the output terminal of the memory array may include a current signal. The current direction of the current signal may be from the memory circuit or into the memory circuit; this application does not limit this.

[0067] The data output by the storage circuit in this application embodiment may include the data stored in the storage circuit, or it may include the calculation results of the storage circuit based on the stored weight data.

[0068] The initial establishment of working conditions can also be understood as the preparation stage for the establishment of the first output signal. During this stage (i.e., the first sub-time period), the first output signal cannot accurately reflect the output of the storage array and is not used for the first conversion. That is, the current output signal is not sampled, but preparations are being made for the establishment of a stable output signal.

[0069] The establishment of stable operating conditions can be understood as the stable establishment stage of the first output signal. By establishing a stable voltage at the first output terminal, the first output signal (e.g., the first output current) at the first output terminal can be stabilized.

[0070] For example, the second sub-time period can also be called the establishment stabilization phase or the establishment adjustment phase. The first output signal in this phase (i.e., the second sub-time period) can accurately reflect the output of the storage array and can be used for the first conversion, that is, the current output signal can be sampled.

[0071] In some embodiments of this application, the result of the first transformation can also be controlled to undergo a second transformation before being output. For example, please refer to [link to relevant documentation]. Figure 5 The above control method may further include: performing a second conversion control on the output of the first conversion of the first output signal during a third time period T3. The first conversion and the second conversion can be described with reference to the above embodiments. For example, the first conversion can convert a current signal into a voltage signal, and the result of the first conversion may include, for example, an analog voltage signal. The second conversion can convert the analog signal into a digital signal to facilitate the subsequent circuitry's processing of the output data in the digital domain. Exemplarily, the second conversion process can also be referred to as a decision-making process.

[0072] In some embodiments of this application, the storage circuit further includes a second storage array. The first storage array and the second storage array can share the hardware resources of the readout circuit, such as sharing the hardware resources for pre-establishment, establishment, conversion 1, and conversion 2. This can significantly reduce the hardware overhead of the readout circuit, thereby reducing the chip area.

[0073] For example, please refer to Figure 7 This is a schematic diagram of a storage system provided in an embodiment of this application. Figure 7As shown, the storage system 700 includes a storage circuit 710, a readout circuit 720, and a control device 730 (or control circuit). The storage circuit 710 may include multiple storage arrays, such as storage array A1 and storage array A2. Each storage array may include multiple output terminals; taking storage array A1 / A2 as an example, it includes output terminals O1, O2, O3, O4, etc. The readout circuit 720 may include a setup circuit 721, a first conversion circuit 722, and a second conversion circuit 723. The setup circuit 721 can be used to stably establish the output signal at the output terminal. For example, it may include a clamping circuit coupled to a reference voltage Vref, clamping the voltage at the output terminal based on the reference voltage Vref. This application does not limit the implementation of the clamping circuit; for example, it may include a feedback loop of an operational amplifier and a transistor. The setup circuit 721 may also include a pre-establishment section, for example, coupled to a first voltage V, which may be the same as or different from the reference voltage Vref, and operates on the setup circuit in a time-division multiplexing manner. The control device 710 can control the output terminal to be coupled to a first voltage V during the pre-establishment sub-stage, and use the first voltage V to pre-charge the output terminal; during the stable establishment sub-stage, the control clamping circuit and the first conversion circuit act on the output terminal to stabilize the voltage of the output terminal, establish the output signal, and control the first conversion circuit 722 to perform a first conversion (e.g., sampling) on ​​the output signal; and then the control device 723 can control the second conversion circuit 723 to perform a second conversion (e.g., analog-to-digital conversion) on the output of the first conversion.

[0074] Storage arrays A1 and A2 can share the readout circuit. The control device 730 can control the first voltage V1 to be applied to storage arrays A1 and A2 in a time-division manner, for example, through switch control. It is evident that the hardware resource overhead for pre-establishment is far less than that for stable establishment. For the same storage array, different output terminals can be configured with independent pre-establishment and stable establishment sub-circuits. Output terminals (e.g., output terminals with the same number) of different storage arrays (e.g., storage arrays A1 and A2) can share the pre-establishment and stable establishment sub-circuits. Optionally, for the same storage array, different output terminals can be configured with independent first conversion circuits. Output terminals (e.g., storage arrays A1 and A2) of different storage arrays (e.g., storage arrays A1 and A2) (e.g., output terminals with the same number) can share the first conversion circuit. Optionally, for the same storage array, different output terminals can be configured with independent second conversion circuits. Output terminals (e.g., storage arrays A1 and A2) of different storage arrays (e.g., storage arrays A1 and A2) (e.g., output terminals with the same number) can share the second conversion circuit. Furthermore, fewer second conversion circuits can be configured for the same memory array, allowing the second conversion circuits to be shared by different output terminals within the memory array. For example, output terminals O1 and O2 can share the same second conversion circuit. The control device 730 is connected to the memory circuit 710 and can use the control method provided in this embodiment to control the output timing of the memory circuit 710. For example, the control timing of the control device 730 for memory cell array A1 and memory cell array A2 can be as follows: Figure 6 As shown.

[0075] In some embodiments of this application, the storage circuit may further include a second storage array, for example, the first storage array is storage array A1, and the second storage array is storage array A2. The above control method may include: controlling the second output terminal of the second storage array to establish a second output signal in a fourth time period; this process may include: controlling the initial establishment of the operating conditions of the second storage array in a first sub-time period of the fourth time period; controlling the stable establishment of the operating conditions of the second storage array in a second sub-time period of the fourth time period, the operating conditions of the second storage array being used to generate the second output signal at the second output terminal, wherein the second sub-time period of the fourth time period and the first sub-time period of the first time period at least partially overlap. For example, please refer to... Figure 6 And taking the first time period as Figure 6 Taking the time periods for A1 pre-establishment and A1 establishment shown in row 5 as an example, the first sub-time period of the first time period is the time period for A1 pre-establishment, and the second sub-time period of the first time period is the time period for A1 establishment. The fourth time period can be... Figure 6The fourth row shows the time periods for A2 pre-establishment and A2 establishment. The first sub-time period of the fourth time period is the time period for A2 pre-establishment, and the second sub-time period of the fourth time period is the time period for A2 establishment. The time periods for A2 establishment and A1 pre-establishment overlap.

[0076] In some embodiments of this application, the above control method may further include: controlling the second output signal to undergo a first conversion during a first sub-time period of the first time period. For example, please refer to... Figure 6 And taking the first time period as Figure 6 Taking the A1 pre-establishment and A1 establishment time period shown in row 5 as an example, within the first sub-time period of the first time period, the second output signal is controlled by a first conversion.

[0077] In some embodiments of this application, the above control method may further include: controlling the second output terminal of the second storage array to establish a third output signal in a fifth time period, including: controlling the initial establishment of the operating conditions of the second storage array in a first sub-time period of the fifth time period; controlling the stable establishment of the operating conditions of the second storage array in a second sub-time period of the fifth time period, wherein the operating conditions of the second storage array are further used to generate a third output signal at the second output terminal, wherein the first sub-time period of the fifth time period and the second sub-time period of the first time period at least partially overlap. For example, please refer to... Figure 6 The first time period is still considered as Figure 6 Taking the time period of A1 pre-establishment and A1 establishment shown in the 5th row as an example, the fifth time period can be... Figure 6 The A2 pre-establishment and A2 establishment time periods are described in line 6. The first sub-time period of the fifth time period is the A2 pre-establishment time period, and the second sub-time period of the fifth time period is the A2 establishment time period; the A2 pre-establishment time period can at least partially overlap with the A1 establishment time period.

[0078] In some embodiments of this application, the first sub-time period of the fifth time period at least partially overlaps with the second time period. For example, please refer to... Figure 6 The first time period is still considered as Figure 6 Taking the time period of A1 pre-establishment and A1 establishment shown in the 5th row as an example, the fifth time period can be... Figure 6 The time periods for A2 pre-establishment and A2 establishment are shown in line 6. The first sub-time period of the fifth time period is the time period for A2 pre-establishment, and the second sub-time period of the fifth time period is the time period for A2 establishment; the second time period can be the time period of A1 transformation 1 shown in line 5. Among them, the time period for A2 pre-establishment can at least partially overlap with the time period of A1 transformation 1.

[0079] In some embodiments of this application, the above control method further includes: a third time period during which the output of the first conversion of the first output signal undergoes a second conversion at least partially overlaps with a second sub-time period of the fifth time period. For example, please refer to... Figure 6 The first time period is still considered as Figure 6 Taking the time periods for A1 pre-establishment and A1 establishment shown in line 5 as an example, the third time period can be... Figure 6 The fifth time segment is shown in row 5, where A1 is converted to segment 2. The fifth time segment can be... Figure 6 The 6th row shows the time periods for A2 pre-establishment and A2 establishment. The first sub-time period of the fifth time period is the time period for A2 pre-establishment, and the second sub-time period of the fifth time period is the time period for A2 establishment; wherein, the time period for A1 to transform into 2 and the time period for A2 establishment overlap at least partially.

[0080] Different storage arrays in the storage circuit, such as storage array A1 and storage array A2, can reuse the resources of the read circuit. While storage array A1 uses some of its resources, storage array A2 can use other resources. This establishes a pipeline, improves the resource utilization of the read circuit, and increases the data output rate of the storage circuit. Establishing different sub-time period allocation ratios within a time period can achieve one or more time period multiplexing methods as described in the above embodiments.

[0081] In some embodiments of this application, the pre-establishment sub-circuit of the establishment circuit 721 may include a switching circuit, and the connection between the output terminal of the storage array A1 or the storage array A2 and the first voltage V1 is selected by the switching circuit in a time-division manner.

[0082] For example, in the pre-establishment sub-stage of the output signal at the output terminal O1 of storage array A1, the transmission path between the first voltage V1 and the output terminal O1 can be opened by the switching circuit, providing the first voltage V1 to the output terminal O1, so that the output terminal O1 establishes an initial operating voltage. At this time, the transmission path between the first voltage V1 and the output terminal O1 of storage array A2 is opened by the switching circuit; and during this period, the establishment sub-stage of the output signal at the output terminal O1 of storage array A2 can be performed in parallel. At this time, the connection between the output terminal O1 of storage array A2 and the clamping circuit of the establishment circuit 721 can be opened, and after the stable establishment of the output signal is completed, the first conversion circuit 722 is enabled.

[0083] During the establishment sub-stage of output signal 1 at output terminal O1 of storage array A2, the pre-establishment sub-stage of output signal 1 at output terminal O1 of storage array A1 in the next cycle can be performed in parallel. The switching circuit disconnects the transmission path between the first voltage V1 and output terminal O1 of storage array A2, and simultaneously connects the transmission path between the first voltage V1 and output terminal O1 of storage array A1. The output control of other output terminals is similar to that of output terminal O1, and will not be described in detail here.

[0084] The pre-establishment sub-circuit in the establishment circuit does not require a stable output voltage and can adopt a simpler structural design, such as a switching circuit. This can reduce the overall hardware cost of the readout circuit. Furthermore, the solution of this application embodiment can improve the data output rate of the storage circuit while reducing hardware costs.

[0085] like Figure 6 The timing diagram shown is only an example. In actual scenarios, there may be other different timing diagrams. For example, the first sub-time period and the second sub-time period can be changed to achieve different time reuse methods. This application embodiment will not elaborate on these in detail.

[0086] The control method provided in this application embodiment can provide feasibility for parallelization between the establishment processes of multiple storage arrays, but in actual use, parallel or non-parallel methods can be adopted depending on the scenario.

[0087] In some embodiments of this application, the first sub-time period of any setup phase is longer than the second sub-time period. This allows for the utilization of a longer pre-setup sub-phase of one memory array to provide parallel possibilities for setup sub-phases and / or at least one conversion phase of other memory arrays, further improving the output rate of the memory circuitry. Furthermore, since the pre-setup resources within the first sub-time period are less than the setup resources within the second sub-time period, increasing the proportion of the first sub-time period within a cycle can further reduce power consumption. Therefore, it is beneficial to save resources consumed in the overall output signal setup process and reduce power consumption.

[0088] During the stabilization process of operating conditions, voltage mismatch may occur in the corresponding readout circuit section. For example, the clamping circuit itself may have voltage mismatch. Optionally, in some embodiments, voltage mismatch can be adjusted during the stabilization phase of operating conditions, thereby further shortening the duration of the second sub-time period. For example, the above control method further includes controlling voltage mismatch adjustment during the establishment process of the first output signal within the second sub-time period of the first time period. In the embodiments of this application, controlling voltage mismatch adjustment during the establishment of the first output signal within the second sub-time period reduces the duration of the second sub-time period, further reducing the output duration of the storage circuit, thereby further improving the data output rate of the storage circuit.

[0089] For example, voltage mismatch regulation can be achieved by establishing a compensation voltage at the feedback receiver and the feedback terminal. Alternatively, voltage mismatch regulation can be achieved by adjusting the settings of energy storage elements (e.g., capacitors) to adapt the compensation voltage between the recording feedback receiver and the feedback terminal, thereby matching and eliminating the voltage difference between the pre-establishment and establishment phases at the feedback terminal. This method is effective in regulating voltage mismatch and helps reduce the duration of the second sub-time period.

[0090] This application embodiment also provides a control device, which may be located in or include the above-mentioned control circuit, and the control device may include... Figure 1 or Figure 2 The control circuit 120 / 220 shown, or independent of the control circuit 120 / 220. This control device can be used to execute any of the above control methods.

[0091] This application embodiment also provides a control device, which may include a processor connected to a memory. The memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above control methods. The memory may be a memory within the control device or a memory outside the control device.

[0092] This application also provides a control device, which can be found in the embodiments of this application. Figure 8 . Figure 8 A schematic diagram of a control device according to an exemplary embodiment of this application is shown. Figure 8 As shown, the control device 800 includes at least one processing circuit 810 and an interface circuit 820. The interface circuit 820 is used to connect to the storage circuit via signals, and the at least one processing circuit 810 is used to execute any of the control methods provided in the above embodiments.

[0093] For example, the processing circuit 810 can execute the above control method, enabling the control device to read the output of the storage circuit.

[0094] For example, the control device can also control other external devices to enable those external devices to read the output of the storage circuit.

[0095] For example, in some embodiments, the processing circuit may include an application-specific integrated circuit (ASIC), which implements some or all of the functions of the control device by designing the logical relationships between the devices within the circuit; as another example, in some embodiments, the processing circuit may be implemented by a programmable logic device (PLD) circuit, which may include a large number of logic devices, and the logical relationships between the logic devices are configured through a configuration file, thereby implementing some or all of the functions of the control device.

[0096] Optionally, the control device provided in the embodiments of this application can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0097] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, such as a central processing unit (CPU), microcontroller unit (MCU), graphics processing unit (GPU), or digital signal processor. Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), deep learning processing unit (DPU), etc.

[0098] This application also provides a storage system, which includes a storage circuit and a control device, the control device being used to execute any of the control methods proposed in this application.

[0099] The storage system includes either a memory-computing chip or a storage chip.

[0100] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0101] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0102] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0103] This application also provides an electronic device, which can be found in [reference 1]. Figure 9 . Figure 9 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. (As...) Figure 9 As shown, the electronic device 900 may include any of the above-mentioned storage systems 910 for storing or processing data within the electronic device. The electronic device may also include an input / output device 920 for receiving user input, outputting processing results, or outputting stored data. This application does not limit the input and output types; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 930, which can process data provided to the storage system 910 or process the output data of the storage system 910. The output of the input / output device 920 may be based on the output of the processor 930 or the output of the storage system 910.

[0104] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0105] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method, characterized in that, The control method is used to control the output of a storage circuit, the storage circuit including a first storage array, and the control method includes: In the first time period, control the first output terminal of the first storage array to establish a first output signal; The first conversion control is performed on the first output signal during the second time period; The first time period includes a first sub-time period and a second sub-time period. The step of controlling the first output terminal of the first storage array to establish a first output signal during the first time period includes: The initial establishment of the operating conditions of the first storage array is controlled during the first sub-time period; The second sub-time period controls the stable establishment of the operating conditions of the first storage array, which are used to generate the first output signal at the first output terminal.

2. The control method according to claim 1, characterized in that, The operating conditions include the voltage at the first output terminal, and the initial establishment of the operating conditions for controlling the first memory array during the first sub-time period includes: A first voltage is provided to the first output terminal during the first sub-time period, and the first voltage is used to generate an initial voltage at the first output terminal. The stable establishment of the operating conditions of the first storage array during the second sub-time period includes: During the second sub-time period, the initial voltage at the first output terminal is controlled to stabilize to a second voltage, which is used to generate the first output signal at the first output terminal.

3. The control method according to claim 2, characterized in that, Controlling the initial voltage at the first output terminal to stabilize to a second voltage during the second sub-time period includes: The initial voltage at the first output terminal is stabilized to a second voltage based on a reference voltage, wherein the absolute value of the difference between the first voltage and the reference voltage is less than or equal to a threshold.

4. The control method according to any one of claims 1 to 3, characterized in that, Also includes: In the third time period, the output of the first conversion of the first output signal is subjected to second conversion control.

5. The control method according to any one of claims 1 to 4, characterized in that, The storage circuit further includes a second storage array, and the method further includes: In the fourth time period, control the second output terminal of the second storage array to establish a second output signal, including: The initial establishment of the operating conditions of the second storage array is controlled in the first sub-time period of the fourth time period; The second sub-time period of the fourth time period controls the stable establishment of the operating conditions of the second storage array, the operating conditions of the second storage array are used to generate the second output signal at the second output terminal, wherein the second sub-time period of the fourth time period and the first sub-time period of the first time period at least partially overlap.

6. The control method according to claim 5, characterized in that, Also includes: Within the first sub-time period of the first time period, the second output signal is controlled by a first conversion.

7. The control method according to claim 5 or 6, characterized in that, Also includes: In the fifth time period, control the second output terminal to establish a third output signal, including: The initial establishment of the operating conditions of the second storage array is controlled in the first sub-time period of the fifth time period; The second sub-time period of the fifth time period controls the stable establishment of the operating conditions of the second storage array, and the operating conditions of the second storage array are also used to generate the third output signal at the second output terminal, wherein the first sub-time period of the fifth time period and the second sub-time period of the first time period at least partially overlap.

8. The control method according to claim 7, characterized in that, The first sub-time period of the fifth time period overlaps at least partially with the second time period.

9. The control method according to claim 7 or 8, characterized in that, The method further includes: The third time period during which the output of the first conversion of the first output signal undergoes a second conversion overlaps at least partially with the second sub-time period of the fifth time period.

10. The control method according to any one of claims 1 to 9, characterized in that, The method further includes: During the second sub-time period of the first time period, the voltage mismatch adjustment during the establishment process of the first output signal is controlled.

11. The control method according to any one of claims 1 to 10, characterized in that, The first sub-time period is longer than the second sub-time period.

12. A control device, characterized in that, include: An interface circuit and a processing circuit, wherein the interface circuit is used to connect to a storage circuit for signal connection, and the processing circuit is used to execute the control method as described in any one of claims 1 to 11.

13. A storage system, characterized in that, include: Storage circuit; A control device for performing the control method as described in any one of claims 1 to 11.

14. The storage system according to claim 13, characterized in that, The first output signal is used to read out the data stored in the storage circuit or to read out the calculation result.

15. An electronic device, characterized in that, include: The storage system as described in claim 13 or 14.

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