A memory and data processing method

Abstract

The application provides a memory, a data processing method and an electronic device. A plurality of IO interfaces are arranged in a die to more efficiently manage the die, and the memory can be used to implement a high-capacity and high-speed memory. The memory comprises a plurality of dies connected through interfaces. Taking the connection mode of a first die as an example, the first die is referred to as a first die for the sake of distinction. The first die comprises a plurality of interface groups, specifically a first interface group and a second interface group, which are input and output interfaces of the first die. Specifically, the first die is used to store data. The first interface group and the second interface group both have the functions of inputting and outputting data. When the first interface group is used as an interface for receiving data, the second interface group is used as an interface for outputting data. When the first interface group is used as an interface for outputting data, the second interface group is used as an interface for inputting data.

Description

Technical Field

[0001] This application relates to the field of storage, and more particularly to a memory and a data processing method. Background Technology

[0002] With the development of big data and the Internet of Things, data will become a core element in various fields. Especially in the era of big data, the amount of data generated and the demand for data storage have increased dramatically, becoming the foundation of artificial intelligence. Therefore, there is a great demand for data storage systems capable of storing massive amounts of data.

[0003] Typically, a storage drive consists of a drive controller and media. The media, which stores the data, requires greater capacity to allow the data system to provide more storage while maintaining its size. Solid-state drives (SSDs), in particular, typically consist of a drive controller and solid-state media. The drive controller manages the solid-state media and handles external I / O (input / output) interactions. Usually, the drive controller and solid-state media on an SSD are interconnected via a NAND flash interface (NFI) bus. A single drive controller typically has multiple NFI channels, supporting the management of more media chips to achieve larger SSD capacities. To further increase SSD capacity, existing solutions may include multiple dies within a single media chip, increasing storage capacity by adding dies to the link. However, as the number of connected dies increases, the data transfer time between dies also increases, leading to a decrease in link speed.

[0004] Therefore, how to increase memory capacity without reducing link speed has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a memory and data processing method that enables more efficient management of the die by setting up multiple sets of IO interfaces in the die, and can be used to realize a memory with both high capacity and high speed.

[0006] In a first aspect, this application provides a memory, including: a plurality of memory dies, which are connected to each other via interfaces; wherein, taking the connection method of the first die as an example, for ease of distinction, the first die includes multiple sets of input / output (I / O) interfaces, such as a first interface group and a second interface group, the first interface group being the input and output interface of the first die, and the second interface group being the input and output interface of the first die; specifically, the first die is used to store data; both the first interface group and the second interface group have the function of inputting and outputting data, when the first interface group is used as the interface for receiving data, the second interface group is used as the interface for outputting data, and when the first interface group is used as the interface for outputting data, the second interface group is used as the interface for inputting data.

[0007] Typically, a memory can contain multiple media chips, each containing one or more dies. For example, in flash memory, multiple flash memory chips are usually used, each chip encapsulating one or more dies. Each die is typically divided into multiple planes, each plane consists of multiple blocks, and each block is composed of pages.

[0008] In this embodiment, at least two sets of I / O interfaces are provided for each die in the memory, both of which can be used for input and output. Compared to setting fewer unidirectional transmission interfaces or only one set of I / O interfaces, the memory provided in this embodiment has multiple sets of I / O interfaces. Data transmitted within the memory can be passed layer by layer through the I / O interfaces that interconnect the dies until the data is transmitted to the corresponding die, at which point the transmission stops. Furthermore, during data transmission, a die can simultaneously input and output data. While one set of interfaces is used for input data, another set of interfaces can be used for output data, thus enabling simultaneous data input and output within the die. For example, when first data is transmitted from the first interface group to the first die, the first die can simultaneously transmit second data to other dies through the second interface group. Compared to existing solutions where dies must wait for interfaces to be idle before unidirectional transmission can occur, the method provided in this embodiment can significantly increase the available transmission bandwidth within the memory. Therefore, even for a memory containing a large number of dies, a larger transmission bandwidth between dies can be achieved through multiple sets of I / O ports, avoiding the reduction in link speed caused by increasing memory capacity, and enabling a memory with both high capacity and high speed. Furthermore, compared to some existing solutions that require the introduction of additional multiplexing devices or chips to manage the memory, the memory provided in this application only requires the addition of IO interfaces in the die, without the need to introduce additional multiplexing devices or chips, and can be adapted to memory with more media particles at a lower cost.

[0009] In one possible implementation, the first interface group and the second interface group can communicate via transistors within the first die. Therefore, signals can be transmitted between interface groups within the die via transistors, achieving highly efficient and selective signal transmission.

[0010] In one possible implementation, the communication structure within the die is a transistor. In this application, a transistor structure can be used within the die; for example, highly efficient signal transmission can be achieved between various components within the die using transistors.

[0011] In one possible implementation, the aforementioned multiple dies are connected in series. These dies also include a second die and a third die, with the second die adjacent to the first die. The second die includes a third interface group and a fourth interface group. The third interface group connects to the second interface group of the first die, and the fourth interface group connects to one set of interfaces on the third die. That is, the dies can be connected in series via interface groups, allowing data to flow sequentially through the memory until it reaches the corresponding die. Even with more dies added to the memory, the time for data transmission between dies will not increase significantly, avoiding a decrease in link speed due to increased memory capacity.

[0012] In one possible implementation, the aforementioned first die further includes a processing circuit; this processing circuit is connected to the first interface group and the second interface group, and can be used to match received data or addresses with the first die. In this embodiment, processing circuits can be set in each die, thereby giving each die a certain data processing capability. The processing circuits set in each die can manage the transmission length of data in multiple dies, which can reduce the load on the memory to a certain extent. That is, data transmission can be terminated after being transmitted to the corresponding die, and there is no need to transmit to the remaining dies that have not been transmitted. Therefore, data does not need to be transmitted to all dies, and there is no need to set up additional multiplexing devices or chips to manage each die individually.

[0013] In one possible implementation, the aforementioned processing circuit is further configured to determine whether the first data received by the first die through the first interface group corresponds to the first die. If the first data corresponds to the first die, the first die stores the first data. For example, if the first data needs to be written to the first die, the processing circuit can write the first data into the first die. If the first data does not correspond to the first die, the first die does not store the first data and outputs the first data through the second interface group. For example, if the first data needs to be stored in other dies, the processing circuit can output the first data to other dies through the second interface group for processing in those other dies. In this embodiment, a processing circuit can be set in the die, thereby processing the received data through the processing circuit in the die. The main controller, which manages the memory, only needs to send the data to the memory, which reduces the workload of the main controller.

[0014] In one possible implementation, the aforementioned processing circuit is further configured to match the first address with the address of the first die to determine whether the first data corresponds to the first die. Accordingly, when the first address matches the address of the first die, the first data corresponds to the first die; when the first address does not match the address of the first die, the first data does not correspond to the first die.

[0015] In one possible implementation, if the first address corresponds to the address of the first die, then the first die stores the first data. For example, the first die sets its data processing mode to a first mode, which indicates that the first data is stored in the first die or that the first data corresponds to the first die when it is received. If the first address is not the address of the first die, then the first die outputs the first address to other dies through the second interface group. In this implementation, after the address is input from the first die, it goes through layers of dies for matching. For dies that match the address, there is no need to transmit the address to the next die, thereby reducing the address transmission channel length and improving data processing efficiency.

[0016] In one possible implementation, when the first die is located in the memory at the position where all dies of the memory's media particle are connected to the external network, such as the first die of a media particle, then the first interface group is connected to the memory's main controller, and the second interface group is connected to the memory's second die. In this embodiment, when the first die is the first of the media particles, i.e., at the position where the external link is connected, then the first interface group can have both input and output functions, and the second interface group can also have both input and output functions.

[0017] In one possible implementation, when the first die is in a position where it is externally connected within the dielectric particle, the first interface group connects to one set of interfaces of the previous die, and the second interface group connects to one set of interfaces of the next die. In a series structure, when the first die is not externally connected, one set of interfaces can connect to the previous die, and another set of interfaces can connect to the next die, thereby realizing the series connection of the dies.

[0018] In one possible implementation, the aforementioned memory is an SSD or universal flash storage (UFS). Therefore, in this application embodiment, the memory can be of various types and can be used for various storage types.

[0019] Secondly, this application provides a memory including a main controller for managing multiple dies connected in series. Among adjacent dies, one die is connected to the previous adjacent die via an interface group, and to the next adjacent die via another interface group. The interface groups of the dies are used for inputting and outputting data; that is, a set of interfaces can have both input and output functions. Typically, the memory can include multiple dielectric particles, each dielectric particle can include one or more dies, and parallel connection between dies can be achieved within the dielectric particle.

[0020] In this embodiment, each die can be connected to adjacent dies via different interface groups, thus connecting multiple dies in series. When the main controller sends data to each media particle, the data is transmitted layer by layer through the dies via the series links until it reaches the die storing the data. During data transmission, a die can simultaneously input and output data. While one set of interfaces is used for data input, another set of interfaces can be used for data output, thereby enabling simultaneous data input and output within the die at the same time. Compared to parallel connection transmission channels with only unidirectional transmission, the media particles of the memory provided in this application have a larger bandwidth. Therefore, even if the memory capacity is increased, the link rate within the memory will not decrease, enabling a memory with both high capacity and high speed.

[0021] In one possible implementation, different interface groups within the same die can communicate via transistors within the die. In this embodiment, transistors can be used to implement signal transmission within the die.

[0022] In one possible implementation, the aforementioned plurality of dies includes a first die, which includes a first interface group and a second interface group. The first die is connected to the main controller through the first interface group and to a second die through the second interface group. The first die is used to: receive first data from the main controller through the first interface group; store data whose storage location is in the first die; and forward data whose storage location is not in the first die to the second die through the second interface group. In this embodiment, when data is transferred between dies, the transfer can be terminated if the data is transferred to the corresponding die; otherwise, it continues to be transferred to the next die through the serial link.

[0023] In one possible implementation, the first die is further used to forward first data between the first interface and the second interface via transistors within the first die. In this embodiment, the first data can be transmitted between interface groups within the die via transistors, thereby enabling data transmission within the die in a cascaded die scenario. In one possible implementation, the aforementioned plurality of dies includes a first die, a second die, and a third die; the first die includes a first processing circuit, a first interface group, and a second interface group, the first processing circuit being connected to the first interface group and the second interface group; the second die includes a second processing circuit, a third interface group, and a fourth interface group, the second processing circuit being connected to the third interface group and the fourth interface group; the first interface group of the first die is connected to a set of interfaces of the previous die, the second interface group of the first die is connected to the third interface group of the second die, and the fourth interface group is connected to one of the sets of interfaces of the third die; furthermore, when the first processing circuit detects that first data corresponds to the first die, the first die is used to store the first data; when the first processing circuit detects that the first data does not correspond to the first die, the first die transmits the first data to the second die through the second interface group; the second die is used to receive the first data through the third interface; if the second processing circuit detects that the first data corresponds to the second die, the second die is used to store the first data; if the second processing circuit detects that the first data does not correspond to the second die, the second processing circuit is used to send the first data to the third die through the fourth interface.

[0024] In this embodiment, a die is connected to adjacent dies via different interface groups, realizing the cascading of multiple dies. When data is transferred between dies, the processing circuitry within the die can determine whether the data is to be processed by the current die. If so, the data is stored in the current die; otherwise, the data is passed to the next die. Therefore, the transmission of the first data can be terminated after it reaches the corresponding die, and subsequent dies that have not yet received the first data do not need to continue transmitting it. Thus, storing the first data can shield the load on subsequent dies, improving the overall efficiency of the memory.

[0025] In one possible implementation, the first processing circuit is specifically used to detect whether the first data corresponds to the first die by determining whether the first address matches the address corresponding to the first die, where the first address is the address of the first data. In this embodiment, before writing data, the corresponding die can be determined by transmitting the first address between the dies, thereby achieving die positioning in advance. Then, when writing data later, the die corresponding to the first data can be directly determined. For example, specifically, the first die is also used to receive the first address through the first interface group, which is sent by the main controller to each particle; if the first processing circuit detects that the first address is the address corresponding to the first die, the first processing circuit sets the data processing mode to the first mode, which is used to indicate that the first data is stored in the first die when the first data is received; if the first address is not the address corresponding to the first die, the first die transmits the first address to the second die through the second interface group;

[0026] The second die is also used to receive the first address through the third interface group; if the second processing circuit detects that the first address is the address corresponding to the second die, the second processing circuit sets the data processing mode to the first mode, which is used to indicate that the first data is stored in the second die when the first data is received; if the second processing circuit detects that the first address is not the address corresponding to the second die, the second processing circuit transmits the first address to the third die through the fourth interface.

[0027] In this embodiment of the application, before writing data, the die to be written to can be determined by passing a first address between the dies. Thus, in the memory where dies are connected in series, the address is passed layer by layer between the dies, and the first address is matched within the die until the die corresponding to the first address is determined, and then returned to the main controller to pass the next step of data or instructions.

[0028] In one possible implementation, the storage device is an SSD or UFS, etc.

[0029] Thirdly, this application provides a data processing method applied to a memory, which includes: a plurality of memory dies connected to each other via interfaces. Taking the connection method of the first die as an example, for ease of distinction, it is referred to as the first die. The first die includes processing circuitry and at least two sets of input / output (IO) interfaces. Specifically, the structure of the memory can be referred to in the description of the first or second aspects above, and will not be repeated here.

[0030] The method includes a first die receiving first data through a first interface group; if the processing circuit detects that the first data corresponds to the first die, the first die stores the first data; if the processing circuit detects that the first data does not correspond to the first die, the first die outputs the first data through a second interface group.

[0031] In this embodiment, a processing circuit can be set in the die to detect whether the received data is to be stored by the current die. This allows data to be transferred between dies until it is delivered to the corresponding die, without the need for the main controller to identify the die corresponding to the data. This reduces the workload of the main controller and avoids a decrease in the physical speed of the link due to excessive load on the main controller.

[0032] In one possible implementation, the processing circuit determines whether the first data corresponds to the first die by matching a first address with the address of the first die. The first address is associated with the first data, and the first address is received by the first die through a first interface group. Specifically, if the first address matches the address of the first die (e.g., the first address is within the address range of the first die), then the first data corresponds to the first die; if the first address does not match the address of the first die (e.g., the first address is not within the address range of the first die), then the first data does not correspond to the first die. In this embodiment, the processing circuit can match the first address corresponding to the first data with the address of the die to determine whether the first data is stored in the first die.

[0033] In one possible implementation, the aforementioned method further includes: if the processing circuit detects that the first address is the address corresponding to the first die, the processing circuit sets the data processing mode to a first mode, the first mode being used to indicate that the first data is stored in the first die when the first data is received; if the first address is not the address of the first die, the first die outputs the first address through the second interface group.

[0034] In this embodiment, the signal flow in the memory is to identify whether the address matches the input address one die at a time. That is, the matching of the input address and the die address can be completed within the die. The die has a certain processing capability. By setting a first mode, it is indicated that the die will process the data to be processed, such as storing or reading, without having to pass the address to the next die. Accordingly, the workload of the main controller set up for the memory can be reduced.

[0035] In one possible implementation, the aforementioned method further includes: if the processing circuit detects that the first address is not the address of the first die, the processing circuit sets the data processing mode to a second mode, which is used to instruct the first die not to store the first data, or the processing circuit corresponding to the next die continues to match the first address. In this embodiment, if the input address identified by the die does not match the address of the die, the address can be passed to the next die to find a die that matches the address.

[0036] Fourthly, this application provides a data processing method applied to a memory, the memory including a main controller and a plurality of dies connected in series, wherein in adjacent dies, one die is connected to the adjacent previous die through an interface group, and is connected to the adjacent next die through another interface group; the structure of the memory can be referred to the description in the second aspect above, and will not be repeated here;

[0037] The method includes: the main controller sending first data to multiple dies, and transmitting the first data to the dies corresponding to the first data for storage through a serial channel between the multiple dies.

[0038] In this embodiment of the application, when data needs to be stored, the main controller can send the first data to be stored to multiple dies, and transfer the first data between the multiple dies through the serial channel between the multiple dies until the first data is transferred to the corresponding dies for storage.

[0039] In one possible implementation, the aforementioned plurality of dies includes a first die, a second die, and a third die;

[0040] The first die includes a first processing circuit, a first interface group and a second interface group, and the second die includes a second processing circuit, a third interface group and a fourth interface group. The first interface group of the first die is connected to the third interface group of the second die, and the third interface group is connected to one of the interface groups of the third die.

[0041] The method specifically includes:

[0042] The first die receives the first data through the first interface group. The first data is the data output by the main controller to multiple dies. When the first processing circuit detects that the first data corresponds to the first die, the first die stores the first data. When the first processing circuit detects that the first data does not correspond to the first die, the first die forwards the first data to the second die through the second interface group.

[0043] When the second die receives the first data through the third interface group, if the second processing circuit detects that the first data corresponds to the second die, the second die is used to store the first data. If the second processing circuit detects that the first data does not correspond to the second die, the second die is used to forward the first data to the third die through the fourth interface group.

[0044] In this embodiment of the application, during the transmission of the first data, the processing circuit in each die identifies whether the first data is stored in each die. Once the die storing the first data is determined, the transmission of the first data can be stopped. Therefore, for subsequent dies that have not transmitted the first data, there is no need to continue transmitting. A certain degree of load shielding can be achieved for the transmission process of the first data, that is, shielding subsequent dies that have not transmitted the first data, thereby improving the overall working efficiency of the memory.

[0045] In one possible implementation, the aforementioned method may specifically include: a first processing circuit determining whether first data corresponds to a first die by matching a first address with the address of a first die, wherein the first address is associated with the first data, and the first address is received by the first die through a first interface group; wherein, when the first address matches the address of the first die, for example, if the first address is within the address range of the first die, then the first data corresponds to the first die; when the first address does not match the address of the first die, for example, if the first address is not within the address range of the first die, then the first data does not correspond to the first die. In this embodiment of the application, the processing circuit can match the first address corresponding to the first data with the address of the die to determine whether the first data is stored in the first die.

[0046] Fifthly, this application provides an electronic device, which includes a processor and at least one memory, the memory including the memory as described in any optional embodiment of the first or second aspect, the memory being used to store data, and the processor being used to process the data stored in the memory. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0048] Figure 2This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0049] Figure 3 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0051] Figure 5 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0052] Figure 6 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0053] Figure 7 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0054] Figure 8 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0057] Figure 11 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0058] Figure 12 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0059] Figure 13 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0060] Figure 14 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0061] Figure 15 A flowchart illustrating another data processing method provided in an embodiment of this application;

[0062] Figure 16 This is a flowchart illustrating another data processing method provided in an embodiment of this application. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0064] First, this application provides a memory that can be deployed in an electronic device, which may specifically include a terminal or a server. For example, the electronic device may include a human-computer interface, a smart home device, a smartphone, or a smart car.

[0065] The deployment method of the memory provided in this application may also differ depending on the type of electronic device.

[0066] In one possible deployment configuration, the electronic device may include a processor, a storage manager, and a memory; the number of memories may be one or more. For example, the structure of the electronic device provided in the embodiments of this application may be as follows: Figure 1 As shown. The electronic device 10 may include a processor 101, a storage controller 102, and one or more memories 103, etc.

[0067] The processor 101 can be used as the control center of the electronic device 10, and can be a conventional processor. For example, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a system on chip (SOC), an application-specific integrated circuit (ASIC), or a combination thereof.

[0068] The memory 103 can be used to store data. One or more memories 103 can be set in an electronic device, depending on the actual application scenario. For example, it can store data such as code or images that the processor 101 needs to execute. For example, in electronic devices such as personal computers or servers, the specific type of memory set can be a solid state drive (SSD), which can be used to store data in the electronic device, such as code, images, point clouds, text or voice data.

[0069] The storage controller 102 can be used to manage the memory 103. For example, if the processor needs to read data from the memory 103, it needs to do so through the storage controller 102, or if the processor 101 uses the storage space in the memory 103, it can request available storage space through the storage controller 102, etc.

[0070] The storage controller 102 is optional, or the processor 101 can directly manage the memory 103. The specific configuration can be determined based on the actual application scenario.

[0071] The aforementioned electronic devices may specifically include personal computers or servers, and typically the processor 101 and memory 103 are deployed on different substrates and connected by lines.

[0072] Of course, in addition to the aforementioned processor 101, storage controller 102 and one or more memory 103, electronic devices may also include other components, which can be determined according to the actual application scenario. This application will not list them all.

[0073] In another possible deployment, the memory provided in this embodiment can also be integrated into the electronic device. For example, the memory provided in this embodiment can be integrated with other components of the electronic device on the same substrate.

[0074] For example, the structure of an electronic device provided in this application embodiment can be as follows: Figure 2 As shown. The electronic device 20 may include a processor 201 and a memory 202.

[0075] Processor 201 is similar to the aforementioned processor 101, and will not be described again here.

[0076] In this electronic device 20, the processor 201 and the memory 202 can be integrated on the same substrate. The memory 202 can store the code required for the processor 201 to run, or it can store data generated by other components in the electronic device. For example, it can store code, images, text, or other types of data.

[0077] Of course, in addition to the aforementioned processor 201 and memory 202, the electronic device 20 may also include other components, such as... Figure 2 The power supply or sensors shown can be determined according to the actual application scenario, and this application will not list them all.

[0078] Specifically, the aforementioned memory may include solid-state drives (SSDs) or universal flash storage (UFS), etc.

[0079] Commonly used memory chips employ NAND dies to comply with ONFI (open NAND flash interface) requirements. The memory's master controller and the media chips are interconnected via an NFI bus. Typically, a master controller has multiple NFI channels to support the management of more chips and achieve larger capacities.

[0080] The number of NFI channels available to the main controller is limited, due to factors such as chip power consumption, package size, and application scenarios. Typically, existing solutions use single-channel connections between dies within the dielectric material. Larger capacity is achieved by increasing the number of dielectric materials or dies within a single channel; however, increased single-channel load leads to reduced single-disk performance, such as decreased link speed or capacity-to-bandwidth ratio.

[0081] For example, in an existing solution, the NAND interface bus is based on the parallel protocol of NV-DDR (an interface of ONFI). When multiple dies are connected in parallel to the link, the physical link speed decreases as the number of dies increases. In some scenarios, a 50% load reduction can be achieved by introducing hardware multiplexing devices (MUX), allowing for a lower load for the same capacity. However, this requires a separate mux device, occupying board space and increasing implementation costs. In other scenarios, chips with active signal processing capabilities can be deployed to shield the load of dies that do not require data processing. However, for different devices, such as those using different NAND flash memory, different adaptation work is required when setting up the chip, increasing implementation costs.

[0082] Therefore, this application provides a memory that enables communication and management of each die by setting multiple sets of IO interfaces in the die, thereby increasing the available bandwidth within each die and avoiding the rate reduction problem caused by increased load on a single-channel link without introducing additional new devices.

[0083] The specific structure of the memory will be further described below.

[0084] Typically, a memory can include multiple media chips, and each media chip can contain one or more dies. For example, in flash memory, multiple flash memory chips are usually used, and each flash memory chip encapsulates one or more dies. Each die is usually divided into multiple planes, each plane consists of multiple blocks, and each block consists of pages. Data in each die can be stored in a page. The location of data storage in each die will not be elaborated below.

[0085] The memory provided in this application embodiment may include multiple dies, which are connected to each other through an interface.

[0086] Exemplary, the structure of a memory 30 provided in this application embodiment can be as follows: Figure 3 As shown. It may include one or more media particles 31, and each storage media particle may include one or more dies 311.

[0087] For example, taking the structure of one of the dies as an example, for ease of distinction, this die will be referred to as the first die, such as... Figure 4 As shown, the first die includes multiple sets of interfaces, including a first interface group and a second interface group. The first interface group is the input and output interface of the first die, and the second interface group is the input and output interface of the first die. That is, both the first interface group and the second interface group have data input and output functions.

[0088] The first die is used to store data, for example, the first die includes a medium for storing data;

[0089] When the first interface group is used as an interface for input data, the second interface group is used as an interface for output data.

[0090] When the first interface group is used as the interface for output data, the second interface group is used as the interface for input data.

[0091] In this embodiment, at least two sets of I / O interfaces are provided in the first die. Compared to providing fewer unidirectional interfaces or only one set of I / O interfaces, the memory provided in this embodiment provides multiple sets of I / O interfaces, enabling simultaneous data input and output without waiting for interfaces to become idle, thus improving the internal transmission bandwidth of the memory. Data input and output can be achieved simultaneously; that is, while using one set of interfaces to input data, other sets of interfaces can be used for data output. For example, while the first die is receiving data through the first set of interfaces, it can simultaneously use the second set of interfaces to output data without waiting for an idle interface. Therefore, even for a memory containing a large number of dies, data transmission between dies can be achieved through multiple sets of I / O ports, avoiding a decrease in link speed due to increased memory capacity. Furthermore, compared to some existing solutions that require additional multiplexing devices or chips for memory management, the memory provided in this embodiment only requires adding I / O interfaces to the dies without introducing additional multiplexing devices or chips, allowing for compatibility with storage products of more media layers at a lower cost.

[0092] In one specific implementation, the first interface group and the second interface group in the first die are connected. Specifically, communication can be achieved through transistors within the die, or through metal wires, thereby enabling data transmission between interfaces within the same die.

[0093] Optionally, the intra-die communication structure of the multiple dies can be made using transistors. For example, when integrating dies, the dies can be integrated into the form of multiple transistors to form a complete circuit.

[0094] In one possible implementation, a main controller may also be located within the memory. This main controller can be located either inside or outside the memory.

[0095] In one possible implementation, the main controller can be located within a memory. Alternatively, embodiments of this application also provide a memory comprising:

[0096] The main controller manages multiple dies connected in series.

[0097] Among the multiple dies, one of the adjacent dies is connected to the adjacent previous die through one set of interfaces, and to the adjacent next die through another set of interfaces; wherein, the interface of the die is used for input data and output data.

[0098] For example, such as Figure 5As shown, one of the die layers in each of the media particles 31 provides a set of interfaces to connect to the main controller 32. The main controller 32 can transmit data between the media particles through the connection between the media particles.

[0099] In another possible implementation, the main controller can be located outside the memory, such as in conjunction with the aforementioned... Figure 2 In this electronic device architecture, the main controller's functions can be directly implemented by the processor 201, or the main controller can be deployed on the electronic device's substrate, in which case the main controller can serve as one of the components of the electronic device. For example, as... Figure 6 As shown, one of the die layers in each of the media particles 31 provides a set of interfaces to connect to the main controller 33. The main controller 33 can transmit data with each media particle through the interfaces connected to each media particle.

[0100] For example, if the memory provided in this embodiment is an SSD, the aforementioned main controller can be a drive controller, that is, a main controller is set inside the SSD, and the aforementioned media particles can be flash memory media particles. The drive controller can be used to manage the flash memory media particles in the SSD. The drive controller and the flash memory media particles can be connected via an NFI bus.

[0101] Therefore, the memory provided in this application embodiment has at least two sets of I / O interfaces in the die of the medium particle, thereby enabling data transmission between dies through more I / O interfaces and improving the data throughput of data transmission between dies. For example, data input and output of the same die can be realized simultaneously through different I / O interfaces. This avoids the reduction in physical link speed caused by adding dies.

[0102] Furthermore, in the aforementioned memory, multiple dies within a single dielectric particle are connected in series sequentially. Specifically, multiple dies can be stacked to form a dielectric particle, and the dies can be connected in series via an interface. For example, these multiple dies may also include a second die and a third die, such as... Figure 7 As shown, the second die includes a third interface group and a fourth interface group.

[0103] The third interface group connects to the second interface group, the fourth interface group connects to one of the interfaces of the third die, the third die also includes interfaces that connect to other dies, and so on.

[0104] Therefore, in this embodiment, dies can be connected in series through interfaces, and each die can be connected to other dies through different interface groups. Thus, communication with different dies can be achieved through different interface groups, enabling simultaneous communication with different dies, thereby making full use of the interfaces set in the dies to achieve a larger transmission bandwidth inside the memory.

[0105] In one specific implementation, the connection method between dies can employ gold wires, copper wires, or other data-transmitting media to support data transfer between dies.

[0106] Furthermore, when the first die is in the position of external connection within the dielectric particle, the first interface group connects to the external link, such as the main controller, and the second interface group connects to the next die, i.e., the second die.

[0107] When the first die is in a non-externally connected position within the dielectric particle, the first interface group connects to one of the interfaces of the previous die, the second interface group connects to the third interface group, and so on.

[0108] Therefore, in this embodiment, the die located in the first layer of the medium particles can be connected to an external link, such as a main controller for managing memory settings or other components for managing memory.

[0109] In one possible implementation, the first die further includes a processing circuit connected to the first interface group and the second interface group; the processing circuit is used to identify whether the received data corresponds to the first die.

[0110] Furthermore, the first die can also include logic circuits for writing, deleting, or reading data. These logic circuits can be integrated with the aforementioned processing circuits or be separate circuits, depending on the specific application scenario. In the following embodiments of this application, only the function of the aforementioned processing circuit in identifying whether the received data corresponds to the first die will be described. The functions of writing, deleting, or reading data will be collectively referred to as being executed by the first die, which is equivalent to considering the function of this logic circuit as the overall function of the first die, and will not be elaborated further below.

[0111] For example, one possible structure of the first die could be as follows: Figure 8 As shown. The processing circuit connects the first interface group and the second interface group, and can typically be implemented using a small processor or logic circuit. This processing circuit can be used to identify whether the data received by the first die corresponds to the first die.

[0112] Therefore, in this embodiment, processing circuits are set in each die to determine whether the current die is responsible for storing data. This gives each die a certain judgment capability, eliminating the need for the main controller to identify the die storing data. This reduces the overhead of the main controller in the memory for managing the memory and avoids a decrease in physical link speed due to the addition of dies. Essentially, it distributes the execution steps of the main controller in existing solutions to the dies for execution.

[0113] Optionally, the processing circuitry in the die may be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0114] In one possible implementation, the first die can also be used to receive first data through a first interface group. The processing circuit can be used to determine whether the first data received by the first die through the first interface group corresponds to the first die. If the processing circuit detects that the first data corresponds to the first die, for example, if the first data needs to be stored in the first die, then the first die stores the first data, for example, by writing the first data into the first die. If the processing circuit detects that the first data does not correspond to the first die, then the first die outputs the first data through a second interface group until the first data is transferred to the die storing the first data. Of course, the first data can also be received through a second interface group and output through a first interface group, etc. The specific input and output interfaces of the data can be determined according to the actual application scenario. This application embodiment exemplifies the example of the first interface group receiving the first data and the second interface group outputting the first data.

[0115] In this embodiment, first data can be transmitted between dies. If the first data is not transmitted to the corresponding die, the transmission to the first die can continue. Once the first data is transmitted to the corresponding die, the transmission of the first data between dies can be stopped. Thus, data processing can be achieved without traversing all dies, which can improve data processing efficiency.

[0116] In one possible implementation, the processing circuit is specifically configured to: determine whether first data corresponds to the first die by matching a first address with the address of the first die, wherein the first address is associated with the first data, and the first address is received by the first die through a first interface group; wherein: when the first address matches the address of the first die, the first data corresponds to the first die; when the first address does not match the address of the first die, the first data does not correspond to the first die. In this embodiment of the application, the processing circuit can specifically identify whether the first data is stored by the first die by determining whether the address of the first data matches the address of the first die.

[0117] In one possible implementation, the first die is further used to obtain a first address through a first interface group. Specifically, the processing circuit matches the first address with the address of the first die, where the first address is the address corresponding to the first data. If the processing circuit detects that the first address is the address corresponding to the first die, it sets the data processing mode to a first mode, which indicates that the first data is stored in the first die when it is received. If the processing circuit detects that the first address is not the address of the first die, the first die outputs the first address through a second interface group. In this embodiment, a processing circuit is provided in the die, which can be implemented using logic circuits or other chips. This gives each die a certain data processing capability, thereby sharing the workload of the main controller, reducing the management overhead of the main controller for each memory, improving the management efficiency of the main controller for each memory, and improving the overall data processing efficiency.

[0118] For example, when dies within the memory are connected in series, during the address matching stage of data processing, address matching is performed within each die. If an address mismatch occurs, the die is set to Bypass mode (the second mode mentioned earlier) during this data processing phase. Once an address match is found, the die is set to Termination mode (the first mode mentioned earlier). After address matching, data transmission and reception can proceed. The address matching steps or data transmission and reception for each die can be executed by the processing circuitry within each die.

[0119] The structure and data / address passing method of the first die have been described above. For ease of understanding, the data / address passing method between multiple dies will be described below.

[0120] For example, the aforementioned multiple dies include a first die, a second die, and a third die; the first die includes a first processing circuit, a first interface group, and a second interface group, with the first processing circuit connected to the first interface group and the second interface group; the second die includes a second processing circuit, a third interface group, and a fourth interface group, with the second processing circuit connected to the third interface group and the fourth interface group; the first interface group of the first die is connected to a set of interfaces of the previous die, the second interface group of the first die is connected to the third interface group of the second die, and the fourth interface group is connected to one of the interface groups of the third die; furthermore, when the first processing circuit detects that the first data corresponds to the first die, the first die is used to store the first data; when the first processing circuit detects that the first data does not correspond to the first die, the first die transmits the first data to the second die through the second interface group; the second die is used to receive the first data through the third interface; if the second processing circuit detects that the first data corresponds to the second die, the second die is used to store the first data; if the second processing circuit detects that the first data does not correspond to the second die, the second processing circuit is used to send the first data to the third die through the fourth interface.

[0121] In this embodiment, a die is connected to adjacent dies via different interface groups, realizing the cascading of multiple dies. When data is transferred between dies, the processing circuitry within the die can determine whether the data is to be processed by the current die. If so, the data is stored in the current die; otherwise, the data is passed to the next die. Therefore, the transmission of the first data can be terminated after it reaches the corresponding die, and subsequent dies that have not yet received the first data do not need to continue transmitting it. Thus, storing the first data can shield the load on subsequent dies, improving the overall efficiency of the memory.

[0122] In one possible implementation, the first processing circuit is specifically used to detect whether the first data corresponds to the first die by determining whether the first address matches the address corresponding to the first die, where the first address is the address of the first data. In this embodiment, before writing data, the corresponding die can be determined by passing the first address between each die, thereby achieving die location in advance. Then, when writing data subsequently, the die corresponding to the first data can be directly determined.

[0123] For example, specifically, the first die is also used to receive a first address through the first interface group, which is sent by the main controller to each particle; if the first processing circuit detects that the first address is the address corresponding to the first die, the first processing circuit sets the data processing mode to the first mode, which is used to indicate that the first data is stored in the first die when the first data is received; if the first address is not the address corresponding to the first die, the first die transmits the first address to the second die through the second interface group.

[0124] The second die is also used to receive the first address through the third interface group; if the second processing circuit detects that the first address is the address corresponding to the second die, the second processing circuit sets the data processing mode to the first mode, which is used to indicate that the first data is stored in the second die when the first data is received; if the second processing circuit detects that the first address is not the address corresponding to the second die, the second processing circuit transmits the first address to the third die through the fourth interface.

[0125] In this embodiment of the application, before writing data, the die to be written to can be determined by passing a first address between the dies. Thus, in the memory where dies are connected in series, the address is passed layer by layer between the dies, and the first address is matched within the die until the die corresponding to the first address is determined, and then returned to the main controller to pass the next step of data or instructions.

[0126] Of course, in order to be compatible with the data transmission methods of existing solutions, the memory provided in this application embodiment can also be configured to connect the various dies in parallel. For example, the structure of a parallel memory can be as follows: Figure 9 As shown. In Figure 9 In the memory 90 shown, the data output by the main controller can be transmitted to all dies through a parallel connection.

[0127] The memory 90 includes a main controller 92 and at least one medium particle 91, wherein one or more dies 911 may be apocalyptic in the medium particle 91.

[0128] The main controller 92 is used to manage multiple dies 911 for storing data, wherein the dies include a medium for storing data, and the multiple dies are connected to each other via an interface;

[0129] In this configuration, one set of interfaces in a die simultaneously connects to a set of interfaces in the previous die and a set of interfaces in the next die. This set of interfaces is used for both input and output data. In other words, within a die, the same set of interfaces enables connections to both the previous and next dies, thus achieving parallel operation between dies.

[0130] This application also provides a memory comprising dies connected in parallel, thereby being compatible with existing parallel-connected memory solutions. Data, instructions, or addresses input to the media particles can be passed layer by layer between the dies via parallel links until they are transmitted to the corresponding die. For example, the connection method of the parallel-structured memory can be as follows: Figure 10 As shown. The first die includes a first interface group and a second interface group, the second die includes a third interface group and a fourth interface group, and the third die includes a fifth interface group and a sixth interface group. The first interface group of the first die is connected to the third interface group of the second die, and the third interface group is connected to the fifth interface group of the third die, thereby realizing the parallel connection of the dies.

[0131] The following example illustrates the difference between parallel and series connection methods between dies.

[0132] When using a series connection, the arrangement of storage devices can be as follows: Figure 11 As shown, there are four dies, such as dies 1 to dies 4. Dies 1 to n represent the first group of IO pads in each layer, i.e., the aforementioned first interface group, and dies 1' to n' represent the second group of IO pads in each layer, i.e., the aforementioned second interface group. The first and second groups of IO pads within each die can be connected using MOSFETs to enable data transfer between interfaces within the die. The bottom die, i.e., die 1, is connected to the external link via the first IO pad. The second group of IO pads in the second-layer die is interconnected with the second group of IO pads in the bottom die via gold or copper wires to enable data transfer between IO pads. The first group of IO pads in the third-layer die is interconnected with the first group of IO pads in the second-layer die, and so on. For example, dies 1 in the first layer are connected to external link 1, dies 1' in the first layer are connected to dies 1' in the second layer, dies 1 in the second layer are connected to dies 1 in the third layer, and so on.

[0133] When using parallel connections, the arrangement of storage devices can be as follows: Figure 12 As shown, similar to the aforementioned Figure 11 Similarly, 1 to n represent the first group of IO pads for each layer, i.e., the aforementioned first interface group, and 1' to n' represent the second group of IO pads for each layer, i.e., the second interface group of the assigned layer. The difference lies in the interconnection between the various dies through either the first or second group of IO pads, such as one connection method as... Figure 12 As shown, the 1 to n of each die layer are connected to achieve a parallel structure.

[0134] The following section will introduce specific memory structures.

[0135] First, taking the method provided in the embodiments of this application applied to an SSD as an example, the structure of the SSD can be as follows: Figure 13 As shown, this includes a main controller and multiple NAND flash chips, each containing multiple NAND dies. The main controller and each NAND flash chip are connected via an NFI interface. Each NAND die has two sets of I / O interfaces, and the NAND dies can be connected in series using gold or copper wires. Of course, they can also be connected in parallel; this scenario exemplifies a series connection.

[0136] Each NAND die also contains processing circuitry to support certain data processing functions, such as data reading, data writing, setting data processing modes, or address matching.

[0137] When any NAND die receives data or an address through one of its I / O interfaces, if the received data or address corresponds to the current NAND die, then data processing is performed on the current NAND die, such as writing data or setting the data processing mode to Termination; if the received data or address does not correspond to the current NAND die, then the NAND die can output the data or address to other NAND dies through another I / O interface so that similar processing steps can be performed in the next NAND die.

[0138] Therefore, in this embodiment, the main controller only needs to send data or addresses at the NAND chip level. The remaining steps, such as address matching or data processing, can be handled by the NAND dies within the NAND chips. This eliminates the need for the main controller to handle all NAND die feedback, significantly reducing its overhead and preventing physical link speed reduction due to excessive load. Even with an increased number of connected dies, memory capacity can be increased with less main controller overhead, without reducing physical link speed or minimizing the reduction.

[0139] Based on the aforementioned memory, this application also provides a data processing method.

[0140] The data processing method provided in this application embodiment is for the aforementioned Figures 3 to 13 The data processing flow of the memory in the memory, and the structure of the memory can be referred to the above. Figures 3 to 13 The introduction will not be repeated here.

[0141] The following section will first take the processing flow of one of the dies (i.e., the first die mentioned above) as an example to introduce the process.

[0142] See Figure 14 The following is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0143] 1401. The processing circuit determines whether the first data received by the first die through the first interface group is stored in the first die.

[0144] This first piece of data can come from the aforementioned... Figures 3 to 13 The main controller mentioned above passes data through layers of dies in the medium particles until it reaches the corresponding die. In the current first die, the first data transmitted from the main controller or the previous die can be received through the first interface group.

[0145] The first data can be data of various types, such as images, audio, or text. The specific content of the first data may vary depending on the specific application scenario.

[0146] After receiving the first data, the processing circuit can determine whether the first data corresponds to the first die, that is, whether the first data is stored in the first die.

[0147] Optionally, the processing circuit can identify whether the first data needs to be stored in the first die by reading the value of the data processing mode. For example, the data processing mode can store Termination or Bypass, etc. If the data processing mode is Termination, it means that the first data corresponds to the first die; if the data processing mode is Bypass, it means that the first data corresponds to the first die, etc.

[0148] 1402. If the first data corresponds to the first die, then the first die stores the first data.

[0149] For example, if the first data is data that needs to be written to the current die, the processing circuit can write the first data into the current die.

[0150] 1403. If the first data does not correspond to the first die, the first die outputs the first data through the second interface group.

[0151] If the first data does not correspond to the first die, for example, if the data processing mode is Bypass, the processing circuit can output the first data to the next die through the second interface group.

[0152] Among them, in combination with the above Figures 3 to 13The description states that the connection relationship between dies in a memory can be divided into series or parallel connection. In the series connection mode, if the first data is received through the first interface group, the first data can be passed to the next die through the second interface group; in the parallel connection mode, if the first data is received from the main controller or the previous die through the first interface group, the first data can continue to be passed to the next die through the first interface group, so as to ensure compatibility with the memory where dies are connected in parallel.

[0153] In this embodiment, each die can be equipped with multiple sets of interfaces, all of which can be used for data input and output. This means it has the ability to receive master control signals (such as addresses or data transmitted by the master controller) and send data to other dies, reducing the load on the master controller. In other words, the master controller does not need to iterate through all dies for matching; the processing circuitry and input / output interfaces in each die can determine the die corresponding to the first data, significantly reducing the load on the master controller. Essentially, the die has a function similar to host / device status settings, enabling it to shield unnecessary load and indirectly manage other dies.

[0154] The following describes the process of transferring the first data between multiple dies.

[0155] See Figure 15 A flowchart illustrating another data processing method provided in this application embodiment includes:

[0156] 1501. The first processing circuit determines whether the first data received through the first interface group corresponds to the first die.

[0157] In the first die, the first data sent by the previous die is received through the first interface group. The first data is the data output by the main controller to multiple media particles. When the first processing circuit detects that the first data corresponds to the first die, the first die stores the first data, that is, step 1502 is executed; when the first processing circuit detects that the first data does not correspond to the first die, the first die forwards the first data to the second die through the second interface group, that is, step 1503 is executed.

[0158] 1502. If so, then the first die stores the first data.

[0159] The first die includes a medium that can be used to store data, meaning that the first data can be written into the first die.

[0160] 1503. If not, the first die will transmit the first data to the second die through the second interface group.

[0161] The second interface group of the first die is connected to the third interface group of the second die. When the first data does not correspond to the first die, the first die can send the first data to the second die through the second interface group, and the second die can receive the first data through the third interface group.

[0162] 1504. The second processing circuit determines whether the first data received through the third interface group corresponds to the second die.

[0163] When the second die receives the first data through the third interface, if the second processing circuit detects that the first data corresponds to the second die, the second die is used to store the first data. If the second processing circuit detects that the first data does not correspond to the second die, the second die is used to forward the first data to the third die through the third interface.

[0164] 1505. If so, then the second die stores the first data.

[0165] The second die includes a medium that can be used to store data, meaning the first data can be written into the second die.

[0166] 1506. If not, the second die will pass the first data to the third die through the fourth interface group.

[0167] The fourth interface group of the second die is connected to a set of interfaces of the third die. When the first data does not correspond to the second die, the second die can send the first data to the third die through the fourth interface group. The third processing circuit in the third die can then continue to perform judgment steps similar to those of the first and second processing circuits, which will not be described in detail below.

[0168] In this embodiment, during the transmission of the first data, the processing circuits in each die identify whether the first data is stored in that die. Once the die storing the first data is identified, the transmission of the first data can be stopped. Therefore, for subsequent dies that have not yet received the first data, there is no need to continue transmitting it. This achieves a certain degree of load shielding during the transmission process, i.e., shielding subsequent dies that have not yet received the first data, thus improving the overall efficiency of the memory. In one possible embodiment, the aforementioned method may further include: before transmitting the first data, the die processing the first data can be located. Specifically, taking the processing of the first die as an example, the first die receives a first address through a first interface group. The processing circuit in the first die determines whether the first address is the address corresponding to the first die. If yes, the first data is stored in the first die; otherwise, the first die transmits the first address to the next die through a second interface group.

[0169] For example, in data processing scenarios, such as data reading, the main controller can send the first address to each memory. This first address can be the address of the data storage, in order to query the location corresponding to the first address, or the corresponding memory, from each memory. Within each memory, the first address can be transmitted within each die to query the die location corresponding to the first address within the memory.

[0170] The processing circuit can match the first address with the address corresponding to the first die. If the first address is within the address range corresponding to the first die, then the first address matches the first die, and the first data corresponds to the first die.

[0171] This can be understood as follows: if the first address is within the address range corresponding to the first die, it means that the location indicated by the first address is in the first die. For example, in a data reading scenario, the location of the data in the memory can first be queried based on the data's storage address, and then the data corresponding to the first address can be read from the first storage medium through the processing circuit; in a data writing scenario, the data to be stored can be written into the location corresponding to the first address.

[0172] Furthermore, a corresponding data processing mode indicator can be set for the data processing process. For example, if the first address is within the address range corresponding to the first die, the processing circuit sets the data processing mode to the first mode, which is used to indicate that data processing is performed through the first storage medium.

[0173] If the first address does not match the address of the first die, the processing circuit can output the first address through the second interface group, that is, transmit the first address to other transmission medium layers or other memories, so that the die corresponding to the first address can be determined later.

[0174] Furthermore, if the first address is not the address of the first die, the processing circuit sets the data processing mode to the second mode. The second mode is used to indicate that the first die does not match the first address, or not to perform data processing operations related to the first address on the first die, and the processing circuit corresponding to the next die continues to match the first address until a die that matches the first address is determined.

[0175] This can be understood as follows: before storing specific data, a data processing mode can be set for each die to indicate whether data should be written to each die during the current data processing process. For example, for each die, a mode for the current data processing can be set, such as Bypass mode and Termination mode. If the first address matches the address of the current die, the mode is set to Termination, indicating that data is written through the current die; if the first address does not match the address of the current storage medium, the mode is set to Bypass, indicating that the first address is not matched with the address of the first die, and so on.

[0176] For example, in conjunction with the aforementioned memory, the specific data flow can be as follows: Figure 16 As shown, after receiving an address, die 1 uses processing circuitry to determine if the address matches the address of die 1. If they match, it is set to Termination mode, and propagation of the address to the next die is interrupted. Die 1 then performs subsequent data processing on that address. If the address does not match the address of die 1, it can be set to Bypass mode, and the address is propagated to die 2 to continue matching the address with the address of die 2, and so on, until the die corresponding to the first one is determined.

[0177] Therefore, in this embodiment, processing circuitry and multiple I / O interfaces are incorporated into the die, enabling it to possess signal processing and data input / output capabilities. This reduces the load on the main controller and prevents a decrease in memory link speed due to excessive main controller load. In other words, compared to existing solutions that increase memory capacity by adding dies, the memory and method provided in this embodiment distribute the management overhead of the main controller over multiple dies in existing solutions. Steps originally executed by the main controller are distributed to the processing circuitry of each die, thereby avoiding the problem of decreased link speed and capacity-bandwidth ratio caused by excessive main controller overhead.

[0178] In addition to the aforementioned data storage, other operations can be performed within the memory, such as data deletion or retrieval. In the case of data deletion or retrieval, similar to the data storage process described above, the instruction to delete or retrieve data is passed layer by layer through each die until it reaches the corresponding die. For example, before deleting or retrieving data, the address corresponding to the data needs to be determined. The method of passing this address is similar to the aforementioned first address passing process. After the corresponding die is determined, the die can then delete or retrieve the stored data. In the case of data retrieval, the die can send the retrieved data to the main controller via the link between the die and the main controller.

[0179] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0180] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. The term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps in this application does not imply that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effect can be achieved. The division of modules in this application is a logical division. In actual applications, there may be other division methods. For example, multiple modules may be combined into or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the modules shown or discussed may be through some ports, and the indirect coupling or communication connection between modules may be electrical or other similar forms, which are not limited in this application. Furthermore, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules. Some or all of the modules can be selected to achieve the purpose of the solution in this application according to actual needs.

Claims

1. A memory, characterized in that, The memory includes a plurality of dies, including a first die, and the plurality of dies are connected to each other via an interface. The first die includes multiple sets of interfaces, including a first interface group and a second interface group. The first interface group is the input and output interface of the first die, and the second interface group is the input and output interface of the first die. When the first interface group is used as an interface for input data, the second interface group is used as an interface for output data; when the first interface group is used as an interface for output data, the second interface group is used as an interface for input data.

2. The memory according to claim 1, characterized in that: The first interface group and the second interface group communicate via in-die transistors.

3. The memory according to claim 1, characterized in that: The communication structure within the die is a transistor.

4. The memory according to any one of claims 1-3, characterized in that, The plurality of dies are connected in series. The plurality of dies also includes a second die and a third die. The second die includes a third interface group and a fourth interface group. The third interface group is connected to the second interface group, and the fourth interface group is connected to a set of interfaces of the third die.

5. The memory according to claim 4, characterized in that, When the first die is located at the position where the media particle containing the first die is connected to the outside in the memory, the first interface group is connected to the main controller of the memory, and the second interface group is connected to the second die in the memory.

6. The memory according to any one of claims 1-5, characterized in that, The first die also includes processing circuitry for: Determine whether the first data received by the first die through the first interface group corresponds to the first die; When the first data corresponds to the first die, the first die is used to store the first data; When the first data does not correspond to the first die, the first die is used not to store the first data and outputs the first data through the second interface group.

7. The memory according to claim 6, characterized in that, The processing circuit is specifically used for: The first address is matched with the address of the first die to determine whether the first data corresponds to the first die. The first address is associated with the first data. The first address is received by the first die through the first interface group. Wherein: when the first address matches the address of the first die, the first data corresponds to the first die; when the first address does not match the address of the first die, the first data does not correspond to the first die.

8. The memory according to claim 7, characterized in that, The processing circuit is also used for: When the first address is the address corresponding to the first die, the processing circuit sets the data processing mode to the first mode, which is used to indicate that the first data is stored in the first die when the first data is received. If the first address is not the address corresponding to the first die, then the first die is used to output the first address through the second interface group.

9. The memory according to any one of claims 1-7, characterized in that, The memory is either a solid-state drive (SSD) or a universal flash storage (UFS).

10. A memory, characterized in that, include: The main controller is used to manage multiple dies connected in series. Among the multiple dies, one of the adjacent dies is connected to the adjacent previous die through one interface group and to the adjacent next die through another interface group; wherein, the interface of the die is used for input data and output data.

11. The memory according to claim 10, characterized in that, include: Different interface groups within the same die communicate with each other via transistors within the die.

12. The memory according to claim 11, characterized in that, The first die of the plurality of dies is connected to the main controller via a first interface group and to the second die via a second interface group. The first die is used for: Receive first data from the main controller through the first interface group; Data stored in the first die is stored; and data not stored in the first die is forwarded to the second die via the second interface group.

13. The memory according to claim 12, characterized in that, The first die is also used for: The first data is forwarded between the first interface and the second interface via the transistors within the first die.

14. The memory according to any one of claims 10-13, characterized in that, The plurality of dies includes a first die, a second die, and a third die; The first die includes a first processing circuit, a first interface group and a second interface group, the second die includes a second processing circuit, a third interface group and a fourth interface group, the second interface group of the first die is connected to the third interface group of the second die, and the fourth interface group is connected to one of the interface groups of the third die. The first die receives first data through the first interface group. The first data is the data output by the main controller to the plurality of dies. When the first processing circuit detects that the first data corresponds to the first die, the first die is used to store the first data. When the first processing circuit detects that the first data does not correspond to the first die, the first die is used to forward the first data to the second die through the second interface group. When the second die receives the first data through the third interface, if the second processing circuit detects that the first data corresponds to the second die, the second die is used to store the first data; if the second processing circuit detects that the first data does not correspond to the second die, the second die is used to forward the first data to the third die through the third interface.

15. The memory according to claim 14, characterized in that, The first processing circuit is specifically used for: The system detects whether the first data corresponds to the first die by determining whether the first address matches the address corresponding to the first die. The first address is the address of the first data.

16. The memory according to any one of claims 10-15, characterized in that, The memory is either a solid-state drive (SSD) or a universal flash storage (UFS).

17. A data processing method, characterized in that, Applied to a memory, the memory includes multiple dies including a first die, and the multiple dies are connected to each other through an interface. The first die includes a processing circuit, a first interface group and a second interface group. The method includes: The first die receives first data through the first interface group; if the processing circuit detects that the first data corresponds to the first die, the first die stores the first data. If the processing circuit detects that the first data does not correspond to the first die, the first die will not store the first data and will output the first data through the second interface group therein.

18. The method according to claim 17, characterized in that, The first die includes a first interface group and a second interface group, and the method further includes: The processing circuit determines whether the first data corresponds to the first die by matching the first address with the address of the first die. The first address is associated with the first data, and the first address is received by the first die through the first interface group. Wherein: when the first address matches the address of the first die, the first data corresponds to the first die; when the first address does not match the address of the first die, the first data does not correspond to the first die.

19. The method according to claim 18, characterized in that, The method further includes: If the first address is the address corresponding to the first die, the processing circuit sets the data processing mode to the first mode, which is used to indicate that the first data is stored in the first die when the first data is received. If the first address is not the address corresponding to the first die, then the first die outputs the first address through the second interface group.

20. The method according to claim 19, characterized in that, The method further includes: If the first address is not the address corresponding to the first die, the processing circuit sets the data processing mode to the second mode, which is used to indicate that the first die does not store the first data.

21. A data processing method, characterized in that, Applied to a memory, the memory includes a main controller and a plurality of dies connected in series. In adjacent dies, one die is connected to the adjacent previous die through an interface group and to the adjacent next die through another interface group. The method includes: The main controller sends first data to the plurality of dies, and transmits the first data to the dies corresponding to the first data for storage through the serial channel between the plurality of dies.

22. The method according to claim 21, characterized in that, The plurality of dies includes a first die, a second die, and a third die; The first die includes a first processing circuit, a first interface group and a second interface group, the second die includes a second processing circuit, a third interface group and a fourth interface group, the first interface group of the first die is connected to the third interface group of the second die, and the third interface group is connected to one of the interface groups of the third die. The method specifically includes: The first die receives first data through the first interface group. The first data is the data output by the main controller to the plurality of dies. When the first processing circuit detects that the first data corresponds to the first die, the first die stores the first data. When the first processing circuit detects that the first data does not correspond to the first die, the first die forwards the first data to the second die through the second interface group. When the second die receives the first data through the third interface, if the second processing circuit detects that the first data corresponds to the second die, the second die is used to store the first data; if the second processing circuit detects that the first data does not correspond to the second die, the second die is used to forward the first data to the third die through the third interface.

23. The method according to claim 22, characterized in that, The method specifically includes: The first processing circuit detects whether the first data corresponds to the first die by determining whether the first address matches the address corresponding to the first die. The first address is the address of the first data.

Images