Control method, control device, compute-in-memory system and electronic device

Abstract

The application provides a control method, a control device, a storage-computing system and an electronic device. The control method comprises: inputting a first data sequence to a first storage array of a storage circuit, the first data sequence being used for first computation of the first storage array; and controlling reading of a computation result of the first computation according to the first data sequence and a second data sequence, wherein the second data sequence is previous input of the first storage array adjacent to the first data sequence. The reading time of the current computation result of the first storage array is dynamically adjusted according to the input data sequences adjacent to each other in the first storage array, the flexibility of reading of the computation result of the first storage array is improved, and the reading efficiency of the storage circuit is further improved, while the accuracy of reading of the computation result is taken into account, so that the reliability and efficiency of the computing performance of the storage-computing integrated architecture are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a control method, control device, memory computing system, and electronic device. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their computational performance still needs improvement. Summary of the Invention

[0004] This application provides a control method, control device, in-memory computing system, and electronic device that can improve the computing performance of in-memory computing architecture.

[0005] In a first aspect, a control method is provided, comprising: inputting a first data sequence into a first storage array of a storage circuit, the first data sequence being used for a first calculation of the first storage array; controlling the reading out of the calculation result of the first calculation based on the first data sequence and a second data sequence; wherein the second data sequence is a previous input of the first storage array adjacent to the first data sequence.

[0006] Based on the two consecutive input data sequences used for computation in the first storage array, the read time of the current computation result of the first storage array is dynamically adjusted, thereby improving the flexibility of reading the computation result of the first storage array, which in turn helps to speed up the read efficiency of the storage circuit, while taking into account the accuracy of the computation result read, so that the computation performance of the in-memory computing architecture can be improved in both reliability and efficiency.

[0007] In some implementations of the first aspect, controlling the reading of the calculation result of the first calculation according to the first data sequence and the second data sequence includes: controlling the reading time of the calculation result of the first calculation according to the first data sequence and the second data sequence.

[0008] In some implementations of the first aspect, the readout time includes the start or completion time of the first transformation of the computation result.

[0009] In some implementations of the first aspect, the readout time also includes the start or completion time of the second transformation of the computation result.

[0010] In some implementations of the first aspect, controlling the reading of the calculation result of the first calculation according to the first data sequence and the second data sequence includes: determining a first time according to the first data sequence and the second data sequence; and controlling the completion time of the first transformation of the calculation result to be no earlier than the end time of the first time.

[0011] In some implementations of the first aspect, controlling the reading of the calculation result of the first calculation based on the first data sequence and the second data sequence includes: determining a first time based on the first data sequence and the second data sequence; and controlling the initiation of a second transformation of the calculation result when the first time expires.

[0012] In some implementations of the first aspect, determining the first time based on the first data sequence and the second data sequence includes: determining a first difference value between the first data sequence and the second data sequence; and determining the first time based on the first difference value.

[0013] In some implementations of the first aspect, determining the first time based on the first difference value includes: determining the first time based on the first difference value and a mapping relationship, wherein the mapping relationship includes a first correspondence relationship or a second correspondence relationship, wherein the first correspondence relationship includes a correspondence relationship between multiple difference values ​​and multiple times, the second correspondence relationship includes a correspondence relationship between multiple difference value ranges and multiple times, the first time is the first time corresponding to the first difference value among the multiple difference values ​​in the first correspondence relationship, or the first time is the first time corresponding to the first difference value range in the second correspondence relationship, and the first difference value is located within the first difference value range.

[0014] In some implementations of the first aspect, in the first correspondence, among multiple difference values, the larger the difference value, the longer the corresponding time; or, in the second correspondence, among multiple difference value ranges, the larger the boundary value, the longer the corresponding time.

[0015] In some implementations of the first aspect, when the first time expires, a third data sequence is input to the first storage array, and the third data sequence is used for a second calculation of the first storage array.

[0016] In some implementations of the first aspect, the setup for the next computation can begin during the decision-making process of the current computation in the first storage array.

[0017] In some implementations of the first aspect, the first time of the second computation overlaps at least partially with the time of the second transformation of the result of the first computation.

[0018] In some implementations of the first aspect, the total value of valid values ​​in the first data sequence does not exceed a valid value threshold.

[0019] In some implementations of the first aspect, the control method further includes: acquiring a data sequence to be input, wherein the total value of valid values ​​in the data sequence exceeds a valid value threshold; converting the data sequence to be input into at least two data sequences and inputting them into a first storage array, wherein the at least two data sequences include the first data sequence.

[0020] In some implementations of the first aspect, converting the input data sequence into at least two data sequences includes: converting the input data sequence into at least two data sequences based on the distribution of valid values ​​in the input data sequence.

[0021] In some implementations of the first aspect, the total value of valid values ​​in at least two data sequences does not exceed a valid value threshold.

[0022] In some implementations of the first aspect, at least two data sequences have the same length as the input data sequence and include a portion of the input data sequence as well as padding with zeros.

[0023] In some implementations of the first aspect, when the reading of the result of the first calculation is completed, an indicator signal is used to indicate the end of the reading of the calculation result or to indicate the availability of the read data.

[0024] In some implementations of the first aspect, the storage circuit further includes a second storage array, the first storage array and the second storage array adopt the same control timing, and the control method further includes: inputting a fourth data sequence to the second storage array, the fourth data sequence being used for a third calculation of the second storage array; controlling the reading out of the calculation results of the first calculation and the calculation results of the third calculation according to the first data sequence, the second data sequence, the fourth data sequence and the fifth data sequence; wherein, the fifth data sequence is the previous input of the second storage array adjacent to the fourth data sequence.

[0025] In a second aspect, a control device is provided, comprising: an interface circuit for communicating with a storage circuit; and at least one processing circuit for executing any of the control methods described in the first aspect above.

[0026] In some implementations of the second aspect, the interface circuitry includes a readout circuit.

[0027] Thirdly, a storage computing system is provided, comprising: a storage circuit; and a control device electrically connected to the storage circuit for executing any of the control methods described in the first aspect above.

[0028] Fourthly, an electronic device is provided, including the in-memory computing system described in the third aspect above.

[0029] Fifthly, a computer program product is provided, the computer program product including instructions that, when executed by a processor, cause any of the control methods of the first aspect above to be executed.

[0030] In a sixth aspect, a computer-readable medium is provided that stores instructions which, when executed by a processor, cause any of the control methods of the first aspect above to be performed. Attached Figure Description

[0031] Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0032] Figure 2 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0033] Figure 3 A schematic diagram of a storage circuit provided according to an exemplary embodiment of this application is shown.

[0034] Figure 4 A control timing diagram according to an exemplary embodiment of this application is shown.

[0035] Figure 5 A schematic diagram of a control method provided according to an exemplary embodiment of this application is shown.

[0036] Figure 6 A schematic diagram illustrating the time relationship between a first storage array calculation, a first conversion, and a second conversion provided according to an exemplary embodiment of this application is shown.

[0037] Figure 7 A schematic diagram illustrating the time relationship between another first storage array calculation, first conversion, and second conversion provided according to an exemplary embodiment of this application is shown.

[0038] Figure 8 A schematic diagram illustrating the time relationship between different memory array calculations, a first conversion, and a second conversion of a memory circuit provided according to an exemplary embodiment of this application is shown.

[0039] Figure 9A schematic diagram of a first data sequence provided according to an exemplary embodiment of this application is shown.

[0040] Figure 10 A schematic diagram of an input data sequence provided according to an exemplary embodiment of this application is shown.

[0041] Figure 11 A schematic diagram is shown of an input data sequence and two data sequences to be converted, provided according to an exemplary embodiment of this application.

[0042] Figure 12 A schematic diagram of another storage circuit provided according to an exemplary embodiment of this application is shown.

[0043] Figure 13 A schematic diagram of another control device according to an exemplary embodiment of this application is shown.

[0044] Figure 14 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0045] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0046] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0047] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0048] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0049] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0050] In in-memory computing technology, storage and computation (or operation) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read out or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0051] For ease of understanding, Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. This in-memory computing system is described as an example of implementing in-memory computation using memory as a carrier.

[0052] like Figure 1As shown, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0053] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0054] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication calculation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0055] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and a readout circuit 140. The input circuit 130, under the control of the control circuit 120, provides an input signal Sin to the storage circuit 110, whereby the input signal Sin can carry input data d1. The storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data. The readout circuit 140, under the control of the control circuit 120, converts the output signal Sout into output data d2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0056] As an example, Figure 2 A schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application is shown.

[0057] like Figure 2 As shown, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij , where i [1,m],j [1, n], where m is the number of rows in the storage cell array and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data w ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula: .

[0058] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. Input circuitry 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal for supply to memory cell array 210. In some possible embodiments, the input signal to memory cell array 210 may include a digital signal, represented by waveform characteristics such as pulse width, amplitude, or area. Input circuitry 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to memory cell array 210.

[0059] In some possible embodiments, the readout circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more of the following: signal type conversion, signal magnitude conversion, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the readout circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Exemplarily, the first conversion performed by the readout circuit 240 may also be referred to as sampling.

[0060] For example, the readout circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. Exemplarily, the second conversion performed by the readout circuit 240 may also be referred to as a decision. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert an analog signal into a digital signal for provision to subsequent circuits. Furthermore, the readout circuit may include a sense amplifier (SA), which can sense, amplify, etc., the signal obtained from the memory cell array 210 or the first conversion circuit 241. Figure 2 In the example, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0061] Figure 2This is merely an example illustrating a connection method of storage cells in a storage cell array 210, except... Figure 2 Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells can be connected in columns along a common line, and the output terminals of the memory cells can be connected in rows along a common line. Furthermore, the input terminals of the memory cells can include the gate of a transistor memory device, or the input terminals of the memory cells can include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell can include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal oxide semiconductor field-effect transistors (MOSFETs), floating gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors. A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0062] Figure 3 A schematic diagram of a storage circuit provided according to an exemplary embodiment of this application is shown. Figure 3 As shown, the storage circuit 300 may include multiple sets of storage cells, which may be, for example... Figure 3 The diagram shows storage planes or banks arranged along the second direction. In the following description, the storage cell set is illustrated using a storage plane as an example, but is not limited to this; the storage cell set can be replaced by a storage bank. For example, storage circuit 300 may include storage cell sets plane_0 to plane_a, where a is a positive integer greater than or equal to 1. For ease of illustration of the structure of the storage cell set, the extensions of storage cell sets plane_1 to plane_a in the third direction are omitted, so that the structure of the storage cell set is shown through plane_0.

[0063] In some possible implementations, a set of storage cells may include multiple subsets of storage cells; for example, a subset of storage cells may be a storage block, such as... Figure 3 The diagram shows multiple storage blocks arranged along a first direction within a set of storage cells. For example, the set of storage cells plane_0 may include subsets of storage cells block_0 to block_b, where b is an integer greater than or equal to 1.

[0064] In some possible implementations, a subset of storage cells may include multiple arrays, which may be stacked along a third direction, and the storage cells in one array may be arranged along a first direction and a second direction. That is, the subset of storage cells may include multiple arrays, which may include two-dimensional arrays, the arrangement directions of which include the first direction and the second direction, and the multiple arrays are stacked in a third direction. For ease of illustration, Figure 3 The diagram only shows the structure of the array in block 0 of plane_0. The arrangement of storage cells in other storage cell subsets can be referenced from block 0 of plane_0.

[0065] For example, in a subset of storage cells, storage cells located at the same coordinate (layer or position) in a third direction can be connected by the same word line. That is, a word line can control the on or off of an array in a subset of storage cells.

[0066] For example, in a storage cell set, storage cells located at the same coordinate (layer or location) in a third-order direction can be connected via the same word line. According to some embodiments, a single word line can control the activation or deactivation of a layer of storage cells within a storage cell set. This layer of storage cells comprises multiple arrays, each belonging to a different subset of storage cells within the storage cell set.

[0067] For example, such as Figure 3 As shown, the storage circuit 300 can include word lines wl_0 to wl_c along a third direction, where c is an integer greater than or equal to 1; these word lines can be used to enable or disable storage cells in the corresponding layer within the storage cell set. Taking w1_1 as an example, array_1 in storage cell set plane_0 is enabled through w1_1. Array_1 can be called a sub-storage unit. Figure 3 As shown, array_1 includes multiple arrays, which belong to the storage cell subsets block_0 to block_b respectively.

[0068] For example, the memory cell set also has a plurality of output signal lines arranged along a second direction, each output signal line extending along a first direction. Taking array_1 as an example, the plurality of memory cells in array_1 that have the same coordinates (positions) in the second direction and are arranged along the first direction can be connected to the same output signal line, and the output current of these memory cells can be output through the same output signal line.

[0069] During a storage and calculation process, the current signal on the output signal line undergoes a process from change to stabilization; this process is also called signal setup. To improve the accuracy of reading the storage and calculation results, the current signal is only read after it has stabilized.

[0070] The control circuit 120 / 220 can control the timing of the readout circuit 140 / 240 to convert the output signal of the storage circuit or storage cell array (hereinafter referred to as storage array). It can also be understood that the control circuit 120 can control the timing of the readout circuit 140 / 240 to read the output signal.

[0071] Figure 4 As an example of a control timing diagram, the control circuit 120 can be configured as follows: Figure 4 The control timing periodically controls the readout circuit to read the output signal. For example... Figure 4 As shown, the duration of one cycle is T. The readout process within one cycle includes the setup phase, the sampling phase, and the decision phase.

[0072] The period from t21 to t22 is the setup phase. After this phase, the memory array generates a stable current signal on the output signal line. For example... Figure 2 In this embodiment, the memory cell array 210 and the readout circuit 240 are connected via an output signal line. The current signal output by the memory cell array 210 is provided to the readout circuit 240 through the output signal line. The current signal undergoes a process from change to stability, which is called signal setup. The current in the current signal may flow from the readout circuit 240 to the memory cell array 210 or from the memory cell array 210 to the readout circuit 240; this embodiment does not impose any limitations on this.

[0073] The sampling phase occurs from time t22 to t23. During this phase, control circuit 220 controls readout circuit 240 to perform a first conversion on the current signal output by the storage array. For example, control readout circuit 240 to convert the current signal into a voltage signal.

[0074] The period from t23 to t24 is the decision-making stage. During this stage, the control circuit 220 controls the readout circuit 240 to perform a second conversion on the result of the first conversion. For example, if the readout circuit 240 converts the current signal into a voltage signal in the first conversion, then in the decision-making stage, the control circuit 240 converts the analog voltage signal into a digital signal.

[0075] By setting the duration of the setup phase in the control timing, such as... Figure 4 The time interval between t21 and t22 ensures that the current signal output by the storage circuit is stable when the readout circuit 240 converts the output signal of the storage circuit. This improves the reliability of the calculation results and enhances the computing performance of the in-memory computing architecture.

[0076] In in-memory computing operations, for the same group of memory cells, due to the capacitive coupling effect, different input data will result in different times for a stable current signal to form on the output signal line. Using the longest time to achieve a stable current signal output in the control timing can ensure that the current signal output by the memory circuit is in a stable state when the read circuit performs output signal conversion, improving the reliability of the computation result read and thus improving the computing performance of the in-memory computing architecture. However, this will reduce the read efficiency of the memory circuit, thereby affecting the overall computing efficiency of the in-memory computing architecture and its computational performance.

[0077] This application provides a control method that can dynamically control the conversion timing during the reading process of calculation results, thereby improving the flexibility of reading calculation results from the storage array, accelerating the reading efficiency of the storage circuit, and taking into account the accuracy of reading calculation results, so that the computing performance of the in-memory computing architecture can be improved in both reliability and efficiency.

[0078] For example, Figure 5 A schematic diagram of a control method 500 provided according to an exemplary embodiment of this application is shown. The control method 500 can be executed by a control device, for example, the control device includes... Figure 1 or Figure 2 The control circuit 120 / 220 shown is shown.

[0079] like Figure 5 As shown, the control method 500 may include the following steps S510 and S520.

[0080] S510, input a first data sequence to the first storage array of the storage circuit, the first data sequence being used for the first calculation of the first storage array.

[0081] S520, based on the first data sequence and the second data sequence, control the reading out of the calculation result of the first calculation. The second data sequence is the previous input of the first storage array adjacent to the first data sequence.

[0082] In the control method provided in this application embodiment, the reading of the current calculation result of the first storage array is dynamically controlled according to the two adjacent input data sequences of the first storage array, thereby improving the flexibility of reading the calculation result of the first storage array, which in turn helps to speed up the reading efficiency of the storage circuit, while taking into account the accuracy of the calculation result reading, so that the computing performance of the in-memory computing architecture can be improved in both reliability and efficiency.

[0083] In some embodiments of this application, the storage circuit may include multiple storage arrays, and inputting a first data sequence into a first storage array of the storage circuit may include inputting a data sequence into any storage array of the storage circuit. For example, a storage array represents an in-memory computation unit, including the storage cells used to perform one computation operation. Depending on the storage circuit structure and application scenario, the storage array may have different partitioning methods. For example, it may include the aforementioned single layer of storage cells, or it may include arrays within one or more subsets of storage cells. When a storage array includes arrays within multiple subsets of storage cells, these arrays may be located on the same layer or in the same position in a third-party direction. This application does not impose further limitations on this aspect.

[0084] The above calculation results can be characterized by the signals output collinearly by the memory cell groups. The output lines where all memory cells in a memory cell group are coupled can be called signal output lines. The memory array can include multiple signal output lines. The above calculation results can include signals output by one signal output line, or signals output by multiple signal output lines. For example, in step S510 above, the first data sequence can be input to the first memory array in the form of a voltage signal.

[0085] For example, the length of the first data sequence does not exceed the number of positions of the first storage array in the first direction, that is, it does not exceed the number of storage cells of the first storage array in the first direction.

[0086] For example, the first data sequence includes 128 elements, and the first storage array has not less than 128 locations or storage cells in the first direction. The first data sequence is input into the first storage array along the first direction, wherein the i-th element is input into the i-th location in the first direction, and i is any integer between 1 and 128.

[0087] At the i-th position, multiple storage cells are arranged along the second direction. These storage cells can perform calculations on the i-th element and output the calculation result in the form of current. For ease of description, assume that the positions of the first storage array in the first direction are described by integers ranging from 0 to 127. Taking the storage cell with position 1 in both the first and second directions (referred to as storage cell 11 for ease of description) as an example, storage cell 11 performs calculations on the second element of the first data sequence and outputs the calculation result in the form of current to the output signal line (referred to as output signal line BL1 for ease of description). Similarly, the storage cell with position 2 in the first direction and position 1 in the second direction (referred to as storage cell 21 for ease of description) performs calculations on the third element of the first data sequence and outputs the calculation result in the form of current to the output signal line BL1.

[0088] For example, one element in the first data sequence can represent one bit of data, and for example, the value of one bit of data can be 0 or 1.

[0089] In this embodiment, the reading of the calculation result of the first calculation is controlled according to a first data sequence and a second data sequence. The second data sequence is the previous input of the first storage array adjacent to the first data sequence.

[0090] For example, multiple calculations can be performed by specifying a single storage array at a time, and the data sequences input to the storage array for different calculations can be the same or different. For instance, if the storage array is a first storage array, calculations can be performed continuously on a first data sequence and a second data sequence using the first storage array. The first and second data sequences can be the inputs for two adjacent calculations within the multiple calculations. This implementation method can save instructions sent to the storage circuit and also improves the computational efficiency of the storage circuit.

[0091] For example, reading out the calculation result includes a first transformation of the calculation result. For example, the calculation result of the first calculation is output in the form of a current signal, and the first transformation includes converting the calculation result of the first calculation from a current signal to a voltage signal. Converting the calculation result to a voltage signal facilitates subsequent processing of the calculation result by the processing circuit. For example, the first transformation can be performed via... Figure 2 The first conversion circuit 241 shown is implemented in this embodiment. In this embodiment, the first conversion can also be referred to as sampling.

[0092] For example, reading out the calculation result includes a second transformation of the result, such as performing a second transformation on the output of the first transformation. This allows the output format of the calculation result to be matched with subsequent processing circuitry. For example, the second transformation includes converting the voltage signal obtained from the first transformation from an analog signal to a digital signal. This second transformation enables subsequent digital circuitry to continue processing the calculation result. For example, the second transformation can be performed via… Figure 2 The second conversion circuit 242 shown is implemented in this embodiment. In this embodiment, the second conversion can also be referred to as a decision.

[0093] In some possible implementations, the readout time of the computation result of the first computation can be controlled based on the first data sequence and the second data sequence. This readout time may include the timing of transitions during the readout process, such as the start or end time of at least one of the first and second transitions. By controlling the readout time, a period of waiting can be allowed before reading the computation result, allowing the current signal on the output signal line to stabilize before reading the result. This improves the accuracy of the readout result and thus enhances the reliability of the in-memory computing architecture.

[0094] The first data sequence is the data input to the first storage array after the second data sequence. For example, the second data sequence is input to the first storage array to obtain the result of the operation, which includes a current signal on an output signal line of the first storage array (referred to as current signal 2 for ease of description). Then, the first data sequence is input to the first storage array to obtain the result of the operation, which includes a current signal on the same output signal line of the first storage array (referred to as current signal 1 for ease of description). The result of the operation of the first data sequence (current signal 1) will vary based on the result of the operation of the second data sequence (current signal 2). The first and second data sequences are related to the establishment process of current signal 1.

[0095] This application embodiment controls the readout time of the calculation result of the first calculation based on the first data sequence and the second data sequence. Using this implementation, the readout time can be dynamically controlled. Compared to setting a uniform maximum waiting time (e.g., including a maximum time establishment phase), this application embodiment can reduce the waiting time in some scenarios, which is beneficial to improving the readout efficiency of the storage circuit, thereby improving the computational efficiency and enhancing the computational performance of the in-memory computing architecture.

[0096] For example, the reading of the calculation result of the first calculation can be controlled in the following way: The first time is determined based on the first data sequence and the second data sequence.

[0097] The completion time of the first transition is controlled to be no earlier than the end time of the first time.

[0098] In this embodiment of the application, a first time can be determined based on a first data sequence and a second data sequence. During this first time, the output signal on the output signal line of the first storage array can be stably established and maintained to maintain its stable output until the first conversion (or sampling) of the output signal is completed.

[0099] For example, when a first data sequence is input into the first storage array, a current signal representing the calculation result is output on the signal output line of the first storage array. This current signal reaches stability after a setup phase. Maintaining the input of the first data sequence allows the output current signal to be maintained until the first conversion of the current signal is completed. This first conversion process can be called the sampling phase.

[0100] For ease of distinction and description, the above first time can also be referred to as the first setup time. During the first setup time, the output signal can be established and maintained to achieve the first conversion (or sampling) of the output signal.

[0101] This application embodiment determines a first time by using a continuously input data sequence. This first time is used for timing control of the first conversion, and the start or end time of the first conversion can be dynamically controlled. This allows the waiting time before the first conversion to be flexibly adjusted based on the input data. Compared to controlling the timing of the first conversion based on the longest setup phase, this first time can include a setup phase with dynamically changing duration. This is equivalent to a setup time that can dynamically change according to the duration set by the continuously input data sequence. This setup time can be used to establish the output signal and perform sampling. This can improve the read efficiency of the storage circuit while ensuring the accuracy of the calculation result read, thus improving both the reliability and efficiency of the computing performance of the in-memory computing architecture.

[0102] For example, Figure 6 This illustration shows a schematic diagram of the time relationship between a first storage array calculation, a first conversion, and a second conversion according to an exemplary embodiment of this application. For example, as... Figure 6 As shown, the completion time of the first conversion can be controlled to align with the end time of the first time period, or the second conversion can be controlled to start when the first time period expires. Figure 6 In the timeline shown, the entire time period of the first transformation overlaps with the first time. This maximizes the utilization of the first time, enabling efficient and reliable result retrieval.

[0103] In another example, the first transition can be controlled based on the end time of the setup phase. For example, Figure 7A schematic diagram illustrating the time relationship between another first storage array calculation, first conversion, and second conversion provided according to an exemplary embodiment of this application is shown. For example, as Figure 7 As shown, at the end of the setup phase (or after), control the first transition.

[0104] In some embodiments of this application, the time of the setup phase can be determined based on a continuously input data sequence, and the reading of the current calculation result can be controlled based on the time of the setup phase. The determination of the setup phase time is similar to the determination of the first time; the method for determining the setup phase time can refer to the method for determining the first time, and will not be elaborated further. For example, a first or second correspondence can be established between the difference values ​​of the data sequence and the time of the setup phase, and the time of the setup phase can be determined based on the first or second correspondence.

[0105] When controlling the reading of computation results, the timing of transformations during the reading process can be dynamically controlled based on a defined setup phase time. For example, when the setup phase time expires, the start of the first transformation can be controlled.

[0106] In this way, the reading of the current calculation result of the first storage array can be dynamically controlled according to the two adjacent input data sequences of the first storage array, thereby improving the flexibility of reading the calculation result of the first storage array, which in turn helps to speed up the reading efficiency of the storage circuit, while taking into account the accuracy of the calculation result reading, so that the computing performance of the in-memory computing architecture can be improved in both reliability and efficiency.

[0107] As mentioned above, after performing a first transformation on the result of the first calculation, a second transformation can be performed on the result of the first transformation. For example, the next calculation of the first storage array can also be performed in parallel during the transformation.

[0108] For example, Figure 8 This diagram illustrates the time relationship between different memory array calculations, a first conversion, and a second conversion in a memory circuit according to an exemplary embodiment of this application. The memory circuit includes multiple memory arrays, with memory arrays A1 and A2 as examples. Based on the current input data sequence and the previous input data sequence of memory array A1, a first time for the current calculation of C11 is determined. Based on this first time, the end time of the first conversion can be controlled to be no earlier than the end time of the first time of the current calculation of C11; for example, the two can be aligned. This allows the second conversion to start quickly when the first time expires, and the next calculation (e.g., calculation of C12) to start simultaneously. This further improves computational efficiency, thereby enhancing the computational performance of the in-memory computing architecture.

[0109] For example, at the end of the first conversion, a third data sequence is input to the first storage array. This third data sequence is used for the second calculation of the first storage array. After the first conversion is completed, the calculation result of the first storage array on the first data sequence is converted into a voltage signal. At this point, the current signal on the output signal line can no longer be maintained, allowing for the next calculation to be performed efficiently, thus utilizing the computing power of the first storage array. For example, the establishment phase of the output signal corresponding to the calculation result of the second calculation can at least partially overlap with the time of the second conversion of the calculation result of the first calculation, or in other words, the first time of the second calculation, for example... Figure 8 The first time of calculating C12 can at least partially overlap with the time of the second transformation of the result of calculating C11. Thus, the parallelism of the second transformation and signal establishment through the two calculations improves the overall computational and read efficiency of the memory circuit. Optionally, the start time of calculating C12 can be aligned with the start time of the second transformation of the result of calculating C11. This maximizes the utilization of the second transformation time, preparing for the next round of second transformation, further improving the computational performance of the in-memory computing architecture. It also allows memory arrays A1 and A2 to reuse the hardware resources of the first and second transformations, reducing the hardware overhead of the in-memory computing architecture.

[0110] In some embodiments of this application, different memory arrays can share the hardware resources of the readout circuit. For example, memory array A1 and memory array A2 can share the hardware resources of the readout circuit. Memory array A1 can perform pre-establishment during the first time of calculating C11. After pre-establishment, memory array A2 is switched to perform pre-establishment. During the first time of calculating C11, memory array A1 achieves stable establishment of the output signal based on the pre-establishment, and then performs the first conversion. Similarly, during the first time of calculating C21, memory array A2 performs pre-establishment. After pre-establishment, memory array A1 is switched to perform pre-establishment; during the first time of calculating C21, memory array A2 achieves stable establishment of the output signal based on the pre-establishment, and then performs the first conversion. In this way, memory arrays A1 and A2 can reuse the hardware resources of the first and second conversions, and can further improve readout efficiency.

[0111] As mentioned above, embodiments of this application can determine a first time based on a first data sequence and a second data sequence. For example, the calculation result of the first data sequence includes current signal 1, and the calculation result of the second data sequence includes current signal 2. Since the first data sequence and the second data sequence are two consecutive input data of the first storage array, current signal 1 can be established based on current signal 2.

[0112] The first and second data sequences are related to the establishment process of current signal 1.

[0113] For example, the greater the difference between the first data sequence and the second data sequence, the greater the difference between current signal 1 and current signal 2, the longer the time from current signal 2 to current signal 1, and the longer the waiting time before reading the calculation result of the first calculation. Conversely, the smaller the difference between the first data sequence and the second data sequence, the shorter the time from current signal 2 to current signal 1, and the shorter the waiting time before reading the calculation result of the first calculation.

[0114] For example, in some embodiments of this application, determining the first time may include: determining a first difference value between a first data sequence and a second data sequence; and determining the first time based on the first difference value.

[0115] In some embodiments of this application, the first difference value can characterize the difference between the first data sequence and the second data sequence. Determining a first time based on the difference value between the currently input data sequence and the previously input data sequence in the first storage array, thereby controlling the readout timing of the current calculation result of the first storage array, is beneficial for improving the reliability of the dynamic adjustment of the readout time of the calculation result of the first storage array, and also for improving the readout efficiency of the storage circuit.

[0116] For example, the first difference value could be the Hamming distance between the first data sequence and the second data sequence.

[0117] For example, the first difference value can be the absolute value of the difference between the sum of valid values ​​between the first data sequence and the second data sequence. For example, the difference value can satisfy the following formula:

[0118] in, The sum of the valid values ​​of the nth input data sequence in the storage array. This represents the sum of the valid values ​​of the (n-1)th input data sequence in the storage array. To find the absolute value, This is the difference between the nth input data sequence and the (n-1)th input data sequence. For example, if the nth input data sequence has 128 bits, with 64 bits being 1 (valid values) and the other 64 bits being 0, then the sum of the valid values ​​of the data sequence is 64.

[0119] For the same memory array, the stored weight data does not change due to variations in the input data. The change in the input data sequence is the primary factor causing changes in the current signal on the output signal line. The greater the difference between two consecutive input data sequences, the greater the change in the current signal on the output signal line, thus making the current signal on the output signal line stabilize for a longer period. For example, if an output signal line connects to 128 memory cells, and each element of the data sequence represents 1 bit of data, then with 64 bits of value 1, 64 valid values ​​are input to a group of memory cells; with 32 bits of value 1, 32 valid values ​​are input to a group of memory cells. The difference in the input data sequence can be reflected by the difference in the number of valid values; the greater the difference in the number of valid values, the longer the current signal on the output signal line takes to establish.

[0120] During a single in-memory computation, the time required to establish the current signal on the signal output line is not fixed, but rather depends on the difference between the current input data sequence and the previous input data sequence. The greater the difference, the longer the establishment process takes. This embodiment determines the waiting time for current signal establishment and sampling during the current in-memory computation based on the difference between the previous and current input data sequences. Compared to a uniform maximum delay strategy, this embodiment improves readout efficiency, thereby enhancing the computational efficiency of the in-memory computing architecture.

[0121] In some embodiments of this application, a mapping relationship between difference values ​​or difference value ranges and time can be configured, and the reading of calculation results can be dynamically controlled using this mapping relationship. For example, determining a first time based on a first difference value includes: determining the first time based on the first difference value and the mapping relationship. The mapping relationship may include a first correspondence relationship, wherein the first correspondence relationship includes a correspondence relationship between multiple difference values ​​and multiple times, and the first time is the first time corresponding to the first difference value among the multiple difference values ​​in the first correspondence relationship.

[0122] By setting a correspondence between multiple difference values ​​and multiple times in the first storage array, during the calculation process using the first storage array, the first time corresponding to the first difference value of the first data sequence and the second data sequence can be determined according to the first relationship.

[0123] For example, there can be a one-to-one correspondence between the difference values ​​and the time. Table 1 shows an example of a first correspondence. The first correspondence shown in Table 1 includes difference values ​​D1-Dn, corresponding to times T1-Tn respectively. For example, if the difference value between the first data sequence and the second data sequence is D2, the time T2 corresponding to D2 is determined as the first time.

[0124] Table 1

[0125] In some embodiments of the present application, the time in the first correspondence may include an offset time. The time obtained by adding a reference time to the first time corresponding to the first difference value in the first correspondence is determined as the first time.

[0126] For example, Table 2 shows another example of the first correspondence. As shown in Table 2, the first correspondence includes difference values D1-Dn, and offset times ΔT1-ΔTn corresponding to the difference values D1-Dn respectively. For example, if the difference value between the first data sequence and the second data sequence is D2, and the offset time corresponding to D2 is ΔT2, the time (T0+ΔT2) obtained by adding the offset time ΔT2 to the reference time T0 is determined as the first time.

[0127] Table 2

[0128] Take the reference time T0 in Table 2 as an example.

[0129] For example, Table 3 shows another example of the first correspondence. As shown in Table 3, the first correspondence includes difference values D1-Dn, where the difference value D1 corresponds to time T1', and the difference values D2-Dn correspond to offset times ΔT2'-ΔTn' respectively. If the difference value between the first data sequence and the second data sequence is D3, D3 corresponds to the offset time ΔT3'. The time (T1' + ΔT3') obtained by adding the offset time corresponding to D3 to the time T1' is determined as the first time.

[0130] Table 3

[0131] Take the reference time in Table 3 as the time T1' corresponding to the difference value D1 as an example.

[0132] In some embodiments of the present application, in the mapping relationship, the larger the difference value, the larger the corresponding time. In this way, the magnitude of the time is set according to the magnitude of the difference between the two data sequences, which is beneficial to reading the calculation result of the first memory array efficiently and reliably.

[0133] For example, in the first correspondence shown in Table 1, if D1<D2<……<Dn, then T1<T2<……<Tn. For another example, in the first correspondence shown in Table 2, if D1<D2<……<Dn, then ΔT1<ΔT2<……<ΔTn.

[0134] In some embodiments of this application, determining a first time based on a first difference value includes: determining a first time based on a first difference value and a mapping relationship, wherein the mapping relationship may include a second correspondence relationship, wherein the second correspondence relationship includes a correspondence relationship between multiple difference value ranges and multiple times, and the first time is the first time corresponding to the first difference value range in the mapping relationship, wherein the first difference value is located within the first difference value range.

[0135] In some embodiments of this application, the second correspondence includes a correspondence between multiple ranges of difference values ​​and multiple times.

[0136] For example, Table 4 shows an example of the second correspondence. As shown in Table 4, the range of difference values ​​includes D1-Dx, Dx-Dy, ..., Dz-Dn, where x < y < z < n, and x, y, z, and n are all integers. D1-Dx corresponds to time t1, Dx-Dy corresponds to time t2, ..., Dz-Dn corresponds to time ts, where s is an integer less than n, 1 ≤ x < y < z ≤ n, and x, y, z, and n are all integers.

[0137] For the same boundary value, such as boundary value Dx, within different ranges of difference values, it can belong to a smaller range or a larger range of difference values. For example, in Table 4, the range of difference values ​​D1~Dx includes the difference value Dx, while the range of difference values ​​Dx~Dy does not include Dx; or, in Table 4, the range of difference values ​​D1~Dx does not include the difference value Dx, while the range of difference values ​​Dx~Dy includes Dx. The following tables are similar and will not be described further.

[0138] Assuming x=20 and y=40, if the difference between the first and second data sequences is D12, the time t1 corresponding to the difference range D1~Dx to which D12 belongs can be determined as the first time. If the difference between the first and second data sequences is D22, the time t2 corresponding to the difference range Dx~Dy to which D22 belongs can be determined as the first time.

[0139] Optionally, when the difference value is Dx, time t1 or t2 can be determined as the first time. The same applies to Dy and Dz, which will not be elaborated further.

[0140] Table 4

[0141] In some embodiments of this application, each difference value range in the second correspondence corresponds to an offset time. The time obtained by adding the offset time corresponding to the difference value range to which the first difference value belongs in the second correspondence to the base time is determined as the first time.

[0142] For example, Table 5 shows another example of the second correspondence. As shown in Table 5, the range of difference values ​​includes D1-Dx, Dx-Dy, ..., Dz-Dn, where 1≤x<y<z≤n, and x, y, z, and n are all integers. D1-Dx corresponds to the bias time Δt1', Dx-Dy corresponds to the bias time Δt2', ..., Dz-Dn corresponds to the bias time Δts', where s is an integer less than n.

[0143] Assuming x=20 and y=40, if the difference between the first and second data sequences is D12, the difference range D1~Dx corresponding to D12 is the offset time Δt1'. The time obtained by adding the offset time Δt1' to the base time t0' (t0'+Δt1') is determined as the first time. If the difference between the first and second data sequences is D22, the difference range Dx~Dy corresponding to D22 is the offset time Δt2'. The time obtained by adding the offset time Δt2' to the base time t0' (t0'+Δt2') is determined as the first time.

[0144] Alternatively, when the difference value is Dx, the time (t0'+△t1') or (t0'+△t2') can be determined as the first time. The same applies to Dy and Dz, which will not be elaborated further.

[0145] Table 5

[0146] Take t0' as the base time in Table 5 as an example.

[0147] For example, Table 6 shows another example of the second correspondence. As shown in Table 6, the range of difference values ​​includes D1-Dx, Dx-Dy, ..., Dz-Dn, where 1≤x<y<z≤n, and x, y, z, and n are all integers. D1-Dx corresponds to time t1'', ​​Dx-Dy corresponds to bias time Δt2'', ..., Dz-Dn corresponds to bias time Δts'', where s is an integer less than n.

[0148] Assuming x=20 and y=40, if the difference between the first and second data sequences is D34, the difference range Dx-Dy corresponding to D34 is the offset time Δt2''. The time obtained by adding the offset time Δt2'' to time t1'' (t1''+Δt2'') is determined as the first time. If the difference between the first and second data sequences is D14, the difference range D1-Dx corresponding to D14 is the reference time t1'', ​​which is also determined as the first time.

[0149] Optionally, when the difference value is Dx, time t1'' or (t1''+Δt2'') may be determined as the first time. The same applies to Dy and Dz, which will not be repeated herein.

[0150] Table 6

[0151] The reference time in Table 6, t1'', is taken as an example.

[0152] In some embodiments of the present application, in the mapping relationship, the larger the boundary value within the difference value range (for example, the minimum or maximum difference value within the difference value range), the larger the corresponding time. The larger the minimum or maximum difference value, the larger the difference value within the corresponding difference value range. Conversely, the smaller the minimum or maximum difference value, the smaller the difference value within the corresponding difference value range. With the above solution, for two difference values in different difference value ranges, a larger difference value corresponds to a larger time, so a larger first time can be determined, and a smaller difference value corresponds to a smaller time, so a smaller first time can be determined. Therefore, the magnitude of the time can be set according to the magnitude of the difference between the two data sequences, which is beneficial to efficiently and reliably read the calculation result of the first memory array.

[0153] For example, in the second correspondence relationship shown in Table 4, if D1<Dx<……<Dz or Dx<Dy<……<Dn, then t1<t2<……<ts. For another example, in the second correspondence relationship shown in Table 5, if D1<Dx<……<Dz or Dx<Dy<……<Dn, then Δt1'<Δt2'<……<Δts'. For another example, in the second correspondence relationship shown in Table 6, if D1<Dx<……<Dz or Dx<Dy<……<Dn, then Δt2''<Δt3''<……<Δts''.

[0154] In addition, the time, reference time, and offset time in Table 1 to Table 6 are all numbers greater than or equal to 0.

[0155] In some embodiments of the present application, the total value of valid values in the first data sequence does not exceed a valid value threshold. Thus, a large difference between the first data sequence and the second data sequence can be avoided, which is beneficial to preventing an excessively long first time caused by a large difference. Taking an example where one element in the first data sequence can represent 1 bit of data, the total value of valid values of the first data sequence is the number of elements with a value of 1 in the first data sequence.

[0156] Figure 9 shows a schematic diagram of a first data sequence provided according to an exemplary embodiment of the present application. As Figure 9As shown, taking a first data sequence containing 128 elements, with the first 64 elements being 1 and the last 64 elements being 0, as an example, the total number of valid values ​​in the first data sequence is 64. The total number of valid values ​​in the first data sequence is the sum of all valid value elements in the first data sequence, which is 64.

[0157] This application does not limit the size of the effective value threshold and can set it according to the computational efficiency requirements of the storage circuit. Alternatively, in some embodiments of this application, the effective value threshold can be set according to the structure of the storage circuit. For example, the effective value threshold can be greater than or equal to half the number of storage cells in the storage cell group, and less than the number of storage cells in the storage cell group. For example, if an output signal line connects 128 storage cells, the effective value threshold can be set to any value less than 128 and greater than 64, such as 80, 100, etc.

[0158] For example, some embodiments of this application can perform sparsification processing on the input data sequence to reduce the density of valid values ​​in the data sequence, thereby helping to reduce the proportion of the total number of valid values ​​in the input data sequence that exceeds the valid value threshold.

[0159] For example, for an input data sequence where the total number of valid values ​​exceeds a valid value threshold, the input data sequence can be converted into two or more data sequences to reduce the density of valid values ​​in the data sequence. For instance, an input data sequence can be obtained where the total number of valid values ​​exceeds a valid value threshold; the input data sequence can be converted into at least two data sequences and input into a first storage array, wherein the at least two data sequences include the first data sequence.

[0160] In this embodiment, the total value of valid values ​​in the data sequence is controlled as a whole. If the total value of valid values ​​in the data sequence to be input is too large, the difference between the data sequence to be input and the previous input data sequence (second data sequence) may be large, or the difference between the data sequence to be input and the next calculation input may be large. Therefore, the data sequence to be input can be converted into multiple data sequences to reduce the difference between two adjacent input data sequences and shorten the first time.

[0161] For example, the total value of the valid values ​​of the multiple data sequences obtained after the conversion is less than the total value of the valid values ​​of the input data sequence. By converting the input data sequence into multiple data sequences, the total value of the valid values ​​of a single data sequence is reduced, which helps to reduce the differences between the data sequences input to the storage array.

[0162] For example, the sum of the valid values ​​in the multiple transformed data sequences is equal to the sum of the valid values ​​in the input data sequence. In this way, a single computation can be converted into multiple computations, and the total input for these multiple computations is equivalent to the input of the original data sequence, thereby reducing the impact on the computational results.

[0163] Figure 10 A schematic diagram of an input data sequence provided according to an exemplary embodiment of this application is shown. Figure 10 As shown, taking an input data sequence containing 128 elements, all of which are 1, as an example, the total number of valid values ​​in the input data sequence is 128, which is greater than the valid value threshold. For example, the total number of valid values ​​in the second data sequence is 0, and the difference between the two data sequences is 128. Therefore, the input data sequence is converted into at least two data sequences to shorten the first calculation time.

[0164] In some embodiments of this application, converting the input data sequence into at least two data sequences includes: converting the input data sequence into at least two data sequences based on the distribution of valid values ​​in the input data sequence. This causes a positive reduction in the difference between the input data sequence and the previous input data sequence.

[0165] This application does not limit the splitting method. For example, it can be split based on a valid value threshold. For instance, if the total valid value of the first / last X elements in the input data sequence reaches the valid value threshold or the valid value threshold - 1, then the X elements are treated as a data sequence. If the total valid value of the remaining elements is less than or equal to the valid value threshold, then the remaining elements are treated as another data sequence. If the total valid value of the remaining elements is greater than the valid value threshold, then the remaining elements are further split using the above method.

[0166] In some embodiments, the number of split sequences can be set. For example, setting the number of split sequences to 2 will convert the input data sequence into two data sequences; setting the number of split sequences to 3 will convert the input data sequence into three data sequences; and so on. Alternatively, a correspondence can be set between the total range of valid values ​​and the number of split sequences. Different total ranges of valid values ​​can have different numbers of split sequences.

[0167] For example, the input data sequence can be split according to a third correspondence between the total value of valid values ​​and the split values. This third correspondence can include the total value of multiple valid values, with each valid value corresponding to multiple split values. For example, the total value of all valid values ​​in the third correspondence exceeds a valid value threshold.

[0168] The input data sequence can be split into a corresponding number of data sequences based on the number of splitting values ​​corresponding to the total number of valid values ​​in the third correspondence. Furthermore, the total number of valid values ​​in each split data sequence can correspond to a separate splitting value. For example, if the total number of valid values ​​in the input data sequence is 120, which exceeds the valid value threshold, and corresponds to splitting values ​​of 50 and 70 in the third correspondence, then the input data sequence can be split into two data sequences based on these splitting values: one sequence has a total valid value of 50, and the other sequence has a total valid value of 70.

[0169] In some embodiments of this application, the total value of valid values ​​in the data sequences of at least two split data sequences does not exceed a valid value threshold.

[0170] The input data sequence is converted into multiple data sequences with a smaller total effective value. This helps to reduce the possibility of a large difference between the input data sequence in the first storage array and the previous input data sequence during the subsequent calculation of the first storage array.

[0171] In some embodiments of this application, the data sequences in at least two converted data sequences have the same length as the input data sequence and include a portion of the input data sequence as well as padding with zeros.

[0172] Taking the splitting of the input data sequence into two data sequences as an example, Figure 11 This illustration shows a schematic diagram of an input data sequence and two data sequences to be transformed, according to an exemplary embodiment of this application. Figure 11 As shown, taking an input data sequence containing 128 elements as an example, the input data sequence is converted into two data sequences. The input data sequence is split into the first 64 elements and the last 64 elements. The first 64 elements are the first 64 elements of one data sequence, and the last 64 elements are the last 64 elements of the other data sequence. Then, the last 64 elements of one data sequence and the first 64 elements of the other data sequence are filled with 0s. Finally, each of the two data sequences contains 128 elements. In one data sequence, the first 64 elements are all 1s and the last 64 elements are all 0s; in the other data sequence, the first 64 elements are all 0s and the last 64 elements are all 1s.

[0173] The input of the first data sequence to the first storage array and subsequent operations are described above and will not be repeated here. The input of at least two data sequences other than the first data sequence to the first storage array and subsequent operations are described in the relevant section on the first data sequence, and will also not be repeated here.

[0174] In some embodiments of this application, when the readout circuit completes the second conversion, it can output a first indication signal. The first indication signal is used to indicate the end of reading the first calculation result or to indicate the availability status of the data read from the first calculation result. Through the first indication signal, when dynamically controlling the timing of reading the calculation result from the storage array, the subsequent processing circuit can promptly obtain the status of the current calculation result so that the subsequent processing circuit can perform subsequent operations. This improves both readout efficiency and the efficiency of subsequent processing of the calculation result.

[0175] In some embodiments of this application, the storage circuit further includes a second storage array, and the first and second storage arrays employ the same control timing. The second storage array can also be used for computation; for example, a fourth data sequence can be input to the second storage array, and this fourth data sequence is used for a third computation of the second storage array. Optionally, the reading of the computation results of the first and third computations can be controlled based on the first, second, fourth, and fifth data sequences; wherein the fifth data sequence is the previous input to the second storage array adjacent to the fourth data sequence.

[0176] In some embodiments of this application, two memory arrays can be controlled using the same control timing. When reading the calculation result of one memory array, the data sequence input to the other memory array can also be considered.

[0177] For example, the storage circuit includes a first set of storage cells and a second set of storage cells. Each set of storage cells comprises multiple sets of storage cells. Optionally, the number of storage cells in the first set and the second set can be equal. A first storage array belongs to the first set of storage cells in the first set, and a second storage array belongs to the second set of storage cells in the second set. The positions of the first and second storage cells in the first and second sets of storage cells in the second set are the same. Therefore, storage cells with the same number (position) in both sets of storage cells are controlled using the same read timing. This allows for parallel computation of the same input in different storage cell sets, enabling the splitting of large-scale computations, improving computational efficiency, simplifying control logic, and further enhancing the reliability of the computation results.

[0178] Figure 12 A schematic diagram of another storage circuit provided according to an exemplary embodiment of this application is shown. Figure 12 As shown, the storage circuit 1200 includes at least two sets of storage cells, each set of storage cells including multiple sets of storage cells. Figure 12Taking two sets of memory cell sets as an example. In the following description, memory cell sets are referred to as memory planes, but are not limited to this; a memory cell set can be replaced by a memory region. For example, memory circuit 1200 includes memory cell set group A and memory cell set group B, which include memory cell sets plane_0 to plane_a. Memory cell set group A and memory cell set group B have the same structure, as described above. Figure 3 The relevant descriptions will not be repeated here.

[0179] For example, in this embodiment of the application, the first set of storage units can be Figure 12 The storage cell set group A shown in the diagram, the second storage cell set can be... Figure 12 The storage cell set group B is shown in the diagram. The first storage array belongs to the storage cell set plane_0 in storage cell set group A, and the second storage array belongs to the storage cell set plane_0 in storage cell set group B. The storage cell set used for parallel computing can be located in the same position in storage cell set group A and storage cell set group B, for example, both being plane_0.

[0180] In some embodiments of this application, controlling the reading of the calculation results of the first calculation and the third calculation according to the first data sequence, the second data sequence, the fourth data sequence and the fifth data sequence includes: determining the second time and the first time according to the first data sequence, the second data sequence, the fourth data sequence and the fifth data sequence; and controlling the reading of the calculation results of the first calculation according to the second time and the first time.

[0181] In some embodiments of this application, determining a second time based on a first data sequence, a second data sequence, a fourth data sequence, and a fifth data sequence includes: determining a second difference value between the fourth data sequence and the fifth data sequence; determining a second time based on the second difference value; if the second time is less than the first time, controlling the reading of the calculation results of the third calculation and the first calculation based on the first time; or, if the second time is greater than the first time, controlling the reading of the calculation results of the third calculation and the first calculation based on the second time.

[0182] Thus, within the larger of the first and second time intervals, both the first and second storage arrays can establish and sample current signals, enabling parallel computation between the first and second storage arrays.

[0183] The step of determining the second difference value between the fourth and fifth data sequences is similar to the step of determining the first difference value between the first and second data sequences. The step of determining the second time based on the second difference value is similar to the step of determining the first time based on the first difference value. These will not be elaborated upon further here.

[0184] In some embodiments of this application, the control method described above is not only applicable to the read control of the first storage array, but also to the read control of the second storage array. That is, the readout of the calculation result of the third calculation can also be controlled according to the first data sequence, the second data sequence, the fourth data sequence, and the fifth data sequence. For details, please refer to the description above; further elaboration will not be repeated here.

[0185] In some embodiments of this application, when the readout circuit completes the second transformation of the second calculation, it can output a second indication signal. The second indication signal is used to indicate the end of reading the second calculation result or to indicate the availability status of the data read from the second calculation result. Through the second indication signal, when dynamically controlling the timing of reading the calculation result from the storage array, the subsequent processing circuit can promptly obtain the status of the current calculation result so that the subsequent processing circuit can perform subsequent operations. This improves both readout efficiency and the efficiency of subsequent processing of the calculation result.

[0186] In some embodiments of this application, when the readout circuit completes the second transformation of the third calculation, it can output a third indication signal. The third indication signal is used to indicate the end of reading the third calculation result or to indicate the availability status of the data read from the third calculation result. Through the third indication signal, when dynamically controlling the timing of reading the calculation results from the storage array, the subsequent processing circuit can promptly obtain the status of the current calculation result so that the subsequent processing circuit can perform subsequent operations. This is beneficial for improving both readout efficiency and the efficiency of subsequent processing of the calculation results.

[0187] In some embodiments of this application, at least two of the first indication signal, the second indication signal, and the third indication signal can reuse the same pin, thereby reducing the number of pins and improving integration.

[0188] This application embodiment also provides a control device, which may be located in or include... Figure 1 or Figure 2 The control circuit 120 / 220 shown, or independent of the control circuit 120 / 220. This control device can be used to execute any of the above control methods.

[0189] This application also provides a control device, which can be found in the embodiments of this application. Figure 13 . Figure 13 A schematic diagram of another control device according to an exemplary embodiment of this application is shown. Figure 13 As shown, the control device 1300 includes at least one processing circuit 1310 and an interface circuit 1320. The interface circuit 1320 is used to connect to the storage circuit via signals, and the at least one processing circuit 1310 is used to execute any of the control methods provided in the above embodiments.

[0190] In some embodiments of this application, the interface circuit 1320 includes a readout circuit for performing a readout operation in any of the control methods provided in the above embodiments.

[0191] This application also provides a memory computing system, which includes: a storage circuit; and a control device electrically connected to the storage circuit for executing any of the control methods proposed in this application.

[0192] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0193] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0194] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0195] This application also provides an electronic device, which can be found in [reference 1]. Figure 14 . Figure 14 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 14 As shown, the electronic device 1400 may include any of the above-mentioned in-memory computing systems 1410 for processing data of the electronic device. The electronic device may also include an input / output device 1420 for receiving user input or outputting processing results. This application does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 1430, which can process data provided to the in-memory computing system 1410 or process the output data of the in-memory computing system 1410. The output of the input / output device 1420 may be based on the output of the processor 1430 or the output of the in-memory computing system 1410.

[0196] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0197] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A control method, characterized in that, include: A first data sequence is input into a first memory array of a memory circuit, and the first data sequence is used for a first calculation of the first memory array. Based on the first data sequence and the second data sequence, control the reading out of the calculation result of the first calculation; The second data sequence is the previous input of the first storage array adjacent to the first data sequence.

2. The control method according to claim 1, characterized in that, The step of controlling the reading of the calculation result of the first calculation based on the first data sequence and the second data sequence includes: The reading time of the calculation result of the first calculation is controlled based on the first data sequence and the second data sequence.

3. The control method according to claim 2, characterized in that, The readout time includes the start or completion time of the first transformation of the calculation result.

4. The control method according to claim 2 or 3, characterized in that, The readout time includes the start or completion time of the second transformation of the calculation result.

5. The control method according to any one of claims 1-4, characterized in that, The step of controlling the reading of the calculation result of the first calculation based on the first data sequence and the second data sequence includes: The first time is determined based on the first data sequence and the second data sequence; The completion time of the first transformation of the calculation result is controlled to be no earlier than the end time of the first time.

6. The control method according to any one of claims 1-5, characterized in that, The step of controlling the reading of the calculation result of the first calculation based on the first data sequence and the second data sequence includes: The first time is determined based on the first data sequence and the second data sequence; When the first time expires, control initiates the second transformation of the calculation result.

7. The control method according to claim 5 or 6, characterized in that, Determining the first time based on the first data sequence and the second data sequence includes: Determine a first difference value between the first data sequence and the second data sequence; The first time is determined based on the first difference value.

8. The control method according to claim 7, characterized in that, Determining the first time based on the first difference value includes: Based on the first difference value and the mapping relationship, the first time is determined. The mapping relationship includes a first correspondence relationship or a second correspondence relationship. The first correspondence relationship includes a correspondence relationship between multiple difference values ​​and multiple times. The second correspondence relationship includes a correspondence relationship between multiple difference value ranges and multiple times. The first time is the first time corresponding to the first difference value among the multiple difference values ​​in the first correspondence relationship, or the first time is the first time corresponding to the first difference value range in the second correspondence relationship. The first difference value is located within the first difference value range.

9. The control method according to claim 8, characterized in that, In the first correspondence, among the plurality of difference values, the larger the difference value, the longer the corresponding time. Alternatively, in the second correspondence, among the multiple difference value ranges, the larger the boundary value, the longer the corresponding time.

10. The control method according to any one of claims 5-9, characterized in that, Also includes: When the first time expires, a third data sequence is input to the first storage array, the third data sequence being used for a second calculation of the first storage array.

11. The control method according to any one of claims 1-10, characterized in that, Also includes: Obtain the input data sequence, wherein the total value of valid values ​​in the input data sequence exceeds a valid value threshold; The input data sequence is converted into at least two data sequences and input into the first storage array, wherein the at least two data sequences include the first data sequence.

12. The control method according to claim 11, characterized in that, The total value of valid values ​​in the data sequences of the at least two data sequences does not exceed the valid value threshold.

13. The control method according to claim 11 or 12, characterized in that, The data sequences in the at least two data sequences have the same length as the input data sequence and include a portion of the input data sequence as well as padding with zeros.

14. The control method according to any one of claims 1-13, characterized in that, When the reading of the calculation result of the first calculation is completed, an indication signal is used to indicate the end of the reading of the calculation result or to indicate the availability status of the read data.

15. The control method according to any one of claims 1-14, characterized in that, The storage circuit further includes a second storage array, wherein the first storage array and the second storage array employ the same control timing, and the control method further includes: A fourth data sequence is input to the second storage array, the fourth data sequence being used for a third calculation of the second storage array; Based on the first data sequence, the second data sequence, the fourth data sequence, and the fifth data sequence, control the reading of the calculation results of the first calculation and the third calculation; The fifth data sequence is the previous input of the second storage array adjacent to the fourth data sequence.

16. A control device, characterized in that, include: Interface circuitry used for communication with storage circuitry; At least one processing circuit is used to perform the control method as described in any one of claims 1 to 15.

17. An in-memory computing system, characterized in that, include: Storage circuit; A control device, electrically connected to the storage circuit, is used to execute the control method as described in any one of claims 1 to 15.

18. An electronic device, characterized in that, Including the in-memory computing system as described in claim 17.

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