Semiconductor device and method of operating the same

Abstract

A semiconductor device and an operating method thereof are provided. The operating method of the semiconductor device includes entering a test mode, storing data in memory cells connected to three word lines that are consecutive to each other, repeating an activation-precharge operation for each of the three word lines a preset number of times, reading data of the memory cells connected to a central word line among the three word lines, and storing an address corresponding to the central word line as a failure address based on a result of the reading. The repeating the activation-precharge operation includes activating two word lines among the three word lines except for the central word line to a voltage level higher than a level of a normal word line driving voltage, and activating the central word line to a voltage level lower than the level of the normal word line driving voltage.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0056188, filed on April 29, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to an integrated circuit technology, and more specifically, to a semiconductor device and a method for testing the same. Background Technology

[0003] As semiconductor devices become increasingly integrated, it becomes increasingly difficult to achieve stable operating characteristics of MOS transistors. Specifically, DRAM includes cell transistors connected to memory cells composed of capacitors, which in turn connect these memory cells to word lines and bit lines. Because gate line widths are drastically reduced and the size of cell transistors is also reduced due to the finer (i.e., higher resolution) processes used to manufacture cell transistors, the required transistor characteristics, such as threshold voltage, current drive capability, and operating speed, are reaching their limits.

[0004] Because faulty memory cells reduce the reliability of semiconductor devices, they need to be detected through testing (including cell transistors with characteristics that have not yet been obtained). Summary of the Invention

[0005] In an embodiment, an operation method of a semiconductor device may include: a test mode entry step to enter a test mode; a step to store data in memory cells connected to three consecutive word lines; a step to repeat an activation-precharge operation a preset number of times for each of the three consecutive word lines; a step to read data from the memory cell of the center word line connected to the three consecutive word lines; and a step to store the address corresponding to the center word line as a fault address based on the result of the read. The step of repeating the activation-precharge operation includes: activating two of the three consecutive word lines other than the center word line to a voltage level higher than the normal word line drive voltage, and activating the center word line to a voltage level lower than the normal word line drive voltage.

[0006] In an embodiment, a semiconductor device may include: a word line driver that drives a plurality of word lines to the level of a word line drive voltage; a sense amplifier array that detects and amplifies data in memory cells via a plurality of bit lines; a memory cell array that includes a plurality of memory cells formed at the intersections of the plurality of word lines and the plurality of bit lines; and a test control circuit that, when the semiconductor device enters a test mode, controls the word line driver and the sense amplifier array to store data in memory cells of each of three consecutive word lines; repeats an activation-precharge operation a preset number of times for each of the three consecutive word lines; reads data from the memory cell of the central word line among the three consecutive word lines; and stores the address corresponding to the central word line as a fault address based on the reading result.

[0007] In an embodiment, an operation method of a semiconductor device may include: a test mode entry step of entering a test mode; a step of storing data in memory cells of each of a first word line, a second word line, and a third word line that are connected consecutively to each other; a step of repeating an activation-precharge operation a preset number of times for each of the first to third word lines; a step of reading data from memory cells connected to the second word line; and a step of storing the address corresponding to the second word line as a fault address based on the reading result. The step of repeating the activation-precharge operation for each of the first to third word lines may include: performing an activation-precharge operation on the first word line; performing an activation-precharge operation on the third word line after the activation-precharge operation on the first word line is completed; and performing an activation-precharge operation on the second word line after the activation-precharge operation on the third word line is completed. Attached Figure Description

[0008] Figure 1 The construction of a semiconductor device according to an embodiment of the present disclosure is shown.

[0009] Figures 2 to 5 This is a flowchart describing a test method for a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0010] In the following description, embodiments based on the technical spirit of this disclosure are illustrated with reference to the accompanying drawings.

[0011] Embodiments of this disclosure provide a storage device capable of detecting faulty storage cells and a testing method thereof.

[0012] It can improve the reliability of semiconductor devices.

[0013] Figure 1The construction of a semiconductor device 100 according to an embodiment of the present disclosure is shown.

[0014] The semiconductor device 100 according to embodiments of the present disclosure may include a test control circuit 10, a word line drive voltage generation circuit 20, a first word line driver 30, a second word line driver 40, a sense amplifier array 50, and a memory cell array 60.

[0015] When the test entry signal Test_s is received, the test control circuit 10 generates a first word line control signal WL_ctrlA, a second word line control signal WL_ctrlB, a word line drive voltage level control signal V_ctrl, and a sense amplifier control signal SA_ctrl. The test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl. The test control circuit 10 can control the first word line driver 30 via the first word line control signal WL_ctrlA. The test control circuit 10 can control the second word line driver 40 via the second word line control signal WL_ctrlB. The test control circuit 10 can control the sense amplifier array 50 via the sense amplifier control signal SA_ctrl.

[0016] The test control circuit 10 may include a fault address storage circuit 11. The test control circuit 10 can receive read data Data_read from the sense amplifier array 50 and compare the read data Data_read with preset test data. In this case, when the read data Data_read differs from the preset test data, the test control circuit 10 can store the address of the memory cell that outputs the read data Data_read in the fault address storage circuit 11. In this case, the address stored in the fault address storage circuit 11 may include a row address for word line selection.

[0017] The word line drive voltage generation circuit 20 can adjust the level of the word line drive voltage VPP based on the word line drive voltage level control signal V_ctrl. For example, the word line drive voltage generation circuit 20 can select one of the first word line drive voltages VPP_h, the second word line drive voltage VPP_n, and the third word line drive voltage VPP_l, which have different levels, based on the word line drive voltage level control signal V_ctrl, and can output the selected word line drive voltage. In this case, the level of the first word line drive voltage VPP_h can be the highest, while the level of the third word line drive voltage VPP_l can be the lowest. The second word line drive voltage VPP_n can be the voltage that activates the word line under normal conditions other than when performing a test. The selected word line drive voltage output from the word line drive voltage generation circuit 20 can be provided to the first word line driver 30 and the second word line driver 40.

[0018] The first word line driver 30 and the second word line driver 40 can select one word line from a plurality of word lines WL0 to WLmax based on the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, respectively. Furthermore, the first word line driver 30 and the second word line driver 40 can drive the selected word line to the level of the voltage provided by the word line drive voltage generation circuit 20. In this case, unselected word lines can be driven to a negative voltage level.

[0019] For example, the first word line driver 30 can control the driving of even-numbered word lines WL0, WL2, ... among a plurality of word lines WL0 to WLmax based on the first word line control signal WL_ctrlA. More specifically, the first word line driver 30 can select one of the even-numbered word lines WL0, WL2, ... based on the first word line control signal WL_ctrlA, and can drive the selected word line to the level of the voltage provided by the word line driving voltage generation circuit 20. In this case, the first word line driver 30 can drive the unselected even-numbered word line to a negative voltage level.

[0020] Furthermore, the second word line driver 40 can control the driving of odd-numbered word lines WL1, WL3, ... among multiple word lines WL0 to WLmax based on the second word line control signal WL_ctrlB. More specifically, the second word line driver 40 can select one of the odd-numbered word lines WL1, WL3, ... based on the second word line control signal WL_ctrlB, and can drive the selected word line to the level of the voltage provided by the word line driving voltage generation circuit 20. In this case, the second word line driver 40 can drive the unselected odd-numbered word line to a negative voltage level.

[0021] The sense amplifier array 50 can detect and amplify data via at least one selected bit line from a plurality of bit lines BL0 to BLmax based on the sense amplifier control signal SA_ctrl, so as to output the data stored in the memory cell as read data Data_read. Furthermore, the sense amplifier array 50 can change the levels of the plurality of bit lines BL0 to BLmax to a specific level based on the sense amplifier control signal SA_ctrl.

[0022] For example, the sense amplifier array 50 may include multiple sense amplifiers (not shown). The multiple sense amplifiers may be electrically connected to multiple bit lines BL0 to BLmax, respectively. At least one of the multiple sense amplifiers may be selected based on a sense amplifier control signal SA_ctrl. The selected at least one sense amplifier may detect and amplify data stored in the memory cell via the bit lines electrically connected to the selected at least one sense amplifier. Furthermore, each of the multiple sense amplifiers may change the level of the bit line connected to each sense amplifier to a specific level based on the sense amplifier control signal SA_ctrl.

[0023] The memory cell array 60 may include a plurality of memory cells (not shown). The plurality of memory cells may be respectively located at the intersection of a plurality of bit lines BL0 to BLmax and a plurality of word lines WL0 to WLmax. For example, each of the plurality of memory cells may include a cell transistor and a capacitor. Each of the plurality of memory cells may be electrically connected to the capacitor and the corresponding bit line when the corresponding word line is driven.

[0024] The testing method for the semiconductor device constructed as described above according to embodiments of this disclosure is described below.

[0025] Figures 2 to 5 This is a flowchart describing a test method for a semiconductor device according to embodiments of the present disclosure.

[0026] Figure 2 This is a flowchart describing a test method for a semiconductor device according to embodiments of the present disclosure.

[0027] refer to Figure 2 The testing method for a semiconductor device according to embodiments of the present disclosure may include a test mode entry step S1, a data storage step S2, an activation precharge repetition step S3, a read and fault address storage step S4, a last word line confirmation step S5, and a word line address increment step S6.

[0028] The test mode entry step S1 may include receiving a test entry signal Test_s via the test control circuit 10. In response, the semiconductor device may enter the test mode.

[0029] The data storage step S2 may include storing data in storage cells connected to three word lines (n-1, n, and n+1, where n is a natural number) that are consecutive to each other and therefore physically adjacent. For example, low-level data may be stored in storage cells connected to the (n-1)th word line and the (n+1)th word line, respectively, while high-level data may be stored in storage cells connected to the nth word line.

[0030] Activating the precharge repetition step S3 may include repeating the following operation a preset number of times: activating each of the three consecutive (n-1)th, nth, and (n+1)th word lines and then precharging. For example, activating the precharge repetition step S3 may include driving each of the (n-1)th and (n+1)th word lines to the level of the first word line drive voltage VPP_h a preset number of times, and driving the nth word line to the level of the third word line drive voltage VPP_l a preset number of times.

[0031] The read and fault address storage step S4 may include the following steps: reading data from the storage cell of the middle word line (i.e., the nth word line) among the three consecutive word lines (n-1), nth, and (n+1)th word lines; comparing the read data with the data stored in the storage cell connected to the nth word line in the data storage step S2; and storing the address of the nth word line as a fault address when the number of bits in the read data that have a value different from the corresponding bit in the data stored in the storage cell is a preset number or greater.

[0032] The last word line confirmation step S5 may include the following steps: confirming whether the middle word line (i.e., the nth word line) among the three consecutive (n-1)th word lines, nth word lines and (n+1)th word lines is the last word line WLmax of the memory cell array 60.

[0033] In the last word line confirmation step S5, when the nth word line is the last word line WLmax of the memory cell array 60 (yes), the test method of the semiconductor device according to the embodiment of the present disclosure can be terminated.

[0034] In the last word line confirmation step S5, if the nth word line is not the last word line WLmax of the memory cell array 60 (no), the word line address increment step S6 can be executed.

[0035] The word line address increment step S6 may include incrementing the address of the word line, thereby enabling the data storage step S2 to be performed on the three consecutive nth word lines, (n+1)th word lines, and (n+2)th word lines.

[0036] Figure 3It is used to describe more specifically. Figure 2 The view of data storage step S2.

[0037] The data storage step S2 may include a first data storage step S2-1, a second data storage step S2-2, and a third data storage step S2-3.

[0038] The first data storage step S2-1 may include the following steps: storing low-level data in a storage unit connected to the (n-1)th word line. (See reference...) Figure 1 The test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl, causing the word line drive voltage generation circuit 20 to output a second word line drive voltage VPP_n. By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB respectively, the test control circuit 10 can drive the (n-1)th word line to the level of the second word line drive voltage VPP_n and drive the remaining word lines to a negative voltage level. The test control circuit 10 can control the sense amplifier array 50 via the sense amplifier control signal SA_ctrl to change the levels of multiple bit lines BL0 to BLmax to a low level. In this case, the memory cell connected to the (n-1)th word line can store low-level data.

[0039] The second data storage step S2-2 may include the following steps: storing low-level data in a storage unit connected to the (n+1)th word line. (See reference) Figure 1 The test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl, causing the word line drive voltage generation circuit 20 to output a second word line drive voltage VPP_n. By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB respectively, the test control circuit 10 can drive the (n+1)th word line to the level of the second word line drive voltage VPP_n and drive the remaining word lines to a negative voltage level. The test control circuit 10 can control the sense amplifier array 50 via the sense amplifier control signal SA_ctrl to change the levels of multiple bit lines BL0 to BLmax to a low level. In this case, the memory cell connected to the (n+1)th word line can store low-level data.

[0040] The third data storage step S2-3 may include the following step: storing high-level data in a memory cell connected to the nth word line. (See reference) Figure 1The test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl, causing the word line drive voltage generation circuit 20 to output a second word line drive voltage VPP_n. By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB respectively, the test control circuit 10 can drive the nth word line to the level of the second word line drive voltage VPP_n and drive the remaining word lines to a negative voltage level. The test control circuit 10 can control the sense amplifier array 50 via the sense amplifier control signal SA_ctrl to change the levels of multiple bit lines BL0 to BLmax to a high level. In this case, the memory cell connected to the nth word line can store high-level data.

[0041] As described above, when data is stored in storage units connected to three consecutive word lines (n-1), n, and (n+1), the data storage step S2 may include: first storing the data in the storage unit connected to the (n-1) word line, and then storing the data in the storage unit connected to the (n+1) word line. Furthermore, the operation of storing the data in the storage unit connected to the n word line may be performed last in the data storage step S2. Additionally, in the data storage step S2, the values ​​of the data stored in the storage units connected to the (n-1) and (n+1) word lines may be different from the values ​​of the data stored in the storage unit connected to the n word line.

[0042] Figure 4 It is used to describe more specifically. Figure 2 The view of the activation precharge repeating step S3.

[0043] refer to Figure 4 The activation of the precharge repeat step S3 may include a first word line drive voltage level setting step S3-1, a first activation of the precharge repeat step S3-2, a second activation of the precharge repeat step S3-3, a second word line drive voltage level setting step S3-4, and a third activation of the precharge repeat step S3-5.

[0044] The first word line drive voltage level setting step S3-1 may include setting the level of the word line drive voltage. For example, the first word line drive voltage level setting step S3-1 may include setting the level of the word line drive voltage to a level higher than the normal word line drive voltage level (e.g., higher than the second word line drive voltage VPP_n). More specifically, the first word line drive voltage level setting step S3-1 may include selecting the first word line drive voltage VPP_h from the first word line drive voltage VPP_h, the second word line drive voltage VPP_n, and the third word line drive voltage VPP_l. (See reference...) Figure 1 The test control circuit 10 can control the word line drive voltage generation circuit 20 through the word line drive voltage level control signal V_ctrl, so that the first word line drive voltage VPP_h is selected from the first word line drive voltage VPP_h, the second word line drive voltage VPP_n and the third word line drive voltage VPP_l and output.

[0045] The first activation pre-charge repetition step S3-2 may include repeating the following operation a preset number of times: activating the (n-1)th word line and then pre-charging it. In this case, the voltage level of the activated (n-1)th word line may be the level of the first word line drive voltage VPP_h, and the voltage level of the pre-charged (n-1)th word line may be a negative voltage level. That is, the first activation pre-charge repetition step S3-2 may include driving the (n-1)th word line to the level of the first word line drive voltage VPP_h a preset number of times. (See reference...) Figure 1 By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can repeat the following operation a preset number of times: selecting the (n-1)th word line from a plurality of word lines WL0 to WLmax and driving the selected (n-1)th word line to the level of the first word line drive voltage VPP_h, and then driving the selected (n-1)th word line to a negative voltage level. In this case, the remaining word lines from the plurality of word lines WL0 to WLmax, excluding the (n-1)th word line, can be driven to a negative voltage level.

[0046] The second activation pre-charge repetition step S3-3 may include repeating the following operation a preset number of times: activating the (n+1)th word line and then pre-charging it. In this case, the voltage level of the activated (n+1)th word line may be the level of the first word line drive voltage VPP_h, and the voltage level of the pre-charged (n+1)th word line may be a negative voltage level. That is, the second activation pre-charge repetition step S3-3 may include the following step: driving the (n+1)th word line to the level of the first word line drive voltage VPP_h a preset number of times. (See reference) Figure 1By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can repeat the following operation a preset number of times: selecting the (n+1)th word line from a plurality of word lines WL0 to WLmax, driving the selected (n+1)th word line to the level of the first word line drive voltage VPP_h, and then driving the selected (n+1)th word line to a negative voltage level. In this case, the remaining word lines from the plurality of word lines WL0 to WLmax, excluding the (n+1)th word line, can be driven to a negative voltage level.

[0047] The second word line drive voltage level setting step S3-4 may include setting the level of the word line drive voltage. For example, the second word line drive voltage level setting step S3-4 may include setting the level of the word line drive voltage to a level lower than the normal word line drive voltage (e.g., lower than the second word line drive voltage VPP_n). More specifically, the second word line drive voltage level setting step S3-4 may include selecting a third word line drive voltage VPP_l from the first word line drive voltage VPP_h, the second word line drive voltage VPP_n, and the third word line drive voltage VPP_l. (See reference...) Figure 1 The test control circuit 10 can control the word line drive voltage generation circuit 20 through the word line drive voltage level control signal V_ctrl, so that the third word line drive voltage VPP_l is selected from the first word line drive voltage VPP_h, the second word line drive voltage VPP_n and the third word line drive voltage VPP_l and output.

[0048] The third activation pre-charge repetition step S3-5 may include repeating the following operation a preset number of times: activating the nth word line and then pre-charging it. In this case, the voltage level of the activated nth word line can be the level of the third word line drive voltage VPP_l, and the voltage level of the pre-charged nth word line can be a negative voltage level. That is, the third activation pre-charge repetition step S3-5 may include driving the nth word line to the level of the third word line drive voltage VPP_l a preset number of times. (See reference...) Figure 1 By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can repeat the following operation a preset number of times: selecting the nth word line from a plurality of word lines WL0 to WLmax, driving the selected nth word line to the level of the third word line drive voltage VPP_l, and then driving the selected nth word line to a negative voltage level. In this case, the remaining word lines from the plurality of word lines WL0 to WLmax, excluding the nth word line, can be driven to a negative voltage level.

[0049] Figure 5 It is used to describe more specifically. Figure 2 The view of reading and storing fault addresses in step S4.

[0050] refer to Figure 5 The reading and fault address storage step S4 may include the third word line drive voltage level setting step S4-1, the reading step S4-2, and the fault address storage step S4-3.

[0051] The third word line drive voltage level setting step S4-1 may include setting the level of the word line drive voltage. For example, the third word line drive voltage level setting step S4-1 may include setting the level of the word line drive voltage to the level of the normal word line drive voltage (e.g., setting it to the second word line drive voltage VPP_n). More specifically, the third word line drive voltage level setting step S4-1 may include selecting the second word line drive voltage VPP_n from the first word line drive voltage VPP_h, the second word line drive voltage VPP_n, and the third word line drive voltage VPP_l. (See reference...) Figure 1 The test control circuit 10 can control the word line drive voltage generation circuit 20 through the word line drive voltage level control signal V_ctrl, so that the second word line drive voltage VPP_n is selected from the first word line drive voltage VPP_h, the second word line drive voltage VPP_n and the third word line drive voltage VPP_l and output.

[0052] The reading step S4-2 may include the following steps: reading data from the memory cell connected to the nth word line. For example, the reading step S4-2 may include: driving the nth word line to the level of the second word line drive voltage VPP_n; detecting and amplifying the data from the memory cell connected to the nth word line (driven by multiple bit lines BL0 to BLmax) by activating the sense amplifier array 50; and transmitting the detected and amplified data to the test control circuit 10. (See reference...) Figure 1 The test control circuit 10 can control the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, thereby selecting the nth word line among multiple word lines WL0 to WLmax, and driving the selected nth word line to the level of the second word line drive voltage VPP_n. The test control circuit 10 can control the sense amplifier array 50 via the sense amplifier control signal SA_ctrl, thereby detecting and amplifying the data in the memory cell connected to the nth word line (driven to the level of the second word line drive voltage VPP_n) via multiple bit lines BL0 to BLmax. The sense amplifier array 50 can provide the detected and amplified data to the test control circuit 10, i.e., read the data Data_read.

[0053] The fault address storage step S4-3 may include the following steps: comparing the data stored in the nth word line in the data storage step S2 with the data read in the reading step S4-2, and storing the address corresponding to the nth word line as a fault address based on the comparison result. For example, the fault address storage step S4-3 may include: comparing the data stored in the nth word line in the data storage step S2 (e.g., data with a high level) with the data read in the reading step S4-2, and storing the address corresponding to the nth word line (e.g., the row address) as a fault address when the number of bits of data in the read data that has a value different from the corresponding bit value of the stored data is greater than a preset number. For example, when high-level data is stored, the fault address storage step S4-3 may include the following steps: when the number of bits of low-level data in the read data is greater than a preset number, storing the address corresponding to the nth word line as a fault address. (Reference) Figure 1 The test control circuit 10 can compare the read data Data_read provided by the sense amplifier array 50 with the data stored in the data storage step S2, and can store the address corresponding to the nth word line (e.g., the row address) in the fault address storage circuit 11 as a fault address based on the comparison result. In this case, when the number of data bits in the read data Data_read that have values ​​different from the corresponding bits of the stored data is greater than a preset number, the test control circuit 10 can store the address corresponding to the nth word line as a fault address. Therefore, in the provided example, when the number of low-level data bits in the read data Data_read is greater than a preset number, the test control circuit 10 can store the address corresponding to the nth word line as a fault address.

[0054] The semiconductor device constructed as described above according to the embodiments of this disclosure and the test method thereof are described below (assuming n=1).

[0055] refer to Figure 1 and Figure 2 The test mode can be entered in step S1. For example, when the test control circuit 10 receives the test entry signal Test_s, the semiconductor device 100 can enter the test mode.

[0056] The data storage step S2 can be performed.

[0057] For example, the test control circuit 10 can control the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, and control the sense amplifier array 50 via the sense amplifier control signal SA_ctrl, storing data in memory cells connected to the 0th word line WL0, the first word line WL1, and the second word line WL2. In this case, low-level data can be stored in memory cells connected to the 0th word line WL0 and the second word line WL2, while high-level data can be stored in memory cells connected to the first word line WL1. Furthermore, after storing data in memory cells connected to the 0th word line WL0, data can be stored in memory cells connected to the second word line WL2. Finally, data can be stored in memory cells connected to the first word line WL1.

[0058] The activation precharge repeat step S3 can be performed.

[0059] For example, the test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl to provide the first word line drive voltage VPP_h to the first word line driver 30 and the second word line driver 40. By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can repeat the following operation a preset number of times: activating the 0th word line WL0 to the level of the first word line drive voltage VPP_h and then pre-charging the 0th word line WL0 to a negative voltage level. Thereafter, by controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can repeat the following operation a preset number of times: activating the second word line WL2 to the level of the first word line drive voltage VPP_h and then pre-charging the second word line WL2 to a negative voltage level. When the activation-precharge operation of the second word line WL2 is completed, the test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl, thereby providing the third word line drive voltage VPP_l to the first word line driver 30 and the second word line driver 40. By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can repeat the following operation a preset number of times: activating the first word line WL1 to the level of the third word line drive voltage VPP_l, and then precharging the first word line WL1 to a negative voltage level.

[0060] Step S4, which involves reading and storing the fault address, can be performed.

[0061] For example, the test control circuit 10 can control the word line drive voltage generation circuit 20 via the word line drive voltage level control signal V_ctrl to provide the second word line drive voltage VPP_n to the first word line driver 30 and the second word line driver 40. By controlling the first word line driver 30 and the second word line driver 40 via the first word line control signal WL_ctrlA and the second word line control signal WL_ctrlB, the test control circuit 10 can drive the first word line WL1 to the level of the second word line drive voltage VPP_n. By controlling the sense amplifier array 50 via the sense amplifier control signal SA_ctrl, the test control circuit 10 can detect and amplify the data of the memory cell connected to the first word line WL1. In this case, the sense amplifier array 50 can detect and amplify the data of the memory cell connected to the first word line WL1 through multiple bit lines BL0 to BLmax. When the number of bits in the read data Data_read that have values ​​different from the corresponding bits of the data stored in the data storage step S2 is greater than a preset number, the test control circuit 10 can store the row address corresponding to the first word line in the fault address storage circuit 11 as a fault address.

[0062] The final word line confirmation step S5 can be performed.

[0063] For example, the test control circuit 10 can confirm whether the word line WL1 driven in the read and fault address storage step S4 is the last word line WLmax. The word line address increment step S6 can be performed because the word line WL1 driven in the read and fault address storage step S4—that is, the first word line WL1—is not the last word line WLmax.

[0064] The word line address increment step S6 may include incrementing the value of n by +1. For example, the test control circuit 10 may select three consecutive word lines WL1, WL2, and WL3 after performing the data storage step S2.

[0065] The data storage step S2, the activation precharge repeat step S3, and the read and fault address storage step S4 can be performed on each of the first word line, the second word line, and the third word line.

[0066] The data storage step S2, the activation precharge repeat step S3, and the read and fault address storage step S4 can be repeated until the word line driven in the read and fault address storage step S4 is the last word line WLmax.

[0067] When the word line driven in the read and fault address storage step S4 is the last word line WLmax, the test operation of the semiconductor device according to the embodiments of this disclosure can be terminated. In this case, high-level data is stored in the memory cell connected to the nth word line, low-level data is stored in the memory cells connected to the (n-1)th and (n+1)th word lines, and each of the (n-1)th and (n+1)th word lines is activated to a first word line drive voltage VPP_h with a higher level than the normal word line drive voltage VPP_n and then precharged, in order to shake the level of the nth word line by using the coupling phenomenon, thereby applying stress to the memory cell connected to the nth word line. Furthermore, the nth word line is activated to a third word line drive voltage VPP_l with a lower level than the normal word line drive voltage VPP_n and then precharged, in order to change the value of the data stored in the memory cell with bad characteristics connected to the nth word line to a high level.

[0068] As described above, the semiconductor device and its testing method according to the embodiments of this disclosure can detect memory cells with relatively bad characteristics, i.e., faulty memory cells, among the memory cells included in the memory cell array 60 based on word line addresses.

[0069] Although embodiments based on the technical spirit of this disclosure have been described above with reference to the accompanying drawings, these embodiments are provided merely to illustrate embodiments according to the concept of this disclosure, and this disclosure is not limited to these embodiments. Those skilled in the art to which this disclosure pertains may substitute, modify, and alter the embodiments in various ways without departing from the technical spirit of this disclosure as set forth in the claims. Such substitutions, modifications, and alterations are said to fall within the scope of this disclosure.

Claims

1. A method of operating a semiconductor device, comprising: Steps to enter test mode; When in the aforementioned test mode: The steps of storing data in storage units connected to three consecutive word lines; The activation-precharge operation is repeated a preset number of times for each of the three consecutive word lines. The step of reading data from the storage unit of the central word line among the three consecutive word lines; as well as The step of storing the address corresponding to the central word line as a fault address based on the reading result. The step of repeating the activation-precharge operation includes: The step of activating two of the three consecutive word lines, excluding the central word line, to a voltage level higher than the normal word line drive voltage, and The step of activating the center word line to a voltage level lower than the normal word line drive voltage.

2. The operating method as described in claim 1, wherein, In the step of storing the data, the data stored in the storage unit connected to the central word line and the data stored in the storage units connected to the two word lines other than the central word line have different data values.

3. The operating method as described in claim 2, wherein: The three consecutive character lines include the first character line, the second character line, and the third character line. The second character line is the central character line, and The step of storing the data includes: The step of storing data with a first voltage level in a memory cell connected to the first word line. The steps of storing data having the first level in a memory cell connected to the third word line, and The step of storing data with a second level different from the first level in a memory cell connected to the second word line.

4. The operating method as described in claim 3, wherein: The first level is a low level, and The second level is a high level.

5. The operating method as described in claim 3, wherein, Repeating the activation-precharge operation includes the following steps: The following steps are repeated a preset number of times for the first word line: activate the first word line to a voltage level higher than the normal word line drive voltage and then precharge the first word line. The following steps are repeated a preset number of times for the second word line: activating the third word line to a voltage level higher than the normal word line drive voltage and then pre-charging the third word line; The following steps are repeated a preset number of times for the third word line: the second word line is activated to a voltage level lower than the normal word line drive voltage and then the second word line is pre-charged.

6. The operating method as described in claim 3, wherein, The step of storing the address corresponding to the central word line as the fault address includes: The step of reading the data from the storage unit connected to the second word line. The step of comparing the read data with the data stored in the storage unit connected to the second word line in the step of storing data, and The steps include determining that the number of bits in the read data that have values ​​different from the corresponding bit values ​​in the stored data is greater than a preset number, and storing the address corresponding to the second word line as the fault address.

7. A semiconductor device, comprising: A word line driver that drives multiple word lines to the level of a word line drive voltage; A sense amplifier array that detects and amplifies data from memory cells via multiple bit lines; A memory cell array comprising a plurality of memory cells formed at the intersections of the plurality of word lines and the plurality of bit lines; as well as Test control circuit, wherein the test control circuit: When the semiconductor device enters test mode, data is stored in the memory cells of each of the three consecutive word lines by controlling the word line driver and the sense amplifier array. The activation-precharge operation is repeated a preset number of times for each of the three consecutive word lines. Read data from the storage cell of the central word line among the three consecutive word lines, and Based on the result of the reading, the address corresponding to the central word line is stored as a fault address.

8. The semiconductor device of claim 7, wherein, When the activation-precharge operation is performed, the test control circuit controls the voltage level of the activated central word line among the three consecutive word lines to be lower than the voltage level of each of the remaining two activated word lines.

9. The semiconductor device of claim 7, wherein, When the activation-precharge operation is performed, the test control circuit controls the activation-precharge operation for the central word line to be performed later than the activation-precharge operation for each of the remaining two word lines.

10. The semiconductor device of claim 7, wherein, In the operation of storing the data in the storage cells of each of the three consecutive word lines, the test control circuit controls the data stored in the storage cell connected to the central word line and the data stored in the storage cells connected to the remaining two word lines to have different levels.

11. The semiconductor device of claim 10, wherein, The test control circuit causes data with a first level to be stored in the storage unit connected to the remaining two word lines, and causes data with a second level to be stored in the storage unit connected to the central word line.

12. The semiconductor device of claim 11, wherein, In the operation of storing the address corresponding to the central word line as the fault address based on the result of the reading, the test control circuit determines that the number of bits of data with the first level in the data read from the storage cell connected to the central word line is greater than a preset number, and in response, stores the address corresponding to the central word line as the fault address.

13. A method of operating a semiconductor device, comprising: Steps to enter test mode; The step of storing data in storage units of each word line that is connected to each other in a continuous sequence of first, second, and third word lines; The activation-precharge operation is repeated a preset number of times for each word line from the first word line to the third word line; The step of reading the data from the storage unit connected to the second word line; as well as The step of storing the address corresponding to the second word line as a fault address based on the reading result. The step of repeating the activation-precharge operation for each of the first to the third word lines includes: Perform the activation-precharge operation on the first word line. After the activation-precharge operation for the first word line is completed, the activation-precharge operation is performed on the third word line. After the activation-precharge operation for the third word line is completed, the activation-precharge operation is performed on the second word line.

14. The operating method as described in claim 13, wherein, In the step of storing the data, the data stored in the storage unit connected to the second word line and the data stored in the storage unit connected to each of the first and third word lines have different data values.

15. The operating method as described in claim 14, wherein, The step of storing the data includes: The step of storing data with a first voltage level in the memory cell connected to the first word line. The steps of storing the data having the first level in the memory cell connected to the third word line, and The step of storing data having a second level different from the first level in the storage unit connected to the second word line.

16. The operating method as described in claim 13, wherein, The voltage level of each of the first and third word lines activated in the steps of performing the activation-precharge operation on the first word line and the third word line is higher than the voltage level of the second word line activated in the step of performing the activation-precharge operation on the second word line.

17. The operating method as described in claim 15, wherein, The step of storing the address corresponding to the second word line as the fault address includes: The step of reading the data from the storage unit connected to the second word line; and The step of determining that the number of bits of the data with the first level in the read data is greater than a preset number, and in response, storing the address corresponding to the second word line as the fault address.

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