Method and system for dram module partition refresh aggregating on-die error events in serial presence detect hub

Abstract

The application discloses a DRAM module partition refresh method and system for aggregating on-die error events in serial presence detect (SPD) hub, and relates to the technical field of DRAM module refresh. The method comprises the following steps: an SPD hub reads on-die error code correction (ECC) event statistics from a DRAM device through a sideband bus; the aggregated results are cached in an SPD hub storage area; the SPD hub maintains an event count histogram for a bank and calculates a retention time distribution representation, maps the retention time distribution representation to a priority level, and connects to form a per-bank refresh priority vector; the SPD hub outputs the per-bank refresh priority vector to a memory controller through the sideband bus; and the memory controller dispatches a per-bank refresh command according to the per-bank refresh priority vector in a fine granularity refresh (FGR) mode of DDR5. The application reduces the overall refresh energy consumption and the probability of uncorrectable errors of a key bank.

Description

Technical Field

[0001] This invention relates to the field of DRAM module refresh technology, and specifically to a DRAM module partition refresh method and system for aggregating on-chip error events by a serial presence detection center. Background Technology

[0002] The DDR5 specification introduced the FGR (Fine Granularity Refresh) mode, which allows per-bank refresh (REFsb) commands to be issued for individual banks. Simultaneously, the DRAM chip integrates on-die ECC to correct single-bit errors during read and write operations and reports error correction events or error rate exceeding limits to the memory controller via the ALERT_n signal.

[0003] In the prior art, for example, US11222685B2 discloses a refresh management method based on activation count. This method uses the refresh control circuit of the memory controller to monitor the rolling count of activation commands sent to a certain region of DRAM. When the count exceeds an intermediate threshold but falls below a maximum threshold, an RFM command is issued when there are no pending REF commands in that region. US11809743B2 discloses a DRAM refresh management list method. When the refresh control circuit of the memory controller detects that an activation command meets predetermined conditions, it identifies its possible candidate aggressor row and adds it to a list for priority mitigation in future REF or RFM events. US20240119991A1 discloses a dynamic refresh rate selection method based on temperature sensor grouping. This method determines whether to use the first refresh rate specified by the DRAM or a second refresh rate derived from temperature based on the temperature change rate obtained from continuous sampling by multiple temperature sensors. The ISCA 2012 retention-aware intelligent DRAM refresh solution performs a one-time offline retention time characterization of the DRAM during the factory or startup phase. It uses a bloom filter to record the retention time bins for each row, and the memory controller sends refresh commands row by row accordingly. The JEDEC JESD406-5 LPDDR5 / 5X SPD specification defines adaptive refresh parameters (directed or partial-array refresh, etc.) for LPDDR5 modules in SPD bytes 200-215, which are written by the manufacturer at the factory.

[0004] However, existing technologies have technical shortcomings in the following aspects:

[0005] The decision signal is disconnected from the hold time characteristics: Both patents with publication numbers US11222685B2 and US11809743B2 use activation counts as the decision input. Activation counts reflect access frequency and are related to RowHammer risk, but are unrelated to the inherent physical differences in cell hold time. Even if a bank is never heavily activated, if it contains many weak hold time cells, a higher refresh frequency is still required to prevent data loss; conversely, the same applies. Relying solely on activation counts to determine the refresh rhythm cannot cover the heterogeneity of hold time.

[0006] Global frequency adjustment masks spatial differences: Patent US20240119991A1 adjusts the overall refresh rate based on temperature rate. Within the same module, the hold time distribution of different banks varies significantly (affected by DRAM process fluctuations, aging processes, and operating temperature gradients). The global frequency scheme applies the same rate to all banks, creating a dilemma of "accommodating the overall over-refresh of the weakest bank or ignoring the overall under-refresh of the weakest bank."

[0007] Offline characterization and online aging are mismatched: ISCA 2012's retention-aware intelligent DRAM refresh solution relies on one-time characterization at the factory or startup phase. DRAM retention time changes during operation due to factors such as aging, the Variable Retention Time (VRT) effect, and operating temperature evolution. Offline characterization cannot capture these online changes, and the deviation between the bloom filter and the true distribution increases over time.

[0008] Static SPD configuration does not support runtime evolution: The adaptive refresh parameters in the JEDEC JESD406-5 LPDDR5 / 5X SPD specification are written to the SPD at the factory and do not change during runtime. This mechanism cannot reflect real-time online ECC event statistics, nor can it be dynamically adjusted under VRT, aging, or changes in operating conditions.

[0009] Therefore, how to utilize the weak hold time cell distribution information exposed by the on-die ECC (on-chip error correction code) within the DRAM chip during DRAM module operation to perform differentiated refresh scheduling for different banks, so as to simultaneously reduce overall refresh energy consumption and the probability of uncorrectable errors (UCE) occurring. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide a DRAM module partition refresh method and system for serial existence detection central aggregation on-chip error events.

[0011] The objective of this invention is achieved through the following technical solution:

[0012] In a first aspect, this application discloses a DRAM module partition refresh method for serial presence detection of on-chip error events, comprising the following steps:

[0013] The aggregation phase of on-die ECC event statistics: Based on the aggregation period T_a, SPD Hub reads the on-die ECC event statistics from the DRAM device via the sideband bus, including the number of correctable errors on each bank of the DRAM device in the current aggregation period, the trigger frequency of the ALERT_n signal, and a summary of the error distribution on the preset bit line or word line; then, the aggregation result is cached in the SPD Hub storage area in the form of a per-bank count vector;

[0014] The construction phase of the time-holding distribution representation: SPD Hub maintains an event count histogram within a sliding time window for each bank, and calculates the time-holding distribution representation of the bank through the event count histogram. The time-holding distribution representation includes a cumulative distribution function or a quantization approximation.

[0015] The generation phase of the per-bank refresh priority vector: SPD Hub maps the hold time distribution of each bank to a priority level, and then concatenates the priority levels of each bank in order of their corresponding bank numbers to form a per-bank refresh priority vector;

[0016] Priority vector cross-chip transfer stage: SPD Hub outputs per-bank refresh priority vector to memory controller via sideband bus;

[0017] Differentiated per-bank refresh scheduling phase: Under the DDR5 fine-grained refresh mode (FGR), the memory controller schedules per-bank refresh commands according to the per-bank refresh priority vector. For banks marked as first risk, the scheduling weight of their per-bank refresh commands is increased to a first predetermined proportion; for banks marked as fourth risk, the scheduling weight of their per-bank refresh commands is decreased to a second predetermined proportion; until the effective average refresh interval of all banks meets the JEDEC tREFI specification requirements.

[0018] Based on the first aspect, in the aggregation phase of on-die ECC event statistics: the aggregation period T_a is between 100 milliseconds and 1 second, the length of the counting vector per-bank is equal to the number of banks in the DRAM device, and the components of the per-bank counting vector correspond to the cumulative number of correctable errors of a bank in the current aggregation period.

[0019] Based on the first aspect, the on-die ECC event statistics also include temperature as a supplementary input.

[0020] Based on the first aspect, in the construction stage of maintaining the time distribution representation: the construction method of the event count histogram includes equal-width binning and quantile binning, and the selection range of the number of bins is 4 to 16; wherein, each bin corresponds to a different cumulative error range, and the count value of each bin represents the number of sampling periods in which the sampled value of the bank falls into the corresponding interval.

[0021] Based on the first aspect, the priority levels include:

[0022] If the proportion of events exceeding the error segment in the bank's event count histogram exceeds the first threshold, it is marked as the first risk.

[0023] If the cumulative proportion of errors exceeds the second threshold but is below the first threshold, it is marked as the second risk.

[0024] If the cumulative proportion of errors exceeds the third threshold but is below the second threshold, it is marked as a third risk.

[0025] If the cumulative proportion of errors is lower than the third threshold, it is marked as the fourth risk.

[0026] The first risk, the second risk, the third risk, and the fourth risk are encoded with 2 bits.

[0027] Based on the first aspect, the priority level can also be represented using continuous weights.

[0028] Based on the first aspect, the SPD Hub communicates with the memory controller via the sideband bus in the following ways:

[0029] The SPD Hub writes the per-bank refresh priority vector into its own mapping register, which is periodically read by the memory controller;

[0030] SPD Hub uses an in-band interrupt on the sideband bus to notify the memory controller to read;

[0031] The memory controller actively polls the SPD Hub.

[0032] Based on the first aspect, in the differentiated per-bank refresh scheduling phase, the memory controller allocates the number of per-bank refresh commands according to the per-bank refresh priority vector within one tREFI cycle, and can also allocate the number of per-bank refresh commands according to the per-bank refresh priority vector within a time window longer than one tREFI cycle.

[0033] Secondly, this application discloses a DRAM module partition refresh system for serial presence detection central aggregation of on-chip error events, employing the aforementioned DRAM module partition refresh method for serial presence detection central aggregation of on-chip error events, including:

[0034] DRAM devices that support on-die ECC and can expose correctable error statistics via sideband or in-band mechanisms;

[0035] SPD Hub, conforming to the JEDEC JESD300-5B.01 specification, communicates with DRAM devices and memory controllers via a sideband bus and has a built-in microcontroller or state machine; it also exports a summary of the priority vector to the host operating system or BIOS via the sideband bus.

[0036] The memory controller supports JEDEC DDR5 fine-grained refresh mode and can receive priority vectors from the SPD Hub.

[0037] Based on the second aspect, the SPD Hub includes a sideband interface unit, a hold time distribution aggregator, a priority generator, an output register group, and a control unit;

[0038] The sideband interface unit is coupled to the DRAM device and the memory controller, respectively;

[0039] The time-distribution aggregator maintains a per-bank event count histogram and its sliding window;

[0040] The priority generator maps the histogram to per-bank priority levels;

[0041] The output register group stores the per-bank refresh priority vector for access by the memory controller;

[0042] The control unit is used to coordinate the timing of the operation of the sideband interface unit, the time distribution aggregator, the priority generator, the output register group, and the control unit.

[0043] The beneficial effects of this invention are:

[0044] 1) The decision signal is directly related to the UCE risk. Since the on-die ECC event statistics directly reflect the error rate of DRAM cells, and the error rate is highly correlated with the distribution of cells with weak hold time, making refresh decisions based on this signal can directly target which banks are more prone to errors. Therefore, it is necessary to refresh more often. This core causal chain can more accurately allocate refresh resources to the banks that truly need them. Under the same tREFI budget, the probability of UCE in high-risk banks can be reduced.

[0045] 2) Online aging and VRT tracking: Since the aggregation cycle is on the order of 100 milliseconds to 1 second, SPD Hub can continuously update and maintain the time distribution characterization during operation, and follow dynamic factors such as DRAM aging, VRT events, and temperature changes, avoiding the defects of offline characterization that cannot evolve.

[0046] 3) Module local decision-making reduces the burden on MC. Since aggregation and priority generation are handled by SPD Hub, the memory controller only needs to receive a vector of length B and perform REFsb allocation accordingly. The additional computation and storage overhead on the MC side is minimal.

[0047] 4) Fully compatible with JEDEC specifications, the execution layer rests on the REFsb command of DDR5 FGR, and the instruction side does not involve new commands or new protocols; the transmission between SPD Hub and MC rests on the I3C sideband, conforms to the JESD300-5B.01 specification, and can be implemented on existing DDR5 RDIMM / LRDIMM / MRDIMM materials through SPD Hub firmware upgrade. Attached Figure Description

[0048] Figure 1 This is a schematic diagram illustrating the steps of the DRAM module partition refresh method for serial presence detection central aggregation on-chip error events according to an embodiment of the present invention;

[0049] Figure 2 This is a flowchart illustrating the DRAM module partition refresh method for serial presence detection central aggregation of on-chip error events according to an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of the DRAM module partition refresh system for serial presence detection center aggregation of on-chip error events according to an embodiment of the present invention. Detailed Implementation

[0051] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Here, the technical terms used in this application are explained:

[0053] On-die ECC event statistics: Statistical signals such as the correctable error count and ALERT_n trigger frequency output by the DRAM chip's internal error correction code mechanism during runtime;

[0054] Durational distribution characterization: A quantitative description of the distribution of weak duration units in a bank, which may take the form of a histogram, cumulative distribution function or its quantitative approximation;

[0055] Refresh priority vector: an ordered set of components representing the refresh urgency of different banks, with each component corresponding to the priority level of a bank;

[0056] Fine-grained refresh mode: The FGR mode in the JEDEC DDR5 specification supports issuing REFsb commands on a single bank basis;

[0057] per-bank refresh (REFsb): Single-bank refresh command in FGR mode;

[0058] tREFIDDR5: Average refresh interval in the JEDEC DDR5 specification;

[0059] VRT (Variable Retention Time): The phenomenon that the retention time of a single DRAM cell changes over time;

[0060] UCE: Uncorrectable Error.

[0061] For example, see Figures 1-2This application discloses a DRAM module partitioned refresh method for aggregating on-chip error events by a serial presence detection hub. The method involves a serial presence detection hub on the DRAM module aggregating on-die ECC event statistics of DRAM devices within the module via a sideband bus; the hub constructs a hold time distribution representation for at least one bank based on the event statistics and generates a per-bank refresh priority vector accordingly; the hub transmits the priority vector to the memory controller via the sideband bus; and the memory controller schedules per-bank refresh commands differentially according to the priority vector in fine-grained refresh mode. This invention uses online ECC events instead of activation counts or offline characterization as the decision source, and uses the SPD Hub as the module-local aggregation and decision-making entity, outputting spatially differentiated refresh scheduling results. This method can reduce overall refresh energy consumption and the probability of uncorrectable errors in critical banks without modifying the DRAM chip design and while complying with JEDEC specifications. Specifically, it includes the following steps:

[0062] S1. Aggregation phase of on-die ECC event statistics: Based on the aggregation period T_a, the SPD Hub reads the on-die ECC event statistics (reflecting the true distribution of hold time) from the DRAM device via the sideband bus, including the number of correctable errors (CE) on each bank of the DRAM device in the current aggregation period, the trigger frequency of the ALERT_n signal, and a summary of the error distribution on the preset bit line or word line; then, the aggregation result is cached in the SPD Hub storage area in the form of a per-bank count vector;

[0063] S2, the construction phase of the hold time distribution representation: SPD Hub maintains an event count histogram within a sliding time window for each bank, and calculates the hold time distribution representation of the bank through the event count histogram. The hold time distribution representation includes a cumulative distribution function or a quantization approximation. The decision-making entity is placed on SPD Hub, which uses its sideband access capability and programmability to realize online aggregation and priority generation, avoiding the need to modify the DRAM chip layout.

[0064] S3, per-bank refresh priority vector generation stage: SPD Hub maps the hold time distribution of each bank to a priority level, and then concatenates the priority levels of each bank according to their corresponding bank numbers to form a per-bank refresh priority vector;

[0065] S4. Priority vector cross-chip transfer stage: The SPD Hub outputs the per-bank refresh priority vector to the memory controller via the sideband bus (e.g., I3C);

[0066] S5. Differentiated per-bank refresh scheduling phase: In DDR5 fine-grained refresh mode (FGR), the memory controller schedules per-bank refresh commands according to the per-bank refresh priority vector. For banks marked as first-risk, the scheduling weight of their per-bank refresh commands is increased to a first predetermined proportion (the per-bank refresh commands with the first predetermined proportion of scheduling weight increase from 20% to 50%). For banks marked as fourth-risk, the scheduling weight of their per-bank refresh commands is decreased to a second predetermined proportion (the per-bank refresh commands corresponding to the second predetermined proportion of scheduling weight increase from 10% to 30%). This step is handled by the memory controller in FGR mode for differentiated scheduling of REFsb, balancing overall tREFI compliance with space differentiation.

[0067] For example, in the aggregation phase of on-die ECC event statistics: the aggregation period T_a is between 100 milliseconds and 1 second, the length of the counting vector per-bank is equal to the number of banks in the DRAM device, and the components of the per-bank counting vector correspond to the cumulative number of correctable errors of a bank in the current aggregation period.

[0068] For example, the on-die ECC event statistics also include temperature as a supplementary input; temperature can indirectly reflect the holding time (the holding time is shortened at high temperatures), but the temperature response is slow and the spatial resolution is insufficient (only 1-3 temperature sensors per rank). Therefore, temperature cannot replace ECC event statistics alone and can only be used as a supplementary input.

[0069] For example, in the construction phase of maintaining the time distribution representation: the construction method of the event count histogram includes equal-width binning (bin boundaries are fixed) and quantile binning (dynamically adjusted according to the quantile of historical samples), and the selection range of the number of bins is 4 to 16; wherein, each bin corresponds to a different cumulative error range, and the count value of each bin represents the number of sampling periods in which the sampled value of the bank falls into the corresponding interval.

[0070] For example, the priority levels include:

[0071] If the proportion of events exceeding the error segment in the bank's event count histogram exceeds the first threshold, it is marked as the first risk (high risk).

[0072] If the cumulative proportion of errors exceeds the second threshold but is lower than the first threshold, it is marked as the second risk (medium-high risk).

[0073] If the cumulative proportion of errors exceeds the third threshold but is lower than the second threshold, it is marked as the third risk (medium to low risk).

[0074] If the cumulative proportion of errors is lower than the third threshold, it is marked as the fourth risk (low risk).

[0075] The first risk, the second risk, the third risk, and the fourth risk are encoded with 2 bits.

[0076] For example, the priority level can also be represented using continuous weights (floating-point or fixed-point ratios).

[0077] For example, the SPD Hub communicates with the memory controller via the sideband bus in the following ways:

[0078] The SPD Hub writes the per-bank refresh priority vector into its own mapping register, which is periodically read by the memory controller;

[0079] SPD Hub uses an in-band interrupt on the sideband bus to notify the memory controller to read;

[0080] The memory controller actively polls the SPD Hub.

[0081] For example, in the differentiated per-bank refresh scheduling phase, the effective average refresh interval of all banks meets the JEDEC tREFI specification requirements. The memory controller allocates the number of per-bank refresh commands according to the per-bank refresh priority vector in one tREFI cycle, or it can allocate the number of per-bank refresh commands according to the per-bank refresh priority vector within a time window longer than one tREFI cycle (e.g., 64 tREFI cycles).

[0082] For example, see Figure 3 This application discloses a DRAM module partition refresh system that aggregates on-chip error events via a serial presence detection center. The DRAM module partition refresh method using the aforementioned serial presence detection center aggregates on-chip error events includes:

[0083] DRAM devices that support on-die ECC and can expose correctable error statistics via sideband or in-band mechanisms;

[0084] SPD Hub, conforming to the JEDEC JESD300-5B.01 specification, communicates with DRAM devices and memory controllers via a sideband bus and has a built-in microcontroller or state machine. It also exports a summary of the priority vector to the host operating system or BIOS via the sideband bus (read during module initialization via the BIOS interface, or polled at runtime via the ACPI method or sysfs interface). The operating system uses this information to make hot page allocation decisions at the NUMA layer or cgroup layer, prioritizing the allocation of volatile or recomputable data to the intervals where high-risk banks are located, and allocating critical data to the intervals where low-risk banks are located, further reducing the UCE probability of critical data.

[0085] The memory controller supports JEDEC DDR5 fine-grained refresh mode and can receive priority vectors from the SPD Hub.

[0086] For example, the SPD Hub includes a sideband interface unit, a hold time distribution aggregator, a priority generator, an output register group, and a control unit;

[0087] The sideband interface unit is coupled to the DRAM device and the memory controller, respectively;

[0088] The time-distribution aggregator maintains a per-bank event count histogram and its sliding window;

[0089] The priority generator maps the histogram to per-bank priority levels;

[0090] The output register group stores the per-bank refresh priority vector for access by the memory controller;

[0091] The control unit is used to coordinate the working timing of the sideband interface unit, the time distribution aggregator, the priority generator, the output register group, and the control unit.

[0092] Aggregators and generators can be implemented as hardware state machines, SPD Hub can be built into microcontroller firmware, or a combination of both.

[0093] Example 1: In the context of the DDR5 RDIMM standard scenario, this application demonstrates the following:

[0094] The DRAM devices are: 16 Gb DDR5 ×8, each containing 32 banks, with a total of 10 located on both sides of the RDIMM; SPD Hub: built-in MCU.

[0095] The specific process includes: Every 500 milliseconds, the SPD Hub reads the per-bank CE count from each DRAM via I3C and writes it to local SRAM (16-bit count per bank, totaling 32 × 10 × 2 = 640 bytes); maintains an 8-bin histogram for each bank with a sliding window length of 60 seconds (corresponding to 120 sampling points); maps to 4 priority levels according to a predetermined threshold, with 2-bit encoding per bank, totaling 32 × 10 × 2 = 640 bits = 80 bytes for the entire module; the vector is written to the MR_PRIO register area of ​​the SPD Hub, and the memory controller reads it once every tREFI × 8 cycles; in FGR mode, the memory controller allocates REFsb every 8 tREFIs: sending 1-2 more REFsb to high-risk banks and 0-1 fewer to low-risk banks, maintaining a total of 10 DRAMs × 32 banks = 10 REFsb per 8 tREFIs. 320. The parameters in this embodiment are exemplary values; specific parameters should be calibrated offline based on the characteristics of the DRAM chips and the capabilities of the SPD Hub.

[0096] Example 2: This application addresses the high-density scenario of DDR5 MRDIMM:

[0097] The DRAM devices are: 32 Gb DDR5 MRDIMMs, two ranks, 10 chips per rank. Key changes: the aggregation cycle is reduced to 200 milliseconds to accommodate scenarios with more frequent rank switching; the priority vector dimension is expanded to 2 × 640 = 1280 bytes; SPD Hub aggregates ECC events for both ranks separately.

[0098] Example 3: In the case of low-power scenarios of LPDDR5X LPCAMM2:

[0099] Since LPCAMM2 focuses on low power consumption, refresh energy consumption is a key bottleneck. In this embodiment, the SPD Hub reduces the REFsb frequency of low-risk banks by 30%-50%, while keeping the frequency of high-risk banks unchanged, prioritizing energy-saving benefits; the aggregation cycle is reduced to 1 second to reduce sideband power consumption.

[0100] Example 4: This application is linked to the operating system's hot page allocation:

[0101] The SPD Hub additionally outputs a per-bank priority summary to the operating system via the ACPI extension method. When selecting a target bank, the operating system's NUMA allocator binds critical data such as transaction logs to the address range of the bank with the highest priority (lowest UCE risk); and prioritizes recalculating data such as page cache in the bank with the lowest priority. This embodiment can be used in combination with embodiments one, two, and three.

[0102] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A DRAM module partition refresh method for serially detecting on-chip error events at a central aggregation point, characterized in that, Includes the following steps: The aggregation phase of on-die ECC event statistics: Based on the aggregation period T_a, SPD Hub reads the on-die ECC event statistics from the DRAM device via the sideband bus, including the number of correctable errors on each bank of the DRAM device in the current aggregation period, the trigger frequency of the ALERT_n signal, and a summary of the error distribution on the preset bit line or word line; then, the aggregation result is cached in the SPD Hub storage area in the form of a per-bank count vector; The construction phase of the time-holding distribution representation: SPD Hub maintains an event count histogram within a sliding time window for each bank, and calculates the time-holding distribution representation of the bank through the event count histogram. The time-holding distribution representation includes a cumulative distribution function or a quantization approximation. The generation phase of the per-bank refresh priority vector: SPD Hub maps the hold time distribution of each bank to a priority level, and then concatenates the priority levels of each bank in order of their corresponding bank numbers to form a per-bank refresh priority vector; Priority vector cross-chip transfer stage: SPD Hub outputs per-bank refresh priority vector to memory controller via sideband bus; Differentiated per-bank refresh scheduling phase: Under the DDR5 fine-grained refresh mode (FGR), the memory controller schedules per-bank refresh commands according to the per-bank refresh priority vector. For banks marked as first risk, the scheduling weight of their per-bank refresh commands is increased to a first predetermined proportion; for banks marked as fourth risk, the scheduling weight of their per-bank refresh commands is decreased to a second predetermined proportion.

2. The DRAM module partition refresh method for serial existence detection central aggregation on-chip error events according to claim 1, characterized in that, In the aggregation phase of on-die ECC event statistics: the aggregation period T_a is between 100 milliseconds and 1 second, the length of the counting vector per-bank is equal to the number of banks in the DRAM device, and the components of the per-bank counting vector correspond to the cumulative number of correctable errors of a bank in the current aggregation period.

3. The DRAM module partition refresh method for serial presence detection central aggregation on-chip error events according to claim 1, characterized in that: The on-die ECC event statistics also include temperature as a supplementary input.

4. The DRAM module partition refresh method for serial existence detection central aggregation on-chip error events according to claim 1, characterized in that, In the construction phase of maintaining the time distribution representation: the construction method of the event count histogram includes equal-width binning and quantile binning, and the number of bins is selected from 4 to 16; wherein, each bin corresponds to a different cumulative error range, and the count value of each bin represents the number of sampling periods in which the sampled value of the bank falls into the corresponding interval.

5. The DRAM module partition refresh method for serial existence detection central aggregation on-chip error events according to claim 1, characterized in that, The priority levels include: If the proportion of events exceeding the error segment in the bank's event count histogram exceeds the first threshold, it is marked as the first risk. If the cumulative proportion of errors exceeds the second threshold but is below the first threshold, it is marked as the second risk. If the cumulative proportion of errors exceeds the third threshold but is below the second threshold, it is marked as a third risk. If the cumulative proportion of errors is lower than the third threshold, it is marked as the fourth risk. The first risk, the second risk, the third risk, and the fourth risk are encoded with 2 bits.

6. The DRAM module partition refresh method for serial existence detection central aggregation on-chip error events according to claim 1, characterized in that, The priority level can also be represented using continuous weights.

7. The DRAM module partition refresh method for serial presence detection central aggregation on-chip error events according to claim 1, characterized in that: The SPD Hub communicates with the memory controller via the sideband bus in the following ways: The SPD Hub writes the per-bank refresh priority vector into its own mapping register, which is periodically read by the memory controller; SPD Hub uses an in-band interrupt on the sideband bus to notify the memory controller to read; The memory controller actively polls the SPD Hub.

8. The DRAM module partition refresh method for serial presence detection central aggregation on-chip error events according to claim 1, characterized in that: During the differentiated per-bank refresh scheduling phase, the effective average refresh interval for all banks meets the JEDEC tREFI specification requirements. The memory controller allocates the number of per-bank refresh commands according to the per-bank refresh priority vector within one tREFI cycle, and can also allocate the number of per-bank refresh commands according to the per-bank refresh priority vector within a time window longer than one tREFI cycle.

9. A DRAM module partition refresh system for serial presence detection of on-chip error events at a central aggregation point, employing the DRAM module partition refresh method for serial presence detection of on-chip error events at a central aggregation point as described in any one of claims 1-8, characterized in that, include: DRAM devices that support on-die ECC and can expose correctable error statistics via sideband or in-band mechanisms; SPD Hub, conforming to the JEDEC JESD300-5B.01 specification, communicates with DRAM devices and memory controllers via a sideband bus and has a built-in microcontroller or state machine; it also exports a summary of the priority vector to the host operating system or BIOS via the sideband bus. The memory controller supports JEDEC DDR5 fine-grained refresh mode and can receive priority vectors from the SPD Hub.

10. The DRAM module partition refresh system for serial presence detection central aggregation of on-chip error events according to claim 9, characterized in that: The SPD Hub includes a sideband interface unit, a hold time distribution aggregator, a priority generator, an output register group, and a control unit; The sideband interface unit is coupled to the DRAM device and the memory controller, respectively; The time-distribution aggregator maintains a per-bank event count histogram and its sliding window; The priority generator maps the histogram to per-bank priority levels; The output register group stores the per-bank refresh priority vector for access by the memory controller; The control unit is used to coordinate the timing of the operation of the sideband interface unit, the time distribution aggregator, the priority generator, the output register group, and the control unit.

Images