Memory device

Abstract

The present disclosure relates to a memory device. The disclosed memory device includes: a memory cell array including a plurality of row lines extending in a first horizontal direction; a plurality of pass transistors connected to the plurality of row lines; and a contact connected to a gate electrode of the pass transistors. The plurality of pass transistors are arranged in a plurality of stages along a second horizontal direction perpendicular to the first horizontal direction. In each stage, two pass transistors are paired to share a gate electrode. The contact connected to the single gate electrode is disposed on an element isolation layer between the two paired pass transistors.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a memory device having a transmission transistor circuit. Background Technology

[0002] Memory devices can be classified into volatile memory devices and non-volatile memory devices. Examples of non-volatile memory devices include flash memory devices and resistive memory devices such as ReRAM (Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), and MRAM (Magnetic Random Access Memory). A memory device includes an array of memory cells and transfer transistor circuitry that delivers operating voltages to the word lines of the memory cell array. Summary of the Invention

[0003] Embodiments of this disclosure provide a memory device having a transmission transistor circuit.

[0004] According to embodiments of this disclosure, a memory device may include: a memory cell array including a plurality of row lines extending in a first horizontal direction; a plurality of transfer transistors connected to the plurality of row lines; and a plurality of contacts connected to the gate electrodes of the plurality of transfer transistors. The plurality of transfer transistors may be arranged in multiple stages in a second horizontal direction perpendicular to the first horizontal direction. In each stage, two transfer transistors may be paired to share a gate electrode, and contacts connected to the shared gate electrode may be vertically disposed above a component isolation layer between the two paired transfer transistors.

[0005] According to embodiments of this disclosure, a memory device may include: a plurality of memory blocks arranged along a second horizontal direction perpendicular to a first horizontal direction, each memory block including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction; a plurality of transfer transistors connected to corresponding electrode layers among the plurality of electrode layers; and a plurality of global row lines disposed on the plurality of transfer transistors and connected to the electrode layers of the plurality of memory blocks through the plurality of transfer transistors. The plurality of electrode layers in each of the plurality of memory blocks may include a plurality of alternately stacked odd-numbered electrode layers and a plurality of even-numbered electrode layers. The plurality of global row lines may include a plurality of odd-numbered global row lines and a plurality of even-numbered global row lines alternately arranged along the second horizontal direction. Each of the odd-numbered electrode layers of the plurality of memory blocks may be connected to one of the odd-numbered global row lines, and each of the even-numbered electrode layers of the plurality of memory blocks may be connected to one of the even-numbered global row lines.

[0006] According to embodiments of this disclosure, a memory device may include: a first semiconductor layer; and a second semiconductor layer, the second semiconductor layer overlapping the first semiconductor layer in a vertical direction. The first semiconductor layer may include: a first substrate; and a plurality of memory blocks arranged on the first substrate along a second horizontal direction perpendicular to a first horizontal direction. Each memory block includes a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in the vertical direction. The second semiconductor layer may include: a second substrate; a plurality of transfer transistors disposed on the second substrate and connected to the electrode layers of the plurality of memory blocks; and a plurality of contacts connected to the gate electrodes of the plurality of transfer transistors. The plurality of transfer transistors may be arranged in multiple stages along the second horizontal direction. In each stage, two transfer transistors may be paired to share a gate electrode, and the contacts connected to the shared gate electrode may be disposed in the vertical direction above a device isolation region on the second substrate between the two paired transfer transistors.

[0007] According to embodiments of the present disclosure, a memory device having a transmission transistor circuit can be provided. Attached Figure Description

[0008] Figure 1 This is a block diagram of a memory device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a schematic diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 3 It shows Figure 1 The first memory block and the second memory block, the first transmission transistor group and the second transmission transistor group, the block selector and the global row line decoder.

[0011] Figure 4 It is shown schematically. Figure 1 A three-dimensional view of the first and second memory blocks.

[0012] Figure 5 This is a schematic plan view illustrating a portion of a transmission transistor circuit according to an embodiment of the present disclosure.

[0013] Figure 6 It is along Figure 5 A cross-sectional view taken from line A-A'.

[0014] Figure 7 It is along Figure 5 The cross-sectional view taken by line B-B'.

[0015] Figure 8It is along Figure 5 A cross-sectional view taken from line C-C'.

[0016] Figure 9 This is a plan view illustrating the transmission transistor and global row lines according to an embodiment of the present disclosure.

[0017] Figure 10 It is along Figure 9 The cross-sectional view taken by line D-D'.

[0018] Figure 11 It is along Figure 9 A cross-sectional view taken from line E-E'.

[0019] Figure 12 It is along Figure 9 The cross-sectional view taken by line F-F'.

[0020] Figure 13 This is a plan view showing the transmission transistor according to the comparative example.

[0021] Figure 14 It is along Figure 13 A cross-sectional view taken from line G-G'.

[0022] Figure 15 This is a plan view showing a transmission transistor according to another comparative example.

[0023] Figure 16 It is along Figure 15 A cross-sectional view taken from line H-H'. Detailed Implementation

[0024] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When assigning reference numerals to components in each figure, the same components may be assigned the same reference numerals even if shown in different figures. Details of known technology or function may be omitted if they are considered to obscure the subject matter of the present disclosure. As used herein, terms such as “comprising,” “having,” or “consisting of” related to components allow for the inclusion of other components, unless explicitly used with terms such as “only.” Additionally, unless the context clearly indicates otherwise, singular expressions such as “a,” “an,” and “the” are intended to include their plural forms.

[0025] Such designations as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used to describe components of this disclosure. These designations are intended to distinguish one component from another only and are not intended to limit the nature, order, sequence, or number of components.

[0026] Regarding the description of the positional relationship between components, when two or more components are described as "connected," "linked," or "coupled," it should be understood that they may be directly "connected," "linked," or "coupled," or may have intermediate components. Here, the intermediate component may be included in one or more of the two or more components that are "connected," "linked," or "coupled" to each other.

[0027] When terms such as “after,” “follow,” “after,” or “before” are used to describe the temporal or sequential relationship between parts, methods of operation, or methods of manufacture, they may also include non-continuous situations unless the terms “immediately following” or “directly” are explicitly used.

[0028] When a component is associated with a value or its corresponding information (e.g., height), such value or information can be interpreted as including tolerances due to various factors (e.g., process variations, internal or external influences, or noise), even without an explicit separate description.

[0029] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a block diagram of a memory device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 The memory device 10 may include a memory cell array 100 and peripheral circuitry 200. The peripheral circuitry 200 may include a row decoder 210, a page buffer circuit (PB circuit) 220, and control logic 230. Although not shown, the peripheral circuitry 200 may also include a voltage generator, data input / output circuitry, a command decoder, and an address decoder.

[0032] The memory cell array 100 may include multiple memory blocks BLK1 to BLKn. Each of the memory blocks BLK1 to BLKn may include multiple memory cells. For example, the memory cell may be a flash memory cell. The following description assumes that the memory cell is a NAND flash memory cell; however, the invention is not limited thereto. The memory cell may also be a resistive memory cell such as ReRAM, PRAM, or MRAM.

[0033] The memory cell array 100 can be connected to the row decoder 210 via row lines RL. The row lines RL may include at least one source select line, multiple word lines, and at least one drain select line. The memory cell array 100 can be connected to the page buffer circuit 220 via multiple bit lines BL.

[0034] The line decoder 210 may include a block selector 211, a global line decoder 212, and a transmission transistor circuit 213.

[0035] Block selector 211 can be connected to transmission transistor circuit 213 via block select signal line BLKWL. Block selector 211 can receive row address X-ADDR from control logic 230 and generate block select signal in response to the received row address X-ADDR.

[0036] The global row line decoder 212 can be connected to the transmission transistor circuit 213 via the global row line GRL. The global row line decoder 212 can receive voltage from a voltage generator (not shown) and, in response to a control signal received from the control logic 230, can output the received voltage to the global row line GRL.

[0037] The transmission transistor circuit 213 may include multiple transmission transistor groups PTG1 to PTGn, each corresponding to one of multiple memory blocks BLK1 to BLKn. Each of the transmission transistor groups PTG1 to PTGn can be connected to the corresponding memory block via a row line RL. Each of the transmission transistor groups PTG1 to PTGn can be connected to the global row line decoder 212 via a global row line GRL. The global row line GRL can be shared by multiple transmission transistor groups PTG1 to PTGn. Multiple transmission transistor groups PTG1 to PTGn can share the global row line GRL.

[0038] In the first mode, block selector 211 can provide a block select signal to one of the selected transmission transistor groups PTG1 to PTGn. In the first mode, global row line decoder 212 can provide operating voltage to transmission transistor groups PTG1 to PTGn via global row line GRL. The transmission transistor group receiving the block select signal can pass the operating voltage provided by global row line decoder 212 to the corresponding memory block via row line RL. The first mode can be a normal operation mode. Normal operation can include read operations, write operations, erase operations, or read / write verification operations.

[0039] In the second mode, block selector 211 can provide a block select signal to at least one of the transmission transistor groups PTG1 to PTGn. In the second mode, global row line decoder 212 can provide a test voltage to the transmission transistor groups PTG1 to PTGn via global row line GRL. The transmission transistor groups PTG1 to PTGn can then transfer the test voltage provided by global row line decoder 212 to memory blocks BLK1 to BLKn via row line RL. The second mode can be a test operation mode.

[0040] As will be referred to later Figure 4The row lines of each of the memory blocks BLK1 to BLKn may include alternately stacked odd-numbered and even-numbered row lines. In the second mode, a first test voltage and a second test voltage may be applied alternately to the odd-numbered row lines. Similarly, a first test voltage and a second test voltage may be applied alternately to the even-numbered row lines. The first test voltage may be a high voltage, while the second test voltage may be a low voltage. The test voltage applied to the odd-numbered row lines may be different from the test voltage simultaneously applied to the even-numbered row lines. While the first test voltage is applied to the odd-numbered row lines, the second test voltage may be applied to the even-numbered row lines, and vice versa. Due to the potential difference between the test voltages applied to the odd-numbered and even-numbered row lines, stress may be applied to the memory cell array 100. Under such stress, defects such as short circuits between adjacent row lines may occur at weak points. After intentionally applying stress in the second mode, testing can be performed to detect grown bad blocks (GBBs).

[0041] Page buffer circuit 220 can select a portion of bit line BL in response to column address Y-ADDR. Depending on the operating mode, page buffer circuit 220 can operate as a write driver or a sense amplifier.

[0042] Control logic 230 can control the overall operation of the memory device 10. Control logic 230 can receive commands CMD, addresses ADDR, and control signals CTRL, and based on the received commands CMD, addresses ADDR, and control signals CTRL, can generate various control signals to program data into the memory cell array 100, read data from the memory cell array 100, or erase data stored in the memory cell array 100. Control logic 230 can output row address X-ADDR and column address Y-ADDR.

[0043] Figure 2 This is a schematic diagram illustrating a memory device according to an embodiment of the present disclosure.

[0044] Reference Figure 2 The memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2. The first semiconductor layer L1 and the second semiconductor layer L2 may overlap in the vertical direction VD. Although for ease of understanding, the first semiconductor layer L1 and the second semiconductor layer L2 are... Figure 2 The layers are shown as being spaced apart in the vertical direction VD, but should be understood as having a structure in which the bottom surface of the first semiconductor layer L1 contacts the top surface of the second semiconductor layer L2.

[0045] In the implementation, the peripheral circuit (see...) Figure 1(200 in the image) can be disposed in the second semiconductor layer L2, and the memory cell array (see [reference]) Figure 1 (100) can be set in the first semiconductor layer L1.

[0046] In the first semiconductor layer L1, multiple row lines RL can extend in a first horizontal direction HD1, and multiple bit lines BL can extend in a second horizontal direction HD2. Although not shown, the first semiconductor layer L1 may include a first substrate. A stack can be formed on the first substrate by vertically stacking multiple row lines RL in a vertical direction VD. The row lines RL can be combined with cell plugs that penetrate the stack in the vertical direction VD to form a three-dimensionally arranged memory cell.

[0047] The second semiconductor layer L2 may include a second substrate. Transistors and wiring patterns for semiconductor devices may be formed on this second substrate to configure peripheral circuitry (see [link to documentation]). Figure 1 (200 in the middle).

[0048] The first semiconductor layer L1 and the second semiconductor layer L2 can be formed on a single wafer. The second semiconductor layer L2 can be formed first, and then the first semiconductor layer L1 can be built on the second semiconductor layer L2. In this case, the memory device 10 can be defined as having a Peri-Under-Cell (PUC) structure. Alternatively, the first semiconductor layer L1 and the second semiconductor layer L2 can be fabricated on separate wafers and then bonded together using a bonding technique. In this case, the memory device 10 can be defined as having a Peri-Over-Cell (POC) structure. The memory device 10 according to this disclosure can be configured as either a PUC structure or a POC structure. Meanwhile, although not shown, a memory cell array (see...) Figure 1 (100 in the middle) and peripheral circuits (see ... Figure 1 (200) can be arranged planarly on a single substrate.

[0049] Figure 3 It shows Figure 1 The first memory block and the second memory block, the first transmission transistor group and the second transmission transistor group, the block selector, and the global row line decoder are shown.

[0050] Reference Figure 3The first memory block BLK1 may include multiple first row lines DSLa, WLa, and SSLa. The first row lines DSLa, WLa, and SSLa may include a first drain select line DSLa, multiple first word lines WLa, and a first source select line SSLa. The second memory block BLK2 may include multiple second row lines DSLb, WLb, and SSLb. The second row lines DSLb, WLb, and SSLb may include a second drain select line DSLb, multiple second word lines WLb, and a second source select line SSLb.

[0051] The first transfer transistor group PTG1 may include multiple transfer transistors PTR1. The second transfer transistor group PTG2 may include multiple transfer transistors PTR2.

[0052] Each of the transfer transistors PRa in the first transfer transistor group PTG1 can be connected between a corresponding line in the global row lines (one of GDSL, GWL, and GSSL) and a corresponding line in the first row lines (one of DSLa, WLa, and SSLa). The gate electrodes of the transfer transistors PRa in the first transfer transistor group PTG1 can be connected together to the first block select signal line BLKWL1, which can be connected to the block selector 211. When an active block select signal is provided from the block selector 211 to the first block select signal line BLKWL1, the transfer transistors PRa in the first transfer transistor group PTG1 can be turned on. Therefore, the operating voltage provided through the global row lines GDSL, GWL, and GSSL can be transmitted to the first memory block BLK1 through the first row lines DSLa, WLa, and SSLa.

[0053] Each of the transfer transistors PTRb in the second transfer transistor group PTG2 can be connected between a corresponding line in the global row (one of GDSL, GWL, and GSSL) and a corresponding line in the second row (one of DSLb, WLb, and SSLb). The gate electrodes of the transfer transistors PTRb in the second transfer transistor group PTG2 can be connected together to the second block select signal line BLKWL2, which can be connected to the block selector 211. When an active block select signal is provided from the block selector 211 to the second block select signal line BLKWL2, the transfer transistors PTRb in the second transfer transistor group PTG2 can be turned on. Therefore, the operating voltage provided through the global row lines GDSL, GWL, and GSSL can be transmitted to the second memory block BLK2 through the second row lines DSLb, WLb, and SSLb.

[0054] Figure 4 It is shown schematically. Figure 1 A three-dimensional view of the first and second memory blocks.

[0055] Reference Figure 4 A first memory block BLK1 and a second memory block BLK2 are disposed on a first substrate SUB1. The first memory block BLK1 and the second memory block BLK2 are adjacent to each other along a second horizontal direction HD2 that intersects with the first horizontal direction HD1.

[0056] The first memory block BLK1 may include a plurality of first interlayer insulating layers 11 and a plurality of first electrode layers 21 alternately stacked on the first substrate SUB1. The first memory block BLK1 may also include a plurality of first cell plugs 31 that vertically penetrate the plurality of first interlayer insulating layers 11 and the plurality of first electrode layers 21.

[0057] At least one of the lowest first electrode layers 21 can form a source select line, and at least one of the uppermost first electrode layers 21 can form a drain select line. The first electrode layers 21 between the source select line and the drain select line can form word lines. The first electrode layers 21 may include a plurality of first odd-numbered electrode layers 21o and a plurality of first even-numbered electrode layers 21e alternately stacked in the vertical direction VD. The first odd-numbered electrode layers 21o are disposed at odd-numbered positions in the first electrode layers 21 starting from the first substrate SUB1, and the first even-numbered electrode layers 21e are disposed at even-numbered positions in the first electrode layers 21 starting from the first substrate SUB1.

[0058] Each of the first cell plugs 31 may include a first channel layer 31A and a first cell gate insulating layer 31B. The first channel layer 31A may include polysilicon or monocrystalline silicon, and may include p-type impurities such as boron (B) in some regions. The first cell gate insulating layer 31B may surround the outer wall of the first channel layer 31A. The first cell gate insulating layer 31B may include a tunnel insulating film, a charge storage layer, and a barrier film sequentially stacked from the outer wall of the first channel layer 31A. In some embodiments, the first cell gate insulating layer 31B may have an ONO (oxide-nitride-oxide) structure, wherein an oxide film, a nitride film, and another oxide film are sequentially stacked.

[0059] The second memory block BLK2 may include a plurality of second interlayer insulating layers 12 and a plurality of second electrode layers 22 alternately stacked on the first substrate SUB1. The second memory block BLK2 may also include a plurality of second cell plugs 32 that vertically penetrate the plurality of second interlayer insulating layers 12 and the plurality of second electrode layers 22.

[0060] At least one of the lowest second electrode layers 22 can form a source select line, and at least one of the uppermost second electrode layers 22 can form a drain select line. The second electrode layers 22 between the source select line and the drain select line can form word lines. The second electrode layers 22 may include a plurality of second odd-numbered electrode layers 22o and a plurality of second even-numbered electrode layers 22e alternately stacked in the vertical direction VD. The second odd-numbered electrode layers 22o are disposed at odd-numbered positions in the second electrode layers 22 starting from the first substrate SUB1, and the second even-numbered electrode layers 22e are disposed at even-numbered positions in the second electrode layers 22 starting from the first substrate SUB1.

[0061] Each of the second cell plugs 32 may include a second channel layer 32A and a second cell gate insulating layer 32B. The second channel layer 32A may be made of the same material as the first channel layer 31A. The second cell gate insulating layer 32B may surround the outer wall of the second channel layer 32A and may have a structure similar to that of the first cell gate insulating layer 31B.

[0062] Figure 5 This is a schematic plan view illustrating a portion of a transmission transistor circuit according to an embodiment of the present disclosure. Figure 6 It is along Figure 5 A cross-sectional view taken from line A-A'. Figure 7 It is along Figure 5 The cross-sectional view taken by line B-B'. Figure 8 It is along Figure 5 A cross-sectional view taken from line C-C'. Figure 5 It shows that it includes Figure 1 and Figure 3 The transmission transistors in the first transmission transistor group PTG1 and the second transmission transistor group PTG2.

[0063] Reference Figures 5 to 8 The first transfer transistor group PTG1 may include a first transfer transistor PTR1, a second transfer transistor PTR2, a ninth transfer transistor PTR9, a tenth transfer transistor PTR10, an eleventh transfer transistor PTR11, and a twelfth transfer transistor PTR12. The second transfer transistor group PTG2 may include a third transfer transistor PTR3, a fourth transfer transistor PTR4, a fifth transfer transistor PTR5, a sixth transfer transistor PTR6, a seventh transfer transistor PTR7, and an eighth transfer transistor PTR8. The transfer transistors PTR1 to PTR12 of the first transfer transistor group PTG1 and the second transfer transistor group PTG2 may be arranged in three stages.

[0064] In the first transfer transistor group PTG1, the first transfer transistor PTR1 and the second transfer transistor PTR2 can be arranged in the first stage (stage). <1> In the third stage (stage), the ninth transfer transistor PTR9 to the twelfth transfer transistor PTR12 can be arranged in the third stage (stage). <3> In the second transfer transistor group PTG2, the third transfer transistor PTR3 to the fourth transfer transistor PTR4 can be arranged in the first stage (stage). <1> In the second stage (stage), the fifth transfer transistor PTR5 to the eighth transfer transistor PTR8 can be arranged. <2> )middle.

[0065] The dimensions of the first memory block BLK1 and the second memory block BLK2 in the second horizontal direction HD2 can both be P1. First level (level) <1> Level 2 (Level) <2> ) and Level 3 (level) <3> The total dimension in the second horizontal direction HD2 can be P2, which can be twice P1 (i.e., P1×2).

[0066] A device isolation layer (STI) can be formed on the second substrate SUB2 to define an active region and a device isolation region. The device isolation region is the area where the device isolation layer STI is formed, while the active region is the area where the device isolation layer STI is not formed. The device isolation layer STI is disposed between adjacent active regions.

[0067] The active regions may include the first active region ACT1 through the eighth active region ACT8. The first active regions ACT1 through the fourth active region ACT4 may be arranged in a row along the first horizontal direction HD1. The fifth active region ACT5 is adjacent to the first active region ACT1 in the second horizontal direction HD2. The sixth active region ACT6 is adjacent to the second active region ACT2 in the second horizontal direction HD2. The seventh active region ACT7 is adjacent to the third active region ACT3 in the second horizontal direction HD2. The eighth active region ACT8 is adjacent to the fourth active region ACT4 in the second horizontal direction HD2. The fifth active regions ACT5 through the eighth active region ACT8 may also be arranged in a row along the first horizontal direction HD1.

[0068] The first transmission transistor PTR1 includes a first gate insulating film GI1 located on the second substrate SUB2, a first gate electrode GE1 located on the first gate insulating film GI1, and a first source region S1 and a first drain region D1 formed in the first active region ACT1 on both sides of the first gate electrode GE1. The first channel region CH1 of the first transmission transistor PTR1 is formed in the first active region ACT1 below the first gate electrode GE1, between the first source region S1 and the first drain region D1.

[0069] The second transmission transistor PTR2 is adjacent to the first transmission transistor PTR1 in the first horizontal direction HD1. The second transmission transistor PTR2 includes a first gate insulating film GI1 located on the second substrate SUB2, a first gate electrode GE1 located on the first gate insulating film GI1, and a second source region S2 and a second drain region D2 formed in the second active region ACT2 of the second substrate SUB2 on both sides of the first gate electrode GE1. The second channel region CH2 of the second transmission transistor PTR2 is formed below the first gate electrode GE1 in the second active region ACT2 between the second source region S2 and the second drain region D2.

[0070] The third transmission transistor PTR3 is adjacent to the second transmission transistor PTR2 in the first horizontal direction HD1. The third transmission transistor PTR3 includes a second gate insulating film GI2 located on the second substrate SUB2, a second gate electrode GE2 located on the second gate insulating film GI2, and a third source region S3 and a third drain region D3 formed in the third active region ACT3 of the second substrate SUB2 on both sides of the second gate electrode GE2. The third channel region CH3 of the third transmission transistor PTR3 is formed below the second gate electrode GE2 in the third active region ACT3 between the third source region S3 and the third drain region D3.

[0071] The fourth transfer transistor PTR4 is adjacent to the third transfer transistor PTR3 in the first horizontal direction HD1. The fourth transfer transistor PTR4 includes a second gate insulating film GI2 located on the second substrate SUB2, a second gate electrode GE2 located on the second gate insulating film GI2, and a fourth source region S4 and a fourth drain region D4 formed in the fourth active region ACT4 of the second substrate SUB2 on both sides of the second gate electrode GE2. The fourth channel region CH4 of the fourth transfer transistor PTR4 is formed below the second gate electrode GE2 in the fourth active region ACT4 between the fourth source region S4 and the fourth drain region D4.

[0072] The fifth transmission transistor PTR5 is adjacent to the first transmission transistor PTR1 on the second horizontal direction HD2. The fifth transmission transistor PTR5 includes a third gate insulating film GI3 located on the second substrate SUB2, a third gate electrode GE3 located on the third gate insulating film GI3, and a fifth source region S5 and a first common drain region CD1 formed in the fifth active region ACT5 of the second substrate SUB2 on both sides of the third gate electrode GE3. The fifth channel region CH5 of the fifth transmission transistor PTR5 is formed below the third gate electrode GE3 in the fifth active region ACT5 between the fifth source region S5 and the first common drain region CD1.

[0073] The sixth transmission transistor PTR6 is adjacent to the fifth transmission transistor PTR5 in the first horizontal direction HD1 and to the second transmission transistor PTR2 in the second horizontal direction HD2. The sixth transmission transistor PTR6 includes a third gate insulating film GI3 located on the second substrate SUB2, a third gate electrode GE3 located on the third gate insulating film GI3, and a sixth source region S6 and a second common drain region CD2 formed in the sixth active region ACT6 of the second substrate SUB2 on both sides of the third gate electrode GE3. The sixth channel region CH6 of the sixth transmission transistor PTR6 is formed below the third gate electrode GE3 in the sixth active region ACT6 between the sixth source region S6 and the second common drain region CD2.

[0074] The seventh transfer transistor PTR7 is adjacent to the sixth transfer transistor PTR6 in the first horizontal direction HD1 and to the third transfer transistor PTR3 in the second horizontal direction HD2. The seventh transfer transistor PTR7 includes a fourth gate insulating film GI4 located on the second substrate SUB2, a fourth gate electrode GE4 located on the fourth gate insulating film GI4, and a seventh source region S7 and a third common drain region CD3 formed in the seventh active region ACT7 of the second substrate SUB2 on both sides of the fourth gate electrode GE4. The seventh channel region CH7 of the seventh transfer transistor PTR7 is formed below the fourth gate electrode GE4 in the seventh active region ACT7 between the seventh source region S7 and the third common drain region CD3.

[0075] The eighth transfer transistor PTR8 is adjacent to the seventh transfer transistor PTR7 in the first horizontal direction HD1 and to the fourth transfer transistor PTR4 in the second horizontal direction HD2. The eighth transfer transistor PTR8 includes a fourth gate insulating film GI4 located on the second substrate SUB2, a fourth gate electrode GE4 located on the fourth gate insulating film GI4, and an eighth source region S8 and a fourth common drain region CD4 formed in the eighth active region ACT8 of the second substrate SUB2 on both sides of the fourth gate electrode GE4. The eighth channel region CH8 of the eighth transfer transistor PTR8 is formed below the fourth gate electrode GE4 in the eighth active region ACT8 between the eighth source region S8 and the fourth common drain region CD4.

[0076] The ninth transmission transistor PTR9 is adjacent to the fifth transmission transistor PTR5 on the second horizontal direction HD2. The ninth transmission transistor PTR9 includes a fifth gate insulating film GI5 located on the second substrate SUB2, a fifth gate electrode GE5 located on the fifth gate insulating film GI5, and a ninth source region S9 and a first common drain region CD1 formed in the fifth active region ACT5 of the second substrate SUB2 on both sides of the fifth gate electrode GE5. The fifth transmission transistor PTR5 and the ninth transmission transistor PTR9 share the first common drain region CD1. The ninth channel region CH9 of the ninth transmission transistor PTR9 is formed below the fifth gate electrode GE5 in the fifth active region ACT5 between the ninth source region S9 and the first common drain region CD1.

[0077] The tenth transmission transistor PTR10 is adjacent to the ninth transmission transistor PTR9 in the first horizontal direction HD1 and to the sixth transmission transistor PTR6 in the second horizontal direction HD2. The tenth transmission transistor PTR10 includes a fifth gate insulating film GI5 located on the second substrate SUB2, a fifth gate electrode GE5 located on the fifth gate insulating film GI5, and a tenth source region S10 and a second common drain region CD2 formed in the sixth active region ACT6 of the second substrate SUB2 on both sides of the fifth gate electrode GE5. The sixth transmission transistor PTR6 and the tenth transmission transistor PTR10 share the second common drain region CD2. The tenth channel region CH10 of the tenth transmission transistor PTR10 is formed below the fifth gate electrode GE5 in the sixth active region ACT6 between the tenth source region S10 and the second common drain region CD2.

[0078] The eleventh transfer transistor PTR11 is adjacent to the seventh transfer transistor PTR7 on the second horizontal direction HD2. The eleventh transfer transistor PTR11 includes a sixth gate insulating film GI6 located on the second substrate SUB2, a sixth gate electrode GE6 located on the sixth gate insulating film GI6, and an eleventh source region S11 and a third common drain region CD3 formed in the seventh active region ACT7 of the second substrate SUB2 on both sides of the sixth gate electrode GE6. The seventh transfer transistor PTR7 and the eleventh transfer transistor PTR11 share the third common drain region CD3. The eleventh channel region CH11 of the eleventh transfer transistor PTR11 is formed below the sixth gate electrode GE6 in the seventh active region ACT7 between the eleventh source region S11 and the third common drain region CD3.

[0079] The twelfth transfer transistor PTR12 is adjacent to the eleventh transfer transistor PTR11 in the first horizontal direction HD1, and adjacent to the eighth transfer transistor PTR8 in the second horizontal direction HD2. The twelfth transfer transistor PTR12 includes a sixth gate insulating film GI6 located on the second substrate SUB2, a sixth gate electrode GE6 located on the sixth gate insulating film GI6, and a twelfth source region S12 and a fourth common drain region CD4 formed in the eighth active region ACT8 of the second substrate SUB2 on both sides of the sixth gate electrode GE6. The eighth transfer transistor PTR8 and the twelfth transfer transistor PTR12 share the fourth common drain region CD4. The twelfth channel region CH12 of the twelfth transfer transistor PTR12 is formed below the sixth gate electrode GE6 in the eighth active region ACT8 between the twelfth source region S12 and the fourth common drain region CD4.

[0080] Level 1, Level 2 and Level 3 (Level) <1> ,class <2> and level <3> In each stage of the transistor, two adjacent transfer transistors on the first horizontal direction HD1 form a pair sharing a common gate electrode. For example, the first transfer transistor PTR1 and the second transfer transistor PTR2 share the first gate electrode GE1. The third transfer transistor PTR3 and the fourth transfer transistor PTR4 share the second gate electrode GE2. The fifth transfer transistor PTR5 and the sixth transfer transistor PTR6 share the third gate electrode GE3. The seventh transfer transistor PTR7 and the eighth transfer transistor PTR8 share the fourth gate electrode GE4. The ninth transfer transistor PTR9 and the tenth transfer transistor PTR10 share the fifth gate electrode GE5. The eleventh transfer transistor PTR11 and the twelfth transfer transistor PTR12 share the sixth gate electrode GE6.

[0081] The first insulating layer ILD1 can be disposed on the second substrate SUB2 to cover the first transmission transistor PTR1 to the twelfth transmission transistor PTR12.

[0082] like Figure 5 and Figure 6 As shown, the first contact CNT1 may be disposed on the first gate electrode GE1. The first contact CNT1 may penetrate the first insulating layer ILD1 in the vertical direction VD to connect to the first gate electrode GE1. The first contact CNT1 may be disposed above the device isolation region between the first transmission transistor PTR1 and the second transmission transistor PTR2. The first contact CNT1 may vertically overlap with the device isolation layer STI between the first transmission transistor PTR1 and the second transmission transistor PTR2. The first contact CNT1 may not overlap with the first channel region CH1 of the first transmission transistor PTR1 and the second channel region CH2 of the second transmission transistor PTR2.

[0083] like Figure 5 and Figure 6 As shown, the second contact CNT2 can be disposed on the second gate electrode GE2. The second contact CNT2 can penetrate the first insulating layer ILD1 in the vertical direction VD to connect to the second gate electrode GE2. The second contact CNT2 can be disposed above the device isolation region between the third transfer transistor PTR3 and the fourth transfer transistor PTR4. The second contact CNT2 can vertically overlap with the device isolation layer STI between the third transfer transistor PTR3 and the fourth transfer transistor PTR4. The second contact CNT2 can not overlap with the third channel region CH3 of the third transfer transistor PTR3 and the fourth channel region CH4 of the fourth transfer transistor PTR4.

[0084] like Figure 5 and Figure 7 As shown, the third contact CNT3 can be disposed on the third gate electrode GE3. The third contact CNT3 can penetrate the first insulating layer ILD1 in the vertical direction VD to connect to the third gate electrode GE3. The third contact CNT3 can be disposed above the device isolation region between the fifth transfer transistor PTR5 and the sixth transfer transistor PTR6. The third contact CNT3 can vertically overlap with the device isolation layer STI between the fifth transfer transistor PTR5 and the sixth transfer transistor PTR6. The third contact CNT3 can not overlap with the fifth channel region CH5 of the fifth transfer transistor PTR5 and the sixth channel region CH6 of the sixth transfer transistor PTR6.

[0085] like Figure 5 and Figure 7 As shown, the fourth contact CNT4 can be disposed on the fourth gate electrode GE4. The fourth contact CNT4 can penetrate the first insulating layer ILD1 in the vertical direction VD to connect to the fourth gate electrode GE4. The fourth contact CNT4 can be disposed above the device isolation region between the seventh transfer transistor PTR7 and the eighth transfer transistor PTR8. The fourth contact CNT4 can vertically overlap with the device isolation layer STI between the seventh transfer transistor PTR7 and the eighth transfer transistor PTR8. The fourth contact CNT4 can not overlap with the seventh channel region CH7 of the seventh transfer transistor PTR7 and the eighth channel region CH8 of the eighth transfer transistor PTR8.

[0086] like Figure 5 and Figure 8As shown, the fifth contact CNT5 can be disposed on the fifth gate electrode GE5. The fifth contact CNT5 can penetrate the first insulating layer ILD1 in the vertical direction VD to connect to the fifth gate electrode GE5. The fifth contact CNT5 can be disposed above the device isolation region between the ninth transfer transistor PTR9 and the tenth transfer transistor PTR10. The fifth contact CNT5 can vertically overlap with the device isolation layer STI between the ninth transfer transistor PTR9 and the tenth transfer transistor PTR10. The fifth contact CNT5 can not overlap with the ninth channel region CH9 of the ninth transfer transistor PTR9 and the tenth channel region CH10 of the tenth transfer transistor PTR10.

[0087] like Figure 5 and Figure 8 As shown, the sixth contact CNT6 can be disposed on the sixth gate electrode GE6. The sixth contact CNT6 can penetrate the first insulating layer ILD1 in the vertical direction VD to connect to the sixth gate electrode GE6. The sixth contact CNT6 can be disposed above the device isolation region between the eleventh transfer transistor PTR11 and the twelfth transfer transistor PTR12. The sixth contact CNT6 can vertically overlap with the device isolation layer STI between the eleventh transfer transistor PTR11 and the twelfth transfer transistor PTR12. The sixth contact CNT6 can not overlap with the eleventh channel region CH11 of the eleventh transfer transistor PTR11 and the twelfth channel region CH12 of the twelfth transfer transistor PTR12.

[0088] Figure 9 This is a plan view illustrating the transmission transistor and global row lines according to an embodiment of the present disclosure. Figure 10 It is along Figure 9 The cross-sectional view taken by line D-D'. Figure 11 It is along Figure 9 A cross-sectional view taken from line E-E'. Figure 12 It is along Figure 9 The cross-sectional view taken by line F-F'.

[0089] Reference Figures 9 to 12 First wiring W1 to sixth wiring W6 can be disposed on first insulating layer ILD1. Second insulating layer ILD2 can be disposed on first insulating layer ILD1 to cover wiring W1 to W6. Global row lines GRLo1 to GRLo3 and GRLe1 to GRLe3 can be disposed on second insulating layer ILD2. Global row lines may include a plurality of odd-numbered global row lines GRLo1 to GRLo3 and a plurality of even-numbered global row lines GRLe1 to GRLe3 arranged alternately along first horizontal direction HD1.

[0090] Odd-numbered global line lines GRLo1 to GRLo3 include the first odd-numbered global line line GRLo1, the second odd-numbered global line line GRLo2, and the third odd-numbered global line line GRLo3. Even-numbered global line lines GRLe1 to GRLe3 include the first even-numbered global line line GRLe1, the second even-numbered global line line GRLe2, and the third even-numbered global line line GRLe3.

[0091] like Figure 9 and Figure 10 As shown, the first odd-numbered global row line GRLo1 can be connected to both the first transmission transistor PTR1 and the third transmission transistor PTR3. The first odd-numbered global row line GRLo1 can be connected to the first wiring W1 via a seventh contact CNT7 that penetrates the second insulating layer ILD2 in the vertical direction VD. This first wiring W1 can be connected to the first drain region D1 of the first transmission transistor PTR1 via an eighth contact CNT8 that penetrates the first insulating layer ILD1 in the vertical direction VD. The first wiring W1 can also be connected to the third drain region D3 of the third transmission transistor PTR3 via a ninth contact CNT9 that penetrates the first insulating layer ILD1 in the vertical direction VD. Therefore, the first odd-numbered global row line GRLo1 can be connected to the first drain region D1 via the seventh contact CNT7, the first wiring W1, and the eighth contact CNT8, and to the third drain region D3 via the seventh contact CNT7, the first wiring W1, and the ninth contact CNT9.

[0092] like Figure 9 and Figure 11 As shown, the first even-numbered global line GRLe1 can be connected to both the second transmission transistor PTR2 and the fourth transmission transistor PTR4. The first even-numbered global line GRLe1 can be connected to the second wiring W2 via the tenth contact CNT10, which penetrates the second insulating layer ILD2 in the vertical direction VD. The second wiring W2 can be connected to the second drain region D2 of the second transmission transistor PTR2 via the eleventh contact CNT11, which penetrates the first insulating layer ILD1 in the vertical direction VD, and to the fourth drain region D4 of the fourth transmission transistor PTR4 via the twelfth contact CNT12, which penetrates the first insulating layer ILD1 in the vertical direction VD. Therefore, the first even-numbered global line GRLe1 can be connected to the second drain region D2 via the tenth contact CNT10, the second wiring W2, and the eleventh contact CNT11, and to the fourth drain region D4 via the tenth contact CNT10, the second wiring W2, and the twelfth contact CNT12.

[0093] like Figure 9 and Figure 12As shown, the second odd-numbered global row line GRLo2 can be connected to both the sixth transmission transistor PTR6 and the tenth transmission transistor PTR10. The second odd-numbered global row line GRLo2 can be connected to the third wiring W3 via the thirteenth contact CNT13, which penetrates the second insulating layer ILD2 in the vertical direction VD. This third wiring W3 can be connected to the second common drain region CD2 via the fourteenth contact CNT14, which penetrates the first insulating layer ILD1 in the vertical direction VD. Therefore, the second odd-numbered global row line GRLo2 can be connected to the second common drain region CD2 via the thirteenth contact CNT13, the third wiring W3, and the fourteenth contact CNT14.

[0094] like Figure 9 and Figure 12 As shown, the second even-numbered global row line GRLe2 can be connected to both the fifth transmission transistor PTR5 and the ninth transmission transistor PTR9. The second even-numbered global row line GRLe2 can be connected to the fourth wiring W4 via the fifteenth contact CNT15, which penetrates the second insulating layer ILD2 in the vertical direction VD. This fourth wiring W4 can be connected to the first common drain region CD1 via the sixteenth contact CNT16, which penetrates the first insulating layer ILD1 in the vertical direction VD. Therefore, the second even-numbered global row line GRLe2 can be connected to the first common drain region CD1 via the fifteenth contact CNT15, the fourth wiring W4, and the sixteenth contact CNT16.

[0095] like Figure 9 and Figure 12 As shown, the third odd-numbered global line GRLo3 can be connected to both the eighth transmission transistor PTR8 and the twelfth transmission transistor PTR12. The third odd-numbered global line GRLo3 can be connected to the fifth wiring W5 via the seventeenth contact CNT17, which penetrates the second insulating layer ILD2 in the vertical direction VD. This fifth wiring W5 can be connected to the fourth common drain region CD4 via the eighteenth contact CNT18, which penetrates the first insulating layer ILD1 in the vertical direction VD. Therefore, the third odd-numbered global line GRLo3 can be connected to the fourth common drain region CD4 via the seventeenth contact CNT17, the fifth wiring W5, and the eighteenth contact CNT18.

[0096] like Figure 9 and Figure 12As shown, the third even-numbered global line GRLe3 can be connected to both the seventh transmission transistor PTR7 and the eleventh transmission transistor PTR11. The third even-numbered global line GRLe3 can be connected to the sixth wiring W6 via the nineteenth contact CNT19, which penetrates the second insulating layer ILD2 in the vertical direction VD. This sixth wiring W6 can be connected to the third common drain region CD3 via the twentieth contact CNT20, which penetrates the first insulating layer ILD1 in the vertical direction VD. Therefore, the third even-numbered global line GRLe3 can be connected to the third common drain region CD3 via the nineteenth contact CNT19, the sixth wiring W6, and the twentieth contact CNT20.

[0097] Refer to together Figure 4 and Figure 9 Each of the first source region S1 of the first transmission transistor PTR1, the tenth source region S10 of the tenth transmission transistor PTR10, and the twelfth source region S12 of the twelfth transmission transistor PTR12 can be connected to a corresponding one of the first odd-numbered electrode layers 21o of the first memory block BLK1. Each of the second source region S2 of the second transmission transistor PTR2, the ninth source region S9 of the ninth transmission transistor PTR9, and the eleventh source region S11 of the eleventh transmission transistor PTR11 can be connected to a corresponding one of the first even-numbered electrode layers 21e of the first memory block BLK1.

[0098] Each of the third source region S3 of the third transfer transistor PTR3, the sixth source region S6 of the sixth transfer transistor PTR6, and the eighth source region S8 of the eighth transfer transistor PTR8 can be connected to a corresponding one of the second odd-numbered electrode layers 22o of the second memory block BLK2. Each of the fourth source region S4 of the fourth transfer transistor PTR4, the fifth source region S5 of the fifth transfer transistor PTR5, and the seventh source region S7 of the seventh transfer transistor PTR7 can be connected to a corresponding one of the second even-numbered electrode layers 22e of the second memory block BLK2.

[0099] Arranged sequentially at the first level (level) <1> The first transmission transistor PTR1 to the fourth transmission transistor PTR4 in the ) can be connected to one of the first odd electrode layer 21o, the first even electrode layer 21e, the second odd electrode layer 22o, and the second even electrode layer 22e, respectively.

[0100] The first odd-numbered electrode layer 21o connected to the first transmission transistor PTR1 can be disposed at the Kth position (where K is an odd number) in the first electrode layer 21, starting from the second substrate SUB2. The second odd-numbered electrode layer 22o connected to the third transmission transistor PTR3 can be disposed at the Kth position in the second electrode layer 22, starting from the second substrate SUB2. The first odd-numbered electrode layer 21o connected to the first transmission transistor PTR1 and the second odd-numbered electrode layer 22o connected to the third transmission transistor PTR3 can be disposed at the same height level starting from the second substrate SUB2.

[0101] The first even-numbered electrode layer 21e, connected to the second transmission transistor PTR2, can be disposed at the Mth position (where M is an even number) in the first electrode layer 21, starting from the second substrate SUB2. The second even-numbered electrode layer 22e, connected to the fourth transmission transistor PTR4, can be disposed at the Mth position in the second electrode layer 22, starting from the second substrate SUB2. The first even-numbered electrode layer 21e and the second even-numbered electrode layer 22e can also be disposed at the same height level starting from the second substrate SUB2.

[0102] M can be equal to K+1. The first odd-numbered electrode layer 21o connected to the first transmission transistor PTR1 and the first even-numbered electrode layer 21e connected to the second transmission transistor PTR2 in the first electrode layer 21 can be adjacent to each other. Similarly, the second odd-numbered electrode layer 22o connected to the third transmission transistor PTR3 and the second even-numbered electrode layer 22e connected to the fourth transmission transistor PTR4 in the second electrode layer 22 can also be adjacent to each other.

[0103] In the second mode, the first and second test voltages can be alternately applied to the first odd-numbered global row line GRLo1, the second odd-numbered global row line GRLo2, and the third odd-numbered global row line GRLo3. Alternatively, in the second mode, the first and second test voltages can also be alternately applied to the first even-numbered global row line GRLe1, the second even-numbered global row line GRLe2, and the third even-numbered global row line GRLe3. At any given time, the test voltages applied to the first odd-numbered global row line GRLo1, the second odd-numbered global row line GRLo2, and the third odd-numbered global row line GRLo3 can be different from the test voltages applied to the first even-numbered global row line GRLe1, the second even-numbered global row line GRLe2, and the third even-numbered global row line GRLe3. For example, when the first test voltage is applied to the odd-numbered global row lines GRLo1, GRLo2, and GRLo3, the second test voltage can be applied to the even-numbered global row lines GRLe1, GRLe2, and GRLe3, and when the second test voltage is applied to the odd-numbered global row lines GRLo1, GRLo2, and GRLo3, the first test voltage can be applied to the even-numbered global row lines GRLe1, GRLe2, and GRLe3.

[0104] According to embodiments of this disclosure, since odd-numbered and even-numbered global rows are arranged alternately, stress may be applied to the global rows in the second mode. When such stress is applied, short circuits may occur at weak points between adjacent global rows. After applying artificial stress in the second mode, defects in the global rows can be detected by testing.

[0105] although Figures 5 to 12 Only connections to the first and second memory blocks are shown. Figure 1 The present disclosure is not limited to the twelve transmission transistors (BLK1, BLK2). Multiple such units can be arranged along the first horizontal direction HD1, each unit comprising twelve transmission transistors. Figure 5 and Figure 12 It shows the connection to Figure 1 The transfer transistors of the first memory block BLK1 and the second memory block BLK2 are arranged in three stages, but connected to... Figure 1 The transfer transistors of memory blocks BLK1 to BLKn in the memory cell array 100 can be arranged in multiple stages along the second horizontal direction HD2.

[0106] Figure 13 This is a plan view showing the transfer transistor according to the comparative example, and Figure 14 It is along Figure 13 A cross-sectional view taken from line G-G'.

[0107] Reference Figure 13 and Figure 14 The contact CNT can be connected to the gate electrode GE of the transfer transistor PTR. The contact CNT can be disposed on the channel region CH of the transfer transistor PTR. When the contact CNT is disposed on the channel region CH, the gate insulating layer GI above the channel region CH may be damaged by the voltage applied to the contact CNT, resulting in a reduction in the thickness of the gate insulating layer GI. Therefore, gate leakage current or hot carrier injection may occur.

[0108] Figure 15 This is a plan view showing the transfer transistor according to another comparative example, and Figure 16 It is along Figure 15 A cross-sectional view taken from line H-H'.

[0109] Reference Figure 15 and Figure 16The left-side transfer transistor PTRc includes a gate insulating film GIc, a gate electrode GEc, a source region Sc, a drain region Dc, and a channel region CHc. The right-side transfer transistor PTRd includes a gate insulating film GId, a gate electrode GEd, a source region Sd, a drain region Dd, and a channel region CHd.

[0110] One contact CNTc is connected to the gate electrode GEc, while another contact CNTc is connected to the gate electrode GEd. Each of the gate electrodes GEc and GEd may extend above the device isolation layer STI. Figure 16 As shown, the gate electrode GEC of the left-side transfer transistor PTRc may include an extension EP that vertically overlaps with the device isolation layer STI. A contact CNTc may be disposed on the extension EP of the gate electrode GECc, thus placing the contact CNTc above the device isolation layer STI. Since the contact CNTc is not placed above the channel region CHc, damage to the gate insulating film GIc above the channel region CHc can be suppressed. However, the gap G1 between the contact CNTc and the channel region CHd of the right-side transfer transistor PTRd may become narrower, potentially forming a parasitic channel in the right-side transfer transistor PTRd due to the voltage applied to the contact CNTc.

[0111] According to embodiments of the present disclosure, by arranging transmission transistors in pairs such that each pair shares a single gate electrode and a contact is provided on the device isolation layer between the two paired transmission transistors, damage to the gate insulation layer above the channel region caused by the voltage applied to the contact can be prevented, and parasitic channels can be prevented from forming in adjacent transistors due to the applied voltage.

[0112] The substrate on which the transfer transistor is disposed may be silicon (Si) with Si dangling bonds. Dangling bonds in the substrate may reduce the hump characteristics of the transfer transistor and may lead to changes in threshold voltage, increased leakage current and reduced reliability.

[0113] A technique is known in which hydrogen atoms are bonded to dangling bonds via a hydrogen passivation process to stabilize defect states. However, during the fabrication of memory devices, hydrogen bonded to dangling bonds tends to undergo outward diffusion. The amount of hydrogen outward diffusion can differ between regions overlapping with and not overlapping the gate electrode. The amount of hydrogen outward diffusion may be greater in regions not overlapping with the gate electrode than in overlapping regions. If the gate electrode structures of the transfer transistors differ from one another, differences in hydrogen outward diffusion between the transfer transistors can result in variations in their hump characteristics. When the variations in hump characteristics are significant, tuning processes designed to improve hump characteristics can successfully enhance the hump characteristics of one transfer transistor while simultaneously reducing the hump performance of another, making the tuning process difficult.

[0114] According to embodiments of this disclosure, the transfer transistors are configured in pairs, such that each pair shares a gate electrode, and the gate electrode has substantially the same structure. As a result, the difference in the amount of hydrogen diffused outward within the transfer transistors can be reduced, and variations in the hump characteristics can be minimized. Therefore, the adjustment process for improving the hump characteristics can be made easier.

[0115] The foregoing description is merely an illustrative interpretation of this disclosure. Therefore, various modifications and variations can be made by those skilled in the art to which this disclosure pertains without departing from the essential characteristics of this disclosure. Furthermore, the embodiments disclosed herein are not intended to limit the scope of this disclosure, but rather to explain it. Therefore, the scope of this disclosure should not be limited by the embodiments.

[0116] Cross-references to related applications

[0117] This application claims priority to Korean Patent Application No. 10-2025-0055091, filed on April 28, 2025, which is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device comprising: A memory cell array, the memory cell array comprising multiple row lines extending in a first horizontal direction; Multiple transmission transistors, the multiple transmission transistors being connected to the multiple row lines; as well as Multiple contacts, the multiple contacts being connected to the gate electrodes of the multiple transmission transistors, The plurality of transmission transistors are arranged in multiple stages in a second horizontal direction perpendicular to the first horizontal direction. Each stage includes a pair of transfer transistors sharing a common gate electrode, and The contact connected to the shared gate electrode is disposed vertically above the device isolation layer between the pair of transmission transistors.

2. The memory device according to claim 1, in, The contact does not overlap with the channel regions of the pair of transmission transistors in the vertical direction.

3. The memory device according to claim 1, in, The memory cell array includes a first memory block and a second memory block that are adjacent to each other in the second horizontal direction, and The transmission transistors connected to the row lines of the first memory block and the row lines of the second memory block are arranged in three stages.

4. The memory device according to claim 3, in, The transmission transistors connected to the row lines of the first memory block are arranged in the first and third stages. The transmission transistors connected to the row lines of the second memory block are arranged in the first and second stages, and The first level and the third level are respectively arranged on opposite sides of the second level in the second horizontal direction.

5. The memory device according to claim 4, in, The transmission transistor in the first stage includes: First transmission transistor; The second transmission transistor is adjacent to the first transmission transistor in the first horizontal direction and shares the first gate electrode with the first transmission transistor; A third transmission transistor, the third transmission transistor being adjacent to the second transmission transistor in the first horizontal direction; and A fourth transmission transistor is adjacent to the third transmission transistor in the first horizontal direction and shares a second gate electrode with the third transmission transistor. Each of the first and second transmission transistors is connected to a corresponding row line in the row lines of the first memory block, and Each of the third and fourth transmission transistors is connected to a corresponding row line in the row lines of the second memory block.

6. A memory device, the memory device comprising: Multiple memory blocks are arranged along a second horizontal direction perpendicular to a first horizontal direction, and each memory block includes multiple electrode layers and multiple interlayer insulating layers alternately stacked in a vertical direction; A plurality of transmission transistors, the plurality of transmission transistors being connected to a corresponding electrode layer in the plurality of electrode layers; as well as Multiple global row lines are disposed on the multiple transfer transistors and connected to the electrode layers of the multiple memory blocks through the multiple transfer transistors. The plurality of electrode layers in each of the plurality of memory blocks include a plurality of odd-numbered electrode layers and a plurality of even-numbered electrode layers stacked alternately. The multiple global row lines include multiple odd-numbered global row lines and multiple even-numbered global row lines arranged alternately along the second horizontal direction. Wherein, each of the plurality of odd-numbered electrode layers of the plurality of memory blocks is connected to one of the plurality of odd-numbered global row lines, and Each of the even-numbered electrode layers of the plurality of memory blocks is connected to one of the plurality of even-numbered global row lines.

7. The memory device according to claim 6, in, The plurality of memory blocks include a first memory block and a second memory block that are adjacent to each other in the second horizontal direction, and The transmission transistors connected to the electrode layers of the first memory block and the second memory block are arranged in three stages.

8. The memory device according to claim 7, in, The transfer transistor in the first stage of the three stages includes: First transmission transistor; The second transmission transistor is adjacent to the first transmission transistor in the first horizontal direction; A third transmission transistor, the third transmission transistor being adjacent to the second transmission transistor in the first horizontal direction; and A fourth transmission transistor, which is adjacent to the third transmission transistor in the first horizontal direction. The first transmission transistor is connected to one of the odd-numbered electrode layers of the first memory block. The second transmission transistor is connected to one of the even-numbered electrode layers of the first memory block. The third transfer transistor is connected to one of the odd-numbered electrode layers of the second memory block, and The fourth transmission transistor is connected to one of the even-numbered electrode layers of the second memory block.

9. The memory device according to claim 8, in, The first transmission transistor and the second transmission transistor share the first gate electrode, and The third transmission transistor and the fourth transmission transistor share the second gate electrode.

10. The memory device according to claim 8, in, The electrode layer connected to the first transmission transistor is located at the Kth position from the bottom in the electrode layers of the first memory block, where K is an odd number and equals 1 at the bottommost layer in the vertical direction. The electrode layer connected to the second transmission transistor is located at the Mth position from the bottom within the electrode layer of the first memory block, where M is an even number. The electrode layer connected to the third transmission transistor is located at the Kth position from the bottom within the electrode layer of the second memory block, and... The electrode layer connected to the fourth transmission transistor is located at the Mth position from the bottom in the electrode layer of the second memory block.

11. The memory device according to claim 10, in, M is 1 greater than K.

12. The memory device according to claim 8, in, The transmission transistor in the second stage, which is adjacent to the first stage in the three stages, includes: A fifth transmission transistor, which is adjacent to the first transmission transistor in the second horizontal direction; A sixth transmission transistor is adjacent to the second transmission transistor in the second horizontal direction; A seventh transmission transistor, which is adjacent to the third transmission transistor in the second horizontal direction; and The eighth transmission transistor is adjacent to the fourth transmission transistor in the second horizontal direction. Each of the fifth and seventh transmission transistors is connected to a corresponding even-numbered electrode layer in the even-numbered electrode layers of the second memory block, and Each of the sixth and eighth transmission transistors is connected to a corresponding odd-numbered electrode layer in the odd-numbered electrode layer of the second memory block.

13. The memory device according to claim 12, in, The fifth transmission transistor and the sixth transmission transistor share the first gate electrode, and The seventh transmission transistor and the eighth transmission transistor share the second gate electrode.

14. The memory device according to claim 12, in, The transmission transistor in the third stage, which is adjacent to the second stage, includes: The ninth transmission transistor shares a first common drain region with the fifth transmission transistor; The tenth transmission transistor shares a second common drain region with the sixth transmission transistor. An eleventh transfer transistor, wherein the eleventh transfer transistor shares a third common drain region with the seventh transfer transistor; and The twelfth transfer transistor shares a fourth common drain region with the eighth transfer transistor. Wherein, each source region of the ninth transmission transistor and the eleventh transmission transistor is connected to a corresponding even-numbered electrode layer in the even-numbered electrode layers of the first memory block, and Each of the source regions of the tenth transmission transistor and the twelfth transmission transistor is connected to a corresponding odd-numbered electrode layer in the odd-numbered electrode layers of the first memory block.

15. The memory device according to claim 14, in, The ninth transmission transistor and the tenth transmission transistor share the first gate electrode, and The eleventh transmission transistor and the twelfth transmission transistor share the second gate electrode.

16. The memory device according to claim 14, in, The multiple even-numbered global row lines include: The first even-numbered global row line is connected to the first common drain region; The second even-numbered global row lines, which together connect to the drain region of the second transmission transistor and the drain region of the fourth transmission transistor; and The third even-numbered global row line is connected to the third common drain region, and The multiple odd-numbered global row lines include: The first odd-numbered global row line is connected to the second common drain region; The second odd-numbered global row lines, which together connect to the drain region of the first transmission transistor and the drain region of the third transmission transistor; and The third odd-numbered global row line is connected to the fourth common drain region.

17. A memory device, the memory device comprising: First semiconductor layer; as well as A second semiconductor layer overlaps with the first semiconductor layer in the vertical direction. The first semiconductor layer includes: First substrate; and Multiple memory blocks are arranged on the first substrate along a second horizontal direction perpendicular to the first horizontal direction. Each memory block includes multiple electrode layers and multiple interlayer insulating layers alternately stacked in the vertical direction. The second semiconductor layer includes: Second substrate; A plurality of transmission transistors are disposed on the second substrate and connected to the electrode layers of the plurality of memory blocks; and Multiple contacts, the multiple contacts being connected to the gate electrodes of the multiple transmission transistors, The plurality of transmission transistors are arranged in multiple stages in the second horizontal direction. Each stage includes two paired transport transistors that share a common gate electrode, and A contact connected to a single gate electrode is disposed in the vertical direction above the device isolation region between the two paired transmission transistors on the second substrate.

18. The memory device according to claim 17, in, The contact does not overlap with the channel regions of the two paired transmission transistors in the vertical direction.

19. The memory device according to claim 17, in, The second semiconductor layer further includes multiple global row lines, which are connected to the electrode layers of the multiple memory blocks via the multiple transfer transistors. The plurality of electrode layers in each of the plurality of memory blocks include a plurality of odd-numbered electrode layers and a plurality of even-numbered electrode layers stacked alternately. The multiple global row lines include multiple odd-numbered global row lines and multiple even-numbered global row lines arranged alternately along the first horizontal direction. Wherein, each of the odd-numbered electrode layers of the plurality of memory blocks is connected to one of the plurality of odd-numbered global row lines, and Each of the even-numbered electrode layers in the plurality of memory blocks is connected to one of the plurality of even-numbered global row lines.

20. The memory device according to claim 17, in, The plurality of memory blocks include a first memory block and a second memory block that are adjacent to each other in the second horizontal direction, and The transmission transistors connected to the electrode layers of the first memory block and the second memory block are arranged in three stages.

21. The memory device according to claim 20, in, The transfer transistors connected to the electrode layers of the first memory block are arranged in the first and third stages, and The transmission transistors connected to the electrode layers of the second memory block are arranged in the first and second stages.

22. The memory device according to claim 21, in, The transmission transistor in the first stage includes: First transmission transistor; The second transmission transistor is adjacent to the first transmission transistor in the first horizontal direction and shares the first gate electrode with the first transmission transistor; A third transmission transistor, the third transmission transistor being adjacent to the second transmission transistor in the first horizontal direction; and A fourth transmission transistor is adjacent to the third transmission transistor in the first horizontal direction and shares a second gate electrode with the third transmission transistor. Each of the first and second transmission transistors is connected to a corresponding electrode layer in the electrode layers of the first memory block, and Each of the third and fourth transmission transistors is connected to a corresponding electrode layer in the electrode layer of the second memory block.

23. The memory device according to claim 22, in, The electrode layers of the first memory block include a plurality of first odd-numbered electrode layers and a plurality of first even-numbered electrode layers that are alternately stacked. The electrode layer of the second memory block includes a plurality of alternately stacked second odd-numbered electrode layers and a plurality of second even-numbered electrode layers. The first transmission transistor is connected to one of the plurality of first odd-numbered electrode layers. The second transmission transistor is connected to one of the plurality of first even-numbered electrode layers. The third transmission transistor is connected to one of the plurality of second odd-numbered electrode layers, and The fourth transmission transistor is connected to one of the plurality of second even-numbered electrode layers.

24. The memory device according to claim 23, in, The transmission transistor disposed in the second stage includes: A fifth transmission transistor, which is adjacent to the first transmission transistor in the second horizontal direction; A sixth transmission transistor is adjacent to the second transmission transistor in the second horizontal direction; A seventh transmission transistor, which is adjacent to the third transmission transistor in the second horizontal direction; and The eighth transmission transistor is adjacent to the fourth transmission transistor in the second horizontal direction. Wherein, each of the fifth and seventh transmission transistors is connected to one of the second even-numbered electrode layers, and Each of the sixth transmission transistor and the eighth transmission transistor is connected to one of the second odd-numbered electrode layers.

25. The memory device according to claim 24, in, The fifth transmission transistor and the sixth transmission transistor share the first gate electrode, and The seventh transmission transistor and the eighth transmission transistor share the second gate electrode.

26. The memory device according to claim 24, in, The transfer transistor in the third stage adjacent to the second stage includes: The ninth transmission transistor shares a first common drain region with the fifth transmission transistor; The tenth transmission transistor shares a second common drain region with the sixth transmission transistor. An eleventh transfer transistor, wherein the eleventh transfer transistor shares a third common drain region with the seventh transfer transistor; and The twelfth transfer transistor shares a fourth common drain region with the eighth transfer transistor. Wherein, each source region of the ninth transmission transistor and the eleventh transmission transistor is connected to a corresponding first even-numbered electrode layer among the plurality of first even-numbered electrode layers, and Each of the source regions of the tenth transmission transistor and the twelfth transmission transistor is connected to a corresponding first odd-numbered electrode layer among the plurality of first odd-numbered electrode layers.

27. The memory device according to claim 26, in, The ninth transmission transistor and the tenth transmission transistor share a third gate electrode, and The eleventh transmission transistor and the twelfth transmission transistor share the fourth gate electrode.

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