Memory device and operating method thereof, storage system

Abstract

Embodiments of the present disclosure disclose a memory device and an operating method thereof, and a storage system. The memory device comprises a memory cell, a power-on initialization circuit, a first driving circuit and a second driving circuit; the memory cell comprises a capacitor and a transistor, wherein the transistor is coupled to a first end of the capacitor; the power-on initialization circuit is coupled to the memory cell; the power-on initialization circuit is configured to perform power-on initialization on the memory cell based on power-on of the memory device; the first driving circuit is coupled to the power-on initialization circuit and a second end of the capacitor respectively; the first driving circuit is configured to apply a first driving voltage to the second end in a power-on initialization stage; the second driving circuit is coupled to the power-on initialization circuit and a word line respectively; the second driving circuit is configured to apply a second driving voltage to the word line in the power-on initialization stage, so as to turn on the transistor coupled to the word line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are classified into volatile memory and non-volatile memory based on whether they retain stored data when power is off. Volatile memory, which loses data when power is off, can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0003] After power-on, DRAM typically undergoes a series of power-on initialization steps, such as setting the operating voltage, timing parameters, and enabling the refresh mechanism, to ensure normal operation. However, power-on initialization may leave memory cells in an uncertain state, affecting the reliability of subsequent data reads. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory device is provided, comprising: a memory cell, a power-on initialization circuit, a first driving circuit, and a second driving circuit; the memory cell includes a capacitor and a transistor, wherein the transistor is coupled to a first terminal of the capacitor; the power-on initialization circuit is coupled to the memory cell; the power-on initialization circuit is configured to perform power-on initialization on the memory cell based on power-on of the memory device; the first driving circuit is coupled to the power-on initialization circuit and a second terminal of the capacitor respectively; the first driving circuit is configured to apply a first driving voltage to the second terminal during the power-on initialization phase; the second driving circuit is coupled to the power-on initialization circuit and a word line respectively; the second driving circuit is configured to apply a second driving voltage to the word line during the power-on initialization phase, such that the transistor coupled to the word line is turned on.

[0005] In some embodiments, the power-on initialization circuit is specifically configured to: generate a first control signal at a first moment during the power-on initialization phase; and generate a power-on completion signal at a second moment during the power-on initialization phase, wherein the second moment is later than the first moment, and the power-on completion signal is used to indicate that the memory device has completed power-on; the first driving circuit is specifically configured to: apply the first driving voltage to the second terminal based on the first control signal; and the second driving circuit is specifically configured to: apply the second driving voltage to the word line at a third moment before the second moment or the first moment.

[0006] In some embodiments, the memory device further includes a control logic circuit coupled to the power-on initialization circuit and the second driving circuit, respectively; the control logic circuit is configured to generate a second control signal at a second time; the first driving circuit is specifically configured to drive the second terminal to charge from an initial voltage to a first driving voltage based on the first control signal, wherein the first terminal is coupled to the charged second terminal; the second driving circuit is specifically configured to apply the second driving voltage to the word line based on the second control signal, wherein the coupled first terminal discharges through the turned-on transistor.

[0007] In some embodiments, the memory device further includes a control logic circuit coupled to the power-on initialization circuit and the second driving circuit, respectively; the control logic circuit is configured to generate a second control signal at the third time; the second driving circuit is specifically configured to apply the second driving voltage to the word line based on the second control signal.

[0008] In some embodiments, the power-on initialization circuit is specifically configured to: generate a power-on completion signal at a second moment during the power-on initialization phase, wherein the power-on completion signal is used to indicate that the memory device has completed power-on; the first driving circuit is specifically configured to: apply the first driving voltage to the second terminal based on the power-on completion signal; the second driving circuit is specifically configured to: apply the second driving voltage to the word line at the second moment.

[0009] In some embodiments, the memory device further includes a control logic circuit coupled to the power-on initialization circuit and the second driving circuit, respectively; the control logic circuit is configured to generate a second control signal at the second time; the second driving circuit is specifically configured to apply the second driving voltage to the word line based on the second control signal.

[0010] In some embodiments, the second driving circuit is further configured to: stop applying the second driving voltage to the word line at a fourth time after the second time.

[0011] In some embodiments, the memory device further includes a third driving circuit coupled to the power-on initialization circuit and the bit line; the third driving circuit is configured to apply a bit line voltage to the bit line during a sensing phase following the power-on initialization phase; the second driving circuit is further configured to apply a word line voltage to the word line during the sensing phase.

[0012] In some embodiments, the third driving circuit is specifically configured to: drive the bit line to charge from an initial bit line voltage to the bit line voltage during the sensing phase; the second driving circuit is specifically configured to: apply the word line voltage to the word line after the bit line is charged to the bit line voltage.

[0013] In some embodiments, the memory device includes dynamic random access memory.

[0014] According to a second aspect of the present disclosure, a method for operating a memory device is provided, comprising:

[0015] Based on the power-on of the memory device, power-on initialization is performed on the memory cell of the memory device, wherein the memory cell includes a capacitor and a transistor, and the transistor is coupled to a first terminal of the capacitor; during the power-on initialization phase, a first driving voltage is applied to a second terminal of the capacitor; during the power-on initialization phase, a second driving voltage is applied to a word line coupled to the transistor to turn on the transistor.

[0016] In some embodiments, the step of performing power-on initialization on the memory cells of the memory device based on power-on of the memory device includes: generating a first control signal at a first moment during the power-on initialization phase; generating a power-on completion signal at a second moment during the power-on initialization phase, wherein the second moment is later than the first moment, and the power-on completion signal is used to indicate that the memory device has completed power-on; the step of applying a first driving voltage to the second terminal of the capacitor during the power-on initialization phase includes: applying the first driving voltage to the second terminal based on the first control signal; the step of applying a second driving voltage to the word line coupled to the transistor during the power-on initialization phase includes: applying the second driving voltage to the word line at a third moment before the second moment or the first moment.

[0017] In some embodiments, the operation method further includes: generating a second control signal at the second moment; applying the first driving voltage to the second terminal based on the first control signal includes: driving the second terminal to charge from an initial voltage to the first driving voltage based on the first control signal, wherein the first terminal is coupled to the charged second terminal; applying the second driving voltage to the word line at the second moment includes: applying the second driving voltage to the word line based on the second control signal, wherein the coupled first terminal discharges through the turned-on transistor.

[0018] In some embodiments, the operation method further includes: generating a second control signal at the third time; and applying the second driving voltage to the word line at the second time includes: applying the second driving voltage to the word line based on the second control signal.

[0019] In some embodiments, the step of performing power-on initialization on the memory cells of the memory device based on power-on of the memory device includes: generating a power-on completion signal at a second time during the power-on initialization phase, wherein the power-on completion signal is used to indicate that the memory device has completed power-on; the step of applying a first driving voltage to the second terminal during the power-on initialization phase includes: applying the first driving voltage to the second terminal based on the power-on completion signal; the step of applying a second driving voltage to the word line coupled to the transistor during the power-on initialization phase includes: applying the second driving voltage to the word line at the second time.

[0020] In some embodiments, the operation method further includes: generating a second control signal at the second time; and applying the second driving voltage to the word line at the second time includes: applying the second driving voltage to the word line based on the second control signal.

[0021] In some embodiments, the operation method further includes: at a fourth time after the second time, stopping the application of the second driving voltage to the word line.

[0022] In some embodiments, the operation method further includes: applying a bit line voltage to a bit line coupled to the transistor during a sensing phase following the power-on initialization phase; and applying a word line voltage to the word line during the sensing phase.

[0023] In some embodiments, applying a bit line voltage to a bit line coupled to the transistor during the sensing phase following the power-on initialization phase includes: driving the bit line to charge from an initial bit line voltage to the bit line voltage during the sensing phase; applying a word line voltage to a word line during the sensing phase includes: applying the word line voltage to the word line after the bit line has been charged to the bit line voltage.

[0024] According to a third aspect of the present disclosure, a storage system is provided, comprising: a memory device as described in any embodiment of the first aspect of the present disclosure, and a controller coupled to the memory device.

[0025] In this embodiment, by setting the second driving circuit to apply a second driving voltage to the word line during the power-on initialization phase, the transistors coupled to the word line can be turned on, and the memory node can discharge through the turned-on transistors. This avoids the memory node being coupled to an uncertain voltage level during the power-on initialization phase, thereby preventing unbalanced current on the cell board. It also ensures that all memory cells are initialized to a "0" state, i.e., the memory cells are in a defined state, thus guaranteeing the sensing margin between data "0" and "1" during subsequent readings, which helps improve the reliability of data reading. Attached Figure Description

[0026] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0027] Figure 1 This is a schematic diagram of a system shown in an embodiment of the present disclosure;

[0028] Figure 2A and Figure 2B This is a schematic diagram of a memory device shown in an embodiment of the present disclosure;

[0029] Figure 3A This is a schematic diagram of a power-on initialization circuit shown in an embodiment of this disclosure;

[0030] Figure 3B This is a timing diagram illustrating a power-on initialization according to an embodiment of this disclosure;

[0031] Figure 4A This is a schematic diagram illustrating the application of voltage to a memory cell according to an embodiment of the present disclosure;

[0032] Figure 4B This is a schematic diagram of a peripheral circuit shown in an embodiment of this disclosure;

[0033] Figure 4C This is a timing diagram illustrating the application of voltage to a memory cell according to an embodiment of the present disclosure;

[0034] Figure 5 This is a schematic diagram of another memory device shown in an embodiment of this disclosure;

[0035] Figure 6A This is a schematic diagram of a peripheral circuit shown in the first embodiment of this disclosure;

[0036] Figure 6B This is a timing diagram showing the application of a second driving voltage to a word line according to the first embodiment of this disclosure;

[0037] Figure 7A This is a schematic diagram of a peripheral circuit shown in the second embodiment of this disclosure;

[0038] Figure 7B This is a timing diagram showing the application of a second driving voltage to a word line according to a second embodiment of this disclosure;

[0039] Figure 8A This is a schematic diagram of a peripheral circuit shown in the third embodiment of this disclosure;

[0040] Figure 8B This is a timing diagram illustrating the application of a second driving voltage to a word line according to a third embodiment of this disclosure;

[0041] Figure 9 This is a schematic flowchart illustrating an operation method of a memory device according to an embodiment of this disclosure. Detailed Implementation

[0042] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0044] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0045] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0047] Figure 1 This is a schematic diagram of a system according to an embodiment of the present disclosure. Figure 2A and Figure 2B This is a schematic diagram of a memory device according to an embodiment of the present disclosure.

[0048] Reference Figure 1 As shown, system 1 may include a host and a storage system 30. In this embodiment of the disclosure, system 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0049] The host can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The storage system 30 has one or more memory devices 20 and a controller 10. The host can be configured to send data to or receive data from the memory device 20. The controller 10 is coupled to both the memory device 20 and the host, and is configured to control the memory device 20. The controller 10 can manage the data stored in the memory device 20 and communicate with the host.

[0050] The controller 10 can be configured to control the operation of the memory device 20, such as read, write, and refresh operations. In some embodiments, the controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 20. The controller 10 can also perform any other suitable function, such as formatting the memory device 20.

[0051] In some specific embodiments, the controller 10 and one or more memory devices 20 can be integrated into various types of storage devices. For example, the controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memory devices 20 can be integrated into a memory module. In other words, the storage system 30 can be implemented and packaged into different types of terminal electronic products.

[0052] The controller 10 can send data to or receive data from the host, and can send commands (CMD) and addresses (ADDR) to the memory device 20. The controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive commands (CMD) and addresses (ADDR) from the host. The command generator 110 can generate access commands, refresh commands, etc., by decoding the commands (CMD) received from the host, and can provide access commands and refresh commands to the memory device 20 through the device interface 130. An access command may be a signal instructing the memory device 20 to write or read data by accessing a row of the memory array 210 corresponding to the address ADDR. A refresh command may instruct the memory array 210 of the memory device 20 to perform a data refresh operation.

[0053] The address generator 120 in the controller 10 can generate the row and column addresses to be accessed in the memory array 210 by decoding the address ADDR received from the host interface 140. Furthermore, the memory device 20 can generate addresses of the memory banks to be accessed when the memory array 210 includes multiple banks.

[0054] Furthermore, the controller 10 can control memory device operations such as writing and reading by providing various signals to the memory device 20 via the device interface 130. For example, the controller 10 can provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data in the memory device 20. The memory device 20 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc.

[0055] Reference Figure 1 , Figure 2A and Figure 2B As shown, the memory device 20 includes a memory array 210 and peripheral circuitry 220. The memory array 210 includes multiple memory cells; as an example, Figure 2B Sixteen memory banks are shown, namely Bank0 to Bank15. Each memory bank includes multiple blocks, each block includes multiple rows of memory cells and multiple columns of memory cells, each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line.

[0056] Peripheral circuitry 220 may include control logic circuitry 230, which may be coupled to the various circuits described below and configured to control the operation of the respective circuits. As an example, control logic circuitry 230 may generate corresponding control signals based on commands issued by controller 10 and send these control signals to the corresponding circuits.

[0057] The peripheral circuit 220 may also include a power-on initialization circuit 240, which is coupled to the memory array 210. The power-on initialization circuit 240 can perform power-on initialization on the memory array 210 when the memory device is powered on, so as to initialize each memory cell 201. After the power-on initialization is completed, read, write or refresh operations can be performed on the selected memory cell 201.

[0058] The peripheral circuit 220 may also include: control circuitry corresponding to each memory block, such as a sensing amplifier (SA) 250 and a word-line driver (WLD); control circuitry corresponding to each memory bank, such as a row decoder 260 and a column decoder 270; and control circuitry corresponding to all memory banks, such as a data input / output buffer 280, a command buffer, a command decoder, an address buffer, and a mode register.

[0059] The peripheral circuit 220 can write data to or read data from the storage array 210 based on the command CMD and address ADDR received from the controller 10, or it can provide the row decoder 260 and column decoder 250 with the control signal CTRL for refreshing the storage cells included in the storage array 210. In other words, the peripheral circuit 220 can perform all operations to process the data in the storage array 210.

[0060] Reference Figure 2A As shown, the memory device includes at least one DRAM chip, each DRAM chip including a memory array 210, the memory array 210 including multiple memory cells 201 arranged in an array, each memory cell 201 including a transistor T and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be regarded as a typical mesh structure. The memory array uses rows and columns to specify addresses. By specifying the intersection of the rows and columns (by specifying the row address and column address of the DRAM), the controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the data stored therein.

[0061] Figure 3A This is a schematic diagram of a power-on initialization circuit according to an embodiment of the present disclosure. Figure 3B This is a timing diagram of power-on initialization according to an embodiment of the present disclosure, which will be described below in conjunction with... Figure 3A and Figure 3B An exemplary description is provided of performing power-on initialization on a memory device.

[0062] The power-on initialization circuit includes at least one power detection circuit; the power detection circuit is configured to detect the power supply voltage upon power-on of the memory device and output a detection signal. The detection signal is used to indicate whether the power supply voltage has reached a stable state.

[0063] As an example, Figure 3AA first power supply detection circuit 302, a second power supply detection circuit 304, and a third power supply detection circuit 306 are shown. When the memory device is powered on, the first power supply detection circuit 302, the second power supply detection circuit 304, and the third power supply detection circuit 306 respectively detect the first power supply voltage vdd2h, the second power supply voltage vdd2l, and the third power supply voltage vdd1, and each outputs a first detection signal pup_vdd2h_n, a second detection signal pup_vdd2l_n, and a third detection signal pup_vdd1_n. The first detection signal pup_vdd2h_n indicates whether the first power supply voltage vdd2h has reached a stable state, the second detection signal pup_vdd2l_n indicates whether the second power supply voltage vdd2l has reached a stable state, and the third detection signal pup_vdd1_n indicates whether the third power supply voltage vdd1 has reached a stable state.

[0064] As an example, Figure 3B It shows that the first power supply voltage vdd2h reaches a steady state at time T1, the third power supply voltage vdd1 reaches a steady state before time T1, and the second power supply voltage vdd2l reaches a steady state after time T1. That is, the different power supply voltages reach a steady state at different times.

[0065] It should be noted that DDR internally typically has three power supply voltages: Vdd1, Vdd2, and VddQ. Vdd2 is further divided into Vdd2h and Vdd2l. Vdd2h is a high-level voltage, commonly used in high-speed operation modes; Vdd2l is a low-level voltage, commonly used in low-speed operation modes. For example, when... Figure 3A When the ulpc_enb pin is activated, the DRAM chip operates in a low-speed mode. In practical applications, the number of power detection circuits is not limited to... Figure 3A As shown, other quantities can also be used to detect different types of power supply voltages.

[0066] The power-on initialization circuit also includes a power-on monitoring and delay circuit 308, which is coupled to a power detection circuit. The power-on monitoring and delay circuit 308 is configured to delay each received detection signal and output a monitoring signal pup_vdd.

[0067] As an example, each input terminal of the power-on monitoring and delay circuit 308 receives a corresponding detection signal and performs delay processing on the detection signals received at each input terminal until the corresponding power supply voltage (e.g., Vdd2h, Vdd2l, or Vdd1) reaches a stable state. Here, by introducing a certain delay, initialization failure caused by starting initialization before the corresponding power supply voltage has fully stabilized can be avoided.

[0068] As an example, combined Figure 3B As shown, the power-on monitoring and delay circuit 308 can output a monitoring signal pup_vdd when the first power supply voltage vdd2h reaches a stable state.

[0069] The power-on initialization circuit also includes a reset signal filtering and buffering circuit 310, which is coupled to the reset pin. The reset signal filtering and buffering circuit 310 is configured to filter the reset signal reset_n received by the reset pin and generate a global reset control signal grst_ctl. Here, the reset signal filtering and buffering circuit 310 can start receiving the reset signal reset_n when the reset control signal reset_b is at a low level.

[0070] As an example, refer to Figure 3B As shown, at time T0, the reset signal reset_n is at a low level; after the first power supply voltage vdd2h reaches a stable state (i.e., at time T1), the reset operation begins, and the reset signal reset_n is maintained for at least approximately 200μs; at time T3, the reset signal reset_n switches to a high level, and the DRAM exits the reset state. In this example, the reset signal reset_n is a low-level active signal.

[0071] The power-on initialization circuit also includes a power-on reset buffer circuit 312, which is coupled to the power-on monitoring and delay circuit 308 and the reset signal filtering buffer circuit 310. The power-on reset buffer circuit 312 is configured to generate a global reset signal grst based on the monitoring signal pup_vdd and the global reset control signal grst_ctl. The global reset signal grst is used to instruct the memory device to perform a reset operation. After power-on initialization is completed, a power-on completion signal pup_a is output, which instructs the memory device to complete power-on.

[0072] As an example, refer to Figure 3B As shown, from time T1 to T3, the global reset signal grst is at a high level, and the memory device performs a reset operation. At time T2, the memory device completes power-on, generating a power-on completion signal pup_a. After power-on, for example, after time T3, write, read, and refresh operations can be performed. However, after DRAM power-on, the memory cells may be in an uncertain state, affecting the reliability of subsequent data reads. The following section discusses... Figures 4A to 4C Please provide an explanation.

[0073] Figure 4A This is a schematic diagram illustrating the application of voltage to a memory cell according to an embodiment of the present disclosure. Figure 4B This is a schematic diagram of a peripheral circuit according to an embodiment of the present disclosure. Figure 4CThis is a timing diagram illustrating the application of voltage to a memory cell according to an embodiment of the present disclosure.

[0074] Reference Figure 4A As shown, the memory cell includes a capacitor and a transistor. As an example, the capacitor includes a first electrode plate, a second electrode plate, and a dielectric material located between the first and second electrode plates. The first electrode plate is coupled to the transistor, and the second electrode plate is coupled to a cell plate. The second electrode plates of multiple capacitors can share a cell plate; that is, the second electrode plates of multiple capacitors are all coupled to a cell plate.

[0075] Reference Figures 4A to 4C As shown, during the power-on initialization phase, the unit board driving circuit can apply a driving voltage vcp to the unit board to initialize all memory cells. After power-on is complete (e.g., at time T4), the bit line driving circuit can apply a bit line driving voltage vblp to the bit lines, and the word line driving circuit can apply a word line driving voltage vwln to the word lines. By selecting the corresponding bit lines and word lines, the corresponding memory cells can be selected, and write, read, or refresh operations can be performed on the selected memory cells.

[0076] However, during the power-on initialization phase, the ramp-up of the drive voltage VCP couples all memory cell storage nodes (sn) to an unpredictable voltage level, for example, Figure 4C The memory node sn is coupled to 500mV. During the first refresh cycle after power-on initialization, the uncertain voltage level on memory node sn will cause unbalanced current on the cell board. This unbalanced current will increase the voltage level on the cell board, and the higher voltage on the cell board will reduce the sensing margin, such as between data "0" and "1", thus reducing the reliability of data reading. Figure 4C In this context, vsn represents the voltage of storage node sn, which can be any node between the transistor and the first electrode plate.

[0077] Based on one or more of the above-mentioned technical problems, embodiments of this disclosure provide a memory device.

[0078] Figure 5 This is a schematic diagram illustrating another memory device according to an embodiment of the present disclosure. The memory device includes, but is not limited to, DRAM; for ease of understanding, DRAM will be used as an example in the following description.

[0079] Reference Figure 2A , Figure 4A and Figure 5As shown, the memory device 400 includes a memory array 402, which includes a plurality of memory cells. Each memory cell includes a capacitor and a transistor, wherein the transistor is coupled to a first terminal of the capacitor. As an example, the first terminal of the capacitor may be a first electrode plate, and the source of the transistor is coupled to the first electrode plate. For a detailed description of the structure of the memory array 402 and the memory cells, please refer to [reference needed]. Figure 2A and Figure 4A The relevant descriptions will not be repeated here.

[0080] The memory device 400 also includes a power-on initialization circuit 404, which is coupled to the memory cells. The power-on initialization circuit 404 is configured to perform power-on initialization on the memory cells upon power-on of the memory device 400. The power-on initialization process can be found in [reference needed]. Figure 3A and Figure 3B Related descriptions.

[0081] The memory device 400 also includes a first driving circuit 406, which is coupled to the power-on initialization circuit 404 and the second terminal of the capacitor, respectively. The first driving circuit 406 is configured to apply a first driving voltage to the second terminal during the power-on initialization phase. The first driving voltage will be referred to as vcp below.

[0082] As an example, the second terminal of the capacitor can be a second electrode plate. During the power-on initialization phase, the first driving circuit 406 can apply a first driving voltage vcp to the second electrode plate. In this example, the first driving circuit 406 can be... Figure 4B The illustrated unit board drive circuit reuses the unit board drive circuit. Of course, in other examples, the first drive circuit 406 can also be a newly added drive circuit.

[0083] The first driving voltage, vcp, is usually set to half of the power supply voltage, which can be one of vdd2h, vdd2l, and vdd1 mentioned above, or any combination thereof.

[0084] As an example, if the DRAM supply voltage is 1.5V, the first drive voltage vcp is approximately 0.75V; if the DRAM uses a higher supply voltage (such as 3.3V), the first drive voltage vcp is approximately 1.65V. This "half-voltage" design can balance the requirements between signal swing, power consumption and reliability to provide a stable reference voltage for the capacitor.

[0085] The memory device 400 further includes a second driving circuit 408, which is coupled to the power-on initialization circuit 404 and the word line. The second driving circuit 408 is configured to apply a second driving voltage to the word line during the power-on initialization phase, thereby turning on the transistor coupled to the word line. The absolute value of the second driving voltage is greater than the absolute value of the transistor's threshold voltage; the second driving voltage will be hereinafter referred to as vwln_high. The second driving circuit 408 may be... Figure 4B The word line driving circuit shown is reused. Of course, in other examples, the second driving circuit 408 can also be a newly added driving circuit.

[0086] As an example, if the transistor in the memory cell is an NMOS transistor, the threshold voltage Vth of the NMOS transistor is positive, meaning the second driving voltage vwln_high is greater than the threshold voltage Vth of the NMOS transistor. If the transistor in the memory cell is a PMOS transistor, the threshold voltage -Vth of the PMOS transistor is negative, meaning the second driving voltage vwln_high is less than the threshold voltage -Vth of the PMOS transistor. Therefore, the absolute value of the second driving voltage vwln_high is greater than the absolute value of the transistor's threshold voltage. For ease of understanding, the following explanation will use an NMOS transistor as an example.

[0087] In this embodiment, by setting the second driving circuit 408 to apply a second driving voltage vwln_high to the word line during the power-on initialization phase, the transistors coupled to the word line can be turned on, and the memory node can discharge through the turned-on transistors. This avoids the memory node being coupled to an uncertain voltage level during the power-on initialization phase, thereby preventing unbalanced current in the cell board. It also ensures that all memory cells are initialized to a "0" state, i.e., the memory cells are in a defined state, thus guaranteeing the sensing margin between data "0" and "1" during subsequent readings, which helps improve the reliability of data reading.

[0088] Figure 6A This is a schematic diagram of a peripheral circuit shown in the first embodiment of this disclosure. Figure 6B This is a timing diagram illustrating the application of a second driving voltage to the word line according to the first embodiment of this disclosure. The following will be combined with... Figure 5 , Figure 6A and Figure 6B The first embodiment of this disclosure will be described by way of example.

[0089] In some embodiments, refer to Figure 5 , Figure 6A and Figure 6BAs shown, the power-on initialization circuit 404 is specifically configured to: generate a first control signal pup_vdd at the first moment T1 of the power-on initialization phase; and generate a power-on completion signal pup_a at the second moment T2 of the power-on initialization phase, wherein the second moment T2 is later than the first moment T1, and the power-on completion signal pup_a is used to indicate that the memory device 400 has completed power-on; the first driving circuit 406 is specifically configured to: apply a first driving voltage vcp to the second terminal based on the first control signal pup_vdd; and the second driving circuit 408 is specifically configured to: apply a second driving voltage vwln_high to the word line at the second moment T2.

[0090] As an example, the power-on initialization circuit 404 can generate a first control signal pup_vdd at the first moment T1 when the first power supply voltage vdd2h reaches a stable state; when the first power supply voltage vdd2h reaches a stable state, the first drive circuit 406 can provide the first drive voltage vcp to the unit board, that is, the first drive circuit 406 applies the first drive voltage vcp to the second terminal based on the first control signal pup_vdd.

[0091] It should be noted that at the initial moment T0, the memory device 400 starts to power on; at the first moment T1, at least part of the power supply voltage (e.g., vdd2h and vdd1) reaches a stable state, and the power-on initialization circuit 404 begins to perform a reset operation, for example, initializing all memory cells to the "0" state. The first control signal pup_vdd is used to indicate that the power supply voltage of the first drive circuit 406 has reached a stable state.

[0092] As an example, the power-on initialization circuit 404 can generate a power-on completion signal pup_a at the second time T2 after power-on completion; when power-on is complete, the second driving circuit 408 can provide the second driving voltage vwln_high to the word line, that is, the second driving circuit 408 applies the second driving voltage vwln_high to the word line at the second time T2.

[0093] In this embodiment of the present disclosure, by setting the second driving circuit 408 to apply the second driving voltage vwln_high to the word line at the second moment T2 after power-on, the coupled memory node can be discharged in time through the conducting transistor, which can avoid the memory cell after initialization being in an uncertain state, thereby ensuring that all memory cells are initialized to the "0" state after the memory device 400 is powered on.

[0094] In some embodiments, the supply voltage of the first driving circuit 406 can be the first power supply voltage vdd2h, and the first driving voltage vcp can be half of the first power supply voltage vdd2h. Of course, in other embodiments, if the supply voltage of the first driving circuit 406 is the second power supply voltage vdd2l, the first time T1 can be the time when the second power supply voltage vdd2l reaches a stable state, and the first driving voltage vcp can be half of the second power supply voltage vdd2l.

[0095] In some embodiments, refer to Figure 5 , Figure 6A and Figure 6B As shown, the memory device 400 further includes a control logic circuit 410, which is coupled to the power-on initialization circuit 404 and the second driving circuit 408. The control logic circuit 410 is configured to generate a second control signal Vwln_en at a second time T2. The first driving circuit 406 is specifically configured to drive the second terminal to charge from the initial voltage to the first driving voltage vcp based on the first control signal pup_vdd, wherein the first terminal is coupled to the charged second terminal. The second driving circuit 408 is specifically configured to apply a second driving voltage vwln_high to the word line based on the second control signal Vwln_en, wherein the coupled first terminal discharges through a conducting transistor.

[0096] As an example, the first driving circuit 406 can drive the cell board to charge from the initial voltage to the first driving voltage vcp based on the first control signal pup_vdd, that is, drive the second terminal to charge from the initial voltage to the first driving voltage vcp. During the charging process of the second terminal, the charge in the capacitor changes, causing the voltage of the first electrode plate to change, that is, the second terminal is coupled while the first terminal is being charged, and the voltage of the storage node increases accordingly. Figure 6B As shown.

[0097] As an example, at the second time T2, the memory device 400 completes power-on, and the control logic circuit 410 can generate a second control signal Vwln_en. The second control signal Vwln_en is used to indicate the selection (or driving) of the corresponding word line. Based on the second control signal Vwln_en, the second driving circuit 408 can provide a second driving voltage vwln_high to the word line, causing the transistor to turn on. The coupled first terminal can discharge through the turned-on transistor, and the voltage of the memory node decreases accordingly. Figure 6B As shown. In this example, the bit line can be coupled to ground while applying the second drive voltage vwln_high to the word line.

[0098] Understandably, during power-on initialization, the first terminal is coupled to the charged second terminal, causing the voltage of the storage node to increase, which will change the state of the storage cell. In this embodiment, after power-on, a second control signal Vwln_en is generated to control the second driving circuit 408 to select the corresponding word line, so that the transistor coupled to the word line is turned on. The coupled first terminal can discharge through the turned-on transistor, and the voltage of the storage node decreases accordingly, allowing the storage cell to return to the "0" state.

[0099] In some embodiments, refer to Figure 5 , Figure 6A and Figure 6B As shown, the second driving circuit 408 is also configured to stop applying the second driving voltage vwln_high to the word line at the fourth time T4 after the second time T2.

[0100] As an example, at time T4, the voltage on the word line switches from high to low, and the transistor coupled to the word line is turned off. In this example, after the voltage of the memory node drops to 0, the control logic circuit 410 can control the second drive circuit 408 to deselect the corresponding word line, and the second drive circuit 408 no longer provides the second drive voltage vwln_high to the word line, that is, it stops applying the second drive voltage vwln_high to the word line.

[0101] It should be noted that the duration for which the second driving voltage vwln_high is applied to the word line (e.g., Figure 6B The duration from the second time point T2 to the fourth time point T4 is related to the degree of coupling of the first terminal. If the first terminal is coupled to a higher voltage level, the duration of applying the second driving voltage vwln_high to the word line can be controlled to be longer to ensure that the coupled first terminal is fully discharged; if the first terminal is coupled to a lower voltage level, the duration of applying the second driving voltage vwln_high to the word line can be controlled to be shorter to save power consumption. In practical applications, the settings can be reasonably configured according to the actual situation, and this disclosure does not impose any special restrictions on this.

[0102] In some embodiments, refer to Figure 5 , Figure 6A and Figure 6B As shown, the memory device 400 further includes a third driving circuit 412, which is coupled to the power-on initialization circuit 404 and the bit line. The third driving circuit 412 is configured to apply a bit line voltage vblp to the bit line during the sensing phase after the power-on initialization phase. The second driving circuit 408 is further configured to apply a word line voltage vwln to the word line during the sensing phase. The third driving circuit 412 may be... Figure 4B The bit line driving circuit shown is used to reuse the bit line driving circuit.

[0103] As an example, during a read operation, the third driving circuit 412 can provide the bit line voltage vblp to the bit line, and the second driving circuit 408 can provide the word line voltage vwln to the word line, thereby selecting the corresponding memory cell for data reading. For example... Figure 2A The sensing amplifier circuit 250 in the example reads out the data stored in the memory cell by sensing and amplifying the electrical signals on the bit lines. In this example, the read operation includes a sensing phase. Of course, in other examples, sensing can also be performed during the refresh operation to read out the data stored in the memory cell and write it back to the memory cell.

[0104] In some embodiments, the third driving circuit 412 is specifically configured to: drive the bit line to charge from the initial bit line voltage to the bit line voltage vblp during the sensing phase; the second driving circuit 408 is specifically configured to: apply the word line voltage vwln to the word line after the bit line is charged to the bit line voltage vblp.

[0105] As an example, from time 5 to time 6, the third driving circuit 412 can drive the bit line to charge from the initial bit line voltage to the bit line voltage vblp based on the third control signal Vblp_en; at time 6, the second driving circuit 408 provides the word line voltage vwln to the word line. Here, the initial bit line voltage can be the ground voltage vss, and the absolute value of the word line voltage vwln is greater than the absolute value of the transistor's threshold voltage.

[0106] Figure 7A This is a schematic diagram of a peripheral circuit shown in the second embodiment of this disclosure. Figure 7B This is a timing diagram illustrating the application of a second driving voltage to the word line according to a second embodiment of this disclosure. The following will be combined with... Figure 5 , Figure 7A and Figure 7B The second embodiment of this disclosure will be described by way of example.

[0107] In some embodiments, refer to Figure 5 , Figure 7A and Figure 7B As shown, the second driving circuit 408 is specifically configured to apply a second driving voltage vwln_high to the word line at a third time T3' before the first time T1.

[0108] As an example, at the third time T3' after the initial time T0, the third power supply voltage vdd1 reaches a stable state; when the third power supply voltage vdd1 reaches a stable state, the second driving circuit 408 can provide the second driving voltage vwln_high to the word line, that is, the second driving circuit 408 applies the second driving voltage vwln_high to the word line at the third time T3'.

[0109] In this embodiment, by setting the second driving circuit 408 to apply a second driving voltage vwln_high to the word line at a third time T3' before the first time T1, the transistor can be turned on before the memory node is coupled. Even if the voltage ramp of the cell board rises between the third time T3' and the first time T1, it is difficult to couple the memory node. This avoids the memory cell being in an uncertain state after initialization, thus ensuring that all memory cells are initialized to a "0" state after the memory device 400 is powered on. Here, the voltage of the cell board ramps up to the first driving voltage vcp at the first time T1.

[0110] In some embodiments, the power supply voltage of the second driving circuit 408 can be the third power supply voltage vdd1, and the second driving voltage vwln_high is less than or equal to the third power supply voltage vdd1. Of course, in other embodiments, if the power supply voltage of the second driving circuit 408 is the first power supply voltage vdd2h, the third time T3' and the first time T1 can be the same time, and the second driving voltage vwln_high is less than or equal to the first power supply voltage vdd2h.

[0111] In some embodiments, the memory device 400 further includes a control logic circuit 410, which is coupled to a power-on initialization circuit 404 and a second driving circuit 408. The control logic circuit 410 is configured to generate a second control signal Vwln_en at a third time T3'. The second driving circuit 408 is specifically configured to apply a second driving voltage vwln_high to the word line based on the second control signal Vwln_en.

[0112] In this embodiment, the control logic circuit 410 can generate a second control signal Vwln_en at the third time T3', thereby controlling the second driving circuit 408 to provide the second driving voltage vwln_high to the word line, so that the transistor is turned on. The second terminal starts charging after the third time T3' and reaches a stable state at the first time T1. During the charging process of the second terminal, since the transistor is in the on state, the first terminal can be grounded through the on transistor, so the first terminal is difficult to couple, and the voltage of the storage node remains unchanged. Figure 7B As shown.

[0113] Figure 8A This is a schematic diagram of a peripheral circuit shown in the third embodiment of this disclosure. Figure 8B This is a timing diagram illustrating the application of a second driving voltage to the word line according to the third embodiment of this disclosure. The following will be combined with... Figure 5 , Figure 8A and Figure 8B The third embodiment of this disclosure will be described by way of example.

[0114] In some embodiments, refer to Figure 5 , Figure 8A and Figure 8B As shown, the power-on initialization circuit 404 is specifically configured to: generate a power-on completion signal pup_a at the second time T2 of the power-on initialization phase, wherein the power-on completion signal pup_a is used to indicate that the memory device 400 has completed power-on; the first driving circuit 406 is specifically configured to: apply a first driving voltage vcp to the second terminal based on the power-on completion signal pup_a; the second driving circuit 408 is specifically configured to: apply a second driving voltage vwln_high to the word line at the second time T2.

[0115] In this embodiment of the present disclosure, at the second time T2, the first driving circuit 406 provides the first driving voltage vcp to the cell board, and the second driving circuit 408 provides the second driving voltage vwln_high to the word line. That is, during the charging process of the second terminal, the transistor is kept in the conducting state, and the first terminal can be grounded through the conducting transistor. Therefore, the first terminal is difficult to couple, and the voltage of the storage node remains unchanged. Figure 8B As shown.

[0116] In some embodiments, the memory device 400 further includes a control logic circuit 410, which is coupled to a power-on initialization circuit 404 and a second driving circuit 408. The control logic circuit 410 is configured to generate a second control signal Vwln_en at a second time T2. The second driving circuit 408 is specifically configured to apply a second driving voltage vwln_high to the word line based on the second control signal Vwln_en.

[0117] As an example, at the second time T2, the control logic circuit 410 can generate a second control signal Vwln_en, thereby controlling the second drive circuit 408 to provide the second drive voltage vwln_high to the word line so that the transistor is turned on. Even if the second terminal is charged at the second time T2, the first terminal is difficult to couple, and the voltage of the storage node remains unchanged.

[0118] This disclosure provides a memory device comprising: a memory cell, a power-on initialization circuit, a first driving circuit, and a second driving circuit; the memory cell includes a capacitor and a transistor, wherein the transistor is coupled to a first terminal of the capacitor; the power-on initialization circuit is coupled to the memory cell; the power-on initialization circuit is configured to perform power-on initialization on the memory cell upon power-on of the memory device; the first driving circuit is coupled to the second terminal of the capacitor and the power-on initialization circuit respectively; the first driving circuit is configured to apply a first driving voltage to the second terminal during the power-on initialization phase; the second driving circuit is coupled to the power-on initialization circuit and a word line respectively; the second driving circuit is configured to apply a second driving voltage to the word line during the power-on initialization phase, thereby turning on the transistor coupled to the word line. In this way, firstly, it avoids the storage node being coupled to an uncertain voltage level during the power-on initialization phase, thereby preventing unbalanced current in the cell board. This allows all storage cells to be initialized to a "0" state, meaning the storage cells are in a definite state, thus ensuring the sensing margin between data "0" and "1" during subsequent readings, which helps improve the reliability of data reading. Secondly, by providing a new power-on timing sequence, it can help set the initial state of the storage cells to a "0" state. Thirdly, the initialization of the storage cells is done through the new power-on timing sequence, eliminating the need to add any additional operations to the storage cells during power-on initialization. Fourthly, it avoids uncertain leakage current before power-on.

[0119] Based on the above-described memory device, this disclosure provides an operation method for the memory device.

[0120] Figure 9 This is a schematic flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure. It should be noted that... Figure 9 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 9 The steps shown can be rearranged in order according to actual needs. (Refer to...) Figure 9 As shown, this operation method includes at least the following steps:

[0121] Step S510: Based on the power-on of the memory device, perform power-on initialization on the memory cell of the memory device, wherein the memory cell includes a capacitor and a transistor, and the transistor is coupled to the first terminal of the capacitor;

[0122] Step S520: During the power-on initialization phase, a first driving voltage is applied to the second terminal of the capacitor;

[0123] Step S530: During the power-on initialization phase, a second driving voltage is applied to the word line of the coupled transistor to turn on the transistor.

[0124] In some embodiments, step S510 includes: generating a first control signal at a first moment during the power-on initialization phase; generating a power-on completion signal at a second moment during the power-on initialization phase, wherein the second moment is later than the first moment, and the power-on completion signal is used to indicate that the memory device has completed power-on; step S520 includes: applying a first driving voltage to a second terminal based on the first control signal; step S530 includes: applying a second driving voltage to a word line at a third moment, either at the second moment or before the first moment.

[0125] In some embodiments, the above operation method further includes: generating a second control signal at a second time; applying a first driving voltage to the second terminal based on the first control signal includes: driving the second terminal to charge from an initial voltage to the first driving voltage based on the first control signal, wherein the first terminal is coupled to the charged second terminal; applying a second driving voltage to the word line at the second time includes: applying a second driving voltage to the word line based on the second control signal, wherein the coupled first terminal discharges through a conducting transistor.

[0126] In some embodiments, the above-described operation method further includes: generating a second control signal at a third time; the above-described application of a second driving voltage to the word line at the second time includes: applying a second driving voltage to the word line based on the second control signal.

[0127] In some embodiments, step S510 includes: generating a power-on completion signal at a second moment during the power-on initialization phase, wherein the power-on completion signal is used to indicate that the memory device has completed power-on; step S520 includes: applying a first driving voltage to the second terminal based on the power-on completion signal; step S530 includes: applying a second driving voltage to the word line at a second moment.

[0128] In some embodiments, the above-described operation method further includes: generating a second control signal at a second time; the above-described application of a second driving voltage to the word line at the second time includes: applying a second driving voltage to the word line based on the second control signal.

[0129] In some embodiments, the above operation method further includes: stopping the application of the second driving voltage to the word line at a fourth time after the second time.

[0130] In some embodiments, the above operation method further includes: applying a bit line voltage to the bit line of the coupled transistor during a sensing phase following the power-on initialization phase; and applying a word line voltage to the word line during the sensing phase.

[0131] In some embodiments, applying a bit line voltage to the bit line of the coupled transistor during the sensing phase following the power-on initialization phase includes: driving the bit line to charge from an initial bit line voltage to a bit line voltage during the sensing phase; applying a word line voltage to the word line during the sensing phase includes: applying a word line voltage to the word line after the bit line has been charged to the bit line voltage.

[0132] In this embodiment, the operation method of the memory device can be executed by the memory device in any of the foregoing embodiments, and the technical effects that the memory devices in the foregoing embodiments can achieve can also be achieved by this operation method, which will not be repeated here. Regarding the operation methods in the above embodiments, the specific implementation methods of each step have been described in detail in the embodiments of the relevant memory devices, and will not be elaborated upon here.

[0133] Based on the memory device described above, this disclosure provides a memory system. The memory system includes a memory device as described in any of the above embodiments and a controller coupled to the memory device. References to the memory system and controller are provided respectively. Figure 1 Descriptions of the storage system 30 and controller 10.

[0134] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0135] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0136] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0137] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0138] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: A storage unit, the storage unit including a capacitor and a transistor, wherein the transistor is coupled to a first terminal of the capacitor; A power-on initialization circuit is coupled to the memory cell; the power-on initialization circuit is configured to perform power-on initialization on the memory cell based on the power-on of the memory device. A first driving circuit is coupled to the power-on initialization circuit and the second terminal of the capacitor, respectively; the first driving circuit is configured to apply a first driving voltage to the second terminal during the power-on initialization phase. A second driving circuit is coupled to the power-on initialization circuit and the word line respectively; the second driving circuit is configured to apply a second driving voltage to the word line during the power-on initialization phase, so that the transistor coupled to the word line is turned on.

2. The memory device according to claim 1, characterized in that, The power-on initialization circuit is specifically configured as follows: At the first moment of the power-on initialization phase, a first control signal is generated; At a second moment during the power-on initialization phase, a power-on completion signal is generated, wherein the second moment is later than the first moment, and the power-on completion signal is used to indicate that the memory device has completed power-on; The first driving circuit is specifically configured to apply the first driving voltage to the second terminal based on the first control signal; The second driving circuit is specifically configured to apply the second driving voltage to the word line at a third time before the second time or the first time.

3. The memory device according to claim 2, characterized in that, The memory device further includes a control logic circuit, which is coupled to the power-on initialization circuit and the second drive circuit respectively; the control logic circuit is configured to generate a second control signal at the second time. The first driving circuit is specifically configured to: drive the second terminal to charge from an initial voltage to the first driving voltage based on the first control signal, wherein the first terminal is coupled to the charged second terminal; The second driving circuit is specifically configured to apply the second driving voltage to the word line based on the second control signal, wherein the coupled first terminal discharges through the turned-on transistor.

4. The memory device according to claim 2, characterized in that, The memory device further includes a control logic circuit, which is coupled to the power-on initialization circuit and the second drive circuit respectively. The control logic circuit is configured to generate a second control signal at the third time. The second driving circuit is specifically configured to apply the second driving voltage to the word line based on the second control signal.

5. The memory device according to claim 1, characterized in that, The power-on initialization circuit is specifically configured to generate a power-on completion signal at the second moment of the power-on initialization phase, wherein the power-on completion signal is used to indicate that the memory device has completed power-on. The first driving circuit is specifically configured to apply the first driving voltage to the second terminal based on the power-on completion signal; The second driving circuit is specifically configured to apply the second driving voltage to the word line at the second time.

6. The memory device according to claim 5, characterized in that, The memory device further includes a control logic circuit, which is coupled to the power-on initialization circuit and the second drive circuit respectively; the control logic circuit is configured to generate a second control signal at the second time. The second driving circuit is specifically configured to apply the second driving voltage to the word line based on the second control signal.

7. The memory device according to claim 2 or 5, characterized in that, The second driving circuit is further configured to stop applying the second driving voltage to the word line at a fourth time after the second time.

8. The memory device according to claim 1, characterized in that, The memory device further includes a third driving circuit, which is coupled to the power-on initialization circuit and the bit line respectively. The third driving circuit is configured to apply a bit line voltage to the bit line during the sensing phase following the power-on initialization phase. The second driving circuit is further configured to apply a word line voltage to the word line during the sensing phase.

9. The memory device according to claim 8, characterized in that, The third driving circuit is specifically configured to: during the sensing phase, drive the bit line to charge from the initial bit line voltage to the bit line voltage; The second driving circuit is specifically configured to apply the word line voltage to the word line after the bit line is charged to the bit line voltage.

10. The memory device according to claim 1, characterized in that, The memory device includes dynamic random access memory.

11. A method of operating a memory device, characterized in that, include: Upon power-on of the memory device, power-on initialization is performed on the memory cells of the memory device, wherein the memory cells include a capacitor and a transistor, and the transistor is coupled to a first terminal of the capacitor; During the power-on initialization phase, a first driving voltage is applied to the second terminal of the capacitor; During the power-on initialization phase, a second drive voltage is applied to the word line coupled to the transistor to turn the transistor on.

12. The operating method according to claim 11, characterized in that, The step of performing power-on initialization on the memory cells of the memory device upon power-on includes: At the first moment of the power-on initialization phase, a first control signal is generated; At a second moment during the power-on initialization phase, a power-on completion signal is generated, wherein the second moment is later than the first moment, and the power-on completion signal is used to indicate that the memory device has completed power-on; The step of applying a first driving voltage to the second terminal of the capacitor during the power-on initialization phase includes: applying the first driving voltage to the second terminal based on the first control signal; The step of applying a second driving voltage to the word line coupled to the transistor during the power-on initialization phase includes applying the second driving voltage to the word line at a third time before the second time or the first time.

13. The operating method according to claim 12, characterized in that, The operation method further includes: generating a second control signal at the second moment; The step of applying the first driving voltage to the second terminal based on the first control signal includes: driving the second terminal to charge from an initial voltage to the first driving voltage based on the first control signal, wherein the first terminal is coupled to the charged second terminal; Applying the second driving voltage to the word line at the second moment includes: applying the second driving voltage to the word line based on the second control signal, wherein the coupled first terminal discharges through the turned-on transistor.

14. The operating method according to claim 12, characterized in that, The operation method further includes: generating a second control signal at the third time point; Applying the second driving voltage to the word line at the second moment includes: applying the second driving voltage to the word line based on the second control signal.

15. The operating method according to claim 11, characterized in that, The step of performing power-on initialization on the memory cells of the memory device upon power-on includes: At the second moment of the power-on initialization phase, a power-on completion signal is generated, wherein the power-on completion signal is used to indicate that the memory device has completed power-on; The step of applying a first driving voltage to the second terminal during the power-on initialization phase includes: applying the first driving voltage to the second terminal based on the power-on completion signal; The step of applying a second driving voltage to the word line coupled to the transistor during the power-on initialization phase includes: applying the second driving voltage to the word line at the second moment.

16. The operating method according to claim 15, characterized in that, The operation method further includes: generating a second control signal at the second moment; Applying the second driving voltage to the word line at the second time includes: applying the second driving voltage to the word line based on the second control signal.

17. The operating method according to claim 12 or 15, characterized in that, The operation method further includes: at a fourth time after the second time, stopping the application of the second driving voltage to the word line.

18. The operating method according to claim 11, characterized in that, The operation method further includes: During the sensing phase following the power-on initialization phase, a bit line voltage is applied to the bit line coupled to the transistor. During the sensing phase, a word line voltage is applied to the word line.

19. The operating method according to claim 18, characterized in that, The step of applying a bit line voltage to the bit line coupled to the transistor during the sensing phase following the power-on initialization phase includes: during the sensing phase, driving the bit line to charge from an initial bit line voltage to the bit line voltage. The step of applying a word line voltage to the word line during the sensing phase includes: applying the word line voltage to the word line after the bit line is charged to the bit line voltage.

20. A storage system, characterized in that, include: The memory device as claimed in any one of claims 1 to 10 and the controller coupled to the memory device.

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