Dynamic random access memory and method of forming the same, memory system

Abstract

The present disclosure provides a dynamic random access memory, a forming method thereof, and a memory system, the dynamic random access memory comprising: a first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein the first semiconductor structure comprises a memory cell array and a first capacitor structure for serving as a capacitor of a charge pump circuit; and the second semiconductor structure comprises a peripheral circuit comprising a voltage regulation circuit of the charge pump circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and for example to a dynamic random access memory and a method for forming the same, and a memory system. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a dynamic random access memory is provided, comprising: a first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein the first semiconductor structure includes a memory cell array and a first capacitor structure, the first capacitor structure being used as a capacitor for a charge pump circuit; the second semiconductor structure includes peripheral circuitry, the peripheral circuitry including a voltage regulation circuitry for the charge pump circuitry.

[0004] In some embodiments, the dynamic random access memory includes a first storage area, a first peripheral area, and a second storage area arranged along a second direction, wherein the first peripheral area is located between the first storage area and the second storage area; the storage cell array is located in the first storage area and the second storage area; and the second direction is perpendicular to the first direction.

[0005] In some implementations, the first capacitor structure is located in the first peripheral region.

[0006] In some implementations, the voltage regulation circuit is located in the first peripheral region.

[0007] In some embodiments, the dynamic random access memory further includes a second peripheral region; the first storage region, the first peripheral region, and the second storage region are located on the same side of two opposite sides of the second peripheral region along a third direction; the first capacitor structure is located in the second peripheral region; the third direction is perpendicular to both the first direction and the second direction.

[0008] In some embodiments, the voltage regulation circuit is located in the second peripheral region.

[0009] In some embodiments, the voltage regulation circuit and the first capacitor structure at least partially overlap in a view perpendicular to the first direction.

[0010] In some embodiments, the memory cell array includes a plurality of memory cells, each memory cell including a transistor structure and a second capacitor structure, wherein the first capacitor structure and the second capacitor structure have the same structure.

[0011] In some embodiments, the charge pump circuit includes the voltage regulation circuit and the capacitor circuit; the voltage regulation circuit includes a plurality of voltage regulation sub-circuits, and the capacitor circuit includes a plurality of capacitor sub-circuits; the capacitor sub-circuits and the correspondingly connected voltage regulation sub-circuits at least partially overlap in a view perpendicular to the first direction.

[0012] In some embodiments, the voltage regulation circuit includes N voltage regulation sub-circuits; the N voltage regulation sub-circuits are connected in series, the input terminal of the first voltage regulation sub-circuit is connected to the voltage input terminal, and the output terminal of the Nth voltage regulation sub-circuit is connected to the voltage output terminal; N is an integer greater than 1.

[0013] In some implementations, the voltage regulation sub-circuit includes a diode.

[0014] In some embodiments, the capacitor circuit includes (N-1) capacitor sub-circuits, each capacitor sub-circuit including at least one of the first capacitor structures; the first terminal of each of the (N-1) capacitor sub-circuits is connected to the output terminal of each of the preceding (N-1) voltage regulation sub-circuits in a one-to-one correspondence.

[0015] In some embodiments, the second terminal of the capacitor sub-circuit with an odd number in the (N-1) capacitor sub-circuit is connected to the first clock signal terminal, and the second terminal of the capacitor sub-circuit with an even number in the (N-1) capacitor sub-circuit is connected to the second clock signal terminal; the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal are complementary clock signals.

[0016] In some embodiments, the capacitor sub-circuit includes M first capacitor structures connected in parallel; where M is an integer greater than or equal to 2.

[0017] In some implementations, M equals 2.

[0018] In some embodiments, the first semiconductor structure further includes a first bonding layer, the first bonding layer including a first bonding structure; the first bonding layer is located between the memory cell array and the second semiconductor structure, and between the first capacitor structure and the second semiconductor structure; the second semiconductor structure further includes a second bonding layer, the second bonding layer including a second bonding structure; the second bonding layer is located between the peripheral circuit and the first semiconductor structure.

[0019] In some embodiments, the first semiconductor structure further includes a first interconnect structure located between the first capacitor structure and the first bonding layer; the second semiconductor structure further includes a second interconnect structure located between the voltage regulation circuit and the second bonding layer; the first capacitor structure is connected to the voltage regulation circuit through the first interconnect structure, the first bonding structure, the second bonding structure, and the second interconnect structure.

[0020] According to a second aspect of the present disclosure, a memory system is provided, the memory system including a memory controller and a dynamic random access memory as described in any of the above embodiments; the memory controller is coupled to the dynamic random access memory and configured to control the dynamic random access memory.

[0021] According to a third aspect of the present disclosure, a method for forming a dynamic random access memory is provided, comprising: forming a first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein the first semiconductor structure includes a memory cell array and a first capacitor structure, the first capacitor structure being used as a capacitor for a charge pump circuit; and the second semiconductor structure includes peripheral circuitry, the peripheral circuitry including a voltage regulation circuit for the charge pump circuit.

[0022] In some embodiments, forming the first semiconductor structure and the second semiconductor structure stacked along the first direction includes forming the first capacitor structure while forming the second capacitor structure of the memory cells of the memory cell array.

[0023] In the disclosed embodiments, the first capacitor structure in the first semiconductor structure is used as the capacitor of the charge pump circuit. There is no need to form an additional metal capacitor or MOSFET capacitor in the second semiconductor structure where the peripheral circuit is located. This allows the area of ​​the second semiconductor structure where the peripheral circuit is located to be saved while meeting the high current capability of the charge pump, which is beneficial to the miniaturization trend of dynamic random access memory. Attached Figure Description

[0024] Figure 1A This is a schematic block diagram of an exemplary electronic device according to an embodiment of the present disclosure;

[0025] Figure 1B A schematic diagram illustrating the composition of an exemplary electronic device provided in an embodiment of this disclosure;

[0026] Figure 2A This is a schematic block diagram of an exemplary solid-state drive (SSD) according to an embodiment of the present disclosure;

[0027] Figure 2BThis is a schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of the present disclosure;

[0029] Figure 4 This is a schematic diagram showing the connection relationship between word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to an embodiment of this disclosure.

[0030] Figure 5 A schematic diagram of the framework structure of a dynamic random access memory provided in an embodiment of this disclosure;

[0031] Figure 6 A schematic diagram of the region distribution of a dynamic random access memory provided in an embodiment of this disclosure;

[0032] Figure 7 A schematic diagram of the regional distribution of a second semiconductor structure provided in an embodiment of this disclosure;

[0033] Figure 8 Schematic diagram 2 of the region distribution of a dynamic random access memory provided in an embodiment of this disclosure;

[0034] Figure 9 This is a schematic diagram of the regional distribution of a second semiconductor structure provided in an embodiment of the present disclosure;

[0035] Figure 10 A schematic diagram showing the relationship between the equivalent circuit of a charge pump circuit and the first and second semiconductor structures provided in an embodiment of this disclosure;

[0036] Figure 11 An equivalent circuit diagram of a charge pump circuit provided in an embodiment of this disclosure;

[0037] Figure 12 This is a schematic diagram of the equivalent circuit of a Dickson charge pump circuit when N is 3.

[0038] Figure 13 A second schematic diagram of the framework structure of a dynamic random access memory provided in an embodiment of this disclosure;

[0039] Figure 14 A three-dimensional structural diagram of a dynamic random access memory provided in an embodiment of this disclosure;

[0040] Figure 15 This is a schematic flowchart illustrating a method for forming a dynamic random access memory according to an embodiment of the present disclosure. Detailed Implementation

[0041] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0043] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0044] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] Figure 1AA schematic block diagram of an exemplary electronic device according to an embodiment of the present disclosure is shown. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1A As shown, electronic device 1 may include a host and a memory system 30. The memory system 30 includes a memory controller 10 and one or more memory devices 20. The host may be a processor of the electronic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The host may be configured to send data to or receive data from the memory device 20. The memory controller 10 is coupled to the memory device 20 and the host and is configured to control the memory device 20. The memory controller 10 may manage the data stored in the memory device 20 and communicate with the host.

[0047] The memory controller 10 can be configured to control the operation of the memory device 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory device 20. The memory controller 10 can also perform any other suitable functions, such as formatting the memory device 20.

[0048] In some specific embodiments, the memory controller 10 and one or more memory devices 20 can be integrated into various types of electronic devices. For example, the memory controller 10 can be integrated into the northbridge of a computer motherboard or directly into the computer CPU, and multiple memory devices 20 can be integrated into a memory module. In other words, the memory system 30 can be implemented and packaged into different types of terminal electronic products.

[0049] The memory controller 10 can send data to / receive data from the host, and can send commands (CMD) and addresses (ADDR) to the memory device 20. The memory controller 10 may include a command generator 110, an address generator 120, a device interface 130, and a host interface 140. The host interface 140 can receive commands (CMD) and addresses (ADDR) from the host. The command generator 110 can generate access commands, row hammer refresh commands, etc., by decoding the commands (CMD) received from the host, and can provide access commands and row hammer refresh commands to the memory device 20 through the device interface 130. An access command may be a signal instructing the memory device 20 to write or read data by accessing a row of the memory cell array 220 corresponding to the address ADDR. A row hammer refresh command may be a signal instructing the memory device 20 to perform an additional refresh operation on word lines adjacent to word lines that are frequently accessed in a short period. In other words, an additional refresh operation can be performed on word lines adjacent to word lines that are accessed multiple times in a short period.

[0050] The address generator 120 in the memory controller 10 can generate the row and column addresses to be accessed in the memory cell array 220 by decoding the address ADDR received from the host interface 140. Furthermore, the memory device 20 can generate addresses of the memory banks to be accessed when the memory cell array 220 comprises multiple banks.

[0051] Furthermore, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory device 20 via the device interface 130. For example, the memory controller 10 can provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data in the memory device 20.

[0052] In some embodiments, the memory device 20 includes a memory cell array 220 and peripheral circuitry 210. The memory cell array 220 includes multiple banks, each bank includes multiple blocks, each block includes multiple rows and columns of memory cells, each row is coupled to a corresponding word line, and each column is coupled to a corresponding bit line. The peripheral circuitry 210 can write data to or read data from the memory cell array 220 based on commands CMD and addresses ADDR received from the memory controller 10, or it can provide control signals CTRL to the row decoding and column decoding circuits for refreshing the memory cells included in the memory cell array 220. In other words, the peripheral circuitry 210 can perform all operations to process the data in the memory cell array 220. The peripheral circuit 210 may include: control circuits corresponding to each memory block, such as sensing amplifier (SA) circuits and word-line driver (WLD) circuits; control circuits corresponding to each memory bank, such as row decoding circuits and column decoding circuits; and control circuits corresponding to all memory banks, such as command buffers, command decoders, address buffers, data input / output buffers, and mode registers.

[0053] The memory device 20 can be random access memory (RAM), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double data rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc. The following explanation uses DRAM as an example only.

[0054] Figure 1BA schematic diagram of the composition of an exemplary electronic device according to an embodiment of the present disclosure is shown. In some embodiments, DRAM may be a structure outside the memory system 30, which may be directly connected to the host as main memory during host operation, or DRAM may be embedded in the host. In some embodiments, DRAM may be a structure outside the memory system 30, which may be coupled to the memory system 30 for use as buffer memory, for example, for storing a mapping table. In some embodiments, DRAM as buffer memory may also be embedded in the memory controller 10. In other embodiments, DRAM may also be part of the memory controller 10, for example, DRAM as buffer memory is embedded in the memory controller 10. In some embodiments, DRAM may also be part of the memory controller 10, for example, part of a DRAM controller, for controlling the memory device 20 to perform operations such as write and read. In other embodiments, a plurality of DRAM stacks may be applied to a high-bandwidth memory (HBM) architecture for use as a storage medium.

[0055] Figure 2A This is a schematic block diagram illustrating the composition of an exemplary SSD according to an embodiment of this disclosure. Here, SSD can be understood as the aforementioned... Figure 1A as well as Figure 1B In this example, DRAM can be used as a buffer memory, representing one type of memory system.

[0056] like Figure 2AAs shown, SSD 30' may include SSD controller 10', buffer memory 20', and non-volatile memory 40. SSD controller 10' provides the physical connection between the host and SSD 30'. That is, SSD controller 10' can provide an interface between the host and SSD 30' according to the host's bus format. SSD controller 10' can decode instructions provided by the host. SSD controller 10' can access non-volatile memory 40 based on the decoding result. Buffer memory 20' can temporarily store write data provided by the host or data read from non-volatile memory 40. When the host issues a read request, if the data present in non-volatile memory 40 is cached, buffer memory 20' can support caching functionality for directly providing cached data to the host. The data transfer rate through the host's bus format (e.g., SATA or SAS) is much higher than the data transfer rate of the SSD 30's memory channel. That is, when the host interface speed is significantly higher, the performance degradation caused by the speed difference can be minimized by providing a high-capacity buffer memory 20'. Additionally, the buffer memory 20' can store the address mapping table of the non-volatile memory 40. The buffer memory 20' can be, but is not limited to, DRAM. The non-volatile memory 40 can be configured as a storage medium for an SSD 30'. The non-volatile memory 40 can be, but is not limited to, NAND flash memory.

[0057] Figure 2B This is a schematic block diagram illustrating the composition of an exemplary memory according to an embodiment of this disclosure; here, memory can be understood as the aforementioned Figure 1A One type of memory system in this example uses DRAM as a storage medium.

[0058] like Figure 2B As shown, memory 30'' can be easily attached to or installed in an electronic device or removed from electronic device 1 via the illustrated interface. Memory 30'' may include multiple volatile memories 20'' (e.g., DRAM) and a memory controller 10''. Memory 30'' can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of a computer's processor. In some embodiments, memory controller 10'' may communicate with DRAM using at least one communication protocol or technology standard typically associated with, for example, dual in-line memory modules (DIMMs), register-based DIMMs (RDIMMs), low-load DIMMs (LRDIMMs), and registerless DIMMs (UDIMMs).

[0059] It should be noted that, Figure 2A Buffer memory 20' and Figure 2B All 20'' of the medium volatile memory Figure 1A One application scenario of the memory device 20.

[0060] Figure 3 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram showing the connection relationship between word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to an embodiment of this disclosure.

[0061] Figure 3 The right side shows the circuitry of a memory cell in a DRAM. A DRAM includes at least one DRAM die, and each DRAM die includes a memory cell array. The memory cell array includes multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T and a capacitor C. The main working principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be viewed as a typical mesh structure. For details on this mesh structure, please refer to [reference needed]. Figure 4 The memory cell array uses rows and columns to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the data stored therein.

[0062] Figure 3 The left side shows the memory cell array and some peripheral circuitry in a DRAM. It's important to note that the row decoding circuit, in response to an address input to it, selects a word line to choose the row of the memory cell to access. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit selects one or more bit lines to input output data into a portion of the row of the memory cell corresponding to the selected word line. For example... Figure 3 As shown, the peripheral circuitry also includes a voltage generator, which can generate and regulate various voltages required within the dynamic random access memory (DRAM). For example, it can provide a high voltage (such as VPP) to the row decoder circuitry to drive selected word lines, a reference voltage to the sense amplifier to detect and amplify small signals on the bit lines, a switching control voltage (such as VDD or a negative voltage) to the column decoder circuitry to connect selected bit lines to the data bus, and an interface voltage (such as VDDQ or a high voltage VDDQ+, matched to the external system) to the data input / output buffers to ensure level compatibility between the DRAM and the external controller.

[0063] To perform write and refresh operations on the memory cells of Dynamic Random Access Memory (DRAM), a voltage higher than the normal operating voltage is required. The charge pump circuit in the voltage generator can convert a low voltage (such as VDD) into the required high voltage (such as VPP, VDDQ+), thereby providing sufficient charge to the memory cells of DRAM. The charge pump circuit has many advantages such as low power consumption, high integration, and stability, making it widely used in DRAM.

[0064] In some embodiments, the capacitor in the charge pump circuit uses a MOSFET capacitor or a metal capacitor in the peripheral circuit. To obtain a larger current capability, a larger capacitor is required. The larger the current capability, the larger the required capacitor size. This results in a larger area occupied by the peripheral circuit, which in turn makes the dynamic random access memory (DRAM) occupy a larger area, hindering the miniaturization of DRAM. As the integration requirements of memory become increasingly stringent, saving memory area has become an urgent problem to be solved.

[0065] The present disclosure provides the following implementation methods.

[0066] This disclosure provides a dynamic random access memory. Figure 5 This is a schematic diagram of the framework structure of the dynamic random access memory provided in the embodiments of this disclosure, as shown below. Figure 5 As shown, the dynamic random access memory includes: a first semiconductor structure 501 and a second semiconductor structure 502 stacked along a first direction; wherein, the first semiconductor structure 501 includes a memory cell array 503 and a first capacitor structure 504, the first capacitor structure 504 being used as a capacitor for a charge pump circuit; the second semiconductor structure 502 includes a peripheral circuit 505, the peripheral circuit 505 including a voltage regulation circuit for the charge pump circuit.

[0067] The first direction in this embodiment can be understood as the Z-axis direction in the attached drawings, the second direction can be understood as the Y-axis direction in the attached drawings, and the third direction can be understood as the X-axis direction in the attached drawings.

[0068] In this embodiment of the present disclosure, the first capacitor structure 504 in the first semiconductor structure 501 is used as the capacitor of the charge pump circuit. There is no need to form an additional metal capacitor or MOSFET capacitor in the second semiconductor structure 502 where the peripheral circuit 505 is located. This allows the area of ​​the second semiconductor structure 502 where the peripheral circuit 505 is located to be saved while meeting the high current capability of the charge pump, which is beneficial to the miniaturization of dynamic random access memory.

[0069] In this embodiment of the present disclosure, the first semiconductor structure includes a memory cell array, and the second semiconductor structure includes peripheral circuitry. The first semiconductor structure and the second semiconductor structure are stacked along a first direction, which reduces the area occupied by the dynamic random access memory.

[0070] Figure 6 A schematic diagram of the region distribution of the dynamic random access memory provided in this embodiment of the present disclosure.

[0071] In some embodiments, such as Figure 6 As shown, the dynamic random access memory includes a first storage area 601, a first peripheral area 602, and a second storage area 603 arranged along a second direction. The first peripheral area 602 is located between the first storage area 601 and the second storage area 603. The storage cell array 503 is located in the first storage area 601 and the second storage area 603. The second direction is perpendicular to the first direction.

[0072] In this embodiment of the present disclosure, the dynamic random access memory includes a first storage area 601, a first peripheral area 602 and a second storage area 603 arranged along the Y-axis direction, and a storage cell array 503 is disposed in the first storage area 601 and the second storage area 603.

[0073] In some embodiments, the first capacitor structure 504 is located in the first peripheral region 602.

[0074] In this embodiment of the present disclosure, the first capacitor structure 504 in the first semiconductor structure 501 is used as the capacitor of the charge pump circuit, thereby saving the area of ​​the peripheral circuit; and the first capacitor structure 504 is disposed in the free area of ​​the first semiconductor structure 501, for example, the first capacitor structure 504 is located in the first peripheral region 602, so that the free area of ​​the first semiconductor structure 501 in the first peripheral region 602 can be fully utilized, which is conducive to reducing the area occupied by the dynamic random access memory and is conducive to the miniaturization of the dynamic random access memory.

[0075] In some embodiments, the voltage regulation circuit is located in the first peripheral region 602.

[0076] In this embodiment of the disclosure, the peripheral circuit in the second semiconductor structure 502 includes a voltage regulation circuit of a charge pump circuit, and the voltage regulation circuit is located in the second semiconductor structure 502 in the first peripheral region 602.

[0077] Figure 7 This is a schematic diagram of the regional distribution of the second semiconductor structure 502 provided in this embodiment. It should be noted that, in order to more clearly illustrate the relationship between the first memory region 601, the second memory region 603, and the first peripheral region 602 and the second semiconductor structure 502, Figure 7Only the second semiconductor structure 502 is shown, and the first semiconductor structure is not shown.

[0078] like Figure 7 As shown, portions of the second semiconductor structure 502 in the first memory region 601 and the second memory region 603 include a first circuit region 605, a second circuit region 607, and a third circuit region 606. Multiple first circuit regions 605 are arranged in an array along a second direction and a third direction, with each memory cell corresponding to one first circuit region 605. For example, as... Figure 7 As shown, the second semiconductor structure 502 includes 16 first circuit regions 605, and the memory cell array 503 includes 16 memory banks Bank0-Bank15. Each memory bank in Bank0-Bank15 corresponds to one first circuit region 605, and each memory bank includes multiple memory blocks. It should be noted that... Figure 7 The number of first circuit regions 605 is for illustrative purposes only and is not intended to limit the number of first circuit regions 605 in the second semiconductor structure 502 in the embodiments of this disclosure.

[0079] like Figure 7 As shown, the second circuit region 607 is located between adjacent first circuit regions 605 along a third direction, and the third circuit region 606 is located between adjacent first circuit regions 605 along a second direction. Control circuits for each memory block of the corresponding memory bank can be configured in the first circuit region 605, such as a sensing amplifier (SA) circuit and a word-line driver (WLD) circuit; control circuits for the corresponding memory bank can be configured in the second circuit region 607, such as a row decoding circuit; and control circuits for the corresponding memory bank can be configured in the third circuit region 606, such as a column decoding circuit. A voltage regulation circuit for a charge pump circuit can be configured in the second semiconductor structure 502 in the first peripheral region 602. In addition to the voltage regulation circuit, control circuits for all memory banks can also be configured in the second semiconductor structure 502 in the first peripheral region 602, such as a command buffer, command decoder, address buffer, data input / output buffer, and mode register.

[0080] In this embodiment of the disclosure, when the first capacitor structure 504 is located in the first peripheral region 602, the voltage regulation circuit is also located in the first peripheral region 602. That is to say, the first capacitor structure 504 and the voltage regulation circuit are located in the same area, which makes the first capacitor structure 504 and the voltage regulation circuit closer together, and can shorten the connection between the first capacitor structure 504 and the voltage regulation circuit.

[0081] In some embodiments, the dynamic random access memory further includes a second peripheral region; the first storage region, the first peripheral region, and the second storage region are located on the same side of two opposite sides of the second peripheral region along a third direction; a first capacitor structure is located in the second peripheral region; the third direction is perpendicular to both the first direction and the second direction.

[0082] In this embodiment of the present disclosure, the first capacitor structure 504 in the first semiconductor structure 501 is used as the capacitor of the charge pump circuit, thereby saving the area of ​​the peripheral circuit. The first capacitor structure 504 is disposed in the idle area of ​​the first semiconductor structure 501, for example, the first capacitor structure 504 is located in the second peripheral area. This allows full utilization of the idle area of ​​the first semiconductor structure 501 in the second peripheral area, which is beneficial to reducing the area occupied by the dynamic random access memory and promoting the miniaturization of the dynamic random access memory.

[0083] Figure 8 Schematic diagram 2 of the region distribution of the dynamic random access memory provided in the embodiments of this disclosure.

[0084] In this embodiment of the disclosure, such as Figure 8 As shown, the dynamic random access memory includes a first storage area 601, a first peripheral area 602, a second storage area 603, and a second peripheral area 604 arranged along the Y-axis. The first storage area 601, the first peripheral area 602, and the second storage area 603 are located on the same side of the two opposite sides of the second peripheral area 604 along the X-axis.

[0085] Figure 9 This is a second schematic diagram showing the regional distribution of the second semiconductor structure 502 provided in this embodiment. It should be noted that, in order to more clearly illustrate the relationship between the first memory region 601, the second memory region 603, the first peripheral region 602, and the second peripheral region 604 and the second semiconductor structure 502, Figure 9 Only the second semiconductor structure 502 is shown, and the first semiconductor structure is not shown.

[0086] like Figure 9 As shown, portions of the second semiconductor structure 502 in the first storage region 601 and the second storage region 603 include a first circuit region 605 and a second circuit region 607. Multiple first circuit regions 605 in the first storage region 601 are arranged along the X-axis, and multiple first circuit regions 605 in the second storage region 603 are also arranged along the X-axis. Each memory cell corresponds to one first circuit region 605. For example, as... Figure 9As shown, the second semiconductor structure 502 includes 16 first circuit regions 605, and the memory cell array 503 includes 16 memory banks Bank0-Bank15. Each memory bank in Bank0-Bank15 corresponds to one first circuit region 605, and each memory bank includes multiple memory blocks. It should be noted that... Figure 9 The number of first circuit regions 605 is for illustrative purposes only and is not intended to limit the number of first circuit regions 605 in the second semiconductor structure 502 in the embodiments of this disclosure.

[0087] In some embodiments, the voltage regulation circuit 701 is located in the second peripheral region 604.

[0088] like Figure 9 As shown, the second circuit region 607 is located between adjacent first circuit regions 605 along the X-axis. Control circuits for each memory block of the corresponding memory bank can be set in the first circuit region 605, such as sensing amplification circuits and word line driving circuits; control circuits for the corresponding memory banks can be set in the second circuit region 607, such as row decoding circuits. Control circuits for the corresponding memory banks can be set in the second semiconductor structure 502 in the first peripheral region 602, such as column decoding circuits. The second semiconductor structure 502 in the first peripheral region 602 can also contain a portion of the control circuits for all memory banks, such as a part of a command buffer, command decoder, address buffer, data input / output buffer, mode register, etc. The voltage regulation circuit of the charge pump circuit can be set in the second semiconductor structure 502 in the second peripheral region 604. The second semiconductor structure 502 in the second peripheral region 604 can also contain another portion of the control circuits for all memory banks, such as another portion of a command buffer, command decoder, address buffer, data input / output buffer, mode register, etc.

[0089] In this embodiment of the disclosure, when the first capacitor structure 504 is located in the second peripheral region 604, the voltage regulation circuit is also located in the second peripheral region 604. That is to say, the first capacitor structure 504 and the voltage regulation circuit are located in the same area, which makes the first capacitor structure 504 and the voltage regulation circuit closer together, and can shorten the connection between the first capacitor structure 504 and the voltage regulation circuit.

[0090] The dynamic random access memory (DRAM) in this embodiment may include at least one charge pump circuit. Each charge pump circuit includes a voltage regulation circuit and a correspondingly connected capacitor circuit, the capacitor circuit including at least one first capacitor structure. The voltage regulation circuit and the first capacitor structure in the same charge pump circuit are located in the same region. For example, the voltage regulation circuit and the first capacitor structure in the same charge pump circuit may both be located in a first peripheral region, or the voltage regulation circuit and the first capacitor structure in the same charge pump circuit may both be located in a second peripheral region. Different charge pump circuits may be located in different regions or in the same region. For example, multiple charge pump circuits may all be located in the first peripheral region, or multiple charge pump circuits may all be located in the second peripheral region, or a portion of the multiple charge pump circuits may be located in the first peripheral region, and another portion of the multiple charge pump circuits may be located in the second peripheral region.

[0091] In some embodiments, the voltage regulation circuit and the first capacitor structure 504 at least partially overlap in a view perpendicular to the first direction.

[0092] Here, when the first direction is the Z-axis direction in the accompanying drawings of this disclosure, the view perpendicular to the first direction can be understood as a view on the XY plane. Furthermore, when the first direction is vertical, the view perpendicular to the first direction can be understood as a top view.

[0093] In this embodiment of the disclosure, the voltage regulation circuit and the first capacitor structure 504 at least partially overlap in a view perpendicular to the first direction, thereby further reducing the distance between the voltage regulation circuit and the first capacitor structure 504, which can further shorten the connection between the first capacitor structure 504 and the voltage regulation circuit 701.

[0094] In some embodiments, the memory cell array 503 includes a plurality of memory cells, each memory cell including a transistor structure and a second capacitor structure, wherein the first capacitor structure 504 has the same structure as the second capacitor structure.

[0095] In this embodiment, the memory cell includes a transistor structure and a second capacitor structure. The second capacitor structure is connected to the transistor structure and serves as the storage capacitor for the memory cell. The first capacitor structure 504 has the same structure as the second capacitor structure, but it is not used as the storage capacitor for the memory cell; instead, it serves as the capacitor for a charge pump circuit. The first capacitor structure 504 is not connected to the transistor structure but is connected to the voltage regulation circuit of the charge pump circuit through a corresponding connection structure. During the formation of the dynamic random access memory, the first capacitor structure 504 and the second capacitor structure can be formed simultaneously, saving process time and reducing process costs.

[0096] In some embodiments, both the first capacitor structure 504 and the second capacitor structure include a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. The dielectric layer is made of a high-dielectric-constant (High-K) material; for example, the material may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The first electrode may be made of a conductive material; for example, it may be titanium nitride. The second electrode may be made of a conductive material; for example, it may be titanium nitride or silicon germanide.

[0097] Figure 10 A schematic diagram showing the relationship between the equivalent circuit of a charge pump circuit provided in this embodiment of the present disclosure and the first semiconductor structure 501 and the second semiconductor structure 502; Figure 11 This is an equivalent circuit diagram of a charge pump circuit provided in an embodiment of the present disclosure.

[0098] In some embodiments, such as Figure 10 as well as Figure 11 As shown, the charge pump circuit includes a voltage regulation circuit 701 and a capacitor circuit 702; the voltage regulation circuit 701 includes multiple voltage regulation sub-circuits 703, and the capacitor circuit 702 includes multiple capacitor sub-circuits 704.

[0099] In some embodiments, the capacitor sub-circuit 704 and the corresponding connected voltage regulation sub-circuit 703 at least partially overlap in a view perpendicular to the first direction.

[0100] In this embodiment of the disclosure, such as Figure 10 As shown, the voltage regulation circuit 701 is located in the second semiconductor structure 502, and the capacitor circuit 702 is located in the first semiconductor structure 501. The capacitor circuit 702 is used to store and transfer charge, and the voltage of the capacitor circuit 702 can be adjusted by the voltage regulation circuit 701.

[0101] In this embodiment of the disclosure, the capacitor sub-circuit 704 and the corresponding connected voltage regulation sub-circuit 703 overlap at least partially in a view perpendicular to the first direction, such that the connection between the capacitor sub-circuit 704 and the corresponding connected voltage regulation sub-circuit 703 can be set to be shorter, thereby further shortening the connection between the first capacitor structure 504 and the voltage regulation circuit 701.

[0102] In some embodiments, such as Figure 11 As shown, the voltage regulation circuit 701 includes N voltage regulation sub-circuits 703; the N voltage regulation sub-circuits 703 are connected in series, the input terminal of the first voltage regulation sub-circuit 703 is connected to the voltage input terminal, and the output terminal of the Nth voltage regulation sub-circuit 703 is connected to the voltage output terminal; N is an integer greater than 1.

[0103] In this embodiment of the disclosure, the number N of voltage regulation sub-circuits 703 can be selected according to the voltage requirements, and this embodiment of the disclosure does not limit this.

[0104] In some embodiments, the voltage regulation sub-circuit 703 includes a diode.

[0105] In some embodiments, the voltage regulation sub-circuit 703 can control the charging and discharging process of the capacitor circuit 702, thereby achieving voltage regulation. In addition to the diodes described in the above embodiments, the voltage regulation sub-circuit in this disclosure can also be a metal-oxide-semiconductor field-effect transistor, a complementary metal-oxide-semiconductor device, a charge transfer switch, or a bipolar transistor.

[0106] In some embodiments, the capacitor circuit 702 includes (N-1) capacitor sub-circuits 704, and each capacitor sub-circuit 704 includes at least one first capacitor structure 504; such as Figure 11 As shown, the first terminal of each of the (N-1) capacitor sub-circuits 704 is connected to the output terminal of each of the previous (N-1) voltage regulation sub-circuits 703 in a one-to-one correspondence.

[0107] In some embodiments, such as Figure 11 As shown, the second terminal of the (N-1) capacitor sub-circuits 704 with odd numbers is connected to the first clock signal terminal, and the second terminal of the (N-1) capacitor sub-circuits 704 with even numbers is connected to the second clock signal terminal; the first clock signal Vclk1 provided by the first clock signal terminal and the second clock signal Vclk2 provided by the second clock signal terminal are complementary clock signals.

[0108] Figure 10 as well as Figure 11 The circuit shown is a Dickson charge pump circuit. The Dickson charge pump circuit gradually increases the voltage by periodically changing the connection of the capacitor. It mainly uses a clock signal to drive the capacitor to switch between different voltage states, thereby achieving voltage accumulation. Figure 10 and Figure 11 The Dickson charge pump circuit shown is an (N-1) stage Dickson charge pump circuit, with each stage including a voltage regulator sub-circuit 703 and a capacitor sub-circuit 704. The input voltage is progressively increased through the combination of the voltage regulator sub-circuit 703 and the capacitor sub-circuit 704. The capacitor sub-circuit can be used to store charge and transfer charge between different stages of the circuit. C1, C3, etc. are capacitor sub-circuits with odd numbers, and C2, C4, etc. are capacitor sub-circuits with even numbers. Among them, C1 is the capacitor sub-circuit of the first stage, C... N-1This is the final stage of the capacitor circuit. The voltage regulation sub-circuit controls the charging and discharging process of the capacitor circuit. The voltage regulation sub-circuit can be controlled by a first clock signal and its inverse second clock control signal. Within each clock cycle, the capacitor circuit alternately charges and discharges under the control of the first and second clock signals. The charge in the capacitor circuit is transferred between different stages, gradually increasing the voltage. Finally, the charge is transferred to the output capacitor, forming a stable high-voltage output.

[0109] Figure 12 This is a schematic diagram of the equivalent circuit of a Dickson charge pump circuit when N is 3. Figure 12 As shown, when N is 3, this Dickson charge pump circuit is a two-stage Dickson charge pump circuit, including two intermediate nodes X and Y. Figure 12 As shown, Vin is the input voltage, which can be VDD for example; Vout is the output voltage; Vclk1 is the first clock signal; Vclk2 is the second clock signal, and Vclk1 and Vclk2 are opposite clock signals with amplitudes ranging from 0 to VDD for example. When the load current Iload is 0, the output voltage of the three-stage charge pump circuit can be calculated using the following formula (I), where VDD is the amplitude of the clock signal, and Vt is the threshold voltage of the diode or MOSFET.

[0110] Vout=2*VDD+Vin-3*Vt (I)

[0111] The following is combined with Figure 12 The charging and discharging process of the two-stage Dickson charge pump circuit is further described. During the first clock cycle, Vclk1 is high and Vclk2 is low. In the first stage:

[0112] When Vclk1 is high, M1 is on. The input voltage Vin charges C1 until its voltage reaches Vin. At this time, Vclk1 = Vin. Second stage: Vclk2 is low, M2 is not on. The charge on C1 remains unchanged. At this time, Vclk2 = Vin (from C1).

[0113] During the second clock cycle, Vclk1 is low and Vclk2 is high. First stage: Vclk1 is low, M1 is not conducting. The charge on C1 remains unchanged. At this time, Vclk1 = Vin. Second stage: When Vclk2 is high, M2 conducts. C2 is charged from C1 through M1, reaching a voltage of 2Vin. At this time, Vclk2 = 2Vin (from C2).

[0114] During the third clock cycle, Vclk1 is high and Vclk2 is low. First stage: When Vclk1 is high, M1 is on. C1 is charged again from the input voltage Vin, but since the voltage across C2 is already 2Vin, the voltage across C1 is now charged to 2Vin. At this time, Vclk1 = 2Vin. Second stage: Vclk2 is low, and M2 is not on. The charge on C2 remains unchanged. At this time, Vclk2 = 2Vin (from C2).

[0115] During the fourth clock cycle, Vclk1 is low and Vclk2 is high. First stage: Vclk1 is low, M1 is not conducting. The charge on C1 remains unchanged. At this time, Vclk1 = 2Vin. Second stage: When Vclk2 is high, M2 conducts. C2 is charged from C1 through M1, reaching a voltage of 3Vin. At this time, Vclk2 = 3Vin (from C2).

[0116] At the end of each cycle, the output voltage Vout is theoretically C. N-1 The voltage on the circuit, that is, in a two-stage Dickson charge pump, Vout = 3Vin (minus the voltage drop of the voltage regulation circuit).

[0117] In some embodiments, such as Figure 12 As shown, the charge pump circuit also includes a load capacitor Cload. The load capacitor Cload is responsible for providing a relatively stable output voltage at the output of the charge pump circuit, ensuring that the load device can obtain the required voltage level. Furthermore, the load capacitor helps reduce voltage fluctuations caused by the charging and discharging operations during the operation of the charge pump circuit, thereby reducing the output voltage ripple.

[0118] In some embodiments, the load circuit includes at least one first capacitor structure.

[0119] Extending to the (N-1) stage Dickson charge pump circuit, when the load current Iload is 0, the output voltage of the charge pump circuit can be calculated using the following formula (II), where VDD is the amplitude of the clock signal and Vt is the threshold voltage of the voltage regulation sub-circuit. Considering the parasitic capacitance of the nodes, the actual amplitude voltage VDD' that the clock signal amplitude VDD can obtain at the node after passing through the capacitor can be expressed by the following formula (III). The internal resistance of the Dickson charge pump circuit can be expressed by the following formula (IV), where Rs is the internal resistance of the charge pump circuit, Cs is the parasitic capacitance at intermediate nodes X / Y, etc., and theoretically, the Cs values ​​at these nodes are equal, and f is the frequency of the clock signal. Therefore, if there is a load current Iload at the output, and considering the parasitic capacitance of the intermediate nodes, the output voltage of the (N-1) stage Dickson charge pump can be expressed by the following formula (V), where the last term includes the load current Iload and the frequency f, which is actually the product of the internal resistance Rs of the charge pump circuit and the load current Iload. Thus, the expression for the output voltage of the (N-1) stage Dickson charge pump is given, which is a steady-state voltage. The actual output voltage is a fluctuating voltage, and a small ripple is achieved thanks to the large load capacitance. The output voltage ripple VR can be expressed by the following formula (VI). When the number of charge pump stages, load current, and load capacitance are fixed, f can be adjusted to improve its performance.

[0120] Vout=(N-1)*VDD+Vin-N*Vt (II)

[0121]

[0122] In some embodiments, such as Figure 10 As shown, the capacitor sub-circuit 704 includes M first capacitor structures 504 connected in parallel; M is an integer greater than or equal to 2.

[0123] In some embodiments, M equals 2.

[0124] In this embodiment of the disclosure, the number of first capacitor structures in the capacitor sub-circuit is not limited to the two mentioned in the above embodiments. The number of first capacitor structures in this embodiment of the disclosure can be set according to the current capability required by the charge pump circuit. The more first capacitor structures in the capacitor sub-circuit, the greater the current capability that the charge pump circuit can provide.

[0125] In this embodiment of the disclosure, the capacitor circuit 702 includes at least one capacitor sub-circuit 704. The number of first capacitor structures 504 in different capacitor sub-circuits 704 may be the same or different. The connection method between the first capacitor structures 504 in different capacitor sub-circuits 704 may be the same or different. This embodiment of the disclosure does not limit this.

[0126] In this embodiment of the disclosure, the first semiconductor structure 501 and the second semiconductor structure 502 are stacked along a first direction, thereby saving the area occupied by the dynamic random access memory. The first semiconductor structure 501 and the second semiconductor structure 502 can be formed on the same wafer, or they can be formed on different wafers and then connected by bonding. The bonding method includes hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technology, such as forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive, and can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. It should be noted that the "bonding" referred to in this embodiment of the disclosure can be any suitable bonding technology, such as the hybrid bonding mentioned above, or, for example, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding. The following is an exemplary description using hybrid bonding as an example.

[0127] In some embodiments, such as Figure 13 as well as Figure 14 As shown, the first semiconductor structure 501 further includes a first bonding layer 801, which includes a first bonding structure 802; the first bonding layer 801 is located between the memory cell array 503 and the second semiconductor structure 502, and between the first capacitor structure 504 and the second semiconductor structure 502; the second semiconductor structure 502 further includes a second bonding layer 803, which includes a second bonding structure 804; the second bonding layer 803 is located between the peripheral circuit 505 and the first semiconductor structure 501.

[0128] In this embodiment of the present disclosure, the first semiconductor structure 501 and the second semiconductor structure 502 are bonded together through a first bonding layer 801 and a second bonding layer 803. In some embodiments, the first bonding layer 801 further includes a first dielectric layer, the first bonding structure 802 is located in the first dielectric layer, the second bonding layer 803 further includes a second dielectric layer, and the second bonding structure 804 is located in the second dielectric layer. The materials of the first dielectric layer and the second dielectric layer include, but are not limited to, silicon oxide and silicon nitride. The materials of the first bonding structure 802 and the second bonding structure 804 include at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0129] In some embodiments, such as Figure 13 as well as Figure 14As shown, the first semiconductor structure 501 further includes a first interconnect layer 805, which is located between the first capacitor structure 504 and the first bonding layer 801, and includes a first interconnect structure 807; the second semiconductor structure 502 further includes a second interconnect layer 806, which is located between the voltage regulation circuit 701 and the second bonding layer 803, and includes a second interconnect structure 808.

[0130] In this embodiment of the disclosure, such as Figure 13 As shown, the first interconnect layer 805 is located between the memory cell array 503 and the first bonding layer 801, and between the first capacitor structure 504 and the first bonding layer 801; the second interconnect layer 806 is located between the peripheral circuit 505 and the second bonding layer 803.

[0131] In some embodiments, the first interconnect structure 807 and the second interconnect structure 808 include, for example, conductive lines extending in a direction perpendicular to a first direction and contact structures extending in the first direction. The first interconnect structure 807 and the second interconnect structure 808 may be formed in one or more interlayer dielectric (ILD) layers. The materials of the first interconnect structure 807 and the second interconnect structure 808 may include conductive materials. The ILD layers in the first interconnect layer 805 and the second interconnect layer 806 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0132] In some embodiments, such as Figure 13 as well as Figure 14 As shown, the first semiconductor structure 501 further includes a first interconnect structure 807, which is located between the first capacitor structure 504 and the first bonding layer 801; the second semiconductor structure 502 further includes a second interconnect structure 808, which is located between the voltage regulation circuit 701 and the second bonding layer 803; the first capacitor structure 504 is connected to the voltage regulation circuit 701 through the first interconnect structure 807, the first bonding structure 802, the second bonding structure 804, and the second interconnect structure 808.

[0133] In this embodiment of the disclosure, the first capacitor structure 504 is not connected to the transistor structure, the first capacitor structure 504 is connected to the first interconnect structure 807, and the first capacitor structure 504 located in the first semiconductor structure 501 is connected to the voltage regulation circuit 701 of the charge pump circuit located in the second semiconductor structure 502 through the first interconnect structure 807, the first bonding structure 802, the second bonding structure 804 and the second interconnect structure 808.

[0134] Based on the above-described dynamic random access memory, this disclosure also provides a memory system, which includes a memory controller and a dynamic random access memory as described in any of the above embodiments; the memory controller is coupled to the dynamic random access memory and configured to control the dynamic random access memory.

[0135] The memory system described above can be referenced here. Figure 1A , Figure 1B , Figure 2A , Figure 2B And the corresponding introduction, for the sake of brevity, will not be repeated here.

[0136] Based on the above-described dynamic random access memory, this disclosure also provides a method for forming a dynamic random access memory. Figure 15 This is a flowchart illustrating a method for forming a dynamic random access memory (DRAM) according to an embodiment of this disclosure. Figure 15 As shown, the method for forming a dynamic random access memory includes the following steps: Step S10: forming a first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein, the first semiconductor structure includes a memory cell array and a first capacitor structure, the first capacitor structure being used as a capacitor for a charge pump circuit; the second semiconductor structure includes peripheral circuitry, the peripheral circuitry including a voltage regulation circuit for the charge pump circuit.

[0137] In this embodiment of the disclosure, the first semiconductor structure and the second semiconductor structure can be formed on the same wafer or on different wafers, and this embodiment of the disclosure does not limit this.

[0138] In some embodiments, forming a first semiconductor structure and a second semiconductor structure stacked along a first direction includes forming a first capacitor structure while forming a second capacitor structure of a memory cell array.

[0139] In this embodiment of the present disclosure, the first capacitor structure is formed simultaneously with the second capacitor structure of the memory cell, which saves process time and reduces process cost.

[0140] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0141] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0142] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A dynamic random access memory, characterized in that, include: A first semiconductor structure and a second semiconductor structure stacked along a first direction; wherein, The first semiconductor structure includes a memory cell array and a first capacitor structure, the first capacitor structure being used as a capacitor for a charge pump circuit; the second semiconductor structure includes peripheral circuitry, the peripheral circuitry including a voltage regulation circuit for the charge pump circuit.

2. The dynamic random access memory according to claim 1, characterized in that, The dynamic random access memory includes a first storage area, a first peripheral area, and a second storage area arranged along a second direction, with the first peripheral area located between the first storage area and the second storage area; the memory cell array is located in the first storage area and the second storage area. The second direction is perpendicular to the first direction.

3. The dynamic random access memory according to claim 2, characterized in that, The first capacitor structure is located in the first peripheral region.

4. The dynamic random access memory according to claim 3, characterized in that, The voltage regulation circuit is located in the first peripheral area.

5. The dynamic random access memory according to claim 2, characterized in that, The dynamic random access memory further includes a second peripheral region; the first storage region, the first peripheral region, and the second storage region are located on the same side of two opposite sides of the second peripheral region along a third direction; the first capacitor structure is located in the second peripheral region; the third direction is perpendicular to both the first direction and the second direction.

6. The dynamic random access memory according to claim 5, characterized in that, The voltage regulation circuit is located in the second peripheral area.

7. The dynamic random access memory according to claim 1, characterized in that, The voltage regulation circuit and the first capacitor structure at least partially overlap in a view perpendicular to the first direction.

8. The dynamic random access memory according to claim 1, characterized in that, The memory cell array includes multiple memory cells, each memory cell including a transistor structure and a second capacitor structure, wherein the first capacitor structure and the second capacitor structure have the same structure.

9. The dynamic random access memory according to claim 1, characterized in that, The charge pump circuit includes the voltage regulation circuit and the capacitor circuit; the voltage regulation circuit includes multiple voltage regulation sub-circuits, and the capacitor circuit includes multiple capacitor sub-circuits; the capacitor sub-circuits and the corresponding connected voltage regulation sub-circuits at least partially overlap in a view perpendicular to the first direction.

10. The dynamic random access memory according to claim 9, characterized in that, The voltage regulation circuit includes N voltage regulation sub-circuits; the N voltage regulation sub-circuits are connected in series, the input terminal of the first voltage regulation sub-circuit is connected to the voltage input terminal, and the output terminal of the Nth voltage regulation sub-circuit is connected to the voltage output terminal; N is an integer greater than 1.

11. The dynamic random access memory according to claim 10, characterized in that, The voltage regulation sub-circuit includes diodes.

12. The dynamic random access memory according to claim 10, characterized in that, The capacitor circuit includes (N-1) capacitor sub-circuits, each capacitor sub-circuit including at least one of the first capacitor structures; the first terminal of each of the (N-1) capacitor sub-circuits is connected to the output terminal of each of the previous (N-1) voltage regulation sub-circuits in a one-to-one correspondence.

13. The dynamic random access memory according to claim 12, characterized in that, The second terminal of the capacitor sub-circuit with an odd number in the (N-1) capacitor sub-circuit is connected to the first clock signal terminal, and the second terminal of the capacitor sub-circuit with an even number in the (N-1) capacitor sub-circuit is connected to the second clock signal terminal; the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal are complementary clock signals.

14. The dynamic random access memory according to claim 12, characterized in that, The capacitor sub-circuit includes M first capacitor structures connected in parallel; M is an integer greater than or equal to 2.

15. The dynamic random access memory according to claim 14, characterized in that, The value of M is 2.

16. The dynamic random access memory according to claim 1, characterized in that, The first semiconductor structure further includes a first bonding layer, which includes a first bonding structure; the first bonding layer is located between the memory cell array and the second semiconductor structure, and between the first capacitor structure and the second semiconductor structure; The second semiconductor structure further includes a second bonding layer, which includes a second bonding structure; the second bonding layer is located between the peripheral circuit and the first semiconductor structure.

17. The dynamic random access memory according to claim 16, characterized in that, The first semiconductor structure further includes a first interconnect structure located between the first capacitor structure and the first bonding layer; the second semiconductor structure further includes a second interconnect structure located between the voltage regulation circuit and the second bonding layer; the first capacitor structure is connected to the voltage regulation circuit through the first interconnect structure, the first bonding structure, the second bonding structure, and the second interconnect structure.

18. A memory system, characterized in that, The memory system includes a memory controller and a dynamic random access memory as described in any one of claims 1-17; the memory controller is coupled to the dynamic random access memory and configured to control the dynamic random access memory.

19. A method for forming a dynamic random access memory, characterized in that, include: A first semiconductor structure and a second semiconductor structure are formed and stacked along a first direction; wherein the first semiconductor structure includes a memory cell array and a first capacitor structure, the first capacitor structure being used as a capacitor for a charge pump circuit; the second semiconductor structure includes peripheral circuitry, the peripheral circuitry including a voltage regulation circuit for the charge pump circuit.

20. The forming method according to claim 19, characterized in that, The formation of the first semiconductor structure and the second semiconductor structure stacked along the first direction includes: forming the first capacitor structure while forming the second capacitor structure of the memory cells of the memory cell array.

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