Memory cell having three terminals and semiconductor memory device including the same

Abstract

The present application relates to a memory cell having three terminals and a semiconductor memory device including the same. The memory cell of the semiconductor memory device can be connected between a write word line, a read word line, and a bit line. The memory cell can include a write transistor, a diode, and a read transistor. The write transistor can be connected between the write word line and the bit line. The diode can include an anode and a cathode. The anode of the diode can be connected with the write transistor. The read transistor can be connected between the read word line and the bit line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2025-0055313, filed on April 28, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure generally relate to electronic devices, and more specifically, to a memory cell having three terminals (three terminals) and a semiconductor memory device including the memory cell. Background Technology

[0004] Dynamic Random Access Memory (DRAM) devices are typical semiconductor memory devices that consist of multiple memory cells. Traditionally, each memory cell may include a transistor as a switch and a capacitor as a storage element. Currently, to improve the performance of DRAM devices, new methods are needed to integrate more memory cells within a limited area and to manufacture larger capacity capacitors within a limited area.

[0005] For example, recently, in order to reduce the area of ​​memory cells, some people have been actively trying to reduce the size of capacitors, or to omit capacitors entirely to create capacitor-free memory cells. These efforts are still in their early stages and require further improvement. Summary of the Invention

[0006] Embodiments of this disclosure provide a storage cell with three terminals (hereinafter also referred to as a three-terminal storage cell) that can improve storage characteristics.

[0007] Embodiments of this disclosure also provide a semiconductor memory device including the three-terminal memory cell.

[0008] According to embodiments of this disclosure, a three-terminal memory cell may be provided, including a write transistor, a diode, and a read transistor. The write transistor may be connected between a write word line and a bit line. The diode may include an anode connected to the write transistor. The read transistor may be connected between the cathode of the diode, the write word line, and the bit line. The gate of the read transistor is connected to the diode.

[0009] According to embodiments of this disclosure, a semiconductor memory device is provided. The semiconductor memory device may include a plurality of write word lines, a plurality of read word lines, a plurality of bit lines, and a plurality of memory cells. The plurality of word lines may extend parallel to a first direction. The plurality of read word lines may extend parallel to a second direction intersecting the first direction. The plurality of bit lines may extend parallel to the second direction. The plurality of bit lines may be arranged alternately with the plurality of read word lines. The plurality of memory cells may be connected to the plurality of write word lines, the plurality of read word lines, and the plurality of bit lines. Each memory cell may include a write transistor, a diode, and a bit line transistor. The write transistor may be connected to one of the plurality of write word lines and one of the plurality of bit lines. The diode may include an anode connected to the write transistor. The read transistor may be connected to the cathode of the diode, one of the plurality of read word lines, and the bit line to which the write transistor is connected.

[0010] According to embodiments of the present disclosure, the write transistor can be configured to transmit the write voltage applied to the bit line as data to the anode of the diode in response to an enable signal on the write word line.

[0011] According to embodiments of this disclosure, the read transistor can be configured to transmit an enable signal for the read word line to the bit line based on data received from the diode.

[0012] According to embodiments of this disclosure, a diode can be configured to conduct when the voltage level of the anode is greater than the voltage level of the cathode and the difference between the voltage levels of the anode and the cathode is not less than the threshold voltage of the diode.

[0013] According to embodiments of this disclosure, the diode may include at least one of a Schottky barrier diode and a PN diode.

[0014] According to exemplary embodiments of the present disclosure, a three-terminal memory cell can be provided. The memory cell having three terminals may include an active region, a write transistor and a read transistor, a write word line, a bit line, a diode, a read word line, and interconnect wiring. The write transistor and the read transistor may be integrated in the active region. The write word line may be electrically connected to the gate of the write transistor. The bit line may be connected to the source of the write transistor and the source of the read transistor. The diode may be located above the gate of the write transistor. The diode may be electrically connected to the gate of the write transistor. The write word line may be connected to the drain of the write transistor. Interconnect wiring may be connected between the diode and the drain of the write transistor. The anode of the diode may be connected to the drain of the write transistor, and the cathode of the diode may be connected to the gate of the read transistor.

[0015] According to embodiments of this disclosure, the active region may have a strip shape having a short axis extending along a first direction and a long axis extending along a second direction perpendicular to the first direction. The gate of the write transistor and the gate of the read transistor may extend parallel to each other along the second direction on the active region. The source of the write transistor and the source of the read transistor may together include a first junction region formed in the active region between the gate of the write transistor and the gate of the read transistor. The drain of the write transistor may include a second junction region formed in the active region outside the gate of the write transistor. The drain of the read transistor may include a third junction region formed in the active region outside the gate of the read transistor.

[0016] According to embodiments of this disclosure, the diode may be located above the gate of a readout transistor that overlaps with the active region. Interconnect wiring may extend to overlap with the active region.

[0017] According to embodiments of this disclosure, the diode may be located above the gate of the readout transistor extending outward from the active region. Interconnect wiring may bypass the active region and extend along the periphery of the active region.

[0018] According to embodiments of this disclosure, the active region may include: a first active region in which a write transistor may be integrated; and a second active region disposed opposite to the first active region at a set spacing, in which a read transistor may be integrated.

[0019] According to embodiments of the present disclosure, the gate of the write transistor may be disposed at the center of the first active region; the source of the write transistor may be located in the first active region on one side of the gate of the write transistor; and the drain of the write transistor may be located in the first active region on the other side of the gate of the write transistor.

[0020] According to embodiments of this disclosure, the gate of the read transistor may be disposed at the center of the second active region and extend a certain length into the first active region. The source of the read transistor may be disposed in the second active region on one side of the gate of the read transistor. The drain of the read transistor may be disposed in the second active region on the other side of the gate of the read transistor.

[0021] According to embodiments of this disclosure, the diode may be located at the end of the gate of the read transistor, and a portion of the interconnect wiring may be located between the first active region and the second active region.

[0022] According to embodiments of this disclosure, the memory cell may be connected to a write word line, a read word line, and a common bit line. The memory cell may include a write transistor connected to the write word line and the common bit line, a read transistor connected to the read word line and the common bit line, and a diode connected between the write transistor and the read transistor.

[0023] Therefore, even if the write transistor and read transistor are connected to a common bit line, the forward drive of the diode can prevent data loss and fluctuation in unselected memory cells, thereby reducing the area of ​​the memory cells while maintaining stable memory characteristics. Attached Figure Description

[0024] The above and other aspects, features and advantages of embodiments of the present disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 This is a circuit diagram showing a three-terminal memory cell according to an embodiment of the present disclosure;

[0026] Figure 2 This is a timing diagram illustrating the operation of a three-terminal memory cell according to an embodiment of the present disclosure;

[0027] Figure 3 This is a circuit diagram illustrating a semiconductor memory device including a memory cell having three terminals according to an embodiment of the present disclosure;

[0028] Figure 4 This is a plan view showing a three-terminal storage cell according to an embodiment of the present disclosure;

[0029] Figure 5 It is along Figure 4 A cross-sectional view taken from line A-A'.

[0030] Figure 6 This is a plan view showing a three-terminal storage cell according to an embodiment of the present disclosure; and

[0031] Figure 7A and Figure 7B This is a plan view showing a three-terminal storage cell according to an embodiment of the present disclosure. Detailed Implementation

[0032] The advantages and features of the embodiments of this disclosure, as well as methods for implementing them, will become apparent from the detailed description of the embodiments with reference to the accompanying drawings. However, the embodiments are not limited to those disclosed herein, but may be embodied in many different forms. These embodiments are provided only to complete the disclosure and to enable those skilled in the art to fully understand the scope of the embodiments as defined by the claims. For clarity, the dimensions and relative sizes of the layers and regions in the drawings may be exaggerated. Throughout the specification, the same reference numerals denote the same components.

[0033] As used herein, the term “configuration” may refer to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structure and device in a predetermined manner.

[0034] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of a structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is one that is substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is one that is substantially perpendicular to the principal plane of the structure. The principal plane of a structure is defined by the surface of the structure with the largest area relative to other surfaces. Referring to the accompanying drawings, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis, or parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, or perpendicular to the indicated “X” axis, or perpendicular to the indicated “Y” axis.

[0035] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” “right,” etc., are used to conveniently describe the relationship between one element or feature and another, as illustrated in the figures. Unless otherwise stated, these spatial relative terms are intended to cover different orientations of material other than those shown in the figures. For example, if the material orientation in the figures were reversed, an element described as “below,” “under,” “below,” or “bottom” of another element or feature would be “above” or “top” of that other element or feature. Thus, the term “below” can encompass both “above” and “below” orientations, depending on the context of the term, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.), and the spatial relative descriptors used herein will be interpreted accordingly.

[0036] As used in this article, “and / or” includes any and all combinations of one or more of the related listed items.

[0037] Figure 1 This is a circuit diagram illustrating a three-terminal storage cell according to an embodiment of the present disclosure.

[0038] refer to Figure 1 According to some embodiments, the memory cell MC may have a three-terminal structure connected between the write word line WWL, the read word line RWL, and the bit line BL.

[0039] For example, the write word line WWL can extend along a first direction DR1. The read word line RWL and the bit line BL can extend parallel to each other. The read word line RWL and the bit line BL can extend along a second direction DR2, which is perpendicular to the first direction DR1.

[0040] A three-terminal memory cell MC may include a write transistor WT, a read transistor RT, and a diode D.

[0041] The write transistor WT may include, for example, an NMOS transistor. The gate of the write transistor WT may be connected to the write word line WWL, the source of the write transistor WT may be connected to the bit line BL, and the write transistor WT may be connected to a diode D.

[0042] The read transistor RT may include, for example, an NMOS transistor. The gate of the read transistor RT may be connected to a diode D, the source of the read transistor RT may be connected to the read word line RWL, and the drain of the read transistor RT may be connected to the bit line BL.

[0043] According to embodiments of this disclosure, the write transistor WT and the read transistor RT may include not only NMOS transistors but also PMOS transistors.

[0044] At least one of the channels of the write transistor WT and the read transistor RT may comprise a semiconductor material such as silicon (Si) or silicon germanium (SiGe), an oxide semiconductor material including at least one of IGZO, IGO, and In2O3, or a two-dimensional material. For example, the two-dimensional material may comprise at least one of MoS2, MoSe2, WS2, WSe2, WTe2, MoTe2, ZrS2, ZrSe2, GaSe, GaTe2, HfS2, HfSe2, SnSe, PtSe2, PdSe2, PdTe2, ReSe2, VS2, VSe2, NbSe2, FeSe2, and FeTe2.

[0045] According to embodiments of this disclosure, the channel of the write transistor WT and the channel of the read transistor RT may comprise the same material or different materials.

[0046] For a memory cell MC with a capacitorless structure, the bandgap of the channel material of the write transistor WT can be larger than that of the read transistor RT, thereby increasing data retention time. In some cases, in addition to adjusting the channel material, the transistor structure can be modified to give the read transistor RT a relatively higher on-state current than the write transistor WT. A wider bandgap in the write transistor channel can suppress leakage current and improve retention time, while a narrower bandgap or structural modification in the read transistor can improve carrier mobility, thereby achieving higher on-state current and faster read access.

[0047] Diode D may include, for example, a forward diode. The anode of diode D may be connected to a write transistor WT. The cathode of diode D may be connected to a read transistor RT. Therefore, diode D can conduct when the anode voltage is greater than the cathode voltage and the difference between the anode and cathode voltages is not less than the threshold voltage of diode D. In other words, diode D can conduct when the anode voltage exceeds the sum of the threshold voltage and the cathode voltage of diode D. Diode D may be at least one of a rectifier diode, a Schottky diode, and a PN diode.

[0048] Bit line BL can be connected to the drain of both the write transistor WT and the read transistor RT. According to some embodiments, the memory cell MC can transmit write voltage or read (sensor) written data via one of the bit lines.

[0049] The sensing amplifier S / A can be connected to one end of the bit line BL to sense data stored in a selected memory cell MC.

[0050] According to some embodiments, a three-terminal memory cell MC may not include a separate storage element such as a capacitor. According to some embodiments, the memory cell MC may use the gate of the read transistor RT as the storage medium. For example, when the memory cell MC is selected, a write voltage provided via bit line BL can be supplied to the gate of the read transistor RT to store data. Furthermore, according to some embodiments, a three-terminal memory cell MC may perform storage operations using only the write word line WWL, the read word line RWL, and the bit line BL. Therefore, compared to conventional capacitor-less memory cells, the number of bit lines can be reduced, thereby significantly improving the integration density of the memory device.

[0051] Figure 2 This is a timing diagram illustrating the operation of a three-terminal storage cell according to an embodiment of the present disclosure.

[0052] Write operation

[0053] refer to Figure 1 and Figure 2 When storing the data "1" in the memory cell MC, the write word line WWL can be enabled to the VPP voltage level, the bit line BL can be enabled to the VDD voltage level, and the read word line RWL can be disabled to the VSS voltage level. Then, the write transistor WT can be turned on, allowing the VDD voltage provided on the bit line BL to be transferred to the anode of the diode D.

[0054] When VDD voltage is applied to the anode of diode D, the voltage difference between the anode and cathode of diode D may become no less than the threshold voltage of diode D, causing diode D to conduct. The voltage difference between the anode and cathode of diode D may reach or exceed the threshold voltage of diode D, thus causing diode D to conduct. Therefore, VDD voltage can be applied to the gate of the read transistor RT corresponding to the memory node SN, thereby writing the data "1" into the memory node SN of the memory cell MC. By activating diode D with VDD voltage, and turning on the associated read transistor, the data "1" can be stored in the memory cell.

[0055] In another embodiment, in order to write the data "0" to the storage cell MC, the VSS voltage can be used to enable the selection line BL.

[0056] Although not shown, after data is written to the storage cell MC, during the hold period for performing subsequent operations, the level of the data stored in the storage node SN can be reduced to a predetermined voltage level.

[0057] Read operation

[0058] refer to Figure 1 and Figure 2 In order to read the data stored in the memory cell MC, the read word line RWL is enabled with a VDD voltage level.

[0059] To store the data "1" in the memory cell MC, the read transistor RT is turned on. Therefore, the VDD voltage transmitted on the read word line RWL can be transmitted to the bit line BL, allowing the sense amplifier S / A to sense the data "1" stored in the memory cell MC.

[0060] On the other hand, if the data "0" is to be stored in the memory cell MC, the read transistor RT can be turned off. Therefore, since no voltage is available to the bit line BL, the data "0" can be considered to be stored in the memory cell MC. The sense amplifier S / A can sense the data "0" stored in the memory cell MC.

[0061] Figure 3 This is a circuit diagram illustrating a semiconductor memory device including a memory cell having three terminals according to an embodiment of the present disclosure.

[0062] refer to Figure 3 The semiconductor memory device 10 may include a first write word line WWL1 and a second write word line WWL2, first to third read word lines RWL1, RWL2 and RWL3, first to third bit lines BL1, BL2 and BL3, and first to sixth memory cells MC1-MC6.

[0063] For example, the first write word line WWL1 and the second write word line WWL2 may extend parallel to each other along the first direction DR1. The first to third read word lines RWL1-RWL3 and the first to third bit lines BL1-BL3 may extend parallel to each other along a second direction perpendicular to the first direction DR1. The first to third read word lines RWL1-RWL3 and the first to third bit lines BL1-BL3 may be arranged alternately.

[0064] Each of the first to sixth memory cells MC1-MC6 can be connected between the first and second write word lines WWL1 and WWL2, the first to third read word lines RWL1, RWL2 and RWL3, and the first to third bit lines BL1, BL2 and BL3. The first to sixth memory cells MC1-MC6 can be arranged in a matrix.

[0065] According to embodiments of this disclosure, a first storage unit MC1 can be connected between a first write word line WWL1, a first read word line RWL1, and a first bit line BL1. A second storage unit MC2 can be connected between a first write word line WWL1, a second read word line RWL2, and a second bit line BL2. A third storage unit MC3 can be connected between a first write word line WWL1, a third read word line RWL3, and a third bit line BL3. A fourth storage unit MC4 can be connected between a second write word line WWL2, a first read word line RWL1, and a first bit line BL1. A fifth storage unit MC5 can be connected between a second write word line WWL2, a second read word line RWL2, and a second bit line BL2. A sixth storage unit MC6 can be connected between a second write word line WWL2, a third read word line RWL3, and a third bit line BL3.

[0066] Each of the first to sixth memory cells MC1-MC6 may include a write transistor WT, a read transistor RT, and a diode D.

[0067] The semiconductor memory device 10 having the above structure can be operated as follows.

[0068] When writing data "1" to the first memory cell MC1, a logic high voltage can be applied to the first write word line WWL1 to enable WWL1 and disable the second write word line WWL2. The write voltage corresponding to data "1" can be applied to the first bit line BL1. The remaining second and third bit lines BL2 and BL3 can be disabled. The first to third read word lines RWL1-RWL3 can also be disabled.

[0069] Since the first write word line WWL1 and the first bit line BL1 are enabled, the write transistor WT and diode D of the first memory cell MC1 can be turned on, thereby allowing the data "1" to be written to the gate of the read transistor RT.

[0070] Even if the first write word line WWL1 is enabled, the second bit line BL2 and the third bit line BL3 can be disabled, so the second memory cell MC2 and the third memory cell MC3 can be unselected.

[0071] According to some embodiments of this disclosure, if the data "1" is stored in the second storage cell MC2 before the first storage cell MC1 is selected, the diode D of the second storage cell MC2 can be turned off even if the first write word line WWL1 is enabled, because the diode D can have a forward diode structure. Therefore, the second storage cell MC2 can retain the previously written data.

[0072] Alternatively, if the data "0" is stored in the third memory cell MC3 before the first memory cell MC1 is selected, the diode D of the third memory cell MC3 will not be driven even if the first write word line WWL1 is enabled. Therefore, the third memory cell MC3 can retain previously written data; that is, even if the write transistor WT of the third memory cell MC3 is turned on, the anode and cathode of the diode D of the third memory cell MC3 can remain low because the third bit line BL3 is disabled. Therefore, the diode D of the third memory cell MC3 can be turned off.

[0073] Because the second write word line WWL2 is disabled, all fourth to sixth memory cells MC4-MC6 connected to the second write word line WWL2 are unselectable.

[0074] The read operation enables the read word line connected to the target memory cell, as described above. The read transistor RT of the target memory cell can be turned on based on the gate voltage level of the read transistor RT to transfer the stored data to the bit line.

[0075] Thus, each memory cell with three terminals can include a switch with a forward diode structure. The forward-biased switch can be connected between the write transistor and the read transistor to improve data retention when the memory cell is not selected and to prevent data fluctuations when an adjacent memory cell is selected. Furthermore, the memory cell with three terminals can be configured such that the write transistor and the read transistor can share a single bit line. Therefore, the number of bit lines connected to the memory cell can be reduced, thereby reducing the area of ​​the memory cell.

[0076] Figure 4 This is a plan view illustrating a three-terminal storage cell according to some embodiments of the present disclosure. Figure 5 It is along Figure 4 A cross-sectional view taken from line A-A'. Figure 6 This is a plan view illustrating a three-terminal storage cell according to some embodiments of the present disclosure.

[0077] refer to Figure 4 and Figure 5 A three-terminal memory cell MC can be integrated into a strip-shaped active region ACT. The active region ACT may have a short axis parallel to a first direction DR1 and a long axis parallel to a second direction DR2 perpendicular to the first direction DR1. For example, the active region ACT may be located on a semiconductor substrate 100. The active region ACT may be defined by a device isolation layer 110 formed in the semiconductor substrate 100. The semiconductor substrate 100 may include impurities of a first conductivity type, such as p-type impurities. A lower layer comprising an oxide semiconductor material or a 2D material may be used instead of the semiconductor substrate 100.

[0078] The gate 120a (hereinafter referred to as the write gate) of the write transistor WT and the gate 120b (hereinafter referred to as the read gate) of the read transistor RT can be respectively disposed on the active region ACT. The write gate 120a and the read gate 120b can be spaced apart by a predetermined distance. For example, the write gate 120a and the read gate 120b can each extend parallel to the first direction DR1. The write gate 120a can be a line drawn from a write word line (not shown). For convenience, the illustration of the write word line can be omitted, but it can be located above the write gate 120a. The read gate 120b can be a structure connected to the diode D and can be configured in a pattern form overlapping the active region ACT.

[0079] Gate insulating layers 115 may be formed between the write gate 120a and the semiconductor substrate 100, and between the read gate 120b and the semiconductor substrate 100, respectively. Gate insulating layer 115 may include, for example, a silicon oxide layer or a high-dielectric metal oxide layer. Gate spacers 125 may be formed on the sidewalls of each of the write gate 120a and the read gate 120b. Gate spacers 125 may include, but are not limited to, a silicon oxide layer.

[0080] The first to third junction regions 130a, 130b, and 130c can be formed in the active region ACT between the write gate 120a and the read gate 120b, in the active region ACT corresponding to the outer side of the write gate 120a, and in the active region ACT corresponding to the outer side of the read gate 120b. Therefore, the write transistor WT and the read transistor RT can be formed on the active region ACT.

[0081] The first to third junction regions 130a, 130b, and 130c may contain impurities of a second conductivity type opposite to the first conductivity type, such as n-type impurities. According to embodiments of this disclosure, the first junction region 130a may be the common source of the write transistor WT and the read transistor RT. The second junction region 130b may be the drain of the write transistor WT, and the third junction region 130c may be the drain of the read transistor RT.

[0082] A first insulating layer 140 may be formed on a semiconductor substrate 100 on which a write transistor WT and a read transistor RT are formed. First and second contacts 145a and 145b may be formed in the first insulating layer 140. For example, the first contact 145a may be electrically connected to a first junction region 130a. The second contact 145b may be electrically connected to a third junction region 130c corresponding to the drain of the read transistor RT.

[0083] A bit line (not shown) may be disposed on the first insulating layer 140 and contact the first contact 145a. A read word line (not shown) may be disposed on the first insulating layer 140 and contact the second contact 145b.

[0084] exist Figure 4 and Figure 5 In this context, the arrangement of bit lines and read word lines can be omitted; for example, they can be arranged along... Figure 4 The first direction DR1 extends. However, considering process technology, the arrangement and position of bit lines and word lines can be changed as needed.

[0085] A second insulating layer 150 may be formed on the first insulating layer 140 and the bit line. A third contact 155 may penetrate the second insulating layer 150 and the first insulating layer 140 to contact the read gate 120b.

[0086] Diode 160 may be formed on the second insulating layer 150 to contact the third contact 155. Diode 160 may be configured to include a semiconductor layer containing n-type impurities, for example, to form a Schottky diode. In another embodiment, diode 160 may be configured to include stacked semiconductor layers containing n-type impurities and semiconductor layers containing p-type impurities to form a pn diode. When diode 160 is a PN diode, the n-type semiconductor layer operating as a cathode may be directly or indirectly connected to the read gate 120b, and the p-type semiconductor layer operating as an anode may be directly or indirectly connected to the drain 130b of the write transistor WT, such that diode 160 can operate as a forward diode.

[0087] A third insulating layer 165 may be formed on the second insulating layer 150. A diode 160 may be formed in the third insulating layer 165. The third insulating layer 165 may be planarized to expose the upper surface of the diode 160. The lower end of the diode 160 may contact the third contact 155, and the upper end of the diode 160 may contact the interconnect wiring 175.

[0088] A fourth contact 170 may be formed in the third, second, and first insulating layers 165, 150, and 140. The fourth contact 170 may be formed through the third, second, and first insulating layers 165, 150, and 140 to be electrically connected to the second junction region 130b corresponding to the drain of the write transistor WT.

[0089] exist Figure 5 In this embodiment, the first to fourth contacts 145a, 145b, 155, and 170 may be shown as single contact plugs extending in a vertical direction, but the embodiment is not limited thereto. For example, the first to fourth contacts 145a, 145b, 155, and 170 may include multiple conductive layers, but are not limited thereto.

[0090] Interconnect wiring 175 may be located on the third insulating layer 165. Interconnect wiring 175 can electrically connect diode 160 to fourth contact 170. For example, interconnect wiring 175 can electrically connect diode 160 to the top surface of fourth contact 170, which is coplanar with the top surface of third insulating layer 165. Interconnect wiring 175 may be formed to overlap with active region ACT, such as... Figure 4 As shown. Furthermore, in Figure 4 In the attached figure, the reference numeral CT can indicate the contact between the write gate 120a and the write word line WWL.

[0091] In another embodiment, such as Figure 6 As shown, diode 161 can be located at the end of read gate 121b that extends outward from active region ACT. In order to connect diode 161 to the drain of write transistor WT (i.e., second junction region 130b), interconnect wiring 176 can bypass active region ACT and extend along the periphery of active region ACT.

[0092] Figure 7A and Figure 7B This is a plan view showing a three-terminal storage cell according to an embodiment of the present disclosure.

[0093] refer to Figure 7A A three-terminal memory cell MC can be integrated into a first active region ACT1 and a second active region ACT2. The first active region ACT1 can be the region where a write transistor WT is formed. The second active region ACT2 can be the region where a read transistor RT is formed. The first active region ACT1 and the second active region ACT2 can be arranged to face each other at a predetermined interval. For example, the first active region ACT1 and the second active region ACT2 can have the same size, but the embodiment is not limited to this configuration. Furthermore, both the first and second active regions ACT1 and ACT2 can have a short axis extending along a first direction DR1 and a long axis extending along a second direction DR2 perpendicular to the first direction DR1. The difference between the long axis and the short axis of the first and second active regions ACT1 and ACT2 can be less than [value missing]. Figure 4 The difference between the major and minor axes of the active region ACT.

[0094] Although some embodiments show the first active region ACT1 located in a lower row than the second active region ACT2, the positions of the first active region ACT1 and the second active region ACT2 can be changed as needed.

[0095] The write gate 122a may be located at the center of the first active region ACT1. The read gate 122b may be located at the center of the second active region ACT2. The write gate 122a and the read gate 122b may extend along a first direction DR1 perpendicular to the second direction DR2, and the write gate 122a and the read gate 122b may be electrically isolated from each other.

[0096] The first end of the read gate 122b may extend beyond a predetermined length on one side of the second active region ACT2 to be located in the gap formed between the first active region ACT1 and the second active region ACT2.

[0097] The source 131a of the write transistor WT can be formed in the first active region ACT1 on one side of the write gate 122a, and the drain 131b of the write transistor WT can be formed in the first active region ACT1 on the other side of the write gate 122a.

[0098] The source 131a-1 of the read transistor RT can be formed in the second active region ACT2 on one side of the read gate 122b, and the drain 131c of the read transistor RT can be formed in the second active region ACT2 on the other side of the read gate 122b.

[0099] In another embodiment, such as Figure 7B As shown, the source 131a of the write transistor WT can be formed in the first active region ACT1 on the other side of the write gate 122a. The drain 131b of the write transistor WT can be formed in the first active region ACT1 on the first side of the write gate 122a.

[0100] The source 131a-1 of the read transistor RT can be formed in the second active region ACT2 on the other side of the read gate 122b. The drain 131c of the read transistor RT can be formed in the second active region ACT2 on the first side of the read gate 122b.

[0101] Bit line BL can be electrically connected between the source 131a of write transistor WT and the source 131a-1 of read transistor RT. Bit line BL can extend, for example, parallel to the first direction DR1. Contact CT can be inserted between bit line BL and the source 131a of write transistor WT and between bit line BL and the source 131a-1 of read transistor RT, respectively.

[0102] Diode 162 may be located at one end of read gate 122b. Diode 162 may be electrically connected to read gate 122b via contact CT in the gap region between the first and second active regions ACT1 and ACT2.

[0103] Interconnect 177 electrically connects diode 162 to the drain 131b of write transistor WT. For example, contact CT may be located between interconnect 177 and the drain 131b of write transistor WT to electrically connect interconnect 177 to the drain 131b of write transistor WT. Figure 7A In the plan view shown, the interconnect wiring can be in the shape of an "L", where two basically straight parts are connected at a right angle to form an "L".

[0104] According to some embodiments of this disclosure, the contact element CT can be a vertically connected structure. The height of the contact element CT can be varied according to design specifications.

[0105] According to some embodiments of this disclosure, the memory cell may be coupled to a write word line, a read word line, and a common bit line. The memory cell may include a write transistor connected to the write word line and the common bit line, a read transistor connected to the read word line and the common bit line, and a diode connected between the write transistor and the read transistor.

[0106] Therefore, even if the write transistor and read transistor can be connected to a common bit line, data loss and fluctuations in unselected memory cells will not occur due to the forward drive of the diode, thereby reducing the area of ​​the memory cell while ensuring memory characteristics.

[0107] The present disclosure has been described in detail above with reference to specific embodiments, but these embodiments are not limited to the above embodiments, and those skilled in the art can make various modifications within the scope of the technical concept of the present disclosure. In addition, these embodiments can be combined to form other embodiments.

Claims

1. A storage cell having three terminals, comprising: The write transistor is connected between the write word line and the bit line; A diode, including an anode connected to the write transistor; and A read transistor is connected between the read word line and the bit line. The gate of the read transistor is connected to the diode.

2. The storage unit according to claim 1, wherein, The write transistor: in response to the enable signal of the write word line, transmits the write voltage applied to the bit line as data to the anode of the diode.

3. The storage unit according to claim 1, wherein, The read transistor transmits the enable signal of the read word line to the bit line based on the data received from the cathode of the diode.

4. The storage unit according to claim 1, wherein, The diode is turned on when the voltage level of the anode is greater than the voltage level of the cathode and the difference between the voltage levels of the anode and the cathode is not less than the threshold voltage of the diode.

5. The storage unit according to claim 1, wherein, The diode includes at least one of a Schottky barrier diode and a PN diode.

6. A semiconductor memory device, comprising: Multiple write word lines extend parallel to a first direction; Multiple read word lines extend parallel to a second direction that intersects the first direction; Multiple bit lines that extend parallel to the second direction and alternate with the multiple read word lines; and Multiple storage units, wherein each of the storage units includes: A write transistor is connected to one of the plurality of write word lines and one of the plurality of bit lines; A diode, comprising an anode connected to the write transistor; and A read transistor is connected to the cathode of the diode, one of the plurality of read word lines, and the bit line to which the write transistor is connected.

7. The semiconductor memory device according to claim 6, wherein, The write transistor: in response to the enable signal of the write word line, transmits the write voltage applied to the bit line as data to the anode of the diode.

8. The semiconductor memory device according to claim 6, wherein, The read transistor transmits the enable signal of the read word line to the bit line based on the data received from the diode.

9. The semiconductor memory device according to claim 6, wherein, The diode is turned on when the voltage level of the anode is greater than the voltage level of the cathode and the difference between the voltage levels of the anode and the cathode is not less than the threshold voltage of the diode.

10. The semiconductor memory device according to claim 6, wherein, The diode includes at least one of a Schottky barrier diode and a PN diode.

11. A storage cell having three terminals, comprising: Active region; The write transistor and the read transistor are integrated in the active region, respectively; A write word line, which is electrically connected to the gate of the write transistor; Bit lines are electrically connected to the source of the write transistor and the source of the read transistor; A diode, which is located above and connected to the gate of the read transistor; A read word line, which is connected to the drain of the read transistor; and Interconnect wiring is provided between the diode and the drain of the write transistor. The anode of the diode is connected to the drain of the write transistor, and the cathode of the diode is connected to the gate of the read transistor.

12. The storage unit according to claim 11, in, The active region has a strip shape, the strip shape having a short axis extending along a first direction and a long axis extending along a second direction perpendicular to the first direction. Wherein, the gate of the write transistor and the gate of the read transistor extend parallel to each other in the active region along the second direction. Wherein, the source of the write transistor and the source of the read transistor together include a first junction region formed in the active region between the gate of the write transistor and the gate of the read transistor. Wherein, the drain of the write transistor includes a second junction region formed in the active region outside the gate of the write transistor, and The drain of the read transistor includes a third junction region formed in the active region outside the gate of the read transistor.

13. The storage unit according to claim 12, in, The diode is located above the gate of the readout transistor, which overlaps with the active region, and The interconnect wiring extends to overlap with the active region.

14. The storage unit according to claim 12, in, The diode is located above the gate of the read transistor, which extends outward from the active region, and The interconnect wiring bypasses the active region and extends along the periphery of the active region.

15. The storage unit according to claim 11, wherein, The active region includes: A first active region, wherein the write transistor is integrated; and The second active region is arranged opposite the first active region at a predetermined interval, and The read transistor is integrated in the second active region.

16. The storage unit according to claim 15, in, The gate of the write transistor is disposed at the center of the first active region, the source of the write transistor is located in the first active region on one side of the gate of the write transistor, and the drain of the write transistor is located in the first active region on the other side of the gate of the write transistor. The gate of the read transistor is disposed at the center of the second active region and extends a certain length into the first active region; the source of the read transistor is disposed in the second active region on one side of the gate of the read transistor; and the drain of the read transistor is disposed in the second active region on the other side of the gate of the read transistor.

17. The storage unit according to claim 16, in, The diode is located at one end of the gate of the read transistor, and A portion of the interconnect wiring is located between the first active region and the second active region.

18. The storage unit according to claim 11, wherein, The diode includes an n-type semiconductor layer.

19. The storage unit according to claim 11, wherein, The diode comprises stacked p-type semiconductor layers and n-type semiconductor layers.

20. A storage cell having three terminals, comprising: The write transistor is connected between the write word line and the bit line; A read transistor connected between the read word line and the bit line, and a diode connected between the read transistor and the write transistor, wherein the anode of the diode is connected to the drain of the write transistor. The cathode of the diode is connected to the gate of the read transistor.

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