Word line drive circuit and semiconductor memory device including the same

Abstract

The present disclosure relates to a word line driving circuit and a semiconductor memory device including the same. A word line driving circuit includes an auxiliary driver configured to provide one of a high voltage and a low voltage to a word line activation voltage terminal in response to an auxiliary selection signal; a main driver configured to drive a word line with one of a voltage of the word line activation voltage terminal and the low voltage in response to a main selection signal, and to drive the word line with the low voltage in response to the auxiliary selection signal; and a voltage discharger configured to drive the word line activation voltage terminal with the low voltage in response to the auxiliary selection signal when a level of the high voltage is determined to be higher than a reference value.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0055897, filed on April 29, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure generally relate to semiconductor memory devices, and more particularly to a word line driving circuit and a semiconductor memory device including the word line driving circuit. Background Technology

[0004] Various integrated circuits not only generate and use the power supply voltage provided by external devices, but also use internal voltages with different levels than the power supply voltage. For example, in semiconductor memory devices, a high voltage higher than the power supply voltage is generated internally and used as the voltage to drive word lines.

[0005] The most frequently performed operations in semiconductor memory devices include activation and precharge operations. Activation activates the word line at a high voltage level, while precharge deactivates it at a low voltage level. When activation and precharge operations are repeatedly executed, the components of the word line drive circuitry that drive the word lines may degrade. Summary of the Invention

[0006] According to one embodiment of this disclosure, the word line driving circuit may include: an auxiliary driver configured to provide one of a high voltage and a low voltage to the word line activation voltage terminal in response to an auxiliary selection signal; a main driver configured to drive the word line with one of the voltage and low voltage of the word line activation voltage terminal in response to a main selection signal, and to drive the word line with a low voltage in response to the auxiliary selection signal; and a voltage discharger configured to drive the word line activation voltage terminal with a low voltage in response to the auxiliary selection signal when the level of the high voltage is determined to be higher than a reference value.

[0007] According to one embodiment of this disclosure, a semiconductor memory device may include: multiple word lines; a high-voltage level detector configured to detect when a high voltage level is higher than a reference value during activation operation; a decoder circuit configured to decode an address and generate multiple main select signals and multiple auxiliary select signals; and multiple word line driving circuits, each of which drives a corresponding word line based on one of the multiple main select signals, one of the multiple auxiliary select signals, and one of the detection results of the high-voltage level detector. Attached Figure Description

[0008] Figure 1 This is a configuration diagram showing a word line driving circuit according to an embodiment of the present disclosure.

[0009] Figure 2This is a configuration diagram showing a word line driving circuit according to an embodiment of the present disclosure.

[0010] Figure 3 This is a configuration diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 4 It is shown Figure 3 The diagram shows an example configuration of a high-voltage level detector.

[0012] Figure 5 It is shown Figure 3 The diagram shows an example configuration of a word line driver circuit. Detailed Implementation

[0013] The various embodiments disclosed herein pertain to techniques for preventing or mitigating the degradation of components constituting word line drive circuits.

[0014] According to embodiments of this disclosure, degradation of components constituting word line drive circuits can be prevented or mitigated.

[0015] Various embodiments based on the technical spirit of this disclosure will now be described in conjunction with the accompanying drawings.

[0016] Figure 1 This is a configuration diagram showing a word line driving circuit 100 according to an embodiment of the present disclosure.

[0017] See Figure 1 The word line driving circuit 100 includes an auxiliary driver 110 and a main driver 120. Figure 1 Only the configuration of the word line driver circuit 100 related to driving a word line WL is shown.

[0018] The auxiliary driver 110 provides one of a high voltage VPP and a low voltage VBBW to the word line activation voltage terminal FX in response to the auxiliary select signal FXB. The auxiliary driver 110 can provide a high voltage VPP to the word line activation voltage terminal FX when the auxiliary select signal FXB is activated at a low level, and can also provide a low voltage VBBW to the word line activation voltage terminal FX when the auxiliary select signal FXB is deactivated at a high level. The auxiliary driver 110 may include a PMOS transistor 111 that drives the word line activation voltage terminal FX with a high voltage VPP in response to the auxiliary select signal FXB; and an NMOS transistor 112 that drives the word line activation voltage terminal FX with a low voltage VBBW in response to the auxiliary select signal FXB.

[0019] The high voltage VPP is the voltage level used to activate the word line WL. A high voltage VPP, which has a higher level than the power supply voltage VDD, can be generated and used by pumping the power supply voltage VDD supplied externally to the semiconductor memory device. The low voltage VBBW is the voltage level used to deactivate the word line WL. The ground voltage VSS is used as the low voltage VBBW. A negative voltage, which has a lower level than the ground voltage VSS, can be generated by voltage pumping and used as the low voltage VBBW.

[0020] The main driver 120 drives word line WL with either the voltage of the word line active voltage terminal FX or the low voltage VBBW in response to the main select signal MWLB, and drives word line WL with the low voltage VBBW in response to the auxiliary select signal FXB. When the main select signal MWLB is activated at a low level, the main driver 120 can drive word line WL with the voltage of the word line active voltage terminal FX, and when the main select signal MWLB is deactivated at a high level, the main driver 120 can drive word line WL with the low voltage VBBW. Additionally, when the auxiliary select signal FXB is deactivated at a high level, the main driver 120 can drive word line WL with the low voltage VBBW. The main driver 120 may include: a PMOS transistor that drives word line WL with a voltage at word line activation voltage terminal FX in response to a main select signal MWLB; an NMOS transistor 122 that drives word line WL with a low voltage VBBW in response to the main select signal MWLB; and an NMOS transistor 123 that drives word line WL with a low voltage VBBW in response to an auxiliary select signal FXB.

[0021] When the main select signal MWLD is activated at a low level and the auxiliary select signal FXB is activated at a low level, the word line WL can be activated at a high voltage VPP. When at least one of the main select signal MWLD and the auxiliary select signal FXB is deactivated at a high level, the word line WL can be deactivated at a low voltage VBBW.

[0022] During the operation of a semiconductor memory device, the operation of activating the word line WL at a high voltage VPP and then deactivating it at a low voltage VBBW can be repeatedly performed. This repeated operation can cause hot carrier injection (HCI) degradation in NMOS transistors 122 and 123. When NMOS transistors 122 and 123 degrade, the threshold voltage may increase, the drain current may decrease, and the switching speed may decrease. Therefore, the transition time of the word line WL from the high voltage VPP to the low voltage VBBW may increase, which may prolong the precharge operation time. The increase in precharge operation time may lead to a deterioration in memory performance. In particular, the larger the drain-source voltage VDS of NMOS transistors 122 and 123, the more severe the HCI degradation may be.

[0023] Figure 2This is a configuration diagram showing a word line driving circuit 200 according to an embodiment of the present disclosure.

[0024] like Figure 2 As shown, the word line driving circuit 200 includes an auxiliary driver 210, a main driver 220, a voltage discharger 230, and a high-voltage auxiliary selection signal generator 240. Figure 2 Only the configuration of the word line driver circuit 200 related to driving a word line WL is shown.

[0025] The auxiliary driver 210 provides one of a high voltage VPP and a low voltage VBBW to the word line activation voltage terminal FX in response to the auxiliary select signal FXB. When the auxiliary select signal FXB is activated at a low level, the auxiliary driver 210 can provide a high voltage VPP to the word line activation voltage terminal FX, and when the auxiliary select signal FXB is deactivated at a high level, the auxiliary driver 210 can apply a low voltage VBBW to the word line activation voltage terminal FX. The auxiliary driver 210 may include a PMOS transistor 211 that drives the word line activation voltage terminal FX with a high voltage VPP in response to the auxiliary select signal FXB; and an NMOS transistor 212 that drives the word line activation voltage terminal FX with a low voltage VBBW in response to the auxiliary select signal FXB.

[0026] The main driver 220 drives word line WL with either the voltage of the word line active voltage terminal FX or the low voltage VBBW in response to the main select signal MWLB, and drives word line WL with the low voltage VBBW in response to the auxiliary select signal FXB. When the main select signal MWLB is activated at a low level, the main driver 220 can drive word line WL with the voltage of the word line active voltage terminal FX; when the main select signal MWLB is deactivated at a high level, the main driver 220 can drive word line WL with the low voltage VBBW. Additionally, when the auxiliary select signal FXB is deactivated at a high level, the main driver 220 can drive word line WL with the low voltage VBBW. The main driver 220 may include: a PMOS transistor 221 that drives word line WL with a voltage at word line activation voltage terminal FX in response to a main select signal MWLB; an NMOS transistor 222 that drives word line WL with a low voltage VBBW in response to the main select signal MWLB; and an NMOS transistor 223 that drives word line WL with a low voltage VBBW in response to an auxiliary select signal FXB.

[0027] The high-voltage auxiliary selection signal generator 240 uses a high-voltage detection signal HVPP_DET and an auxiliary selection signal FXB to generate a high-voltage auxiliary selection signal HVPP_FXB. The high-voltage detection signal HVPP_DET is a signal activated at a high level when the high-voltage VPP level is higher than a reference value. When the high-voltage detection signal HVPP_DET is activated at a high level, the high-voltage auxiliary selection signal generator 240 can generate a high-voltage auxiliary selection signal HVPP_FXB, which has the same level as the auxiliary selection signal FXB. Alternatively, when the high-voltage detection signal HVPP_DET is deactivated at a low level, the high-voltage auxiliary selection signal HVPP_FXB can be fixed at a low level. The high-voltage auxiliary selection signal generator 240 may include a NAND gate 241 that receives the high-voltage detection signal HVPP_DET and the auxiliary selection signal FXB; and an inverter 242 that inverts the output of the NAND gate 241 and outputs the inverted signal as the high-voltage auxiliary selection signal HVPP_FXB.

[0028] The voltage discharger 230 can activate the voltage terminal FX by driving the word line with a low voltage VBBW in response to a high voltage auxiliary selection signal HVPP_FXB. The voltage discharger 230 may include an NMOS transistor that activates the voltage terminal FX by driving the word line with a low voltage VBBW in response to the high voltage auxiliary selection signal HVPP_FXB.

[0029] When the high voltage VPP level is greater than or equal to the reference value and the word line WL is deactivated, the voltage discharger 230 is activated to operate, thereby allowing the voltage level of the word line activation voltage terminal FX to decrease more quickly. Accordingly, in one embodiment, a high drain-source voltage VDS is prevented from being applied to the NMOS transistors 222 and 223 of the main driver 220, thus preventing or mitigating degradation of the NMOS transistors 222 and 223. In one embodiment, when the high voltage VPP level is not higher than the reference value, the NMOS transistors 222 and 223 do not degrade; instead, there is a risk that the pre-charge operation time may become too short due to the operation of the voltage discharger 230. Accordingly, in one embodiment, the voltage discharger 230 may operate only when the high voltage VPP level is greater than or equal to the reference value.

[0030] Figure 3 This is a configuration diagram of a semiconductor memory device 300 according to an embodiment of the present disclosure. Figure 3 The configuration associated with word lines WL0 to WL1023 in the driving semiconductor memory device 300 is shown.

[0031] like Figure 3 As shown, the semiconductor memory device 300 includes a high-voltage level detector 310, a decoder circuit 320, and a word line drive circuit 200.

[0032] The high voltage level detector 310 detects the level of the high voltage VPP. The level of the high voltage VPP can vary depending on various factors, such as changes in the level of the power supply voltage input from outside the semiconductor memory device 300 and changes in the internal temperature of the semiconductor memory device 300. The high voltage level detector 310 can detect whether the level of the high voltage VPP is higher than a reference value and generate a high voltage detection signal HVPP_DET. The high voltage level detection time of the high voltage level detector 310 can be when the activation pulse signal ACT_P is activated, i.e., when the activation operation is executed.

[0033] Decoder circuit 320 can decode address ADD<0:9> and generate main selection signal MWLB<0:127> and auxiliary selection signal FXB<0:7>. Decoder circuit 320 can decode some bits of address ADD<0:9> (e.g., 7 bits) and select one from 128 (=2^7) main selection signals MWLB<0:127>, and can decode other bits of address ADD<0:9> (e.g., 3 bits) and select one from 8 (=2^3) auxiliary selection signals FXB<0:7>. In response to activation by activation pulse signal ACT_P, the selected signal in main selection signal MWLB<0:127> and the selected signal in auxiliary selection signal FXB<0:7> can be activated at a low level. Furthermore, the signal activated during activation by activation pulse signal ACT_P can be deactivated at a high level in response to activation by precharge pulse signal PCG_P.

[0034] The activation pulse signal ACT_P can be a pulse signal activated when indicative of an activation operation of the semiconductor memory device 300, while the precharge pulse signal PCG_P can be a pulse signal activated when indicative of a precharge operation of the semiconductor memory device 300. Since the refresh operation of the semiconductor memory device 300 includes both an activation operation and a precharge operation, the precharge pulse signal PCG_P can be activated after the activation pulse signal ACT_P is activated, even during the refresh operation.

[0035] The word line driver circuit 200 can drive word lines WL0 to WL1023 using a high-voltage detection signal HVPP_DET, a main selection signal MWLB<0:127>, and an auxiliary selection signal FXB<0:7>. The word line driver circuit 200 activates one of the word lines WL0 to WL1023 during activation operation and deactivates the activated word line during pre-charge operation. Since the number of main selection signals MWLB<0:127> is 128 and the number of auxiliary selection signals FXB<0:7> is 8, 1024 (=128*8) word lines WL0 to WL1023 can be selected. Figure 2Only the configuration of the word line driver circuit 200 related to driving a single word line WL is shown, while Figure 5 The word line drive circuit 200 that drives multiple word lines WL0 to WL1023 is shown in detail in how it is configured.

[0036] Figure 3 In this example, we have an address ADD<0:9> with 10 bits, 128 primary select signals MWLB<0:127>, 8 secondary select signals FXB<0:7>, and 1024 word lines WL0 to WL1023. These numbers are for illustrative purposes only and can be changed at any time depending on the design.

[0037] Figure 4 It is shown Figure 3 The diagram shows an example configuration of the high voltage level detector 310.

[0038] See Figure 4 The high voltage level detector 310 includes a comparator 410 and a latch circuit 420.

[0039] Comparator 410 compares the level of the high voltage VPP with the level of the reference voltage VREF. Comparator 410 outputs a high-level signal when the level of the high voltage VPP is higher than the level of the reference voltage VREF, and outputs a low-level signal when the level of the high voltage VPP is lower than the level of the reference voltage VREF. Here, we take a direct comparison of the high voltage VPP with the reference voltage VREF as an example. However, according to one embodiment, a voltage obtained by dividing the high voltage VPP can be compared with the reference voltage VREF. For example, instead of comparing the 4V high voltage VPP with the reference voltage VREF, comparator 410 can compare a 2V voltage obtained by dividing the high voltage VPP by half (VPP / 2) with the reference voltage VREF.

[0040] The latch circuit 420 can receive the output signal of the comparator 410 during the period when the activation pulse signal is activated at a high level, and output the input signal as a high-voltage detection signal HVPP_DET by maintaining the level of the input signal during the period when the activation pulse signal is deactivated at a low level. Accordingly, the high-voltage detection signal HVPP_DET can be updated whenever the activation pulse signal ACT_P is activated. The latch circuit 420 may include a pass gate 421, a tri-state inverter 422, and inverters 423 and 424. The reference numeral "ACT_PB" in the figure can be the inverted signal of the activation pulse signal ACT_P.

[0041] Figure 5 It is shown Figure 3 The diagram shows an example configuration of the word line driver circuit 500.

[0042] like Figure 5 As shown, the word line driver circuit 500 includes high-voltage auxiliary selection signal generators 240_0 to 7, auxiliary drivers 210_0 to 7, voltage dischargers 230_0 to 7, and main drivers 220_0 to 1023. The tilde “~” used herein indicates a range of components. For example, “240_0 to 7” indicates… Figure 5 The high-voltage auxiliary selection signal generators 240_0, 240_1, ... and 240_7 are shown.

[0043] The high-voltage auxiliary selection signal generator 240_0~7, the auxiliary driver 210_0~7, and the voltage discharger 230_0~7 can be provided according to the number of auxiliary selection signals FXB<0:7>.

[0044] The high-voltage auxiliary selection signal generators 240_0 to 7 can generate the high-voltage auxiliary selection signal HVPP_FXB<0:7> using the high-voltage detection signal HVPP_DET and the auxiliary selection signal FXB<0:7>. The reference symbol "i" in the figure can be an integer from 0 to 7.

[0045] The auxiliary drivers 210_0 to 7 can respond to the auxiliary selection signal FXB<0:7> to provide one of the high voltage VPP and the low voltage VBBW to the word line activation voltage terminal FX<0:7>.

[0046] Voltage dischargers 230_0~7 can respond to the high voltage auxiliary selection signal HVPP_FXB<0:7> to activate the voltage terminal FX<0:7> by driving the word line with low voltage VBBW.

[0047] The main drivers 220_0 to 1023 can be provided in the same number as word lines WL0 to WL1023. The main drivers 220_0 to 1023 can drive word lines WL0 to WL1023 via a combination of the main select signal MWLB<0:127> and the word line activation voltage terminal FX<0:7>. Since the number of main select signals MWLB<0:127> is 128 and the number of word line activation voltage terminals FX<0:7> is 8, 1024 (=128*8) word lines WL0 to WL1023 can be driven. (Reference symbol MWLB in the figure) <j>In this context, "j" can be an integer from 0 to 127, while "k" can be an integer from 0 to 1023.

[0048] Although the technical spirit of this disclosure has been described above in conjunction with embodiments, these descriptions are merely illustrative of embodiments consistent with the concepts of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art can apply various embodiments within the scope of the technical spirit of this disclosure.< / j>

Claims

1. A word line driving circuit, comprising: An auxiliary driver that, in response to an auxiliary selection signal, provides one of a high voltage and a low voltage to the word line activation voltage terminal; A main driver, which: drives the word line in response to a main select signal with one of the voltage at the word line activation voltage terminal and the low voltage, and drives the word line in response to the auxiliary select signal with the low voltage; and A voltage discharger that, in response to the auxiliary selection signal, drives the word line to activate the voltage terminal with the low voltage when the level of the high voltage is determined to be higher than a reference value.

2. The word line driving circuit according to claim 1, wherein the auxiliary driver comprises: A first PMOS transistor, wherein: in response to the auxiliary selection signal, the word line activation voltage terminal is driven by the high voltage; and A first NMOS transistor, which: in response to the auxiliary selection signal, drives the word line activation voltage terminal with the low voltage.

3. The word line driving circuit according to claim 2, wherein, The voltage discharger includes a second NMOS transistor, which, when the level of the high voltage is determined to be higher than the reference value, drives the word line activation voltage terminal with the low voltage in response to a high voltage auxiliary selection signal having the same level as the auxiliary selection signal.

4. The word line driving circuit according to claim 3, wherein, The main drive includes: The second PMOS transistor: drives the word line with the voltage of the word line activation voltage terminal in response to the main selection signal; A third NMOS transistor, which: drives the word line with the low voltage in response to the main select signal; and A fourth NMOS transistor, which: drives the word line at the low voltage in response to the auxiliary selection signal.

5. The word line driving circuit according to claim 1, wherein, The determination that the high voltage level is higher than the reference value is performed during the activation operation.

6. A semiconductor memory device, comprising: A high voltage level detector, which detects when the high voltage level is higher than a reference value during activation operation; The decoder circuit includes: address decoding and generation of multiple main selection signals and multiple auxiliary selection signals; and A word line driving circuit that drives multiple word lines based on the multiple main selection signals, the multiple auxiliary selection signals, and the detection results of the high voltage level detector.

7. The semiconductor memory device according to claim 6, wherein, The word line driving circuit includes: Multiple high-voltage auxiliary selection signal generators, each of which generates a corresponding high-voltage auxiliary selection signal using a corresponding auxiliary selection signal and a high-voltage detection signal; Multiple auxiliary drivers, each of which: in response to a corresponding auxiliary selection signal, provides one of the high voltage and low voltage to the corresponding word line activation voltage terminal; A plurality of master drivers, each of which: drives a corresponding word line in response to a corresponding master select signal with one of the voltage of a corresponding word line activation voltage terminal and the low voltage; and drives the corresponding word line with the low voltage in response to a corresponding auxiliary select signal; and Multiple voltage dischargers, each of which: in response to a corresponding high-voltage auxiliary selection signal, drives the corresponding word line activation voltage terminal with the low voltage.

8. The semiconductor memory device of claim 7, wherein each of the high-voltage auxiliary selection signal generators comprises: A NAND gate, which: receives the corresponding auxiliary selection signal and the high voltage detection signal; and An inverter that receives the output of the NAND gate and generates the corresponding high-voltage auxiliary selection signal.

9. The semiconductor memory device according to claim 7, wherein, Each of the auxiliary drivers includes: A first PMOS transistor, wherein: in response to the corresponding auxiliary selection signal, the corresponding word line activation voltage terminal is driven by the high voltage; and The first NMOS transistor, in response to the corresponding auxiliary selection signal, drives the corresponding word line activation voltage terminal with the low voltage.

10. The semiconductor memory device according to claim 9, wherein, Each of the voltage dischargers includes a second NMOS transistor, which drives the corresponding word line activation voltage terminal with the low voltage in response to the corresponding high voltage auxiliary selection signal.

11. The semiconductor memory device according to claim 10, wherein, Each of the aforementioned master drives includes: The second PMOS transistor: in response to the corresponding master selection signal, drives the corresponding word line with the voltage of the corresponding word line activation voltage terminal; A third NMOS transistor, which: in response to the corresponding master select signal, drives the corresponding word line with the low voltage; and The fourth NMOS transistor, which: drives the corresponding word line with the low voltage in response to the corresponding auxiliary selection signal.

12. The semiconductor memory device according to claim 6, wherein, The high-voltage level detector includes: A comparator that: compares the level of the high voltage with the level of a reference voltage; and A latching circuit that receives the output signal of the comparator when the activation pulse signal is activated, and outputs the input signal as the detection result by maintaining the level of the input signal during the period when the activation pulse signal is deactivated.

13. The semiconductor memory device according to claim 7, in, The decoder circuit decodes n bits of the address to generate 2^n main selection signals, and decodes the other m bits of the address to generate 2^m auxiliary selection signals. Where n is a natural number, and Where m is a natural number.

14. The semiconductor memory device according to claim 13, wherein, The number of high-voltage auxiliary selection signal generators is 2^m, the number of auxiliary drivers is 2^m, the number of voltage dischargers is 2^m, and the number of main drivers is 2^n*2^m.

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