A novel 4-tube SRAM bitcell and architecture

Abstract

The application discloses a novel 4-tube SRAM bitcell and architecture, and belongs to the technical field of semiconductor memories. The novel 4-tube SRAM bitcell comprises a write transistor WT, a storage transistor ST, a read transistor RT and a refresh read transistor RFRT, and the four transistors are all N-channel MOS transistors. The storage transistor ST stores charges by using a gate capacitor. A write operation is completed by a write word line WWL and a write bit line WBL. A read operation is completed by an independent read word line RWL and a read bit line RBL. A refresh operation is executed to read out by an independent refresh read path and is written back in a second clock cycle. Compared with a 6T-SRAM, the application has the advantages of significantly reduced area, improved speed and power consumption, and no influence on reading and writing during refresh, and can completely replace a conventional 6T-SRAM.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, specifically relating to a novel 4-transistor SRAM bit cell and its architecture. Background Technology

[0002] Traditional 6T-SRAM requires six MOS transistors to form a bit cell, which consumes a significant amount of space. DRAM uses a 1T1C scheme, which can reduce the area considerably, but it requires special processes and constant refreshing during use. Refreshing can easily cause conflicts with read and write operations, leading to read and write delays, thus limiting the application scenarios of DRAM. Summary of the Invention

[0003] The purpose of this invention is to provide a novel 4-transistor SRAM bitcell and architecture, which uses only 4 NMOS transistors to form a bitcell, significantly reducing the area compared to 6T-SRAM. It also solves the conflict between refresh and read / write operations, so users cannot perceive the refresh process at all. In addition, the read / write speed and power consumption are actually improved compared to 6T-SRAM, so it can completely replace traditional 6T-SRAM in any situation and solve the problems mentioned in the background art.

[0004] To achieve the above objectives, according to one aspect of the present invention, a novel 4-transistor SRAM bit cell is provided, comprising: The write transistor WT has its gate connected to the write word line WWL, its first on terminal connected to the write bit line WBL, and its second on terminal connected to the memory node SN. A storage transistor ST is used to store charge to characterize data state. Its gate is connected to the storage node SN, its first on terminal is connected to the reference potential terminal, and its second on terminal is connected to the common node A. A read transistor RT, whose gate is connected to the read word line RWL, whose first on-terminal is connected to the read bit line RBL, and whose second on-terminal is connected to the common node A; and The refresh read transistor RFRT has its gate connected to the refresh read word line RFWL, its first on terminal connected to the refresh read bit line RFBL, and its second on terminal connected to the common node A. Among them, the write transistor WT, storage transistor ST, read transistor RT, and refresh read transistor RFRT are all N-channel MOS transistors.

[0005] Preferably, the storage transistor ST stores charge using its gate capacitance.

[0006] Preferably, the refresh read transistor RFRT and the read transistor RT form independent read paths. The refresh read transistor RFRT is used for readout during refresh operation, and the read transistor RT is used for readout during normal read operation.

[0007] According to another aspect of the present invention, the present invention provides a novel 4-tube SRAM memory architecture, comprising: Multiple 4-tube SRAM bitcells are arranged in a matrix; Multiple write word lines WWL, each of which is connected to the gate of the write transistor WT of each bit cell in the same row of bit cells; Multiple write bit lines WBL, each of which is connected to the first on terminal of the write transistor WT of each bit cell in the same column of bit cells; Multiple read word lines RWL, each of which is connected to the gate of the read transistor RT of each bit cell in the same row of bit cells; Multiple read bit lines RBL, each of the read bit lines RBL is connected to the first conducting terminal of the read transistor RT of each bit cell in the same column of bit cells; Multiple refresh read word lines RFWL, each of which is connected to the gate of the refresh read transistor RFRT of each bit cell in the same row of bit cells; and Multiple refresh read bit lines RFBL, each of which is connected to the first on terminal of the refresh read transistor RFRT of each bit cell in the same column of bit cells.

[0008] Preferably, the 4-tube SRAM memory architecture also includes: The write operation circuit is connected to the write bit line WBL and is used to provide the data to be written to the selected write bit line WBL and to provide the write control pulse to the selected write word line WWL during the write operation cycle, so as to write the data to be written to the storage transistor ST of the corresponding bit cell. A read operation circuit, connected to the read bit line RBL, is used to pre-charge the selected read bit line RBL to a first potential during the read operation cycle, form a discharge path through the read transistor RT and the read word line RWL, and determine the stored data status based on a comparison between the discharge rate of the read bit line RBL and a reference discharge path; and A refresh read operation circuit, connected to the refresh read bit line RFBL, is used to form an independent discharge path through the refresh read transistor RFRT and the refresh read word line RFWL during the read cycle of the refresh operation to read the stored data state. The refresh read operation circuit is independent of the read operation circuit.

[0009] Preferably, the write operation circuit outputs the write control pulse in the second half of the write operation cycle; the storage architecture further includes a refresh write operation circuit, which outputs a refresh write control pulse in the first half of the write-back cycle of the refresh operation, and the refresh write operation circuit shares the write bit line WBL and the write word line WWL with the write operation circuit.

[0010] Preferably, during the read cycle of the refresh operation, the read data is transmitted to the write operation circuit for writing back to the same bit cell during the write-back cycle of the refresh operation.

[0011] Preferably, when the address corresponding to the read cycle of the refresh operation is the same as the address corresponding to the normal write operation in the same cycle, the write-back operation of the refresh operation is canceled.

[0012] Preferably, when the address corresponding to the read cycle of the refresh operation is the same as the address corresponding to the normal read operation in the same cycle, the read operation of the refresh operation is canceled, and the write-back operation of the refresh operation uses the data read by the normal read operation.

[0013] Preferably, the write operation circuit further includes a boost unit, which is used to boost the voltage of the write word line WWL to a level higher than the power supply voltage during a write operation or a refresh write-back operation, preferably to 1.5 times the power supply voltage.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1) Area reduction: Compared to 6T-SRAM, 4N SRAM-SIR requires only 2 / 3 of the number of tubes; 4N RAM does not require P-tubes, and the ARRAY section does not need NWELL tubes, making the layout more compact and further reducing the area. 2) Faster speed: Because the bitcell is smaller, the bitline is shorter, the capacitance on the bitline is smaller, and the discharge is faster. 3) Lower power consumption: The read operation can select only the BL to be read, and the unselected BL does not need to be charged or discharged, so there is almost no power consumption; the bitline is shorter and the capacitor is smaller, so charging and discharging is more energy-efficient.

[0015] 4) Automatic refresh operation has no impact on read / write operations: Automatic refresh is completely unaffected by read / write operations and will not cause delays in normal read / write operations. Attached Figure Description

[0016] Figure 1 A schematic diagram of the circuit structure of the novel 4-transistor SRAM bitcell of the present invention is shown.

[0017] Figure 2 A schematic diagram of the memory array connection structure of the novel 4-tube SRAM architecture of the present invention is shown.

[0018] Figure 3 A block diagram of the novel 4-transistor SRAM architecture of the present invention is shown.

[0019] Figure 4 The timing waveforms of read, write, and refresh operations of the novel 4-transistor SRAM architecture of the present invention are shown. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] Example 1: The novel 4-transistor SRAM bitcell structure of the present invention like Figure 1 As shown, the novel 4-transistor SRAM bitcell of the present invention includes four NMOS transistors: write transistor WT, storage transistor ST, read transistor RT, and refresh read transistor RFRT.

[0022] The gate of the write transistor WT is connected to the write word line WWL, its first source / drain (first on-terminal) is connected to the write bit line WBL, and its second source / drain (second on-terminal) is connected to the memory node SN. The gate of the memory transistor ST is connected to the memory node SN, its first source / drain (first on-terminal) is connected to a reference potential (e.g., ground), and its second source / drain (second on-terminal) is connected to the common node A. The gate of the read transistor RT is connected to the read word line RWL, its first source / drain (first on-terminal) is connected to the read bit line RBL, and its second source / drain (second on-terminal) is connected to the common node A. The gate of the refresh read transistor RFRT is connected to the refresh read word line RFWL, its first source / drain (first on-terminal) is connected to the refresh read bit line RFBL, and its second source / drain (second on-terminal) is connected to the common node A.

[0023] In this embodiment, the storage transistor ST uses its gate capacitance to store charge representing the data state. When the storage node SN is high, it indicates that the data "1" is stored; when the storage node SN is low, it indicates that the data "0" is stored.

[0024] Since all four transistors are N-channel MOS transistors and the bitcell does not contain any PMOS transistors, there is no need to place an N-well in the array region, which is beneficial for further reduction of the layout area.

[0025] Example 2: Array Connection Structure like Figure 2 As shown, multiple bitcells are arranged in a matrix to form the 4-tube SRAM memory array of the present invention.

[0026] All bitcells in the same row share the same write word line WWL, the same read word line RWL, and the same refresh read word line RFWL. Specifically, each write word line WWL is connected to the gate of the write transistor WT of each bitcell in the same row; each read word line RWL is connected to the gate of the read transistor RT of each bitcell in the same row; and each refresh read word line RFWL is connected to the gate of the refresh read transistor RFRT of each bitcell in the same row.

[0027] All bit cells in the same column share the same write bit line WBL, the same read bit line RBL, and the same refresh read bit line RFBL. Specifically, each write bit line WBL is connected to the first source / drain (first on-terminal) of the write transistor WT of each bit cell in the same column; each read bit line RBL is connected to the first source / drain (first on-terminal) of the read transistor RT of each bit cell in the same column; and each refresh read bit line RFBL is connected to the first source / drain (first on-terminal) of the refresh read transistor RFRT of each bit cell in the same column.

[0028] Example 3: Modular Architecture like Figure 3 As shown, the novel 4-transistor SRAM architecture of the present invention includes a write operation circuit, a read operation circuit, a refresh read operation circuit, a controller, and a WL decoder; The controller is connected to the write operation circuit, the read operation circuit, and the refresh read operation circuit respectively. It is used to control the operation of the write operation circuit, the read operation circuit, and the refresh read operation circuit, and to coordinate the timing of the write operation, the read operation, the refresh read operation, and the refresh write-back operation. Specifically, the controller can generate write enable signal, read enable signal, refresh read enable signal, and refresh write-back enable signal. It controls the write operation circuit to output a write control pulse in the second half of the write operation cycle and controls the refresh write operation circuit to output a refresh write control pulse in the first half of the refresh write-back cycle. When the address read in the refresh read cycle is the same as the address of the normal write operation in the same cycle, the refresh write-back operation is canceled to avoid old data overwriting new data. When the address read in the refresh read cycle is the same as the address of the normal read operation in the same cycle, the refresh read operation is canceled, and the data read by the normal read operation is used directly to perform refresh write-back.

[0029] The WL decoder is connected to the controller and is used to receive the operation mode selection signal and row address signal sent by the controller. It decodes the row address signal to selectively activate the selected write line WWL, read line RWL and refresh read line RFWL, thereby selecting the row where the target bit cell is located. Specifically, during a write operation or a refresh write-back operation, the WL decoder activates the write word line WWL of the corresponding row based on the row address; during a normal read operation, the WL decoder activates the read word line RWL of the corresponding row based on the row address; and during a refresh read operation, the WL decoder activates the refresh read word line RFWL of the corresponding row based on the row address.

[0030] The write operation circuit is connected to each write bit line WBL. During the write operation, the write operation circuit provides the data value to be written to the selected write bit line WBL and provides a narrow pulse to the selected write word line WWL to complete the data writing.

[0031] The read operation circuit is connected to each read bit line RBL and internally contains a reference discharge path and a comparator. During a read operation, the read operation circuit precharges the selected read bit line RBL to a high potential, then monitors its discharge rate. By comparing it with the discharge rate of the reference discharge path, it determines whether the data being read is "0" or "1".

[0032] The refresh read operation circuit is connected to each refresh read bit line RFBL. Its internal structure is similar to that of the read operation circuit, but it is set independently of the read operation circuit. During the read cycle of the refresh operation, the refresh read operation circuit completes data reading through the refresh read path.

[0033] Read operations and refresh read operations use independent paths—the read operation circuit and the refresh read operation circuit are connected to different bit lines and different word lines, so the two read operations can be executed in parallel within the same clock cycle without interfering with each other.

[0034] Example 4: Write Operation During a write operation, the selected write bit line WBL is first set to the data value to be written (e.g., WBL is set high (VDD) when writing "1" and low (GND) when writing "0"). Then, a narrow pulse (e.g., a pulse width of approximately 0.5 to 2 nanoseconds) is provided to the selected write word line WWL to turn on the write transistor WT. At this time, the data value on the write bit line WBL is transferred to the memory node SN through the write transistor WT and stored in the gate capacitance of the memory transistor ST.

[0035] Preferably, the WWL pulse for a write operation occurs in the second half of the clock cycle. More preferably, during a write operation, the WWL voltage can be boosted to approximately 1.5 times the supply voltage (1.5VDD) using bootstrap technology to facilitate writing a "1".

[0036] For unselected rows, their WWL remains low, the write transistor WT remains off, and the data in the storage node SN is unaffected. For unselected columns, the data on their WBL does not affect the unselected bitcells.

[0037] Example 5: Read Operation During a read operation, the selected read bit line RBL is first precharged to a high potential (e.g., VDD). Then, the selected read word line RWL is turned on (set to a high level), enabling the read transistor RT to conduct.

[0038] At this time, the read bit line RBL forms a discharge path through the read transistor RT and the storage transistor ST. When the storage node SN is high (storing "1"), the storage transistor ST is turned on, the resistance of the discharge path is small, and the read bit line RBL discharges quickly. When the storage node SN is low (storing "0"), the storage transistor ST is turned off or in a weakly conducting state, the resistance of the discharge path is large, and the read bit line RBL discharges slowly.

[0039] The read operation circuit determines whether the stored data is "1" or "0" by comparing the discharge rate of the selected read bit line RBL with the discharge rate of the reference discharge path. Each read operation is completed within one clock cycle.

[0040] It is worth noting that the read operation reads data through the gate of the read transistor RT (connected to the memory node SN). The read operation does not change the charge state of the memory node SN, therefore the read operation is non-destructive. Unselected read bit lines RBL do not require pre-charging or charging / discharging operations, thus significantly reducing read power consumption.

[0041] Example 6: Refresh Operation Since the storage transistor ST uses gate capacitance to store charge, the charge leaks over time, thus requiring periodic refreshing. The refresh operation of this invention consists of two clock cycles.

[0042] First clock cycle (refresh read cycle): In the first clock cycle, a read operation is performed through an independent refresh read path. Specifically, the selected refresh read bit line RFBL is pre-charged to a high potential, and then the selected refresh read word line RFWL is turned on (set to a high level), enabling the refresh read transistor RFRT to conduct. The refresh read bit line RFBL forms a discharge path through the refresh read transistor RFRT and the storage transistor ST, and its discharge speed reflects the data state of the storage node SN. The refresh read operation circuit determines the stored data by comparing the discharge speed of the refresh read bit line RFBL with the discharge speed of the reference discharge path. The read data value is temporarily stored in the write operation circuit.

[0043] Second clock cycle (refresh write-back cycle): In the first half of the second clock cycle, the write bit line WBL is set to refresh the read data value, and then a narrow pulse is provided to the selected write word line WWL to turn on the write transistor WT, writing the data value back to the memory node SN, thus completing the refresh.

[0044] Example 7: Synchronization Control of Refresh and Write Operations like Figure 4 As shown, since read operations and refresh read operations use completely independent paths (different bit lines and word lines), they can be executed in parallel within the same clock cycle without interfering with each other.

[0045] When a flush write-back operation and a normal write operation occur within the same clock cycle, a time-division multiplexing strategy is employed: the flush write-back operation is performed in the first half of the clock cycle (providing a write pulse to the corresponding WWL), and the normal write operation is performed in the second half of the clock cycle (providing a write pulse to the WWL of another address). Since write operations are much faster than read operations and do not require pre-charging, half a clock cycle is sufficient to complete the write operation.

[0046] If the address read during the refresh read cycle is the same as the address of the normal write operation in the same clock cycle, the write-back operation in the second refresh cycle is canceled to avoid overwriting the newly written data with old data.

[0047] If the address read in the refresh read cycle is the same as the address of the normal read operation in the same clock cycle, the refresh read operation is canceled (because the normal read operation has already obtained the correct data), and the refresh write-back operation directly uses the data value read by the normal read operation to write back.

[0048] Through the above mechanism, the refresh operation is completely unaffected by normal read and write operations and will not cause any read and write delays.

[0049] This invention discloses a novel 4-transistor SRAM bitcell and architecture. Compared to 6T-SRAM, the area of ​​the 4 NMOS transistor bitcell is smaller, and the architecture is not limited by the transistor size ratio, allowing for further area optimization. Furthermore, this architecture separates the refresh and read / write paths, enabling seamless refresh and thus achieving a complete replacement of 6T-SRAM. Additionally, because this architecture uses a pre-charge method for reading, and because the read operation has no impact on the bitcell's stored value, unselected bitlines do not require pre-charging, significantly reducing read power consumption.

[0050] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0051] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A novel 4-transistor SRAM bitcell, characterized in that, include: The write transistor WT has its gate connected to the write word line WWL, its first on terminal connected to the write bit line WBL, and its second on terminal connected to the memory node SN. A storage transistor ST is used to store charge to characterize data state. Its gate is connected to the storage node SN, its first on terminal is connected to the reference potential terminal, and its second on terminal is connected to the common node A. The read transistor RT has its gate connected to the read word line RWL, its first on terminal connected to the read bit line RBL, and its second on terminal connected to the common node A. as well as The refresh read transistor RFRT has its gate connected to the refresh read word line RFWL, its first on terminal connected to the refresh read bit line RFBL, and its second on terminal connected to the common node A. Among them, the write transistor WT, storage transistor ST, read transistor RT, and refresh read transistor RFRT are all N-channel MOS transistors.

2. The novel 4-transistor SRAM bitcell according to claim 1, characterized in that, The storage transistor ST stores charge using its gate capacitance.

3. A novel 4-transistor SRAM bitcell according to claim 1, characterized in that, The refresh read transistor RFRT and the read transistor RT form independent read paths. The refresh read transistor RFRT is used for readout during refresh operation, and the read transistor RT is used for readout during normal read operation.

4. A novel 4-transistor SRAM memory architecture, characterized in that, include: Multiple novel 4-tube SRAM bitcells as described in any one of claims 1-3 are arranged in a matrix; Multiple write word lines WWL, each of which is connected to the gate of the write transistor WT of each bit cell in the same row of bit cells; Multiple write bit lines WBL, each of which is connected to the first on terminal of the write transistor WT of each bit cell in the same column of bit cells; Multiple read word lines RWL, each of which is connected to the gate of the read transistor RT of each bit cell in the same row of bit cells; Multiple read bit lines RBL, each of the read bit lines RBL is connected to the first conducting terminal of the read transistor RT of each bit cell in the same column of bit cells; Multiple refresh read word lines RFWL, each of which is connected to the gate of the refresh read transistor RFRT of each bit cell in the same row of bit cells; and Multiple refresh read bit lines RFBL, each of which is connected to the first on terminal of the refresh read transistor RFRT of each bit cell in the same column of bit cells.

5. A novel 4-transistor SRAM memory architecture according to claim 4, characterized in that, Also includes: The write operation circuit is connected to the write bit line WBL and is used to provide the data to be written to the selected write bit line WBL and to provide the write control pulse to the selected write word line WWL during the write operation cycle, so as to write the data to be written to the storage transistor ST of the corresponding bit cell. The read operation circuit is connected to the read bit line RBL and is used to precharge the selected read bit line RBL to a first potential during the read operation cycle, form a discharge path through the read transistor RT and the read word line RWL, and determine the state of the stored data based on the comparison result between the discharge rate of the read bit line RBL and the reference discharge path. as well as A refresh read operation circuit, connected to the refresh read bit line RFBL, is used to form an independent discharge path through the refresh read transistor RFRT and the refresh read word line RFWL during the read cycle of the refresh operation to read the stored data state. The refresh read operation circuit is independent of the read operation circuit.

6. A novel 4-transistor SRAM memory architecture according to claim 5, characterized in that, The write operation circuit outputs the write control pulse in the second half of the write operation cycle; the storage architecture also includes a refresh write operation circuit, which outputs a refresh write control pulse in the first half of the write-back cycle of the refresh operation, and the refresh write operation circuit and the write operation circuit share the write bit line WBL and the write word line WWL.

7. A novel 4-transistor SRAM memory architecture according to claim 5, characterized in that, During the read cycle of the refresh operation, the read data is transmitted to the write operation circuit for writing back to the same bit cell during the write-back cycle of the refresh operation.

8. A novel 4-transistor SRAM memory architecture according to claim 7, characterized in that, When the address corresponding to the read cycle of a refresh operation is the same as the address corresponding to a normal write operation in the same cycle, the write-back operation of the refresh operation is canceled.

9. A novel 4-transistor SRAM memory architecture according to claim 7, characterized in that, When the address corresponding to the read cycle of the refresh operation is the same as the address corresponding to the normal read operation in the same cycle, the read operation of the refresh operation is canceled, and the write-back operation of the refresh operation uses the data read by the normal read operation.

10. A novel 4-transistor SRAM memory architecture according to claim 5, characterized in that, The write operation circuit also includes a boost unit, which is used to boost the voltage of the write word line WWL to a level higher than the power supply voltage during a write operation or a refresh write-back operation.

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