Semiconductor device and method of operating the same

Abstract

A semiconductor device includes a first memory cell connected between a first bit line and a word line, a second memory cell connected between a second bit line and the word line, a first voltage supply circuit that supplies a first logic input voltage to the first memory cell, a second voltage supply circuit that supplies a second logic input voltage to the second memory cell, and a third voltage supply circuit that supplies one of a first logic operation voltage and a second logic operation voltage to the word line. The first memory cell and the second memory cell are both components of the device that perform a specific logic operation.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0057273, filed with the Korean Intellectual Property Office on April 30, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to integrated circuit technology, and more specifically, to a semiconductor device and a method of operating the same. Background Technology

[0003] In recent years, with the reduction in size, power consumption, performance improvement, and functional diversification of electronic devices, various electronic devices (such as computers and portable communication devices) require memory capable of storing information. Furthermore, research on memory with various characteristics continues.

[0004] Memory under investigation also includes memory capable of storing data by utilizing the property of switching between different resistance states based on voltage or current. Such memories include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and fuse-only selector memory (SOM). Summary of the Invention

[0005] In one embodiment, the semiconductor device may include: a first memory cell connected between a first bit line and a word line; a second memory cell connected between a second bit line and a word line; a first voltage supply circuit configured to provide a first logic input voltage to the first bit line for use of the first memory cell in a logic operation; a second voltage supply circuit configured to provide a second logic input voltage to the second bit line for use of the second memory cell in a logic operation; and a third voltage supply circuit configured to provide one of a first logic operation voltage and a second logic operation voltage to the word line for use of the first memory cell and the second memory cell in a logic operation.

[0006] In one embodiment, an operation method of a semiconductor device may include: writing to a first memory cell connected between a first bit line and a word line; writing to a second memory cell connected between a second bit line and a word line, the second memory cell being in the same state as the first memory cell; providing a first logic input voltage to the first bit line; providing a second logic input voltage to the second bit line; and providing one of a first logic operation voltage and a second logic operation voltage to the word line according to the type of logic operation performed on the first and second memory cells, the second logic operation voltage having a level lower than the first logic operation voltage.

[0007] In another embodiment, the storage device may include: a first storage cell connected between a first bit line and a word line, and written such that current flows better in a first direction than in a second direction; a second storage cell connected between a second bit line and a word line, and written such that current flows better in the first direction than in the second direction; a first voltage supply circuit configured to provide a first logic input voltage to the first bit line; a second voltage supply circuit configured to provide a second logic input voltage to the second bit line; and a third voltage supply circuit configured to provide a first logic operation voltage to the word line, the level of the first logic operation voltage being higher than the second logic operation voltage. The result of an AND operation on the levels of the first logic input voltage and the second logic input voltage may correspond to the voltage level of the word line.

[0008] In another embodiment, the storage device may include: a first storage cell connected between a first bit line and a word line, and written such that current flows better in a second direction than in a first direction; a second storage cell connected between a second bit line and a word line, and written such that current flows better in the second direction than in the first direction; a first voltage supply circuit configured to provide a first logic input voltage to the first bit line; a second voltage supply circuit configured to provide a second logic input voltage to the second bit line; and a third voltage supply circuit configured to provide a second logic operation voltage to the word line, the level of the second logic operation voltage being lower than the first logic operation voltage. The result of an OR operation on the levels of the first logic input voltage and the second logic input voltage may correspond to the voltage level of the word line. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 and Figure 3 This is a diagram illustrating a write operation of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 This is a diagram illustrating a readout operation of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5 and Figure 6 This is a diagram used to describe a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 and Figure 8 This is a diagram used to describe a semiconductor device according to another embodiment of the present disclosure.

[0014] Figure 9This is a diagram used to describe a memory cell array according to an embodiment of the present disclosure. Detailed Implementation

[0015] Some embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0016] Embodiments of this disclosure relate to a technique in which some regions of a memory cell array are used for logical operations.

[0017] Semiconductor devices capable of performing arithmetic operations.

[0018] Figure 1 This is a diagram illustrating a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0019] refer to Figure 1 According to embodiments of the present disclosure, the memory cell MC of the semiconductor device can be disposed between the bit line BL and the word line WL. Furthermore, the memory cell MC can be electrically connected to the bit line BL and the word line WL. Figure 1 The diagram shows the bit line BL positioned above the word line WL, but according to one embodiment, the bit line BL may also be positioned below the word line WL. Furthermore, both the bit line BL and the word line WL may comprise conductive material.

[0020] The storage cell MC may include a first electrode TE, a storage material MM, and a second electrode BE. The storage material MM may be located between the first electrode TE and the second electrode BE. In this case, both the first electrode TE and the second electrode BE may comprise conductive materials. The threshold voltage level of the storage material MM may vary depending on the direction of the current flowing through the storage material MM. The storage material MM may comprise chalcogenide series materials.

[0021] For example, the second electrode BE can be formed on the word line WL. Storage material MM can be formed on the second electrode BE. The first electrode TE can be formed on the storage material MM. The bit line BL can be formed on the first electrode TE. In this case, depending on the positions where the first electrode TE and the second electrode BE are formed, the first electrode TE, located above the second electrode BE, can be called the upper electrode TE, and the second electrode BE, located below the first electrode TE, can be called the lower electrode TE.

[0022] Figure 2 and Figure 3 This is a diagram illustrating a write operation of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 2A diagram illustrating a write operation can be provided, where the write current WC flows from the word line WL through the memory cell MC to the bit line BL. The write operation can be performed by providing a voltage to the word line WL and the bit line BL such that the voltage level difference between the word line WL and the bit line BL is greater than the voltage level required to turn on the memory cell MC. In this case, a voltage higher than the voltage provided to the bit line BL can be provided to the word line WL.

[0024] Such a write operation can be performed by changing the storage material properties (MMC) of the storage material MM, so that current flows better in a first direction rather than a second direction. In this case, the storage material properties (MMC) can be similar to those of a diode, causing current to flow in the first direction. The first direction can be the direction in which current flows from the word line WL through the storage material MM to the bit line BL. The second direction can be the direction in which current flows from the bit line BL through the storage material MM to the word line WL.

[0025] Figure 3 A diagram illustrating a write operation can be provided, where the write current WC flows from the bit line BL through the memory cell MC to the word line WL. The write operation can be performed by providing voltages to the bit line BL and the word line WL such that the voltage level difference between the bit line BL and the word line WL is greater than the voltage level required to turn on the memory cell MC. In this case, a voltage higher than the voltage provided to the word line WL can be provided to the bit line BL.

[0026] Such a write operation can be performed by changing the storage material properties (MMC) of the storage material MM, so that current flows better in a second direction than in the first direction. In this case, the storage material properties (MMC) can be similar to those of a diode, causing current to flow in the second direction. The first direction can be the direction in which current flows from the word line WL through the storage material MM to the bit line BL. The second direction can be the direction in which current flows from the bit line BL through the storage material MM to the word line WL.

[0027] Figure 4 This is a diagram illustrating a readout operation of a semiconductor device according to an embodiment of the present disclosure.

[0028] refer to Figure 4 The read operation can be performed as follows: the state of the memory cell MC is determined by providing a voltage higher than the voltage supplied to the bit line BL than the voltage supplied to the word line WL. In this case, the read operation can be performed as follows: causing the read current FRC to have a voltage at... Figure 3 The write current WC flows in the same direction after the write operation begins. Furthermore, after the read operation begins, the voltage level difference between the bit line BL and the word line WL corresponds to the level of the read voltage Vread. The read voltage Vread can have a value according to a reference... Figure 2 The threshold voltage level of the memory cell MC described in the write operation is consistent with that according to the reference. Figure 3 The voltage levels between the threshold voltage levels of the memory cell MC described in the write operation.

[0029] Therefore, when considering the properties of storage materials such as MMC Figure 4 As shown, the writing current WC is as follows Figure 3 As shown in the diagram, when a write operation occurs in the memory cell MC, the read current FRC can flow from the bit line BL through the conducted memory cell MC to the word line WL. At this time, the memory cell MC can be turned on because the storage material characteristic MMC is referenced... Figure 3 The threshold voltage level of the memory cell MC, which varies with the write operation described, is lower than the read voltage Vread level.

[0030] When the storage material properties MMC such Figure 4 As shown by reference Figure 2 When the memory cell MC, which varies with the write operation described, performs a read operation, the read current FRC may not flow substantially. In this case, the memory cell MC may not be able to conduct because the storage material properties MMC are referenced... Figure 2 The threshold voltage level of the memory cell MC, which varies with the write operation described, is higher than the read voltage Vread. Therefore, the read current FRC may not flow at all.

[0031] The state of a memory cell MC with a threshold voltage lower than the read voltage Vread is called the set state (SET). The state of a memory cell MC with a threshold voltage higher than the read voltage Vread is called the reset state (RST).

[0032] That is, it can be referenced Figure 3 The described write operation changes the state of the memory cell MC to the set state. Additionally, it can be found by referring to... Figure 2 The described write operation changes the state of memory cell MC to the reset state RST. In this case, a write operation that changes the state of memory cell MC to the set state SET can be called a set write operation. A write operation that changes the state of memory cell MC to the reset state RST can be called a reset write operation.

[0033] Figure 5 and Figure 6 This is a schematic diagram used to describe a semiconductor device according to an embodiment of the present disclosure.

[0034] Figure 5 It is a diagram used to describe semiconductor devices, using a reference. Figures 1 to 4 The described characteristics of the storage unit are used to implement a first logic circuit (e.g., an AND operation logic circuit) with two inputs and one output.

[0035] refer to Figure 5 According to one embodiment of the present disclosure, the AND logic circuit may include two memory cells MC1 and MC2 connected between a word line WL0 and two bit lines BL1 and BL2. At this time, both memory cells MC1 and MC2 are in a write-to-memory state, causing current to flow from the word line WL0 to the two bit lines BL1 and BL2, i.e., a first state (e.g., a reset state RST). In some embodiments, both the first and second memory cells MC1 and MC2 can perform specific logical operations (e.g., such as...). Figure 5 and Figure 6 The semiconductor device components shown are for AND operations. For example, the first and second memory cells MC1 and MC2 can both be two-terminal components (e.g., diodes) that allow current to flow along a first direction from the word line WL0 to a corresponding one of the first and second bit lines BL1 and BL2, and prevent current from flowing along a second direction from a corresponding one of the first and second bit lines BL1 and BL2 to the word line WL0.

[0036] The first storage unit MC1 can be located between word line WL0 and the first bit line BL1.

[0037] The second storage unit MC2 can be located between word line WL0 and the second bit line BL2.

[0038] The first voltage supply circuit 10 can provide one of the first logic input voltage INPUT1, the first write voltage Write(+), and the second write voltage Write(-) to the first bit line BL1.

[0039] The second voltage supply circuit 20 can provide the second bit line BL2 with one of the second logic input voltage INPUT2, the first write voltage Write(+), and the second write voltage Write(-).

[0040] The third voltage supply circuit 30 can provide one of a first write voltage Write(+), a second write voltage Write(-), a first logic operation voltage (e.g., +5V), and a second logic operation voltage (e.g., 0V) to the word line WL0. At this time, when one of the first logic operation voltage +5V and the second logic operation voltage +0V is provided to the word line WL0 through the resistor element R, the third voltage supply circuit 30 can electrically connect the word line WL0 and the operation output terminal Output.

[0041] In this configuration, the first write voltage (Write(+)) can be a higher voltage level than the second write voltage (Write(-)). The first write voltage (Write(+)) can have a positive voltage level, while the second write voltage (Write(-)) can have a negative voltage level. The difference between the levels of the first write voltage (Write(+)) and the second write voltage (Write(-)) can be greater than the threshold voltage levels of the first memory cell MC1 and the second memory cell MC2 in the reset state RST. The first logic operation voltage +5V can have a higher voltage level than the second logic operation voltage +0V. The difference between the levels of the first logic operation voltage +5V and the second logic operation voltage +0V can be less than the difference between the levels of the first write voltage (Write(+)) and the second write voltage (Write(-)). An example is described where the first logic operation voltage +5V is 5V and the second logic operation voltage +0V is ground voltage +0V, but the first logic operation voltage +5V can be higher or lower than 5V, and the second logic operation voltage +0V can be higher or lower than 0V. In addition, both the first logic input voltage INPUT1 and the second logic input voltage INPUT2 can have a level of +5V for the first logic operation voltage or a level of +0V for the second logic operation voltage.

[0042] The operation of setting the states of the first storage unit MC1 and the second storage unit MC2 so that the semiconductor device constructed according to an embodiment of the present disclosure as operated as an operational logic circuit is described below.

[0043] The first memory cell MC1 can be written to a reset state RST. For example, a second write voltage Write(-) can be provided to the first bit line BL1 from the first voltage supply circuit 10. A first write voltage Write(+) can be provided to the word line WL0 from the third voltage supply circuit 30. The first memory cell MC1, connected between the first bit line BL1 and the word line WL0, can be turned on by the level difference between the first write voltage Write(+) and the second write voltage Write(-), thereby enabling the writing of the reset state RST.

[0044] The second memory cell MC2 can be written to a reset state RST. For example, a second write voltage Write(-) can be provided to the second bit line BL2 from the second voltage supply circuit 20, and a first write voltage Write(+) can be provided to the word line WL0 from the third voltage supply circuit 30. The second memory cell MC2, connected between the second bit line BL2 and the word line WL0, can be turned on by the level difference between the first write voltage Write(+) and the second write voltage Write(-), thereby enabling the writing of the reset state RST.

[0045] The first memory cell MC1 and the second memory cell MC2 can be written to the reset state RST individually or simultaneously. Specifically, each of the first memory cell MC1 and the second memory cell MC2 can be written to the reset state RST by causing current to flow from the word line WL0 to the corresponding bit line BL1 and the second bit line BL2.

[0046] After the first storage cell MC1 and the second storage cell MC2 are written to the reset state RST, an AND operation can be performed using the first storage cell MC1 and the second storage cell MC2, which are in the reset state RST.

[0047] like Figure 5 As shown, the case where the first storage cell MC1 and the second storage cell MC2 are in the reset state RST is... Figure 6 The equivalent circuit shown is used to represent this.

[0048] For reference as follows Figure 5 and Figure 6 Description and operation.

[0049] The third voltage supply circuit 30 can provide the first logic operation voltage +5V to the word line WL0, and can electrically connect the operation output terminal Output to the word line WL0. At this time, the voltage level of the word line WL0 and the operation output terminal Output can be the level of the first logic operation voltage +5V.

[0050] The first voltage supply circuit 10 can provide the first logic input voltage INPUT1 to the first bit line BL1.

[0051] The second voltage supply circuit 20 can provide the second logic input voltage INPUT2 to the second bit line BL2.

[0052] Therefore, the first logic input voltage INPUT1 provided from the first bit line BL1 and the first logic operation voltage +5V provided from the word line WL0 can be supplied to both ends (or terminals) of the first memory cell MC1 in the reset state RST. The first memory cell MC1 in the reset state RST can be in a state in which current flows better in a first direction rather than a second direction. In this case, the first direction can be the direction in which current flows from the word line WL0 through the first memory cell MC1 to the first bit line BL1. In addition, the second direction can be the direction in which current flows from the first bit line BL1 through the first memory cell MC1 to the word line WL0.

[0053] For example, the first memory cell MC1 can be used as a diode, allowing current to flow in a first direction from word line WL0 to first bit line BL1, and substantially blocking current from flowing in a second direction from first bit line BL1 to word line WL0. Therefore, when the voltage level of first bit line BL1 is lower than the voltage level of word line WL0, current can flow in the first direction from word line WL0 through the first memory cell MC1 to first bit line BL1.

[0054] The second logic input voltage INPUT2 provided from the second bit line BL2 and the first logic operation voltage +5V provided from the word line WL0 can be supplied to the two ends of the second memory cell MC2 in the reset state RST. The second memory cell MC2 in the reset state RST can be in a state in which current flows better in a first direction than in a second direction. In this case, the first direction can be the direction in which current flows from the word line WL0 through the second memory cell MC2 to the second bit line BL2. Furthermore, the second direction can be the direction in which current flows from the second bit line BL2 through the second memory cell MC2 to the word line WL0.

[0055] For example, the second memory cell MC2 can be used as a diode, allowing current to flow in the first direction from word line WL0 to the second bit line BL2, and substantially preventing current from flowing in the second direction from the second bit line BL2 to the word line WL0. Therefore, when the voltage level of the second bit line BL2 is lower than the voltage level of the word line WL0, current can flow in the first direction from word line WL0 through the second memory cell MC2 to the second bit line BL2.

[0056] Therefore, when the level of one of the first logic input voltages INPUT1 and INPUT2 is lower than the level of the first logic operation voltage +5V, current can flow from the memory cell supplied with a logic input voltage lower than the first logic operation voltage +5V to the bit line. For example, when the level of the first logic input voltage INPUT1 is lower than the level of the first logic operation voltage +5V, current can flow from the word line WL0 with the level of the first logic operation voltage +5V to the first bit line BL1 through the first memory cell MC1. At this time, due to the current flowing into the first bit line BL1 through the first memory cell MC1, the voltage level of the operational output terminal Output with the level of the first logic operation voltage +5V can be reduced. Furthermore, when the level of the second logic input voltage INPUT2 is lower than the level of the first logic operation voltage +5V, current can flow from the word line WL0, which has the level of the first logic operation voltage +5V, through the second memory cell MC2 to the second bit line BL2. At this time, due to the current flowing into the second bit line BL2 through the second memory cell MC2, the voltage level of the operational output terminal Output, which has the level of the first logic operation voltage +5V, can be reduced. In other words, when the level of one or both of the first logic input voltage INPUT1 and the second logic input voltage INPUT2 is lower than the level of the first logic operation voltage +5V, the current flowing through one or both of the first memory cell MC1 and the second memory cell MC2, as well as the resistive element R, can reduce the voltage level of the operational output terminal Output.

[0057] When the average of the first logic input voltage INPUT1 and the second logic input voltage INPUT2 is higher than the level of the first logic operation voltage +5V, current may not flow into the first bit line and the second bit lines BL1 and BL2 through the first memory cell MC1 and the second memory cell MC2. Therefore, the voltage level of the operational output terminal Output, which has the level of the first logic operation voltage +5V, can be substantially maintained. For example, the voltage level of the operational output terminal Output can be maintained in the range of approximately 95% to approximately 105%, approximately 97% to approximately 103%, or approximately 99% to approximately 101% of the first logic operation voltage +5V.

[0058] In some embodiments, when the first logic input voltage INPUT1 has a level substantially the same as the first logic operation voltage +5V, the level of the first logic input voltage INPUT1 is high; when the first logic input voltage INPUT1 has a level lower than the first logic operation voltage +5V, the level of the first logic input voltage INPUT1 is low. For example, when the absolute difference between the first logic input voltage INPUT1 and the first logic operation voltage +5V is less than or equal to 5%, 3%, or 1% of the first logic operation voltage +5V, the first logic input voltage INPUT1 has a level substantially the same as the first logic operation voltage +5V. Furthermore, in such embodiments, when the second logic input voltage INPUT2 has a level substantially the same as the first logic operation voltage +5V, the level of the second logic input voltage INPUT2 is high; when the second logic input voltage INPUT2 has a level lower than the first logic operation voltage +5V, the level of the second logic input voltage INPUT2 is low. Furthermore, in these embodiments, when the voltage level of the operational output terminal (Output) is substantially equal to the first logic operation voltage + 5V, the voltage level of the operational output terminal (Output) is high. In these embodiments, when the voltage level of the operational output terminal (Output) is lower than the first logic operation voltage + 5V, the voltage level of the operational output terminal (Output) is low.

[0059] Therefore, when either the first logic input voltage INPUT1 or the second logic input voltage INPUT2 is low, the voltage level of the operational output terminal Output can become low. Furthermore, when both the first logic input voltage INPUT1 and the second logic input voltage INPUT2 are high, the voltage level of the operational output terminal Output can remain high. This change in the voltage level of the operational output terminal Output relative to the levels of the first logic input voltage INPUT1 and the second logic input voltage INPUT2 corresponds to the result of an AND gate operation.

[0060] In other words, according to Figure 5 and Figure 6 The semiconductor device of one embodiment can perform an AND operation on a first logic input voltage INPUT1 and a second logic input voltage INPUT2, and output the voltage level of the word line WL0 at the output terminal as the result of the AND operation. Therefore, the semiconductor device according to one embodiment of the present disclosure can operate as an AND operation logic circuit.

[0061] Figure 7 and Figure 8 This is a diagram used to describe a semiconductor device according to another embodiment of the present disclosure.

[0062] Figure 7It is a diagram used to describe semiconductor devices, using a reference. Figures 1 to 4 The described characteristics of the storage unit are used to implement a second logic circuit (e.g., an OR operation logic circuit) with two inputs and one output.

[0063] refer to Figure 7 According to one embodiment of the present disclosure, the OR operation logic circuit may include two memory cells MC1 and MC2 connected between a word line WL0 and two bit lines BL1 and BL2. At this time, both memory cells MC1 and MC2 can be in a state where the memory cell has been written to, such that current flows from the first bit line and the second bit lines BL1 and BL2 to the word line WL0, i.e., the second state (e.g., the set state). In some embodiments, both the first and second memory cells MC1 and MC2 can be used to perform specific logical operations (e.g., ...). Figure 7 and Figure 8 The semiconductor device components shown are for OR operations. For example, the first and second memory cells MC1 and MC2 can both be two-terminal components (e.g., diodes) that allow current to flow in a second direction from a corresponding one of the first and second bit lines BL1 and BL2 to the word line WL0, and prevent current from flowing in a first direction from the word line WL0 to a corresponding one of the first and second bit lines BL1 and BL2.

[0064] The first storage unit MC1 can be located between word line WL0 and the first bit line BL1.

[0065] The second storage unit MC2 can be located between word line WL0 and the second bit line BL2.

[0066] The first voltage supply circuit 10 can provide one of the first logic input voltage INPUT1, the first write voltage Write(+), and the second write voltage Write(-) to the first bit line BL1.

[0067] The second voltage supply circuit 20 can provide the second bit line BL2 with one of the second logic input voltage INPUT2, the first write voltage Write(+), and the second write voltage Write(-).

[0068] The third voltage supply circuit 30 can provide one of a first write voltage Write(+), a second write voltage Write(-), a first logic operation voltage (e.g., +5V), and a second logic operation voltage (e.g., 0V) to the word line WL0. At this time, when one of the first logic operation voltage +5V and the second logic operation voltage +0V is provided to the word line WL0 through the resistor element R, the third voltage supply circuit 30 can electrically connect the word line WL0 and the operation output terminal Output.

[0069] In this configuration, the first write voltage (Write(+)) can be a voltage with a higher level than the second write voltage (Write(-)). The first write voltage (Write(+)) can be a positive voltage level. The second write voltage (Write(-)) can be a negative voltage level. The difference between the levels of the first write voltage (Write(+)) and the second write voltage (Write(-)) can be greater than the threshold voltage levels of the first memory cell MC1 and the second memory cell MC2 in the reset state RST. The first logic operation voltage +5V can be higher than the level of the second logic operation voltage +0V. The difference between the levels of the first logic operation voltage +5V and the second logic operation voltage +0V can be less than the difference between the levels of the first write voltage (Write(+)) and the second write voltage (Write(-)). An example is described where the first logic operation voltage +5V is 5V and the second logic operation voltage +0V is ground voltage +0V, but the first logic operation voltage +5V can be higher or lower than 5V, and the second logic operation voltage +0V can be higher or lower than 0V. In addition, both the first logic input voltage INPUT1 and the second logic input voltage INPUT2 can have a level of +5V for the first logic operation voltage or a level of +0V for the second logic operation voltage.

[0070] The operation of setting the states of the first storage unit MC1 and the second storage unit MC2 to enable the semiconductor device constructed according to an embodiment of the present disclosure to operate as an OR operation logic circuit is described below.

[0071] The first memory cell MC1 can be written to the set state SET. For example, a first write voltage Write(+) can be provided to the first bit line BL1 from the first voltage supply circuit 10. A second write voltage Write(-) can be provided to the word line WL0 from the third voltage supply circuit 30. The first memory cell MC1, connected between the first bit line BL1 and the word line WL0, can be turned on by the level difference between the first write voltage Write(+) and the second write voltage Write(-), thereby being written to the set state SET.

[0072] The second memory cell MC2 can be written to the set state SET. For example, a first write voltage Write(+) can be provided to the second bit line BL2 from the second voltage supply circuit 20. A second write voltage Write(-) can be provided to the word line WL0 from the third voltage supply circuit 30. The second memory cell MC2, connected between the second bit line BL2 and the word line WL0, can be turned on by the level difference between the first write voltage Write(+) and the second write voltage Write(-), thereby being written to the set state SET.

[0073] The first memory cell MC1 and the second memory cell MC2 can be written to the set state SET, or they can be written to the set state SET simultaneously. Specifically, by causing current to flow from one of the first bit line BL1 and the second bit line BL2 to the word line WL0, each of the first and second memory cells MC1 and MC2 can be written to the set state SET.

[0074] After the first storage unit MC1 and the second storage unit MC2 are written to the set state SET, the first storage unit MC1 and the second storage unit MC2, which are in the set state SET, can be used to perform OR operations.

[0075] like Figure 7 As shown, the first storage unit MC1 and the second storage unit MC2 can be in the SET state as follows: Figure 8 The equivalent circuit form is shown.

[0076] The following will refer to Figure 7 and Figure 8 Operations that describe or perform calculations.

[0077] The third voltage supply circuit 30 can provide the second logic operation voltage +0V to the word line WL0 and electrically connect the operation output terminal Output to the word line WL0. At this time, the voltage levels of both the word line WL0 and the operation output terminal Output can be the level of the second logic operation voltage +0V.

[0078] The first voltage supply circuit 10 can provide the first logic input voltage INPUT1 to the first bit line BL1.

[0079] The second voltage supply circuit 20 can provide the second logic input voltage INPUT2 to the second bit line BL2.

[0080] Therefore, the first logic input voltage INPUT1 provided from the first bit line BL1 and the second logic operation voltage +0V provided from the word line WL0 can be supplied to the two ends (or terminals) of the first memory cell MC1 in the set state SET. The first memory cell MC1 in the set state SET can be in a state in which current flows better in a second direction than in the first direction. In this case, the first direction can be the direction in which current flows from the word line WL0 through the first memory cell MC1 to the first bit line BL1. In addition, the second direction can be the direction in which current flows from the first bit line BL1 through the first memory cell MC1 to the word line WL0.

[0081] For example, the first memory cell MC1 can be used as a diode, allowing current to flow in the second direction from the first bit line BL1 to the word line WL0, and substantially preventing current from flowing in the first direction from the word line WL0 to the first bit line BL1. Therefore, when the voltage level of the first bit line BL1 is higher than the voltage level of the word line WL0, current can flow in the second direction from the first bit line BL1 through the first memory cell MC1 to the word line WL0.

[0082] The second logic input voltage INPUT2 provided from the second bit line BL2 and the second logic operation voltage +0V provided from the word line WL0 can be supplied to both ends of the second memory cell MC2 in the set state. The second memory cell MC2 in the set state can be in a state where current flows better in a second direction than in a first direction. In this case, the first direction can be the direction in which current flows from the word line WL0 through the second memory cell MC2 to the second bit line BL2. Furthermore, the second direction can be the direction in which current flows from the second bit line BL2 through the second memory cell MC2 to the word line WL0.

[0083] For example, the second memory cell MC2 can be used as a diode, allowing current to flow in a second direction from the second bit line BL2 to the word line WL0, and substantially blocking current flow in the first direction from the word line WL0 to the second bit line BL2. Therefore, when the voltage level of the second bit line BL2 is higher than the voltage level of the word line WL0, current can flow in the second direction from the second bit line BL2 through the second memory cell MC2 to the word line WL0.

[0084] Therefore, when the level of one of the first logic input voltage INPUT1 and the second logic input voltage INPUT2 is higher than the level of the second logic operation voltage +0V, current can flow into the word line through the memory cell provided with a logic input voltage higher than the second logic operation voltage +0V. For example, when the level of the first logic input voltage INPUT1 is higher than the level of the second logic operation voltage +0V, current can flow from the first bit line BL1 through the first memory cell MC1 to the word line WL0. At this time, since current flows into the word line WL0 through the first memory cell MC1, the voltage level of the operation output terminal Output, which has a level of the second logic operation voltage +0V, can rise. Furthermore, when the level of the second logic input voltage INPUT2 is higher than the level of the second logic operation voltage +0V, current can flow from the second bit line BL2 through the second memory cell MC2 to the word line WL0. At this time, because current flows into word line WL0 through the second storage cell MC2, the voltage level of the operational output terminal Output, which has a second logic operation voltage of +0V, can rise. In other words, when the level of one or both of the first logic input voltage INPUT1 and the second logic input voltage INPUT2 is higher than the level of the second logic operation voltage +0V, the current flowing into the resistor element R through one or both of the first and second storage cells MC1 and MC2 can increase the voltage level of the operational output terminal Output.

[0085] When both the first logic input voltage INPUT1 and the second logic input voltage INPUT2 have a level of the second logic operation voltage +0V, no current will flow into the word line WL0 through the first memory cell MC1 and the second memory cell MC2. Therefore, the voltage level of the output terminal Output can be basically maintained at the level of the second logic operation voltage +0V.

[0086] In some embodiments, when the level of the first logic input voltage INPUT1 is substantially the same as the first logic operation voltage +5V, the level of the first logic input voltage INPUT1 is high; when the level of the first logic input voltage INPUT1 is lower than the first logic operation voltage +5V, the level of the first logic input voltage INPUT1 is low. Furthermore, in these embodiments, when the level of the second logic input voltage INPUT2 is substantially the same as the first logic operation voltage +5V, the level of the second logic input voltage INPUT2 is high; when the level of the second logic input voltage INPUT2 is lower than the first logic operation voltage +5V, the level of the second logic input voltage INPUT2 is low. Furthermore, in these embodiments, when the voltage level of the operational output terminal Output is substantially the same as the first logic operation voltage +5V, the voltage level of the operational output terminal Output is high. In these embodiments, when the voltage level of the operational output terminal Output is lower than the first logic operation voltage +5V, the voltage level of the operational output terminal Output is low.

[0087] Therefore, when either the first logic input voltage INPUT1 or the second logic input voltage INPUT2 is high, the voltage level of the operational output terminal Output can become high. Furthermore, when both the first logic input voltage INPUT1 and the second logic input voltage INPUT2 are low, the voltage level of the operational output terminal Output can remain low. This change in the voltage level of the operational output terminal Output relative to the levels of the first logic input voltage INPUT1 and the second logic input voltage INPUT2 corresponds to the result of an OR gate operation.

[0088] In other words, according to Figure 7 and Figure 8 The semiconductor device of the illustrated embodiment can perform an OR operation on the first logic input voltage INPUT1 and the second logic input voltage INPUT2, and output the voltage level of the word line WL0 at the operation output terminal as the result of the OR operation. Therefore, the semiconductor device according to one embodiment of the present disclosure can operate as an OR operation logic circuit.

[0089] Figure 9 This is a diagram used to describe a memory cell array according to an embodiment of the present disclosure.

[0090] A semiconductor device according to one embodiment of the present disclosure can write multiple memory cells to a specific state (e.g., a set state), and then use the written memory cells for AND and OR operations. For example, refer to... Figure 5 and Figure 6According to one embodiment of the semiconductor device disclosed herein, two memory cells can be written to a reset state, and then the two memory cells in the reset state are used for a bitwise AND operation. Furthermore, refer to... Figure 7 and Figure 8 According to one embodiment of the present disclosure, a semiconductor device can write two memory cells into a set state, and then use the two memory cells in the set state for an OR operation.

[0091] Storage cells used for AND and OR operations can be manufactured in the same manner as storage cells used for storing data, and can be used as components constituting a storage cell array.

[0092] Therefore, refer to Figure 9 A semiconductor device according to one embodiment of the present disclosure may include a memory cell array.

[0093] A memory cell array may include multiple memory cells MC connected between multiple bit lines BL and multiple word lines WL. In this case, each of the multiple memory cells MC may be located at each position where each of the multiple bit lines BL intersects with each of the multiple word lines WL.

[0094] Some of the multiple storage cells (MCs) included in the storage cell array can be used to store data, while the rest can be used for logical operations.

[0095] A storage cell array may include a data storage area and a computation area. The data storage area may include storage cells for storing data. The computation area may include storage cells for logical operations.

[0096] Therefore, a semiconductor device including a memory cell array according to an embodiment of the present disclosure can perform computational functions in addition to data storage functions. The memory cells in the computational region of the memory cell array can be written to perform various logical operations, thereby ensuring the design flexibility of the semiconductor device including the memory cell array according to an embodiment of the present disclosure. Furthermore, the semiconductor device according to an embodiment of the present disclosure can omit logic components (e.g., logic transistors) that are separately formed from the memory cell array in conventional semiconductor devices, thereby facilitating the implementation of a relatively large number of logic components to improve computing performance.

[0097] Although some embodiments of this disclosure have been described above with reference to the accompanying drawings, the various embodiments of this disclosure are not limited to those described above. Those skilled in the art to which this disclosure pertains can substitute, modify, and change these embodiments in various ways based on the teachings of this disclosure, and such substitutions, modifications, and changes may be part of the various embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: The first storage unit is connected between the first bit line and the word line; A second storage unit is connected between the second bit line and the word line; A first voltage supply circuit provides a first logic input voltage to the first memory cell; The second voltage supply circuit provides the second logic input voltage to the second memory cell; as well as A third voltage supply circuit provides one of a first logic operation voltage and a second logic operation voltage to the word lines. Each of the first storage unit and the second storage unit is a component of the device that performs specific logical operations.

2. The semiconductor device according to claim 1, wherein, The state of the first storage unit is the same as the state of the second storage unit.

3. The semiconductor device according to claim 2, wherein, The logical operation is an AND operation, and each of the first storage unit and the second storage unit is in a first state. Each of the first storage unit and the second storage unit is written into the first state by causing current to flow from the word line to the corresponding one of the first bit line and the second bit line.

4. The semiconductor device according to claim 3, wherein, The third voltage supply circuit provides the first logic operation voltage to the word line through a resistor element, wherein the level of the first logic operation voltage is higher than that of the second logic operation voltage.

5. The semiconductor device according to claim 4, wherein, The device performs an AND operation on the first logic input voltage and the second logic input voltage, and outputs the voltage level of the word line as the result of the AND operation.

6. The semiconductor device according to claim 2, wherein, The logical operation is an OR operation, each of the first storage unit and the second storage unit is in a second state, and each of the first storage unit and the second storage unit is written into the second state by causing current to flow from one of the corresponding first bit lines and the second bit lines to the word line.

7. The semiconductor device according to claim 6, wherein, The third voltage supply circuit provides the second logic operation voltage to the word line through a resistor element, wherein the level of the second logic operation voltage is lower than that of the first logic operation voltage.

8. The semiconductor device according to claim 7, wherein, The device performs the OR operation on the first logic input voltage and the second logic input voltage, and outputs the voltage level of the word line as the result of the OR operation.

9. The semiconductor device according to claim 2, wherein, The first voltage supply circuit and the second voltage supply circuit provide a second write voltage to the first bit line and the second bit line respectively, and the third voltage supply circuit provides a first write voltage to the word line. The level of the first write voltage is higher than the second write voltage, so as to write the first memory cell and the second memory cell into a reset state.

10. The semiconductor device according to claim 2, wherein, The first voltage supply circuit and the second voltage supply circuit provide a first write voltage to the first bit line and the second bit line respectively, and the third voltage supply circuit provides a second write voltage to the word line. The level of the second write voltage is lower than the first write voltage, so as to write the first memory cell and the second memory cell into a set state.

11. A method of operating a semiconductor device, comprising: Write the first memory cell connected between the first bit line and the word line into a specific state; The second memory cell connected between the second bit line and the word line is written to the specific state; Provide a first logic input voltage to the first bit line; Provide a second logic input voltage to the second bit line; as well as One of a first logic operation voltage and a second logic operation voltage is provided to the word line according to the type of logic operation performed by the device including the first memory cell and the second memory cell.

12. The operating method according to claim 11, wherein, The logical operation is an AND operation, whereby the first memory cell is written by causing current to flow from the word line to the first bit line, and the second memory cell is written by causing current to flow from the word line to the second bit line.

13. The operating method according to claim 12, wherein, The first logic operation voltage is provided to the word line through a resistor element.

14. The operating method according to claim 12, further comprising: Check the voltage level of the word line as a result of the AND operation.

15. The operating method according to claim 11, wherein, The logical operation is an OR operation, whereby the first memory cell is written by causing current to flow from the first bit line to the word line, and the second memory cell is written by causing current to flow from the second bit line to the word line.

16. The operating method according to claim 15, wherein, The second logic operation voltage is provided to the word line through a resistive element.

17. The operating method according to claim 15, further comprising: Check the voltage level of the word line as a result of the OR operation.

18. A storage device comprising: The first storage cell is connected between the first bit line and the word line and serves as the first double-ended component; The second storage unit is connected between the second bit line and the word line and serves as a second double-ended component; A first voltage supply circuit provides a first logic input voltage to the first bit line; The second voltage supply circuit provides the second logic input voltage to the second bit line; as well as A third voltage supply circuit provides one of a first logic operation voltage and a second logic operation voltage to the word line, wherein the level of the first logic operation voltage is higher than that of the second logic operation voltage. The device performs specific logic operations on the first logic input voltage and the second logic input voltage, and outputs the voltage level of the word line as the result of the logic operation.

19. The storage device according to claim 18, wherein, The logical operation is an AND operation, and each of the first dual-ended component and the second dual-ended component is a diode, which allows current to flow in a first direction from the word line to a corresponding one of the first bit line and the second bit line, and prevents current from flowing in a second direction from a corresponding one of the first bit line and the second bit line to the word line.

20. The storage device according to claim 18, wherein, The logical operation is an OR operation, and each of the first dual-ended component and the second dual-ended component is a diode, which allows current to flow along the second direction from one of the first bit line and the second bit line to the word line, and prevents current from flowing along the first direction from the word line to one of the first bit line and the second bit line.

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